Memory controllers, memory devices, and memory systems

Abstract

This invention discloses a memory controller, a memory device, and a memory system. In an embodiment, the memory system includes a memory device configured to provide data processing functions, such as computational functions. In the memory system, during at least a portion of the time when some of the N memory rows sharing a data channel perform computational operations, at least one of the remaining memory rows performs general memory operations (such as write or read operations), thereby enabling the memory system to reduce latency of general memory operations while still providing computational operations.

Description

[0001] Cross-reference to related applications

[0002] This patent document claims priority and benefit to Korean patent application No. 10-2024-0197826, filed on December 27, 2024, which is incorporated herein by reference in its entirety. Technical Field

[0003] Various embodiments of the disclosed technology relate to a memory controller, a memory device, and a memory system. Background Technology

[0004] A memory device may include multiple memory cells for data storage. For example, a memory device may store data or provide previously stored data to a host device in response to a command from a host device.

[0005] The host device can perform calculations using data stored in the memory device and generate data processing results based on these calculations. As the computational workload of the host device increases, the volume of data transferred between the host device and the memory device may also increase.

[0006] As the amount of data transferred between the host device and the memory device increases, the operational performance of the memory device or the entire computing system including the memory device and the host device may degrade. Summary of the Invention

[0007] The disclosed technology can be implemented in some embodiments to address the problems mentioned in this patent document and other problems not explicitly mentioned herein.

[0008] The disclosed techniques can be implemented in some embodiments to enable memory devices to perform computational functions while improving their operational efficiency during computation.

[0009] In an embodiment, a memory system may include: a memory device including a plurality of memory rank, each of the plurality of memory rank including at least one memory bank, the at least one memory bank including an array of memory cells for storing data and computational logic circuitry for performing data processing; and a memory controller configured to control the operation of the plurality of memory rank based on commands waiting in a command queue for each of the plurality of memory rank, wherein during at least a portion of a first time period during which P of the N memory rank (N is an integer satisfying N≥2) of the N memory rank (P is an integer satisfying N>P≥1) operate in response to a first command, at least one of the (NP) memory rank operates in response to a second command without utilizing computational logic circuitry.

[0010] In an embodiment, a memory controller may include: at least one command queue configured to store a first command and a second command for each of a plurality of memory rows in one or more memory devices; and a scheduler configured to schedule commands to be executed by each of the plurality of memory rows during a preset operation period based on the number of the first commands and the number of the second commands, and, when at least one second command is present, schedule an operation to be executed by at least one of the other portions of the plurality of memory rows in response to the second command while an operation in response to the first command is being performed by a portion of the plurality of memory rows.

[0011] In an embodiment, a memory device may include: a first memory row including a plurality of first memory banks, each first memory bank including a first memory cell array and a first computational logic circuit that performs computations using the first memory cell array; and a second memory row including a plurality of second memory banks, each second memory bank including a second memory cell array and a second computational logic circuit that performs computations using the second memory cell array, wherein the first memory row and the second memory row share a data channel, and during a first time period of operation of the first computational logic circuit included in the first memory row, programming operations or reading operations on the second memory cell array are performed without using the second computational logic circuit included in the second memory row.

[0012] In an embodiment, a memory device may include: a first memory chip including a plurality of first memory banks, each first memory bank including a first memory cell array and a first computational logic circuit that performs computation using the first memory cell array; and a second memory chip including a plurality of second memory banks, each second memory bank including a second memory cell array and a second computational logic circuit that performs computation using the second memory cell array, wherein, during a first time period, the first computational logic circuit included in a first group of the plurality of first memory banks and the second computational logic circuit included in the first group of the plurality of second memory banks operate, while the first computational logic circuit included in a second group of the plurality of first memory banks and the second computational logic circuit included in the second group of the plurality of second memory banks do not operate.

[0013] In an embodiment, a memory device may include: a first memory chip including a plurality of first memory banks, each first memory bank including a first memory cell array and a first computational logic circuit that performs computation using the first memory cell array; and a second memory chip including a plurality of second memory banks, each second memory bank including a second memory cell array, wherein a programming operation or a reading operation is performed on the first group of the plurality of second memory banks during at least a portion of a first time period during which the first computational logic circuit included in the first group of the plurality of first memory banks operates.

[0014] Based on some embodiments of the disclosed technology, the data processing performance of the memory device can be improved by utilizing the computing function of the memory device, and the operational performance of the memory device can be improved by scheduling the operation of the memory device during the period in which the computing function of the memory device is executed.

[0015] The effects of the embodiments of the disclosed technology are not limited to those described above, and those skilled in the art will clearly understand from the description of the claims other effects not mentioned. Attached Figure Description

[0016] Figure 1 This is a diagram illustrating an example of a memory system based on some embodiments of the disclosed technology.

[0017] Figure 2 This is a diagram illustrating examples of memory devices within a memory system based on some embodiments of the disclosed technology.

[0018] Figure 3 This is a diagram illustrating examples of memory devices within a memory system based on some embodiments of the disclosed technology.

[0019] Figures 4 to 5 It is shown Figure 3 A diagram illustrating an example of the operating scheme of the memory system shown.

[0020] Figures 6 to 7 It is shown Figure 3 A diagram illustrating an example of the operating timing of the memory system shown.

[0021] Figure 8 This is a diagram illustrating an example of an operating scheme for a memory system based on some embodiments of the disclosed technology.

[0022] Figure 9A , Figure 9B and Figure 10 This is a diagram illustrating examples of operating schemes for various types of memory systems based on some embodiments of the disclosed technology. Detailed Implementation

[0023] In the following text, various embodiments of the disclosed technology will be described in detail with reference to the accompanying drawings.

[0024] Figure 1 This is a diagram illustrating an example of a memory system 100 based on some embodiments of the disclosed technology.

[0025] Reference Figure 1 The memory system 100 according to embodiments of the disclosed technology may include at least one memory device 110. The memory system 100 may include a memory controller 120 for controlling the operation of the memory device 110.

[0026] Memory device 110 may be, for example, volatile memory, such as DRAM (e.g., SDRAM, such as DDR SDRAM or LPDDR SDRAM), but embodiments of the disclosed technology are not limited thereto. Memory device 110 may be non-volatile memory, such as NAND flash memory, 3D NAND flash memory, or NOR flash memory. In some embodiments, a portion of the memory device 110 included in memory system 100 may be volatile memory, and another portion may be non-volatile memory.

[0027] The memory device 110 can be one of various types of memory, such as resistive RAM, phase-change memory, magnetoresistive memory, ferroelectric memory, or spin-transfer torque memory.

[0028] In some embodiments, memory device 110 may be a part-in-memory (PIM) process that includes computing and / or data processing functions. In some embodiments, PIM is a computer architecture in which data operations, such as computing and / or data processing operations, are performed directly on the memory storing the data without first sending the data to a separate data processing unit, thereby improving speed and efficiency. Components performing computing functions in memory device 110 may be located inside or outside the memory bank of memory device 110. When components performing computing functions are located outside the memory bank of memory device 110, the components may be adjacent to the memory bank of memory device 110 or may be located in a separate region spaced apart from the memory bank of memory device 110. In some embodiments of the disclosed technology, memory device 110 may also be referred to as a "memory chip" or simply "memory".

[0029] The memory controller 120 can control the operation of the memory device 110 in response to commands received from an external device. The memory controller 120 can also control the operation of the memory device 110 based on commands it generates independently, without receiving commands from an external device.

[0030] The memory controller 120 can send commands, addresses, data, etc., to the memory device 110 to control the operation of the memory device 110. The physical layer for sending and receiving signals can be located outside or inside the memory controller 120. The memory controller 120 can include various logic circuits performing various functions and can be implemented as a single chip. In some embodiments, at least a portion of the various logic circuits can be implemented as a chipset. The memory controller 120 can control operations such as writing data to the memory device 110. The memory controller 120 can control operations such as reading data written to the memory device 110.

[0031] When the memory device 110 is a specific type of memory device (such as a specific non-volatile memory device), the memory controller 120 can control refresh operations or erase operations on data written to the memory device 110.

[0032] The memory controller 120 can perform error detection and / or correction operations to detect and / or correct errors in data read from the memory device 110. In some embodiments, the error correction operations can be performed internally within the memory device 110. For example, the error correction operations can be performed by logic circuitry within the memory device 110.

[0033] The memory controller 120 can control the operation of the memory device 110 based on commands received from the external host device 200.

[0034] For example, host device 200 can be a computer, ultra-mobile PC (UMPC), workstation, personal digital assistant (PDA), tablet computer, mobile phone, smartphone, e-book reader, portable multimedia player (PMP), portable game console, navigation device, black box, digital camera, digital multimedia broadcast (DMB) player, smart TV, digital audio recorder, digital audio player, digital image recorder, digital image player, digital video recorder, digital video player, storage device configured for data center, one of various electronic devices configured for home network, one of various electronic devices configured for telematics network, radio frequency identification (RFID) device, mobile device capable of driving or autonomous driving under human control (e.g., vehicle, robot, or drone), etc. Optionally, host device 200 can be a virtual / augmented reality device that provides 2D or 3D virtual reality images or augmented reality images. In addition to the examples above, host device 200 can be any of various electronic devices that require the storage system 100 to store data for data processing. Additionally, the host device 200 may be a processor, such as a central processing unit (CPU), graphics processing unit (GPU), neural processing unit (NPU), and tensor processing unit (TPU), but is not limited thereto. The host device 200 and the memory system 100 may be collectively referred to as a computing system. The computing system may include at least one memory system 100 disposed around the host device 200, and may further include at least one data storage device other than the memory system 100.

[0035] The host device 200 may include at least one operating system. The operating system can manage and control the overall functions and operation of the host device 200, and can control the interaction between the host device 200 and the memory system 100. Depending on the mobility of the host device 200, the operating system can be classified as a general operating system or a mobile operating system.

[0036] In one embodiment, the memory controller 120 and the host device 200 may be separate devices. In another embodiment, the memory controller 120 and the host device 200 may be integrated into a single device. In one embodiment, all functions of the memory controller 120 may be integrated into the host device 200. In another embodiment, some functions of the memory controller 120 may be integrated into the host device 200. For ease of explanation, the following description assumes that the memory controller 120 and the host device 200 are separate devices. For example, an example will be provided where the memory controller 120 is located within the memory system 100. However, this is merely an example, and embodiments of the disclosed technology are not limited thereto.

[0037] Based on some embodiments of the disclosed technology, the memory system 100 can perform some computational functions on behalf of the host device 200 and can provide the computation results to the host device 200. The memory system 100 may include at least one memory device 110 that provides computational functions. The memory controller 120 can control whether the memory device 110 performs some computational functions and its execution timing. By having the memory system 100 provide computational functions, the operational performance of a computing system using the memory system 100 to perform data processing can be improved.

[0038] Figure 2 This is a diagram illustrating an example of a memory device 110 within a memory system 100 based on some embodiments of the disclosed technology.

[0039] Reference Figure 2 The memory system 100 may include a memory device 110 and a memory controller 120.

[0040] The memory system 100 may include, for example, a first memory device 111 and a second memory device 112.

[0041] The first memory device 111 may include a plurality of first memory banks 310. Each of the plurality of first memory banks 310 may include a first memory cell array 311 of first memory cells and a first computational logic circuit 312. Although the first computational logic circuit 312 is shown as an example located inside the first memory bank 310, embodiments of the disclosed technology can also be applied to cases where the first computational logic circuit 312 is located outside the first memory bank 310.

[0042] The second memory device 112 may include a plurality of second memory banks 320. Each of the plurality of second memory banks 320 may include a second memory cell array 321 of second memory cells. Each of the plurality of second memory banks 320 may include circuitry for operating the second memory cell array 321.

[0043] In some embodiments, the memory system 100 may include a memory device 110 (such as a first memory device 111) that provides computing functions, and may also include a memory device 110 (such as a second memory device 112) that does not provide computing functions. The memory system 100 may include at least one first memory device 111 and at least one second memory device 112. In some embodiments, the memory system 100 may include only a memory device 110 (such as a first memory device 111) that provides computing functions.

[0044] To ensure efficient operation of the first memory device 111 and the second memory device 112, the memory system 100 can schedule commands processed by the first memory device 111 and the second memory device 112 and control the operation of the first memory device 111 and the second memory device 112.

[0045] For example, the memory controller 120 of the memory system 100 may include a command queue 121 and a scheduler 122. The command queue 121 may store commands, for example, received from the host device 200. The command queue 121 may store all commands sequentially, or it may store commands to be processed sequentially for each memory device 110.

[0046] The scheduler 122 can control the type and order of commands to be processed by the first memory device 111 and the second memory device 112 based on the commands stored in the command queue 121.

[0047] For example, the first memory device 111 can share a data channel with the second memory device 112. The scheduler 122 can control the command processing operations of the first memory device 111 and the second memory device 112 through the shared data channel. The scheduler 122 can control the operation of the first memory device 111 and the second memory device 112 according to the commands stored in the command queue 121.

[0048] Scheduler 122 can control the first memory device 111 to perform operations using the first computational logic circuit 312 based on commands stored in the command queue 121. During at least a portion of the time that the first computational logic circuit 312 of the first memory device 111 is performing operations, scheduler 122 can control the operation of writing data to or reading data written to the second memory device 112.

[0049] Scheduler 122 can execute operations of writing data to or reading data written to the first memory device 111 based on the waiting command queue stored in command queue 121. Scheduler 122 can control the write or read operations to be performed on the first memory device 111 based on the waiting queues of commands from the first memory device 111 and commands from the second memory device 112.

[0050] When the scheduler 122 controls the operation order of the first memory device 111 and the second memory device 112 based on the type, order and number of commands to be processed in the first memory device 111 and the second memory device 112 with a shared data channel, the scheduler 122 can improve the command processing performance of both the first memory device 111 and the second memory device 112.

[0051] As illustrated in the examples above, memory system 100 may include memory devices 110 that provide computing functions and memory devices 110 that do not provide computing functions. In another embodiment, all memory devices 110 in memory system 100 may provide computing functions. Even in this case, the scheduler 122 of memory controller 120 may improve the operating efficiency of memory system 100 by controlling the operation of memory devices 110 sharing a data channel.

[0052] Figure 3 This is a diagram illustrating an example of a memory device 110 within a memory system 100 based on some embodiments of the disclosed technology.

[0053] Reference Figure 3 The memory system 100 may include at least one memory device 110. The memory system 100 may include a memory controller 120, which controls the operation of at least one memory device 110.

[0054] At least one memory device 110 may include a memory rank, or may be divided into multiple memory ranks 400 (e.g., 410, 420). A memory rank 400 may refer to a unit operating under the control of a memory controller 120. For example, a memory rank 400 may include a group of memory chips that operate independently or are accessed simultaneously within a memory system. For example, a group of memory devices 110 may constitute a single memory rank 400. In some embodiments, a memory rank 400 may be a region of memory device 110. In some embodiments, a memory rank 400 may include corresponding regions of multiple memory devices 110. In some embodiments that provide two or more different memory ranks, providing memory operation commands based on a memory rank may allow the memory controller to enable another memory rank to perform computations or data processing by logic circuitry in the memory bank or memory device belonging to that other memory rank, while it can control the memory bank or memory device belonging to one memory rank to perform general memory operations (such as read or write operations).

[0055] exist Figure 3 In one example, memory system 100 may include example 400 having a first memory bus 410 and a second memory bus 420. The first memory bus 410 may share a data path with the second memory bus 420. Figure 4 The example 400 of the memory system 100 shown having two memory rows 410 and 420 is an example of a particular implementation, but the number of memory rows 400 included in the memory system 100 may vary based on the needs of the memory system 100 in a particular application.

[0056] The first storage row 410 may include a plurality of first storage banks 310a, 310b, ..., 310k. The plurality of first storage banks 310a, 310b, ..., 310k may be included in the same memory device 110. Optionally, each of the plurality of first storage banks 310a, 310b, ..., 310k may be included in a separate memory device 110.

[0057] The plurality of first memory banks 310a, 310b, ..., 310k may each include a first memory cell array 311a, 311b, ..., 311k and a first computing logic circuit 312a, 312b, ..., 312k. The first computing logic circuits 312a, 312b, ..., 312k may be located inside the plurality of first memory banks 310a, 310b, ..., 310k, or, in some embodiments, may be located outside the plurality of first memory banks 310a, 310b, ..., 310k.

[0058] The second storage row 420 may include a plurality of second storage banks 320a, 320b, ..., 320k. The plurality of second storage banks 320a, 320b, ..., 320k may be included in the same memory device 110 or in different memory devices 110. Corresponding areas of at least a plurality of second storage banks 320a, 320b, ..., 320k may be included in the same memory device 110 as corresponding areas of a plurality of first storage banks 310a, 310b, ..., 310k. For example, first storage bank 310a and second storage bank 320a may be included in the same memory device 110.

[0059] The plurality of second memory banks 320a, 320b, ..., 320k may each include a second memory cell array 321a, 321b, ..., 321k and a second computing logic circuit 322a, 322b, ..., 322k. In one embodiment, the second computing logic circuits 322a, 322b, ..., 322k may be located inside the plurality of second memory banks 320a, 320b, ..., 320k. In another embodiment, the second computing logic circuits 322a, 322b, ..., 322k may be located outside the plurality of second memory banks 320a, 320b, ..., 320k.

[0060] The memory controller 120 may include a command queue 121 and a scheduler 122. The command queue 121 may store commands for each memory row 400.

[0061] For example, command queue 121 may store the first command CMDa and the second command CMDb to be processed for the first storage row 410 (e.g., storage row #1 CMDa, storage row #1 CMDb). Command queue 121 may also store the first command CMDa and the second command CMDb to be processed for the second storage row 420 (e.g., storage row #2 CMDa, storage row #2 CMDb). The number and type of commands stored in command queue 121 may be different.

[0062] For example, the first command CMDa can be a command that requires operation of the computational logic circuits included in each memory row 400 (or a memory row including computational logic circuits). In the operation performed in response to the first command CMDa, the first computational logic circuit 312 included in the first memory row 410 can be operated, or the second computational logic circuit 322 included in the second memory row 420 can be operated. The first command CMDa can be referred to as a computation command, and the operation performed in response to the first command CMDa can be referred to as a computation operation.

[0063] Computational logic circuits can perform computations using data stored in a memory cell array in response to specific commands. For example, a computational logic circuit can read data stored in at least one region of the memory cell array and perform computations on the read data. The computational logic circuit can then store the computation results in the memory cell array.

[0064] For example, the second command CMDb can be a command that does not require the operation of computational logic circuitry included in each memory row 400. The second command CMDb can be a command instructing the writing of data to or reading data written to the memory cell array included in each memory row 400. The second command CMDb can include commands other than those requiring the operation of computational logic circuitry. The second command CMDb can be referred to as a general memory command, and the operation based on the second command CMDb can be referred to as a general memory operation.

[0065] In response to the second command CMDb, the first memory row 410 or the second memory row 420 can perform operations to write data to the memory cell array included in each memory row 400, or to read data written to the memory cell array. When performing operations according to the second command CMDb, the computational logic circuitry included in each memory row 400 does not operate.

[0066] The scheduler 122 of the memory controller 120 can set the commands to be processed by each memory row 400 based on the type, order, and number of commands waiting in the command queue 121 for each memory row 400. The scheduler 122 can set the commands to be processed by the first memory row 410 and the commands to be processed by the second memory row 420 every preset period.

[0067] For example, when the number of second commands CMDb stored in command queue 121 is greater than 0, scheduler 122 can control at least one of the multiple storage queues 400 to operate according to the second command CMDb.

[0068] During at least a portion of the time period when P of the N storage rows 400 (N is an integer satisfying N≥2) of the shared data channel are operated according to the first command CMDa, the scheduler 122 can control at least one of the (NP) storage rows 400 to operate according to the second command CMDb.

[0069] For example, in Figure 3In the example shown, during at least a portion of the time period during which the first storage row 410 operates according to the first command CMDa, the scheduler 122 can control the second storage row 420 to operate according to the second command CMDb. Among the storage rows sharing a data channel, during the same time period, the first storage row 410 can operate according to the first command CMDa, while the second storage row 420 can operate according to the second command CMDb.

[0070] When the number of second commands CMDb stored in command queue 121 is 0, scheduler 122 can control all multiple storage queues 400 to operate according to the first command CMDa.

[0071] Even if the number of second commands CMDb stored in command queue 121 is greater than 0, when the waiting time of the first command CMDa stored in command queue 121 is longer than the preset threshold time, scheduler 122 can control all multiple storage queues 400 to perform operations according to the first command CMDa.

[0072] Since the scheduler 122 controls the operation of the first storage row 410 and the second storage row 420 of the shared data channel based on commands stored in the command queue 121, computational operations of the memory device 110, including computational logic circuitry, can be executed efficiently. Furthermore, while computational operations are being performed on some storage rows 400 of the shared data channel, write or read operations on other storage rows can be performed simultaneously, thereby avoiding or reducing latency in write or read operations caused by providing computational functionality.

[0073] Figure 4 and Figure 5 It is shown Figure 3 A diagram illustrating an example of the operating scheme of the memory system 100 shown.

[0074] Reference Figure 4 The memory controller 120 can check the type, order, and number of commands stored in the command queue 121. The first command CMDa and the second command CMDb can be stored in the command queue for the first storage row 410. The first command CMDa and the second command CMDb can be stored in the command queue for the second storage row 420.

[0075] The 400-wait commands for each memory row can be divided into a first command CMDa that requires logic circuit calculations and a second command CMDb that does not require logic circuit calculations. The number of 400-wait commands for each memory row can be three or more.

[0076] Since the number of second command CMDb stored in command queue 121 is greater than 0 (command queue 121 stores at least one second command CMDb), memory controller 120 can set at least one storage queue 400 among multiple storage queues 400 of the shared data channel to perform operations based on the second command CMDb.

[0077] For example, the memory controller 120 can configure the second memory row 420 to operate according to the second command CMDb during a preset operation period. During the preset operation period, the memory controller 120 can configure the first memory row 410, which shares a data channel with the second memory row 420, to operate according to the first command CMDa.

[0078] During a preset operation period, the second storage row 420 may operate according to the second command CMDb during at least a portion of the time period during which the first storage row 410 operates according to the first command CMDa.

[0079] Since the first storage row 410 operates according to the first command CMDa, the first computational logic circuits 312a, 312b, ..., 312k included in the first storage banks 310a, 310b, ..., 310k of the first storage row 410 can operate. Since the second storage row 420 operates according to the second command CMDb, the second computational logic circuits 322a, 322b, ..., 322k included in the second storage banks 320a, 320b, ..., 320k of the second storage row 420 can be left inactive. Data can be written to at least a portion of the second memory cell arrays 321a, 321b, ..., 321k included in the second storage banks 320a, 320b, ..., 320k, or a read operation on the written data can be performed.

[0080] During the period when the storage row 400 performs computational functions, write or read operations are performed on the storage row 400, which shares a data channel with the storage row 400. Therefore, performance degradation of data write or read operations due to the performance of computational functions can be prevented.

[0081] The memory controller 120 can set the operating status of each memory row 400 in each cycle corresponding to the length of a preset operating period.

[0082] For example, refer to Figure 5 ,exist Figure 4 After the operation period shown ends, the memory controller 120 can set the operation of the first memory row 410 and the second memory row 420 in the next operation period.

[0083] When computational operations on the first storage row 410 and general memory operations on the second storage row 420 are completed, the memory controller 120 can set the operations of the first storage row 410 and the second storage row 420 based on commands stored in the command queue 121.

[0084] The memory controller 120 can control at least a portion of the first memory banks 310a, 310b, ..., 310k included in the first memory bank 410 to operate according to the second command CMDb. The first computational logic circuits 312a, 312b, ..., 312k included in the first memory banks 310a, 310b, ..., 310k may not be operated. Data can be written to the first memory cell arrays 311a, 311b, ..., 311k included in the first memory banks 310a, 310b, ..., 310k, or read operations can be performed on the written data.

[0085] The memory controller 120 can control at least a portion of the second memory banks 320a, 320b, ..., 320k included in the second memory bank 420 to operate according to the first command CMDa. The second computing logic circuits 322a, 322b, ..., 322k included in the second memory banks 320a, 320b, ..., 320k can operate.

[0086] When reading data written to the second memory cell array 321a, 321b, ..., 321k, calculations can be performed by the second computing logic circuits 322a, 322b, ..., 322k, and the data calculated by the second computing logic circuits 322a, 322b, ..., 322k can be written to the second memory cell array 321a, 321b, ..., 321k.

[0087] During at least a portion of the time period during which the second storage row 420 performs computational operations in the first storage row 410 and the second storage row 420 of the shared data channel, the first storage row 410 may perform general memory operations.

[0088] The memory row 400, which includes computational logic circuitry, can provide computational functionality. Simultaneously, since general memory operations are performed by the memory row 400, which does not perform computational operations, delays in general memory operations due to computational operations are prevented. The memory row 400 performing computational operations may use the data path to a relatively low extent. Since the data path is used by the memory row 400 performing general memory operations, the efficiency of data path utilization can be improved.

[0089] Figure 6 and Figure 7 It is shown Figure 3 A diagram illustrating an example of the operating timing of the memory system 100 shown.

[0090] Reference Figure 6 The memory banks included in the multiple memory devices 110 of the memory system 100 can form multiple memory rows 400. N memory rows 400 among the multiple memory rows 400 included in the memory system 100 can share a data channel.

[0091] The memory controller 120 can schedule the operating modes of N memory rows 400 sharing a data channel based on commands waiting for each memory row 400.

[0092] For example, the memory controller 120 can select a memory row 400 from N memory rows 400 to perform a computational operation. The memory row 400 performing the computational operation can be referred to as the memory row 400 operating in a first operating mode. The memory controller 120 can also select a memory row 400 from the N memory rows 400 to perform a general memory operation. The memory row 400 performing the general memory operation can be referred to as the memory row 400 operating in a second operating mode.

[0093] Reference Figure 6 In Example 1, during the first time period P1, the memory controller 120 can configure memory rows #1 to #N-1 of the N memory rows 400 to operate according to a first operating mode. The computational logic circuits included in memory rows #1 to #N-1 can operate. Computational functions can be performed through memory rows #1 to #N-1.

[0094] During the first time period P1, the memory controller 120 can configure memory row #N 400 out of the N memory rows 400 to operate according to the second operating mode. The computational logic circuitry included in memory row #N 400 may not be operated. General memory operations can be performed through memory row #N 400.

[0095] The memory controller 120 can send and receive a second command CMDb of a second operating mode, as well as data based on the second command CMDb, during periods other than the period during which the first command CMDa of the first operating mode is sent via a data channel shared by the N memory rows 400. For example, during each period, the memory controller 120 can send the first command CMDa to the corresponding memory row 400 via the data channel, and then send and receive the second command CMDb and data based on the second command CMDb.

[0096] When the second command CMDb is included in the command waiting for #N memory row 400, the memory controller 120 can control #N memory row 400 to perform general memory operations. Additionally, when the wait time for the second command CMDb waiting for #N memory row 400 among the second commands CMDb waiting for each memory row 400 is the longest, the memory controller 120 can control #N memory row 400 to operate according to the second command CMDb.

[0097] The memory controller 120 can configure the memory row 400 to operate in each cycle according to a first operating mode and a second operating mode.

[0098] The memory controller 120 can set the operating mode of each memory row 400 in the second time period P2 following the first time period P1. In response to a wait command for each memory row 400 during the first time period P1, the memory controller 120 can set the operating mode of the memory row 400 in the second time period P2.

[0099] During the second time period P2, the memory controller 120 can configure memory rows #1 to #N-2 and memory row #N 400 to operate according to a first operating mode. The computational logic circuits included in memory rows #1 to #N-2 and memory row #N 400 can operate and perform computational functions.

[0100] During the second time period P2, the memory controller 120 can configure memory row #N-1 400 to operate according to a second operating mode. The computational logic circuitry included in memory row #N-1 400 may not operate. General memory operations can be performed via memory row #N-1 400.

[0101] At least one of the storage rows 400 that operated according to the first command CMDa during the first time period P1 can operate according to the second command CMDb during the second time period P2. The storage row 400 that operates according to the second command CMDb during the second time period P2 can be different from the storage row 400 that operated according to the second command CMDb during the first time period P1.

[0102] In response to commands for waiting for each memory row 400 during the second time period P2, the memory controller 120 can set the operating mode of each memory row 400 during the third time period P3.

[0103] When the number of second commands (CMDb) waiting for each memory row 400 during the second time period P2 is 0, the memory controller 120 can control all N memory rows 400 sharing the data channel to operate according to the first operating mode during the third time period P3. During the third time period P3, computational operations can be performed through the N memory rows 400. In response to the commands waiting for each memory row 400, the memory controller 120 can set the operating mode of each memory row 400 in the next cycle.

[0104] In some implementations, the memory controller 120 can control multiple memory rows 400 to operate in a second operating mode during each time period.

[0105] For example, refer to Figure 6 In Example 2, during the first time period P1, storage rows 400 #1 to #N-1 can operate according to the first operating mode. During the first time period P1, storage row 400 #N can operate according to the second operating mode.

[0106] During the second period P2 following the first period P1, storage row #N 400 can operate according to the first operating mode. During the second period P2, storage rows #1 to #N-1 400 can operate according to the second operating mode.

[0107] When the number of first commands (CMDa) waiting for each memory row 400 is small, or the number of second commands (CMDb) waiting for each memory row 400 is large, the memory controller 120 can control at least two memory rows 400 to operate according to the second operating mode. The memory controller 120 can control the memory row 400 with the longest waiting time for the second command (CMDb) among memory rows #1 to #N-1 to execute the operation according to the second command (CMDb). Optionally, the memory controller 120 can control at least two memory rows 400 among memory rows #1 to #N-1 to perform general memory operations during the time-sharing period of the second time period P2.

[0108] The memory controller 120 can schedule the operating modes of the memory rows 400 based on the shared state of the data channels and the waiting commands, and can set the operating mode of each memory row 400 based on the type, state, and waiting time of the waiting commands. For example, if the waiting time of the first command CMDa, which requires the calculation of logic circuit operations, exceeds a preset threshold time (e.g., equivalent to two cycles), the memory controller 120 can control all memory rows 400 to process the first command CMDa even if a second command CMDb exists in the command queue 121.

[0109] In this way, the memory controller 120 can efficiently control the operation of the memory rows, including the computational logic circuitry, based on the commands awaited for each memory row 400, and can control the refresh operation of each memory row 400 based on the operating mode.

[0110] For example, refer to Figure 7 In Example 1, among the N storage rows 400 of the shared data channel, the memory controller 120 can configure a storage row 400 to operate in a first operating mode and a storage row 400 to operate in a second operating mode.

[0111] The memory controller 120 can control the execution of a refresh operation on the memory row 400 operating in a second operating mode in each cycle. For example, during a first time period P1, the #N memory row 400 can operate according to the second operating mode, and a refresh operation can be performed on the memory banks included in the #N memory row 400 during a portion of the first time period P1. Even when the memory system 100 includes memory banks that perform computational operations by computational logic circuitry, the refresh operation can be performed during periods when general memory operations (such as write or read operations) are performed.

[0112] For example, refer to Figure 7 In Example 2, within each cycle, the memory controller 120 can control the execution of refresh operations on the memory row 400 operating in the first operating mode. When a computation operation through the memory row 400 operating in the first operating mode is completed, the memory controller 120 can control the execution of refresh operations on all memory banks included in the corresponding memory row 400. The computation operation and the refresh operation can be executed consecutively.

[0113] In some implementations, refresh operations can be performed simultaneously on storage row 400 operating in a first operating mode and storage row 400 operating in a second operating mode.

[0114] In addition, in some implementations, the length of the period during which the refresh operation is performed can be variably adjusted.

[0115] For example, refer to Figure 7 In Example 3, during the first time period P1, N-1 memory rows 400 can operate according to a first operating mode, and one memory row 400 can operate according to a second operating mode. In response to a command waiting for each memory row 400 during the first time period P1, the memory controller 120 can set the operating mode of each memory row 400 in the second time period P2.

[0116] The memory controller 120 can control the execution of refresh operations on each memory row 400 during the second time period P2. The memory controller 120 can configure the refresh operation to be performed after the completion of a computational operation or general memory operation on each memory row 400. The memory controller 120 can configure the length of the second time period P2 for performing the refresh operation to be different from the length of the first time period P1. The length of the second time period P2 can be longer than the length of the first time period P1. By increasing the length of the time period for performing the refresh operation, the memory controller 120 can control the refresh operation to be performed after the completion of a computational operation or general memory operation on each memory row 400.

[0117] The memory controller 120 can control the operating mode or refresh operation execution method of each memory row 400 of the shared data channel based on commands awaited for each memory row 400, and can independently control the operation of the memory row 400 of each data channel.

[0118] Figure 8 This is a diagram illustrating an example of an operation scheme for a memory system 100 based on some embodiments of the disclosed technology.

[0119] Reference Figure 8 The memory system 100 may include a first memory row 410 and a second memory row 420 sharing a first data channel. The memory system 100 may also include a third memory row 430 and a fourth memory row 440 sharing a second data channel.

[0120] The memory controller 120 can control the operating modes of the first memory row 410 and the second memory row 420 based on commands awaited for the first memory row 410 and the second memory row 420 sharing the first data channel. The memory controller 120 can control the operating modes of the third memory row 430 and the fourth memory row 440 sharing the second data channel based on commands awaited for the third memory row 430 and the fourth memory row 440.

[0121] For example, the memory controller 120 can control the first memory row 410 and the fourth memory row 440 to operate according to a first operating mode during the same operating period. Computational operations can be performed while the computational logic circuitry included in the first memory row 410 and the fourth memory row 440 is operating.

[0122] During the period when the first memory row 410 and the fourth memory row 440 operate according to the first operating mode, the memory controller 120 can control the second memory row 420 and the third memory row 430 to operate according to the second operating mode. The computational logic circuitry included in the second memory row 420 and the third memory row 430 may not operate. General memory operations can be performed through the second memory row 420 and the third memory row 430.

[0123] Optionally, during the same operation period, when the first storage row 410 and the second storage row 420 share the first data channel, the memory controller 120 can control the first storage row 410 to operate according to the first operation mode and control the second storage row 420 to operate according to the second operation mode. During the corresponding period, the memory controller 120 can control the third storage row 430 and the fourth storage row 440, which share the second data channel, to operate according to the first operation mode.

[0124] Based on the status of the command waiting for each data channel, the memory controller 120 can set the operating mode of each of the multiple memory rows 400 that share each data channel in each cycle, thereby improving the efficiency of computational operations and general memory operations.

[0125] Even when the type and connection structure of the memory devices 110 included in the memory system 100 are implemented in various ways, the memory controller 120 can control the operating mode of each memory row 400 in each cycle based on the waiting command of each memory row 400.

[0126] Figure 9A , Figure 9B and Figure 10 This is a diagram illustrating examples of operating schemes for various types of memory systems 100 based on some embodiments of the disclosed technology.

[0127] Reference Figure 9A Examples are shown of memory system 100 including memory rows 400 with computing logic circuitry and memory rows 400 without computing logic circuitry.

[0128] For example, the first memory row 410, the second memory row 420, the third memory row 430, and the fourth memory row 440 can share a first data channel. The first memory row 410 may include a first memory cell array 311 and a first computational logic circuit 312. The second memory row 420 may include a second memory cell array 321 and a second computational logic circuit 322. The third memory row 430 may include a third memory cell array 331 and a third computational logic circuit 332. The fourth memory row 440 may include a fourth memory cell array 341. The fourth memory row 440 may not include computational logic circuitry.

[0129] The storage row 400 sharing the first data channel may include storage rows 400 that include computing logic circuitry and storage rows 400 that do not include computing logic circuitry. The number of storage rows 400 that include computing logic circuitry and the number of storage rows 400 that do not include computing logic circuitry may be different from each other.

[0130] For example, among the memory rows 400 sharing the first data channel, the number of memory rows 400 including computational logic circuits can be greater than the number of memory rows 400 not including computational logic circuits. In some embodiments, the number of memory rows 400 including computational logic circuits can be less than the number of memory rows 400 not including computational logic circuits.

[0131] Based on commands for waiting for storage row 400 sharing the first data channel, memory controller 120 can set the operating mode of each storage row 400 during each operating period.

[0132] For example, such as Figure 9A As shown, the first storage row 410, the second storage row 420, and the third storage row 430 can operate according to the first operating mode. The fourth storage row 440 can operate according to the second operating mode.

[0133] The memory controller 120 can control at least one of the memory rows 400, including computing logic circuitry, to operate according to a second operating mode.

[0134] For example, refer to Figure 9B The first storage row 410 and the third storage row 430 can operate according to the first operating mode. During the corresponding time period, the second storage row 420 can operate according to the second operating mode. Since the second storage row 420 operates according to the second operating mode, the fourth storage row 440 can remain inactive during the corresponding time period.

[0135] During periods when the first storage row 410, second storage row 420, and third storage row 430 sharing the first data channel are not operating in the second operating mode, the fourth storage row 440 may operate in the second operating mode. During periods when at least one of the first storage row 410, second storage row 420, and third storage row 430 sharing the first data channel is operating in the second operating mode, the fourth storage row 440 may be idle. In some embodiments, during periods when at least one of the first storage row 410, second storage row 420, and third storage row 430 is operating in the second operating mode, the fourth storage row 440 may perform a refresh operation.

[0136] Memory devices 110 including computational logic circuitry and memory devices 110 excluding computational logic circuitry can constitute memory system 100, thereby improving the operational performance of memory system 100 while efficiently controlling computational operations and general memory operations. Even in this case, the operational performance of memory system 100 can be improved by reducing the latency of computational operations and general memory operations through scheduling by memory controller 120.

[0137] Scheduling control based on commands waiting for each memory row 400 can be applied to various types of memory systems 100, and can also be applied to situations such as stacking multiple memory devices 100 to form a memory row 400.

[0138] For example, refer to Figure 10 Multiple memory devices 111, 112, 113, and 114 can be stacked on substrate 600. Substrate 600 may include, for example, silicon, and may further include an intermediate substrate to facilitate wiring connections between substrate 600 and memory device 110. This intermediate substrate may be referred to as an interposer.

[0139] A memory controller 120 may be disposed on a substrate 600. Multiple memory devices 110 may be stacked on a base die 500. The base die 500 may be referred to as a logic circuit die, in which various circuits for the operation of the memory devices 110 may be disposed. The base die 500 may be controlled according to commands from the memory controller 120, and the memory devices 110 on the base die 500 may be operated.

[0140] The first memory device 111, the second memory device 112, the third memory device 113, and the fourth memory device 114 can be stacked on the die 500.

[0141] The memory cells included in the first memory device 111, the second memory device 112, the third memory device 113, and the fourth memory device 114 can be configured in various ways to form a memory row 400.

[0142] In some implementation schemes, such as Figure 10 As shown in Example 1, the first group of the first memory device 111, the first group of the second memory device 112, the first group of the third memory device 113, and the first group of the fourth memory device 114 can constitute a first memory row 410. The second group of the first memory device 111, the second group of the second memory device 112, the second group of the third memory device 113, and the second group of the fourth memory device 114 can constitute a second memory row 420.

[0143] During at least a portion of the time period during which the first storage row 410 operates according to the first operating mode, the second storage row 420 may operate according to the second operating mode.

[0144] In some implementation schemes, such as Figure 10As shown in Example 2, at least a portion of the first memory device 111 and at least a portion of the second memory device 112 can constitute a first memory row 410. At least a portion of the third memory device 113 and at least a portion of the fourth memory device 114 can constitute a second memory row 420. During a period when the first memory row 410 operates in a first operating mode, the second memory row 420 can operate in a second operating mode.

[0145] In some implementations, the first storage row 410 and the second storage row 420 can be configured in various ways according to the data channel connection structure. During at least a portion of the time when some storage rows or a portion of the storage rows sharing a data channel perform computational operations, the remaining storage rows can perform general memory operations. In this way, latency in the general memory operations of the memory system 100 can be prevented or reduced while still providing computational functionality within the memory system 100.

[0146] A memory device according to an embodiment of the present disclosure may include: a first storage row of the memory including a plurality of first storage banks of the memory, each first storage bank including a first memory cell array and a first computational logic circuit that performs computation using the first memory cell array; and a second storage row including a plurality of second storage banks, each second storage bank including a second memory cell array and a second computational logic circuit that performs computation using the second memory cell array, wherein the first storage row and the second storage row share a data channel, and during a first time period of operation of the first computational logic circuit included in the first storage row, programming operations or reading operations on the second memory cell array are performed without using the second computational logic circuit included in the second storage row.

[0147] During the second time period following the first time period, at least one of the first computational logic circuits included in the first storage row or the second computational logic circuits included in the second storage row can operate.

[0148] During the second time period following the first time period, programming or reading operations can be performed on the first memory cell array included in the first memory row.

[0149] During the second time period, the second computational logic circuitry included in the second storage row can operate.

[0150] After the calculation of the first computational logic circuit is completed, a refresh operation on the first memory row can be performed.

[0151] After programming or reading operations on the second storage row are completed, a refresh operation on the second storage row can be performed.

[0152] During the second period following the first period, refresh operations can be performed on the first and second storage rows, wherein the length of the second period is different from the length of the first period.

[0153] After sending a command instructing the first computing logic circuit to perform calculations via the data channel, a command instructing programming or reading operations on the second memory cell array can be sent.

[0154] The memory device may further include: a third memory row including a plurality of third memory banks, each third memory bank including a third memory cell array and a third computational logic circuit that performs computation using the third memory cell array; and a fourth memory row including a plurality of fourth memory banks, each fourth memory bank including a fourth memory cell array and a fourth computational logic circuit that performs computation using the fourth memory cell array, the fourth memory row sharing a data channel with the third memory row, wherein, during a first time period, the third computational logic circuit included in the third memory row and the fourth computational logic circuit included in the fourth memory row operate.

[0155] During the second time period following the first time period, the first and second computational logic circuits can operate, and one of the third and fourth computational logic circuits can operate while the other can remain inactive.

[0156] A memory device according to an embodiment of the present disclosure may include: a first memory chip including a plurality of first memory banks, each first memory bank including a first memory cell array and a first computational logic circuit that performs computation using the first memory cell array; and a second memory chip including a plurality of second memory banks, each second memory bank including a second memory cell array and a second computational logic circuit that performs computation using the second memory cell array, wherein, during a first time period, the first computational logic circuit included in a first group of the plurality of first memory banks and the second computational logic circuit included in a first group of the plurality of second memory banks operate, while the first computational logic circuit included in a second group of the plurality of first memory banks and the second computational logic circuit included in a second group of the plurality of second memory banks do not operate.

[0157] During the first time period, programming or reading operations can be performed on the second group of multiple first storage units or at least a portion of the second group of multiple second storage units.

[0158] During the second period following the first period, the first computational logic circuit included in the second group of the plurality of first memory banks and the second computational logic circuit included in the second group of the plurality of second memory banks can operate; during the second period, the first computational logic circuit included in the first group of the plurality of first memory banks and the second computational logic circuit included in the first group of the plurality of second memory banks can not operate.

[0159] During the first time period, refresh operations can be performed on the first group of multiple first storage banks and the first group of multiple second storage banks.

[0160] During a third time period following the second time period, a refresh operation may be performed on at least a portion of the plurality of first storage units or at least a portion of the plurality of second storage units, wherein the length of the third time period is different from the length of the second time period.

[0161] The time period for sending commands for the first group of multiple first memory banks and the first group of multiple second memory banks may be different from the time period for sending commands for the second group of multiple first memory banks and the second group of multiple second memory banks.

[0162] A first group of multiple first memory banks and a first group of multiple second memory banks may be included in a first memory row, and a second group of multiple first memory banks and a second group of multiple second memory banks may be included in a second memory row.

[0163] The first and second storage rows can share a data channel.

[0164] The first memory chip and the second memory chip can be stacked.

[0165] A memory device according to an embodiment of the present disclosure may include: a first memory chip including a plurality of first memory banks, each first memory bank including a first memory cell array and a first computational logic circuit that performs computation using the first memory cell array; and a second memory chip including a plurality of second memory banks, each second memory bank including a second memory cell array, wherein, during at least a portion of a first time period during which the first computational logic circuit included in a first group of the plurality of first memory banks operates, a programming operation or a reading operation is performed on the first group of the plurality of second memory banks.

[0166] During the second period following the first period, programming or reading operations can be performed on the first group of multiple first storage banks, and the first group of multiple second storage banks can be in an idle state.

[0167] During at least a portion of the time period during which the first computational logic circuitry included in the first group of the plurality of first memory banks is not in operation, the first group of the plurality of second memory banks may be in an idle state.

[0168] The first group of multiple first storage banks can share a data channel with the first group of multiple second storage banks.

[0169] During the first time period, programming or reading operations can be performed on the second group of multiple first storage units.

[0170] The second group of multiple first storage units may not share a data channel with the first group of multiple first storage units and the first group of multiple second storage units.

[0171] During the first time period, a refresh operation can be performed on the first group of multiple first storage banks.

[0172] During the second period following the first period, a refresh operation can be performed on the first group of multiple first storage units or the first group of multiple second storage units, and the length of the second period can be different from the length of the first period.

[0173] During the first time period, the time period for receiving commands for the first group of multiple first memory banks may be different from the time period for receiving commands for the first group of multiple second memory banks.

[0174] Only a few embodiments and examples have been described. Enhancements and modifications can be made to the disclosed embodiments and other embodiments based on the content described and illustrated in this patent document.

Claims

1. A memory system, comprising: A memory device includes a plurality of memory rows, each of the plurality of memory rows including one or more memory banks, the one or more memory banks including a memory cell array of memory cells for storing data and computational logic circuitry for performing data processing; as well as A memory controller controls the operation of the plurality of memory rows based on commands in a command queue for each of the plurality of memory rows, wherein, during at least a portion of a first time period in which P of the N memory rows of the shared data channel operate in response to a first command, at least one of the NP memory rows performs an operation in response to a second command without utilizing the computational logic circuitry, where N is an integer satisfying N≥2 and P is an integer satisfying N>P≥1.

2. The memory system of claim 1, wherein, When at least one second command exists in the command queue for at least one of the N memory rows before the first time period, the memory controller controls at least one of the N memory rows to operate in response to the second command during at least a portion of the first time period.

3. The memory system of claim 1, wherein, When there is no second command in the command queue for the N storage rows, the memory controller controls all N storage rows to operate in response to the first command during a second time period following the first time period.

4. The memory system of claim 1, wherein, The memory controller controls Q of the N memory rows to operate in response to the first command during a second time period following the first time period, and controls at least one of the NQ memory rows to operate in response to the second command during at least a portion of the second time period, where Q is an integer satisfying N>Q≥1.

5. The memory system of claim 4, wherein, The storage queue that operates in response to the second command during the second time period is different from the storage queue that operates in response to the second command during the first time period.

6. The memory system of claim 4, wherein, At least one of the P storage rows that operated in response to the first command during the first time period operated in response to the second command during the second time period.

7. The memory system of claim 1, wherein, In each cycle based on the length of the first time period, the memory controller allocates the memory row that performs an operation in response to the first command and the memory row that performs an operation in response to the second command from among the N memory rows.

8. The memory system of claim 1, wherein, The memory controller allocates a memory row to operate in response to the first command based on the waiting time of the first command waiting in the command queue for each of the N memory rows.

9. The memory system of claim 1, wherein, The memory controller performs a refresh operation on at least one of the memory rows that operated in response to the second command during the first time period.

10. The memory system of claim 1, wherein, When the operation of the memory row that was operated in response to the first command during the first time period is completed, the memory controller performs a refresh operation on all memory rows that were operated in response to the first command.

11. The memory system of claim 1, wherein, The memory controller performs a refresh operation on at least a portion of the N memory rows during a second time period following the first time period, the length of the second time period being different from the length of the first time period.

12. The memory system according to claim 1, wherein, The memory controller sends the first command to the P memory rows that operate in response to the first command during the first time period, and then sends the second command to at least one of the NP memory rows.

13. The memory system according to claim 1, wherein, During the first time period, excluding the time period in which the first command is sent through the data channel shared by the N storage rows, the second command and data are sent and received in response to the second command.

14. The memory system according to claim 1, wherein, During the first time period, for the first storage row and the second storage row that share the first data channel, the first storage row operates in response to the first command, and the second storage row operates in response to the second command; and During the first time period, the third and fourth storage rows that share the second data channel operate in response to the first command.

15. The memory system according to claim 1, wherein, The operation in response to the first command includes the operation of the computational logic circuit.

16. A memory controller, comprising: At least one command queue stores a first command and a second command for each of a plurality of storage rows, wherein each storage row includes one or more storage banks, and each storage bank includes one or more memory cell arrays of memory cells storing data; and Scheduler: Based on the number of first commands and the number of second commands, schedules commands to be executed by each of the plurality of storage queues during a preset operation period; and, when at least one second command exists, schedules operations to be executed by another portion of the plurality of storage queues in response to the second command while an operation in response to the first command is being performed by a portion of the plurality of storage queues.

17. The memory controller of claim 16, wherein, Based on the number of first commands and the number of second commands stored in the at least one command queue during the first time period, the scheduler allocates storage queues that operate in response to the first commands and storage queues that operate in response to the second commands during a second time period following the first time period.

18. The memory controller of claim 16, wherein, The scheduler allocates a first group of the plurality of storage rows to operate in response to the first command during a first time period, and allocates at least one storage row included in the first group to operate in response to the second command during a second time period following the first time period.

19. The memory controller of claim 18, wherein, The scheduler allocates a second group of the plurality of storage rows to operate in response to the second command during the first time period, wherein the storage rows included in the second group do not share data channels with each other.

20. The memory controller of claim 16, wherein, At least one of the plurality of storage rows that performs an operation in response to the first command shares a data channel with at least one of the storage rows that performs an operation in response to the second command.

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