Method for optimizing computing unit area of fused multiply in single-precision floating-point multiplier-adder
By merging the multiplication module and the multiply-accumulate module in single-precision floating-point calculations, and reusing the logic of the multiply-accumulate module to complete the multiplication operation, the problem of excessive hardware area and power consumption is solved, and the area and cost are reduced.
CN122308779APending Publication Date: 2026-06-30HEFEI JUNZHENG TECH CO LTD
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- HEFEI JUNZHENG TECH CO LTD
- Filing Date
- 2024-12-27
- Publication Date
- 2026-06-30
AI Technical Summary
Technical Problem
In existing single-precision floating-point calculations, the multiplication module and the multiply-accumulate module are designed separately, which makes it impossible to reuse logic, increases hardware area and power consumption, and cannot effectively reduce area overhead while ensuring performance.
Method used
The multiplication module and the multiply-add module are merged into a single module, and the logic in the multiply-add module is reused to complete the multiplication operation, thereby reducing the hardware design area.
Benefits of technology
While maintaining basic performance, the hardware design area and power consumption were reduced by reusing the multiply-accumulate module logic, thus lowering the cost.
✦ Generated by Eureka AI based on patent content.
Smart Images
Figure CN122308779A_ABST
Abstract
This invention provides a method for optimizing the area of the computational unit in a single-precision floating-point multiplier-accumulator that integrates multiplication. During the single-precision floating-point multiplication calculation, existing logic is used to perform functions at each pipeline stage: P0 stage (first pipeline stage): performs multiplication, leading zero statistics, and special value judgment; P1 stage (second pipeline stage): adjusts only for data with product exponent less than 0 and overflow during mantissa multiplication; P2 stage (third pipeline stage): performs post-regulation, rounding, final result processing, and final exception state judgment. In the multiplication instruction implementation, while ensuring basic performance, the multiplication module and the multiply-accumulator module are integrated into the same module, ensuring that the same logic module can be reused, thereby reducing area overhead.
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