Hardware circuit for floating point arctangent function

Abstract

The application provides a hardware circuit of a floating point inverse tangent function, and belongs to the field of integrated circuits and electronic technology.The hardware circuit of the floating point inverse tangent function comprises: a preprocessing module, which is used for converting an input non-exception floating point number format tangent value into a corresponding fixed point number format tangent value; an operation module, which is used for solving a corresponding fixed point number format angle value through binary shift and addition and subtraction operation according to the fixed point number format tangent value output by the preprocessing module; and a post-processing module, which is used for performing leading zero detection and data format conversion on the fixed point number format angle value output by the operation module to obtain a floating point number format angle value.The operation module at least comprises an adder, and the adder comprises a logic gate circuit composed of PMOS transistors and single electron transistors.The application can be better applied to a resource-limited and power-sensitive environment, the hardware structure of the circuit is simplified while the operation performance is ensured, and miniaturization and low power consumption are better realized.

Description

Technical Field

[0001] This application relates to the fields of integrated circuits and electronic technology, and in particular to a hardware circuit for a floating-point arctangent function. Background Technology

[0002] The arctangent function circuit is a nonlinear computational hardware circuit used to realize the arctangent mapping relationship between input and output signals. In future-oriented applications, such as integrated sensing and computing smart sensors, robot navigation, quantum computing interfaces, and wireless communication systems, this circuit is widely used for angle calculation, signal demodulation, and motion control. In industrial manufacturing, such as the automated production and deformation monitoring of precast highway beams, this circuit can also be used to analyze sensor angle data in real time, ensuring precise control of component posture and structural safety. With the rapid development of IoT, edge computing, and artificial intelligence technologies, the market demand for low-power, high-performance, and miniaturized hardware architectures is becoming increasingly urgent.

[0003] Currently, the implementation of nonlinear mathematical operations using software algorithms is relatively mature, but it typically relies on an operating system environment. Even with lightweight custom systems like TinyOS, they still need to be deployed on corresponding microprocessor hardware, introducing additional cost, size, and power consumption. If complex nonlinear computation tasks are migrated to servers or the cloud to control terminal hardware costs, the terminal devices need to continuously upload data. This not only increases the overhead and transmission load of communication modules and brings additional communication power consumption, but also exposes local data privacy to potential risks. In industrial environments such as precast beam production sites, deploying real-time monitoring and control systems that rely on remote servers also suffers from high transmission latency and poor network reliability, making it difficult to meet the stringent requirements for response speed and stability in key process stages.

[0004] Existing mathematical algorithms for implementing arctangent function circuits mainly fall into three categories: lookup table method, piecewise nonlinear method, and Taylor polynomial approximation method. Lookup tables are only suitable for applications with fixed input and low computational load. Taylor polynomial approximation and piecewise nonlinear methods employ numerous multipliers in their hardware implementations. On the one hand, multipliers limit the portability of the design and are unsuitable for hardware carriers containing only basic logic gates. On the other hand, multipliers have high dynamic power consumption; in power-sensitive applications, such as implantable medical sensor nodes or long-term embedded engineering monitoring equipment, using multipliers significantly shortens the node's lifespan.

[0005] Therefore, there is an urgent need for a technical solution that can better suit resource-constrained and power-sensitive environments to realize arctangent function circuits. Summary of the Invention

[0006] This application provides a hardware circuit for a floating-point arctangent function, which is better suited for resource-constrained and power-sensitive environments. It simplifies the hardware structure while maintaining good computational performance, facilitating miniaturization and low power consumption. The technical solution includes at least the following: On one hand, a hardware circuit for a floating-point arctangent function is provided, comprising: a preprocessing module for converting an input, error-free floating-point tangent value into a corresponding fixed-point tangent value; an arithmetic module, the input of which is connected to the output of the preprocessing module, for obtaining a corresponding fixed-point angle value by binary shifting and addition / subtraction operations based on the fixed-point tangent value output by the preprocessing module; and a post-processing module, the input of which is connected to the output of the arithmetic module, for performing leading zero detection and data format conversion on the fixed-point angle value output by the arithmetic module to obtain a floating-point angle value; wherein the arithmetic module includes at least an adder, the adder comprising a logic gate circuit composed of a P-type metal-oxide-semiconductor (PMOS) transistor and a single-electron transistor (SET).

[0007] Optionally, the calculation module is used to treat the fixed-point tangent value output by the preprocessing module as a value from the origin to ( , The initial vector of is obtained by rotating it multiple times. , Rotate to approximate the target vector on the x-axis. (0), the angle of each rotation is accumulated to obtain the fixed-point number format angle value corresponding to the tangent value of the fixed-point number format, where, and Let x and y represent the x and y coordinates of the initial vector, respectively. The x-coordinate of the target vector is represented.

[0008] Optionally, the calculation module performs iterative calculations for multiple rotations using the following formula:

[0009]

[0010] Where i = 0, 1, ..., N-1, and N is the total number of iterations. This is the x-coordinate variable stored after the (i+1)th iteration. This is the ordinate variable stored after the (i+1)th iteration. This is the variable containing the accumulated rotation angle value after the (i+1)th iteration. This is the x-coordinate variable stored after the i-th iteration. This is the ordinate variable stored after the i-th iteration. This is the accumulated rotation angle value stored after the i-th iteration. =0, As the rotation direction determination factor, when The time indicates that the rotation direction is counterclockwise. The time indicates that the rotation direction is clockwise. Let be the angle of the i-th rotation.

[0011] Optionally, the adder is used to calculate the generation signal and propagation signal of each data bit in parallel based on the addend and the augend; calculate the carry signal of each data bit based on the generation signal and the propagation signal of each data bit; and calculate the sum signal based on the propagation signal and the carry signal of each data bit.

[0012] Optionally, the logic gate circuit includes AND gate circuit, OR gate circuit, and XOR gate circuit. The AND gate circuit, OR gate circuit, and XOR gate circuit are all composed of a variety of preset circuit modules. The preset circuit modules include a two-input PMOS series module, a two-input PMOS parallel module, a PMOS-SET series module, a two-input SET series module, and a two-input SET parallel module.

[0013] Optionally, the two-input PMOS series module includes two PMOS transistors connected in series, wherein the source of the first PMOS transistor is connected to the power supply terminal V. DD The substrate of the first PMOS transistor is connected to its source, and the source of the second PMOS transistor is connected to its drain. The substrate of the second PMOS transistor is also connected to its source. The gate of the first PMOS transistor is the first input terminal of the two-input PMOS series module, and the gate of the second PMOS transistor is the second input terminal. The drain of the second PMOS transistor is the terminal of the two-input PMOS series module. The two-input PMOS parallel module includes two PMOS transistors connected in parallel, wherein the sources and substrates of the two PMOS transistors are interconnected and connected to the power supply terminal V. DDThe drains of the two PMOS transistors are interconnected and serve as the terminals of the two-input PMOS parallel module. The gates of the two PMOS transistors are the first and second input terminals of the two-input PMOS parallel module, respectively. The PMOS-SET series module includes a SET and a PMOS transistor connected in series. The source of the PMOS transistor serves as the first terminal of the PMOS-SET series module, and the substrate of the PMOS transistor is connected to the power supply terminal V. DD The gate of the PMOS transistor is connected to the gate of the SET and serves as the second terminal of the PMOS-SET series module. The drain of the PMOS transistor is connected to the source of the SET and serves as the third terminal of the PMOS-SET series module. The drain of the SET is grounded. The two-input SET series module includes two SETs connected in series. The drain of the first SET is connected to the source of the second SET, and the drain of the second SET is grounded. The gate of the first SET is the first input terminal of the two-input SET series module, and the gate of the second SET is the second input terminal of the two-input SET series module. The source of the first SET is the terminal of the two-input SET series module. The two-input SET parallel module includes two SETs connected in parallel. The sources of the two SETs are connected to each other and serve as the terminals of the two-input SET parallel module. The drains of the two SETs are connected to each other and grounded. The gates of the two SETs are the first input terminal and the second input terminal of the two-input SET parallel module, respectively.

[0014] Optionally, the AND gate circuit includes a two-input PMOS series module, a two-input SET parallel module, and a PMOS-SET series module. The terminals of the two-input PMOS series module are connected to the terminals of the two-input SET parallel module and to the second terminal of the PMOS-SET series module. The first input terminal of the two-input PMOS series module is connected to the first input terminal of the two-input SET parallel module and serves as the first input terminal of the AND gate circuit. The second input terminal of the two-input PMOS series module is connected to the second input terminal of the two-input SET parallel module and serves as the second input terminal of the AND gate circuit. The first terminal of the PMOS-SET series module is connected to the power supply terminal V. DD The third terminal of the PMOS-SET series module is the output terminal of the AND gate circuit.

[0015] Optionally, the OR gate circuit includes a two-input PMOS parallel module, a two-input SET series module, and a PMOS-SET series module. The terminals of the two-input PMOS parallel module are connected to the terminals of the two-input SET series module and to the second terminal of the PMOS-SET series module. The first input terminal of the two-input PMOS parallel module is connected to the first input terminal of the two-input SET series module and serves as the first input terminal of the OR gate circuit. The second input terminal of the two-input PMOS parallel module is connected to the second input terminal of the two-input SET series module and serves as the second input terminal of the OR gate circuit. The first terminal of the PMOS-SET series module is connected to the power supply terminal V. DD The third terminal of the PMOS-SET series module is the output terminal of the OR gate circuit.

[0016] Optionally, the XOR gate circuit includes a two-input PMOS series module, a two-input PMOS parallel module, a PMOS-SET series module, a two-input SET series module, and a two-input SET parallel module. The terminals of the two-input PMOS series module are connected to the terminals of the two-input SET parallel module and to the second terminal of the PMOS-SET series module. The terminals of the two-input PMOS parallel module are connected to the first terminal of the PMOS-SET series module. The terminals of the two-input SET series module are connected to the PMOS-SET... The third terminal of the series module is connected and serves as the output terminal of the XOR gate circuit. The first input terminals of the two-input PMOS series module, the two-input PMOS parallel module, the two-input SET parallel module, and the two-input SET series module are all interconnected and serve as the first input terminal of the XOR gate circuit. The second input terminals of the two-input PMOS series module, the two-input PMOS parallel module, the two-input SET parallel module, and the two-input SET series module are all interconnected and serve as the second input terminal of the XOR gate circuit.

[0017] Optionally, after performing 12 to 16 iterations, the calculation module outputs a fixed-point format angle value corresponding to the fixed-point format tangent value.

[0018] The beneficial effects of the technical solution provided in this application include at least the following: In this embodiment, the preprocessing module converts the input, error-free floating-point tangent value into the corresponding fixed-point tangent value. The arithmetic module, based on the fixed-point tangent value output by the preprocessing module, calculates the corresponding fixed-point angle value using binary shift and addition / subtraction operations. The post-processing module performs leading zero detection and data format conversion on the fixed-point angle value output by the arithmetic module to obtain the floating-point angle value. The arithmetic module includes at least an adder, which comprises logic gate circuits composed of PMOS transistors and single-electron transistors. That is, the hardware circuit of the floating-point arctangent function in this embodiment only requires shift and addition / subtraction operations during the calculation process without a multiplier. This effectively solves the high power consumption and portability limitations caused by multipliers, making it easier to implement and optimize, and thus better suited for resource-constrained and power-sensitive environments. Furthermore, SETs possess unique Coulomb blocking and Coulomb oscillation effects, exhibiting extremely low power consumption and ultra-small device size. SETs are highly compatible with Complementary Metal Oxide Semiconductor (CMOS) processes. By combining PMOS transistors and SETs to construct logic gate circuits to build adders in arithmetic modules, the inherent leakage current and power consumption bottleneck of CMOS processes can be effectively avoided compared to using all CMOS devices. The cooperation between PMOS transistors and SETs eliminates the need for complex control of the SET's background charge, reducing the complexity of background charge injection compared to using all SETs. This simplifies the hardware structure of the circuit while ensuring good computational performance, facilitating miniaturization and low power consumption. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a schematic diagram of the hardware circuit structure of a floating-point arctangent function provided in an embodiment of this application.

[0021] Figure 2 This is a schematic diagram of the rotational iteration process of the arctangent function, which implements the nonlinear mapping from tangent value to angle value, according to an embodiment of this application.

[0022] Figure 3 This is a schematic diagram illustrating the operational principle of the adder provided in the embodiments of this application.

[0023] Figure 4This is a schematic diagram of the circuit structure of a preset circuit module composed of PMOS transistors and SET provided in the embodiments of this application.

[0024] Figure 5 This is a schematic diagram of the logic symbol of a preset circuit module composed of PMOS transistors and SET provided in the embodiments of this application.

[0025] Figure 6 This is a schematic diagram of an AND gate circuit provided in an embodiment of this application.

[0026] Figure 7 This is a schematic diagram of an OR gate circuit provided in an embodiment of this application.

[0027] Figure 8 This is a schematic diagram of an XOR gate circuit provided in an embodiment of this application. Detailed Implementation

[0028] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. The terms “first,” “second,” “third,” and similar terms used in this patent application specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an” or “a” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “comprising” or “including” and similar terms mean that the elements or objects preceding “comprising” or “including” encompass the elements or objects listed following “comprising” or “including” and their equivalents, and do not exclude other elements or objects. The terms “connected” or “linked” and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0029] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0030] Figure 1 This is a schematic diagram of the hardware circuit structure of a floating-point arctangent function provided in an embodiment of this application. For example... Figure 1As shown, the hardware circuit of the floating-point arctangent function includes: a preprocessing module, used to convert the input, error-free floating-point tangent value into the corresponding fixed-point tangent value; an arithmetic module, whose input is connected to the output of the preprocessing module, used to obtain the corresponding fixed-point angle value through binary shift and addition / subtraction operations based on the fixed-point tangent value output by the preprocessing module; and a post-processing module, whose input is connected to the output of the arithmetic module, used to perform leading zero detection and data format conversion on the fixed-point angle value output by the arithmetic module to obtain the floating-point angle value. The arithmetic module includes at least an adder, which comprises logic gate circuits composed of PMOS transistors and single-electron transistors.

[0031] In this embodiment, the preprocessing module converts the input, error-free floating-point tangent value into the corresponding fixed-point tangent value. The arithmetic module, based on the fixed-point tangent value output by the preprocessing module, calculates the corresponding fixed-point angle value using binary shift and addition / subtraction operations. The post-processing module performs leading zero detection and data format conversion on the fixed-point angle value output by the arithmetic module to obtain the floating-point angle value. The arithmetic module includes at least an adder, which comprises logic gate circuits composed of PMOS transistors and single-electron transistors. That is, the hardware circuit of the floating-point arctangent function in this embodiment only requires shift and addition / subtraction operations during the calculation process without a multiplier. This effectively solves the high power consumption and portability limitations caused by multipliers, making it easier to implement and optimize, and thus better suited for resource-constrained and power-sensitive environments. Furthermore, SETs possess unique Coulomb blocking and Coulomb oscillation effects, exhibiting extremely low power consumption and ultra-small device size. SETs are highly compatible with CMOS processes. By combining PMOS transistors and SETs to form logic gate circuits to construct adders in arithmetic modules, the inherent leakage current and power consumption bottleneck of CMOS processes can be effectively avoided compared to using all CMOS devices. The cooperation between PMOS transistors and SETs eliminates the need for complex control of the SET's background charge, reducing the complexity of background charge injection compared to using all SETs. This simplifies the hardware structure of the circuit while ensuring good computational performance, facilitating miniaturization and low power consumption.

[0032] In this embodiment, the input floating-point number format tangent value is a 32-bit single-precision floating-point number.

[0033] For example, the preprocessing module includes an exception handling submodule and a floating-point to fixed-point conversion submodule. The input terminal of the preprocessing module is also the input terminal of the exception handling submodule. The exception handling submodule is used to detect whether the input floating-point format tangent value is abnormal. For example, if the input value is detected as zero, infinity (+∞ or -∞), or a non-numeric type (NaN), the corresponding exception flag signal (such as a high level) is output to indicate an input abnormality. If the input value is not abnormal, the floating-point format tangent value is split into a sign bit S, an exponent bit E, and a mantissa bit M according to the IEEE 754 standard, and then sent to the floating-point to fixed-point conversion submodule. The floating-point to fixed-point conversion submodule is used to convert the valid single-precision floating-point number into a fixed-point number format that is compatible with the calculation range of the arithmetic module. The floating-point to fixed-point conversion submodule determines the shift operation based on the exponent part of the floating-point number, and then performs fixed-point processing on the mantissa, achieving a precise fixed-point representation of the mantissa through shifting. It should be noted that this application does not limit the specific fixed-point implementation method; any implementation that meets the functional requirements of floating-point to fixed-point conversion can be adopted.

[0034] Optionally, the floating-point to fixed-point conversion module also utilizes the property that the graph of the arctangent function is symmetric about the origin during the floating-point to fixed-point conversion process. It performs a central symmetric transformation, centering on the origin, to map input data located in the second quadrant to the fourth quadrant, which is symmetric to the origin. Similarly, it performs a central symmetric transformation on input data located in the third quadrant to the first quadrant, which is symmetric to the origin. This reduces the computational complexity of subsequent modules and improves computational efficiency.

[0035] Figure 2 This is a schematic diagram of the rotational iteration process of the arctangent function, which implements the nonlinear mapping from tangent value to angle value, according to an embodiment of this application. Figure 2 Part (a) represents the initial state of the fixed-point tangent value output by the preprocessing module and the process of obtaining the angle value after calculation by the computation module. For example... Figure 2 As shown in part (a), in this embodiment, the calculation module is used to treat the fixed-point tangent value output by the preprocessing module as a value from the origin to ( , The initial vector of is obtained by rotating it multiple times. , Rotate to approximate the target vector on the x-axis. (0), the angle of each rotation is accumulated to obtain the fixed-point format angle value corresponding to the fixed-point format tangent value. ,in, and Let x and y represent the x and y coordinates of the initial vector, respectively. The x-coordinate represents the target vector. Figure 2 Part (b) represents a clockwise rotation process. Figure 2Part (c) indicates a rotation process in the counterclockwise direction. See also Figure 2 In parts (b) and (c), during the process of rotating the initial vector to approximate the target vector using multiple rotations, the first vector is obtained after the i-th rotation. , ), and Let x and y represent the x and y coordinates of the first vector, respectively. The second vector is obtained after the (i+1)th rotation. , ), and Let x and y represent the x-coordinate and y-coordinate of the second vector, respectively. Since the goal of the rotation iteration is to approximate the target vector on the x-axis (…),… ,0), therefore, when the ordinate of the first vector When, the next clockwise rotation to the second vector ( , ); when the ordinate of the first vector When, the next counterclockwise rotation to the second vector ( , ).

[0036] For example, during vector rotation, the initial rotation angle is 45°, and the rotation angle decreases sequentially with each subsequent rotation.

[0037] Optionally, the calculation module performs iterative calculations for multiple rotations using the following formula:

[0038]

[0039] Where i = 0, 1, ..., N-1, and N is the total number of iterations. This is the x-coordinate variable stored after the (i+1)th iteration. This is the ordinate variable stored after the (i+1)th iteration. This is the variable containing the accumulated rotation angle value after the (i+1)th iteration. This is the x-coordinate variable stored after the i-th iteration. This is the ordinate variable stored after the i-th iteration. This is the accumulated rotation angle value stored after the i-th iteration. =0, As the rotation direction determination factor, when The time indicates that the rotation direction is counterclockwise. The time indicates that the rotation direction is clockwise. Let be the angle of the i-th rotation.

[0040] Optionally, the calculation module outputs a fixed-point format angle value corresponding to the fixed-point format tangent value after performing 12 to 16 iterations. Within this range, the number of iterations ensures high accuracy of the calculated angle value while improving computational efficiency. In this embodiment, the calculation module outputs a fixed-point format angle value corresponding to the fixed-point format tangent value after 16 iterations. Through 10,000 sets of random tests, the absolute error of the angle value calculated by the calculation module is within 10. -5 Within this range, it can well meet the requirements for high precision.

[0041] In this embodiment, according to the formula for the iterative calculation described above, the nonlinear operation of the arctangent by the arithmetic module is mainly achieved through shifting and addition / subtraction operations. In binary digital circuits, shifting a number to the right by i bits is equivalent to multiplying by 2. -i In arithmetic operations, shift operations can be implemented by changing the positions of the connections in a binary number. Subtraction operations can usually be performed using an adder; therefore, the adder is the core circuit module of the arithmetic module. This application does not limit the data width of the adder. As an example, this embodiment uses a parallel pipelined structure to implement the adder.

[0042] For example, the data width of the adder is 32 bits.

[0043] Figure 3 This is a schematic diagram illustrating the operational principle of the adder provided in the embodiments of this application. For example... Figure 3 As shown, the adder is used to calculate the generation signal for each data bit in parallel based on the addend and augend. With propagation signal Based on the generation signal of each data bit With propagation signal Calculate the carry signal for each data bit. According to the propagation signal of each data bit With carry signal Calculate the sum signal of each data bit Thus, the sum signal S is obtained.

[0044] In this embodiment, the logic gates in the adder include AND gates, OR gates, and XOR gates. For example, the addend is A, and the augend is B. and These represent the i-th binary digit. Generate signal. That is, generating signal yes and The result of AND operation; propagation signal That is, the propagation signal yes and The result after XOR. The hardware resources required to calculate the generation and propagation signals of each data bit are proportional to the bit width of the adder. In this embodiment, this calculation step uses 32 AND gates and 32 XOR gates.

[0045] For example, a 5-level merging tree logic can be used, based on the generation signal of each data bit. With propagation signal Calculate the carry signal for each data bit. Each merge operation requires two AND gates and one OR gate. In this embodiment, the calculation step uses 62 AND gates and 31 OR gates.

[0046] For example, the calculation and signal are the result of parallel circuitry, with each data bit being summed to the signal. You can get them at the same time. That is, the sum signal of each data bit. yes and The result after XOR operation is calculated using 32 XOR gates in this embodiment.

[0047] Based on the analysis of the above calculation steps, in this embodiment, the 32-bit wide adder includes 94 AND gates, 31 OR gates, and 64 XOR gates.

[0048] For example, AND gates, OR gates, and XOR gates are all composed of a variety of preset circuit modules, including a two-input PMOS series module, a two-input PMOS parallel module, a PMOS-SET series module, a two-input SET series module, and a two-input SET parallel module.

[0049] Figure 4 This is a schematic diagram of the circuit structure of a preset circuit module composed of PMOS transistors and SET provided in the embodiments of this application. Figure 4 Parts (a) to (e) represent a two-input PMOS series module, a two-input PMOS parallel module, a PMOS-SET series module, a two-input SET series module, and a two-input SET parallel module, respectively. Figure 5 This is a schematic diagram of the logic symbol of a preset circuit module composed of PMOS transistors and SET provided in the embodiments of this application. Figure 5 Parts (a) to (e) represent a two-input PMOS series module, a two-input PMOS parallel module, a PMOS-SET series module, a two-input SET series module, and a two-input SET parallel module, respectively.

[0050] For example, see Figure 4 part (a) and Figure 5Part (a) of the two-input PMOS series module includes two PMOS transistors connected in series, wherein the source of the first PMOS transistor is connected to the power supply terminal V. DD The substrate of the first PMOS transistor is connected to the source of the first PMOS transistor, the source of the second PMOS transistor is connected to the drain of the first PMOS transistor, the substrate of the second PMOS transistor is connected to the source of the first PMOS transistor, the gate of the first PMOS transistor is the first input terminal X of the two-input PMOS series module, the gate of the second PMOS transistor is the second input terminal Y of the two-input PMOS series module, and the drain of the second PMOS transistor is the terminal of the two-input PMOS series module.

[0051] For example, see Figure 4 Part (b) and Figure 5 Part (b) of the two-input PMOS parallel module includes two PMOS transistors connected in parallel, wherein the sources and substrates of the two PMOS transistors are interconnected and connected to the power supply terminal V. DD The drains of the two PMOS transistors are connected to each other and serve as the terminals of the two-input PMOS parallel module. The gates of the two PMOS transistors are the first input terminal X and the second input terminal Y of the two-input PMOS parallel module, respectively.

[0052] For example, see Figure 4 Part (c) and Figure 5 In part (c), the PMOS-SET series module includes a SET and a PMOS transistor connected in series, wherein the source of the PMOS transistor serves as the first terminal of the PMOS-SET series module, and the substrate of the PMOS transistor is connected to the power supply terminal V. DD The gate of the PMOS transistor is connected to the gate of the SET and serves as the second terminal of the PMOS-SET series module. The drain of the PMOS transistor is connected to the source of the SET and serves as the third terminal of the PMOS-SET series module. The drain of the SET is grounded (GND).

[0053] For example, see Figure 4 part (d) and Figure 5 In part (d), the two-input SET series module includes two SETs connected in series, wherein the drain of the first SET is connected to the source of the second SET, the drain of the second SET is grounded, the gate of the first SET is the first input terminal X of the two-input SET series module, the gate of the second SET is the second input terminal Y of the two-input SET series module, and the source of the first SET is the terminal of the two-input SET series module.

[0054] For example, see Figure 4part (e) and Figure 5 In part (e), the two-input SET parallel module includes two SETs connected in parallel. The sources of the two SETs are connected to each other and serve as the terminals of the two-input SET parallel module. The drains of the two SETs are connected to each other and grounded. The gates of the two SETs are the first input terminal X and the second input terminal Y of the two-input SET parallel module, respectively.

[0055] Modularizing PMOS transistors and SETs simplifies the hardware structure of the circuit and allows for better differentiation between the manufacturing processes of PMOS and SET.

[0056] In this embodiment, the PMOS transistor is simulated using both the BSIM4 model and the Predictive Technology Model (PTM), while the SET is simulated using the Master Equation model. The SET master equation model is based on quantum mechanics principles and describes the probabilistic evolution of a single-electron tunneling event, representing a precise nanoscale SET simulation. The parameter settings for the PMOS transistor and SET are shown in Table 1.

[0057] Table 1

[0058] With the parameters of the PMOS transistor and SET set as shown in Table 1, the tunnel junction capacitance of the SET is larger, making it easier to implement in terms of technology. Moreover, there is no need to perform complex control on the background charge of the SET, which can reduce the complexity of background charge injection and facilitate better implementation of various logic gate circuits.

[0059] Figure 6 This is a schematic diagram of an AND gate circuit provided in an embodiment of this application. See also... Figures 4 to 6 The AND gate circuit includes a two-input PMOS series module, a two-input SET parallel module, and a PMOS-SET series module. The terminals of the two-input PMOS series module are connected to the terminals of the two-input SET parallel module and also to the second terminal of the PMOS-SET series module. The first input terminal X of the two-input PMOS series module is connected to the first input terminal X of the two-input SET parallel module and serves as the first input terminal X of the AND gate circuit. The second input terminal Y of the two-input PMOS series module is connected to the second input terminal Y of the two-input SET parallel module and serves as the second input terminal Y of the AND gate circuit. The first terminal of the PMOS-SET series module is connected to the power supply terminal V. DD The third terminal of the PMOS-SET series module is the output terminal L of the AND gate circuit. The truth table of the AND gate circuit is shown in Table 2.

[0060] Table 2

[0061] Figure 7 This is a schematic diagram of an OR gate circuit provided in an embodiment of this application. See also... Figure 4 , Figure 5 and Figure 7 The OR gate circuit includes a two-input PMOS parallel module, a two-input SET series module, and a PMOS-SET series module. The terminals of the two-input PMOS parallel module are connected to the terminals of the two-input SET series module and also to the second terminal of the PMOS-SET series module. The first input terminal X of the two-input PMOS parallel module is connected to the first input terminal X of the two-input SET series module and serves as the first input terminal X of the OR gate circuit. The second input terminal Y of the two-input PMOS parallel module is connected to the second input terminal Y of the two-input SET series module and serves as the second input terminal Y of the OR gate circuit. The first terminal of the PMOS-SET series module is connected to the power supply terminal V. DD The third terminal of the PMOS-SET series module is the output terminal L of the OR gate circuit. The truth table of this OR gate circuit is shown in Table 3.

[0062] Table 3

[0063] Figure 8 This is a schematic diagram of an XOR gate circuit provided in an embodiment of this application. See also... Figure 4 , Figure 5 and Figure 8 The XOR gate circuit includes a two-input PMOS series module, a two-input PMOS parallel module, a PMOS-SET series module, a two-input SET series module, and a two-input SET parallel module. The terminals of the two-input PMOS series module are connected to the terminals of the two-input SET parallel module and also to the second terminal of the PMOS-SET series module. The terminals of the two-input PMOS parallel module are connected to the first terminal of the PMOS-SET series module, and the terminals of the two-input SET series module are connected to the third terminal of the PMOS-SET series module. The first input terminals X of the two-input PMOS series module, the two-input PMOS parallel module, the two-input SET parallel module, and the two-input SET series module are all interconnected and serve as the first input terminal X of the XOR gate. Similarly, the second input terminals Y of the two-input PMOS series module, the two-input PMOS parallel module, the two-input SET parallel module, and the two-input SET series module are all interconnected and serve as the second input terminal Y of the XOR gate. The truth table of this XOR gate is shown in Table 4.

[0064] Table 4

[0065] Optionally, the post-processing module is also used to detect whether the fixed-point format angle value output by the arithmetic module is abnormal. In the first quadrant, the angle value output by the arithmetic module is in the range of (0, 90°), and in the fourth quadrant, the angle value output by the arithmetic module is in the range of (-90°, 0). Angle values ​​exceeding the above ranges are abnormal output results. If an abnormal output value is detected, a corresponding abnormal flag signal (such as a high level) is output to indicate an abnormal output. If no abnormal output value is detected, leading zero detection and data format conversion are performed on the fixed-point format angle value output by the arithmetic module to obtain a floating-point format angle value.

[0066] For example, the post-processing module can determine the floating-point sign bit S based on the quadrant marker (sign bit) of the fixed-point angle value Z. If the angle value Z is negative, it is converted from two's complement to sign-magnitude representation; if the angle value Z is positive, it remains unchanged. Then, leading zero detection is performed on Z to determine the position of the first "1" outside the sign bit, thereby determining the magnitude of the exponent E. After obtaining the exponent E, the corresponding mantissa M is selected based on the position of the first "1". Finally, the sign bit S, exponent E, and mantissa M are combined into a single-precision floating-point number to obtain the floating-point format angle value, which serves as the output value of the hardware circuit for the floating-point arctangent function, thus better meeting the needs of floating-point applications.

[0067] The above description is merely an optional embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A hardware circuit for a floating-point arctangent function, characterized in that, include: The preprocessing module is used to convert the input tangent value in the form of an error-free floating-point number into the corresponding tangent value in the form of a fixed-point number. The arithmetic module has its input end connected to the output end of the preprocessing module. It is used to obtain the corresponding fixed-point number format angle value by binary shift and addition / subtraction operations based on the fixed-point number format tangent value output by the preprocessing module. The post-processing module, whose input is connected to the output of the arithmetic module, is used to perform leading zero detection and data format conversion on the fixed-point angle value output by the arithmetic module to obtain the floating-point angle value. The arithmetic module includes at least an adder with a data width of 32 bits. The adder comprises logic gates composed of PMOS transistors and single-electron transistors, with the tunneling junction capacitance of the single-electron transistor being 0.3aF. The logic gates include AND gates, OR gates, and XOR gates. The 32-bit adder includes 94 AND gates, 31 OR gates, and 64 XOR gates. Each AND, OR, and XOR gate is composed of multiple preset circuit modules, including a two-input PMOS series module, a two-input PMOS parallel module, a PMOS-SET series module, a two-input SET series module, and a two-input SET parallel module. The two-input PMOS series module includes two PMOS transistors connected in series, wherein the source of the first PMOS transistor is connected to the power supply terminal V. DD The substrate of the first PMOS transistor is connected to its source, and the source of the second PMOS transistor is connected to its drain. The substrate of the second PMOS transistor is also connected to its source. The gate of the first PMOS transistor is the first input terminal of the two-input PMOS series module, and the gate of the second PMOS transistor is the second input terminal. The drain of the second PMOS transistor is the terminal of the two-input PMOS series module. The two-input PMOS parallel module includes two PMOS transistors connected in parallel, wherein the sources and substrates of the two PMOS transistors are interconnected and connected to the power supply terminal V. DD The drains of the two PMOS transistors are interconnected and serve as the terminals of the two-input PMOS parallel module. The gates of the two PMOS transistors are the first and second input terminals of the two-input PMOS parallel module, respectively. The PMOS-SET series module includes a SET and a PMOS transistor connected in series. The source of the PMOS transistor serves as the first terminal of the PMOS-SET series module, and the substrate of the PMOS transistor is connected to the power supply terminal V. DD The gate of the PMOS transistor is connected to the gate of the SET and serves as the second terminal of the PMOS-SET series module. The drain of the PMOS transistor is connected to the source of the SET and serves as the third terminal of the PMOS-SET series module. The drain of the SET is grounded. The two-input SET series module includes two SETs connected in series, wherein the drain of the first SET is connected to the source of the second SET, the drain of the second SET is grounded, the gate of the first SET is the first input terminal of the two-input SET series module, the gate of the second SET is the second input terminal of the two-input SET series module, and the source of the first SET is the terminal of the two-input SET series module. The two-input SET parallel module includes two SETs connected in parallel, wherein the sources of the two SETs are connected to each other and serve as the terminals of the two-input SET parallel module, the drains of the two SETs are connected to each other and grounded, and the gates of the two SETs are the first input terminal and the second input terminal of the two-input SET parallel module, respectively. The XOR gate circuit includes a two-input PMOS series module, a two-input PMOS parallel module, a PMOS-SET series module, a two-input SET series module, and a two-input SET parallel module. The terminals of the two-input PMOS series module are connected to the terminals of the two-input SET parallel module and to the second terminal of the PMOS-SET series module. The terminals of the two-input PMOS parallel module are connected to the first terminal of the PMOS-SET series module. The terminals of the two-input SET series module are connected in series with the PMOS-SET. The third terminal of the module is connected and serves as the output terminal of the XOR gate circuit. The first input terminals of the two-input PMOS series module, the two-input PMOS parallel module, the two-input SET parallel module, and the two-input SET series module are all interconnected and serve as the first input terminal of the XOR gate circuit. The second input terminals of the two-input PMOS series module, the two-input PMOS parallel module, the two-input SET parallel module, and the two-input SET series module are all interconnected and serve as the second input terminal of the XOR gate circuit.

2. The hardware circuit for the floating-point arctangent function according to claim 1, characterized in that, The calculation module is used to treat the fixed-point format tangent value output by the preprocessing module as a value from the origin to ( , The initial vector of is obtained by rotating it multiple times. , Rotate to approximate the target vector on the x-axis. (0), the angle of each rotation is accumulated to obtain the fixed-point number format angle value corresponding to the tangent value of the fixed-point number format, where, and Let x and y represent the x and y coordinates of the initial vector, respectively. The x-coordinate of the target vector is represented.

3. The hardware circuit for the floating-point arctangent function according to claim 2, characterized in that, The calculation module performs iterative calculations for multiple rotations using the following formula: Where i = 0, 1, ..., N-1, and N is the total number of iterations. This is the x-coordinate variable stored after the (i+1)th iteration. This is the ordinate variable stored after the (i+1)th iteration. This is the variable representing the accumulated rotation angle value stored after the (i+1)th iteration. This is the x-coordinate variable stored after the i-th iteration. This is the ordinate variable stored after the i-th iteration. This is the accumulated rotation angle value stored after the i-th iteration. =0, As the rotation direction determination factor, when The time indicates that the rotation direction is counterclockwise. The time indicates that the rotation direction is clockwise. Let be the angle of the i-th rotation.

4. The hardware circuit for the floating-point arctangent function according to claim 3, characterized in that, The adder is used to calculate the generation signal and propagation signal of each data bit in parallel based on the addend and augend; calculate the carry signal of each data bit based on the generation signal and propagation signal of each data bit; and calculate the sum signal based on the propagation signal and carry signal of each data bit.

5. The hardware circuit for the floating-point arctangent function according to claim 1, characterized in that, The AND gate circuit includes a two-input PMOS series module, a two-input SET parallel module, and a PMOS-SET series module. The terminals of the two-input PMOS series module are connected to the terminals of the two-input SET parallel module and to the second terminal of the PMOS-SET series module. The first input terminal of the two-input PMOS series module is connected to the first input terminal of the two-input SET parallel module and serves as the first input terminal of the AND gate circuit. The second input terminal of the two-input PMOS series module is connected to the second input terminal of the two-input SET parallel module and serves as the second input terminal of the AND gate circuit. The first terminal of the PMOS-SET series module is connected to the power supply terminal V. DD The third terminal of the PMOS-SET series module is the output terminal of the AND gate circuit.

6. The hardware circuit for the floating-point arctangent function according to claim 1, characterized in that, The OR gate circuit includes a two-input PMOS parallel module, a two-input SET series module, and a PMOS-SET series module. The terminals of the two-input PMOS parallel module are connected to the terminals of the two-input SET series module and to the second terminal of the PMOS-SET series module. The first input terminal of the two-input PMOS parallel module is connected to the first input terminal of the two-input SET series module and serves as the first input terminal of the OR gate circuit. The second input terminal of the two-input PMOS parallel module is connected to the second input terminal of the two-input SET series module and serves as the second input terminal of the OR gate circuit. The first terminal of the PMOS-SET series module is connected to the power supply terminal V. DD The third terminal of the PMOS-SET series module is the output terminal of the OR gate circuit.

7. The hardware circuit for the floating-point arctangent function according to any one of claims 2 to 6, characterized in that, After performing 12 to 16 iterations, the calculation module outputs a fixed-point format angle value corresponding to the fixed-point format tangent value.

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