A service processing method and device, electronic equipment and storage medium
By identifying the target business logic in the network device and updating the FPGA configuration, the problem of high hardware costs was solved, and a low-cost business acceleration effect was achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- BEIJING XINWANG RUIJIE NETWORK TECH CO LTD
- Filing Date
- 2024-12-30
- Publication Date
- 2026-06-30
AI Technical Summary
In existing technologies, network devices have high hardware costs when accelerating services, especially when increasing the number of CPUs or using large-capacity FPGAs, which are too expensive.
By determining the target business logic when the triggering conditions are met, finding the target configuration file, and updating the FPGA based on the configuration file, the FPGA is switched to the target business logic, thereby accelerating the business.
By processing multiple business logics in a single operation using FPGA, hardware costs are reduced, achieving a business acceleration effect similar to that of high-capacity FPGAs, with fast update speeds and no noticeable impact on users.
Smart Images
Figure CN122308928A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of communication technology, and in particular to a service processing method, apparatus, electronic device and storage medium. Background Technology
[0002] Currently, network devices such as routers are handling an increasing number of services. However, a single core of a processing unit such as the Central Processing Unit (CPU) in a network device can only process instructions related to one service at a time. When it is necessary to accelerate a certain service, one approach is to increase the number of CPUs or CPU cores, which is relatively expensive. Another approach is to implement the service logic under all configurations on a large-capacity Field Programmable Gate Array (FPGA) to accelerate the service. However, this requires a large-capacity FPGA, which is also relatively expensive. Summary of the Invention
[0003] This application provides a business processing method, apparatus, electronic device, and storage medium to solve the problem of high hardware costs for business acceleration in related technologies.
[0004] In a first aspect, embodiments of this application provide a business processing method, including:
[0005] When the triggering conditions for processing the target service through the FPGA are met, the target service logic to be switched to is determined.
[0006] From the stored set of configuration files, locate the target configuration file for the target service under the target service logic;
[0007] Based on the target configuration file, the FPGA is updated to switch to the target business logic and the target business is processed according to the target business logic.
[0008] In some embodiments, the target service is a service that includes multiple sub-services, and the triggering condition includes receiving a switching instruction for the target service, wherein the switching instruction contains a service logic identifier corresponding to each sub-service;
[0009] Determining the target service logic to be switched to includes:
[0010] The business logic corresponding to each sub-business is determined based on the business logic identifier corresponding to each sub-business.
[0011] The business logic corresponding to each of the various sub-businesses is determined as the target business logic.
[0012] In some embodiments, retrieving the target configuration file for the target service under the target service logic from a stored configuration file set includes:
[0013] Find the configuration file for each sub-service under the corresponding business logic from the configuration file set;
[0014] The configuration files corresponding to the various sub-services are determined as the target configuration file.
[0015] In some embodiments, the target service is multiple services, and the triggering condition includes receiving a switching instruction for the target service, wherein the switching instruction contains a service logic identifier corresponding to each service;
[0016] Determining the target service logic to be switched to includes:
[0017] The business logic corresponding to each business is determined based on the business logic identifier corresponding to each business.
[0018] The business logic corresponding to each of the various services is determined as the target business logic.
[0019] In some embodiments, retrieving the target configuration file for the target service under the target service logic from a stored configuration file set includes:
[0020] Find the configuration file for each service under the corresponding business logic from the configuration file set;
[0021] The configuration files corresponding to the various services are determined as the target configuration file.
[0022] In some embodiments, the target service is a service corresponding to multiple segments of serial service logic, and the triggering condition includes data processing conditions that satisfy any segment of the service logic.
[0023] Determining the target service logic to be switched to includes:
[0024] The business logic that meets the data processing conditions is identified as the target business logic.
[0025] In some embodiments, it also includes:
[0026] After adding a preset identifier to the business data corresponding to the target business logic, the data is stored in memory. The FPGA reads the business data containing the preset identifier from the memory and executes the instructions corresponding to the business data according to the target business logic.
[0027] In some embodiments, the FPGA is in an online state, and before updating the FPGA's functionality based on the target configuration file, the following steps are also included:
[0028] Stop accessing the FPGA;
[0029] Control the FPGA's input / output I / O to enter a holding state;
[0030] After updating the functionality of the FPGA, the following is also included:
[0031] The FPGA is initialized, which includes restoring access to the FPGA and switching the FPGA's I / O state to a new I / O state.
[0032] Secondly, embodiments of this application provide a business processing apparatus, including:
[0033] The determination module is used to determine the target service logic to be switched to when the triggering conditions for processing the target service through the field-programmable gate array (FPGA) are met.
[0034] The lookup module is used to find the target configuration file of the target service under the target service logic from the stored configuration file set;
[0035] The update module is used to update the FPGA based on the target configuration file, so that the FPGA switches to the target business logic and processes the target business according to the target business logic.
[0036] Thirdly, embodiments of this application provide an electronic device, including: at least one processor, and a memory communicatively connected to the at least one processor, wherein:
[0037] The memory stores a computer program that can be executed by at least one processor, which enables the at least one processor to perform any of the above-described business processing methods.
[0038] Fourthly, embodiments of this application provide a storage medium in which, when a computer program in the storage medium is executed by a processor of an electronic device, the electronic device is able to execute any of the above-described business processing methods.
[0039] Fifthly, embodiments of this application provide a computer program product, including a computer program, which, when executed by a processor, implements any of the above-described business processing methods.
[0040] In this embodiment, when the triggering condition for processing the target service via FPGA is met, the target service logic to be switched to is determined. The target configuration file for the target service under the target service logic is searched from the stored configuration file set. Based on the target configuration file, the FPGA is functionally updated, causing it to switch to the target service logic, and the target service is processed according to that logic. In this way, service acceleration is performed according to the service logic that the FPGA can process in a single operation, breaking the constraint that the FPGA must support all service logics requiring acceleration in a single operation. Service acceleration functionality that typically requires a large-capacity FPGA is achieved with a small-capacity FPGA, thus resulting in lower hardware costs for service acceleration. Attached Figure Description
[0041] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:
[0042] Figure 1 A schematic diagram of a network device provided in an embodiment of this application;
[0043] Figure 2 A flowchart of a business processing method provided in an embodiment of this application;
[0044] Figure 3 A functional diagram of an IPSec service provided in this application;
[0045] Figure 4 A flowchart illustrating yet another business processing method provided in this application embodiment;
[0046] Figure 5 A business interaction flowchart provided for an embodiment of this application;
[0047] Figure 6 A flowchart illustrating yet another business processing method provided in this application embodiment;
[0048] Figure 7 This application provides yet another business interaction flowchart.
[0049] Figure 8 A schematic diagram of a business processing procedure provided in an embodiment of this application;
[0050] Figure 9 A flowchart illustrating yet another business processing method provided in this application embodiment;
[0051] Figure 10 This application provides yet another business interaction flowchart.
[0052] Figure 11 This is a schematic diagram of the structure of a service processing device provided in an embodiment of this application;
[0053] Figure 12 This is a schematic diagram of the hardware structure of an electronic device for implementing a business processing method, provided as an embodiment of this application. Detailed Implementation
[0054] To address the issue of high hardware costs for business acceleration in related technologies, embodiments of this application provide a business processing method, apparatus, electronic device, and storage medium.
[0055] The preferred embodiments of this application are described below with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are for illustration and explanation only and are not intended to limit this application. Furthermore, the embodiments and features in the embodiments of this application can be combined with each other without conflict.
[0056] See Figure 1 , Figure 1 This is a schematic diagram of a network device provided in an embodiment of this application. The network device, such as a router or switch, includes a processing unit and an FPGA. The processing unit and the FPGA can be connected via a high-speed interface such as PCIe, and both can access the same memory area. The network device can install software such as routing software, which can support various services. Under normal circumstances, the processing unit handles the services; under acceleration conditions, the FPGA handles the services to speed them up.
[0057] Generally, the processing unit in a network device is the CPU. However, with the improvement of the computing performance of network devices, it is possible that the processing unit in a network device may use a Graphics Processing Unit (GPU) or other processing units. In other words, the processing unit in a network device can be a CPU, a GPU, or other processing units. The following discussion will focus on the example where the processing unit in a network device is a CPU.
[0058] The business processing method proposed in this application will be described below with specific embodiments.
[0059] See Figure 2 , Figure 2 A flowchart of a business processing method provided in this application embodiment, wherein the executing entity of the method may be... Figure 1 The processing unit in the method includes the following steps.
[0060] In step 201, when the triggering conditions for processing the target service through the FPGA are met, the target service logic to be switched to is determined.
[0061] In practical applications, there can be one or more target businesses, and each business can correspond to one or more business logics. The main business processing procedures under different business logics are similar, but there will be some differences.
[0062] Taking Internet Protocol Security (IPSec) services as an example, see [link / reference]. Figure 3 , Figure 3 This application provides a schematic diagram of the processing procedure for an IPSec service, which authenticates and decrypts external input packets (packets input from the external port of the processing unit) and outputs them to other services for processing, and encrypts and authenticates output packets (packets to be output from the external port of the processing unit after processing by other services) before outputting them.
[0063] Assume that IPSec services support four encryption / decryption algorithms: Data Encryption Standard (DES), Triple Data Encryption Algorithm (3DES), Advanced Encryption Standard (AES), and SM4. Also assume that IPSec services support four authentication algorithms: Message Digest Algorithm (MD5), Secure Hash Algorithm 1 (SHA-1), Secure Hash Algorithm 256-bit (SHA2-256), Secure Hash Algorithm 384-bit (SHA2-384), Secure Hash Algorithm 384-bit 512-bit (SHA2-512), and SM3. It should be noted that all instances of SHA2 represent a single algorithm.
[0064] In practical use, only one encryption / decryption algorithm and one authentication algorithm need to be selected for input or output. That is, the IPSec service processing can proceed with just one encryption / decryption algorithm and one authentication algorithm. However, the processing logic of IPSec services will differ depending on the combination of encryption / decryption and authentication algorithms. Specifically, when IPSec services are the target services that need to be processed by FPGA, one encryption / decryption algorithm and one authentication algorithm correspond to one target service logic for IPSec services.
[0065] In some embodiments, the target service is a service that includes multiple sub-services. In this case, the triggering condition may be receiving a switching instruction for the target service, and the switching instruction may contain a business logic identifier corresponding to each sub-service. Then, the business logic corresponding to each sub-service can be determined based on the business logic identifier, and the business logic corresponding to each of the multiple sub-services can be determined as the target service logic.
[0066] In some embodiments, the target service is multiple services. In this case, the triggering condition may be receiving a switching instruction for the target service, and the switching instruction may contain a business logic identifier corresponding to each service. Then, the business logic corresponding to each service can be determined based on the business logic identifier, and the business logic corresponding to each of the multiple services can be determined as the target business logic.
[0067] In some embodiments, the target service is a service corresponding to multiple segments of serial service logic. In this case, if the triggering condition satisfies the data processing condition of any segment of service logic, then the service logic that satisfies the data processing condition can be identified as the target service logic.
[0068] In step 202, the target configuration file for the target business under the target business logic is located from the stored configuration file set.
[0069] In practical applications, configuration file sets can be pre-stored in the memory area. The target configuration file corresponding to the component identifier can be found in the memory area. Furthermore, the files in the configuration file set can be bin files.
[0070] If the target business is a business that includes multiple sub-businesses, the configuration file for each sub-business under the corresponding business logic can be found in the configuration file set. Then, the configuration files corresponding to each of the multiple sub-businesses can be determined as the target configuration file.
[0071] When the target business involves multiple businesses, the configuration file for each business under the corresponding business logic can be found in the configuration file set. Then, the configuration files corresponding to the multiple businesses can be determined as the target configuration file.
[0072] For a business scenario where the target business involves multiple sequential business logic segments, the configuration file corresponding to the target business logic is retrieved from the configuration file set and used as the target configuration file.
[0073] In step 203, based on the target configuration file, the FPGA is updated to switch to the target business logic and the target business is processed according to the target business logic.
[0074] In some embodiments, based on the target configuration file, the functionality of all blocks of the FPGA can be updated. In some embodiments, the FPGA supports partial area updates; in this case, based on the target configuration file, only a portion of the FPGA's blocks can be updated. In either case, writing the data from the target configuration file into the FPGA completes the FPGA's functionality update, after which the FPGA possesses the business logic corresponding to the target functional component.
[0075] In addition, when the FPGA supports high-speed I / O (such as PCIe) update capabilities, the FPGA can be updated online to improve the function switching speed of the FPGA. Online update refers to updating the FPGA itself directly, which is different from updating only the external memory of the FPGA and then powering off the FPGA to load it.
[0076] Furthermore, before updating the functionality of an online FPGA, access to the FPGA can be stopped to avoid access errors, and the FPGA's input / output I / O can be instructed to enter a holding state to prevent I / O errors. After updating the functionality of the online FPGA, it can be initialized. Initialization includes restoring access to the FPGA, switching the FPGA's I / O state to a new I / O state, setting the FPGA to active state, running the FPGA, and assigning initial values to the corresponding FPGA registers. After initialization, the FPGA can process data normally.
[0077] In practical applications, after determining the target business logic to be switched to, a preset identifier can be added to the business data corresponding to the target business logic and stored in memory. Then, the FPGA reads the business data containing the preset identifier from memory, executes the instructions corresponding to the business data according to the target business logic, so as to accelerate the target business through the FPGA.
[0078] The following section provides examples of business acceleration scenarios in this solution.
[0079] Scenario 1: Accelerate a target business process.
[0080] Let's take accelerating IPSec services as an example. Assume the IPSec service is divided into two sub-services: encryption / decryption and authentication. Also, assume the encryption / decryption sub-service supports four encryption / decryption algorithms, and the authentication sub-service supports four authentication algorithms. In actual use, only one encryption / decryption algorithm and one authentication algorithm need to be selected for input or output.
[0081] When accelerating IPSec services using FPGAs, related technologies require implementing all encryption / decryption algorithms and all authentication algorithms simultaneously on the FPGA, necessitating a large FPGA capacity. In this application's solution, bin files can be pre-defined for each encryption / decryption algorithm and each authentication algorithm, resulting in 16 bin file combinations (4 encryption / decryption algorithms × 4 authentication algorithms). After the encryption / decryption and authentication algorithms are selected for practical application, the corresponding bin file combination (i.e., the target configuration file) is updated in the FPGA. This significantly reduces the FPGA capacity compared to previous methods. If calculated based on the same FPGA capacity for each encryption / decryption algorithm and each authentication algorithm, the required FPGA capacity is only 1 / 16 of the original, greatly saving hardware costs. The FPGA capacity characterizes the FPGA's data processing speed, and the FPGA's capacity is positively correlated with its data processing speed.
[0082] In addition, when customers change the encryption and decryption algorithms and authentication algorithms, the FPGA can be quickly updated in the background to support the new configuration. Because a high-speed update is used, the FPGA will also be updated quickly after the user completes the configuration (usually the update is short, such as less than 2 seconds, so the customer will not have any noticeable changes when configuring).
[0083] For the business processing procedure in scenario one above, please refer to [link / reference]. Figure 4 , Figure 4 A flowchart of another business processing method provided in this application embodiment includes the following steps.
[0084] In step 401, a switching instruction for the target service is received. The target service is a service that includes multiple sub-services. The switching instruction contains the service logic identifier corresponding to each sub-service.
[0085] The switching command can be sent by the user terminal through a command-line interface (CLI) that is not easily perceived by the user. In practical applications, each sub-service can correspond to multiple business logics, and each business logic corresponds to a configuration file, such as the FPGA's bin file. The user terminal can switch which business logic the sub-service operates under through the CLI.
[0086] In step 402, access to the FPGA is stopped, and the FPGA's I / O is controlled to enter the holding state.
[0087] In step 403, based on the business logic identifier corresponding to each sub-service, the configuration file of the sub-service under the corresponding business logic is searched from the stored configuration file set, and the configuration files corresponding to the various sub-services are determined as the target configuration files.
[0088] In step 404, the FPGA in the online state is updated based on the target configuration file.
[0089] The implementation of this step can be found in step 203, and will not be repeated here.
[0090] In step 405, after a successful update, the FPGA is initialized, including restoring access to the FPGA and switching the FPGA's I / O state to a new I / O state.
[0091] In step 406, a preset identifier is added to the business data corresponding to the target business logic and stored in memory. The FPGA reads the business data containing the preset identifier from memory and executes the instructions corresponding to the business data according to the target business logic.
[0092] Among them, preset identifiers such as "1" and "T" are used.
[0093] Taking IPSec service as an example, the service data includes external input packets and output packets. Assuming the encryption / decryption algorithm corresponding to the target service logic is DES and the authentication algorithm is SHA-1, the FPGA first authenticates the external input packets using the SHA-1 algorithm, then decrypts them using the DES algorithm; similarly, the output packets are first encrypted using the DES algorithm, then authenticated using the SHA-1 algorithm. Because the FPGA can execute a large number of instructions at once, it is fast, thus achieving the goal of accelerating IPSec services.
[0094] For scenario one above, the business interaction process can be found here. Figure 5 , Figure 5 This application provides a business interaction flowchart, in which the Expedited Forwarding Control (EFC) driver (DRV) and the Board Support Package (BSP) both run on the CPU. The flowchart includes the following steps.
[0095] In step 501, the user terminal sends a switching instruction for the target service to EFC_DRV via CLI. The target service is a service that includes multiple sub-services, and the switching instruction contains the service logic identifier corresponding to each sub-service.
[0096] In step 502, EFC_DRV stops PCIe access to the FPGA.
[0097] In step 503, EFC_DRV searches for the bin file corresponding to the business logic identifier of each sub-service from the stored bin file set.
[0098] In step 504, EFC_DRV sends the found bin files to the BSP.
[0099] In step 505, the BSP stops accessing the FPGA's PCIe and configures the FPGA's I / O to enter a holding state.
[0100] In step 506, the BSP updates the FPGA based on multiple bin files.
[0101] During the update process, the FPGA acts like a memory module, and you only need to write multiple bin files to the FPGA.
[0102] In step 507, BSP returns the update result to EFC_DRV.
[0103] The update result can be either successful or failed.
[0104] In step 508, EFC_DRV reinitializes the FPGA via the BSP.
[0105] When the update result is successful, the FPGA is reinitialized via BSP. After initialization, the FPGA can process data normally.
[0106] In step 509, EFC_DRV returns the handover result to the user.
[0107] In step 510, EFC_DRV adds a preset identifier to the business data corresponding to the target business logic and stores it in memory.
[0108] In step 511, the FPGA reads service data containing preset identifiers from memory and executes the instructions corresponding to the service data according to the target service logic.
[0109] In this embodiment of the application, during the online update of the FPGA via the bin file, the CPU does not lose power or restart, and the FPGA can complete the online update within 2 seconds. The update speed is fast and the user is basically unaware of it, thus reducing the impact of FPGA updates on the user.
[0110] Scenario 2: Accelerate multiple target services.
[0111] Take accelerating IPSec services and Hierarchical Quality of Service (HQOS) services as an example.
[0112] Assume there are four configurations for IPSec and four configurations for HQOS. When accelerating IPSec and HQOS services using an FPGA, related technologies require a large-capacity FPGA to simultaneously support all configuration combinations for both services. The solution proposed in this application only requires pre-setting bin files for each IPSec and HQOS configuration, resulting in 16 bin file combinations. Subsequently, the required bin file combination (i.e., the target configuration file) is loaded onto the FPGA according to the actual configuration. Assuming all configurations occupy the same FPGA capacity, the solution uses only 1 / 16th the FPGA capacity of the original, significantly saving hardware costs. Furthermore, when the customer changes the configuration, the FPGA can be quickly updated in the background using the corresponding bin file to support the new configuration.
[0113] For the business processing procedures in Scenario 2 above, please refer to [link / reference]. Figure 6 , Figure 6 A flowchart of another business processing method provided in this application embodiment includes the following steps.
[0114] In step 601, a switching instruction for the target service is received. The target service is multiple services, and the switching instruction contains the service logic identifier corresponding to each service.
[0115] The switching command can be sent by the user terminal via CLI, which is not easily perceived by the user. In practical applications, each service can correspond to multiple service logics, and each service logic corresponds to a configuration file, such as the FPGA's bin file. The user terminal can switch which service logic is working under via CLI.
[0116] In step 602, access to the FPGA is stopped, and the FPGA's I / O is controlled to enter the holding state.
[0117] In step 603, based on the business logic identifier corresponding to each service, the configuration file for the service under the corresponding business logic is searched from the stored configuration file set, and the configuration files corresponding to the various services are determined as the target configuration files.
[0118] In step 604, the FPGA in the online state is updated based on the target configuration file.
[0119] The implementation of this step can be found in step 203, and will not be repeated here.
[0120] In step 605, after a successful update, the FPGA is initialized, including restoring access to the FPGA and switching the FPGA's I / O state to a new I / O state.
[0121] In step 606, a preset identifier is added to the business data corresponding to the target business logic and stored in memory. The FPGA reads the business data containing the preset identifier from memory and executes the instructions corresponding to the business data according to the target business logic.
[0122] For scenario two above, the business interaction process can be found in [reference needed]. Figure 7 , Figure 7 This application provides another business interaction flowchart, in which both EFC_DRV and BSP run on the CPU, and the process includes the following steps.
[0123] In step 701, the user terminal sends a switching instruction for the target service to EFC_DRV via CLI. The target service is multiple services, and the switching instruction contains the service logic identifier corresponding to each service.
[0124] In step 702, EFC_DRV stops PCIe access to the FPGA.
[0125] In step 703, EFC_DRV searches for the bin file corresponding to the business logic identifier of each service from the stored bin file set.
[0126] In step 704, EFC_DRV sends the found bin files to the BSP.
[0127] In step 705, the BSP stops accessing the FPGA's PCIe and configures the FPGA's I / O to enter a holding state.
[0128] In step 706, the BSP updates the FPGA based on multiple bin files.
[0129] During the update process, the FPGA acts like a memory module, and you only need to write multiple bin files to the FPGA.
[0130] In step 707, BSP returns the update result to EFC_DRV.
[0131] The update result can be either successful or failed.
[0132] In step 708, EFC_DRV reinitializes the FPGA via the BSP.
[0133] When the update result is successful, the FPGA is reinitialized via BSP. After initialization, the FPGA can process data normally.
[0134] In step 709, EFC_DRV returns the handover result to the user.
[0135] In step 710, EFC_DRV adds a preset identifier to the business data corresponding to the target business logic and stores it in memory.
[0136] In step 711, the FPGA reads service data containing preset identifiers from memory and executes the instructions corresponding to the service data according to the target service logic.
[0137] In this embodiment, the FPGA online fast update function can use high-speed interfaces such as PCIe, and the update time can be controlled within 2 seconds. The fast update time enables seamless FPGA function switching for users. It is a solution for service acceleration using software plus a small-capacity FPGA. Here, the software refers to the software installed in the network device, such as routing software, and the service accelerated by the small-capacity FPGA is the service provided by the routing software.
[0138] Scenario 3: Accelerate a target business (which is not sensitive to latency, such as having no latency requirements).
[0139] See Figure 8 , Figure 8 This is a schematic diagram of a service processing procedure provided in an embodiment of this application. For service A, which occupies a long CPU time, time-sharing multiplexing can be used to accelerate it. Specifically, service A can be divided into four approximately equal service logic segments, generating a bin file corresponding to each segment. Subsequently, the bin file corresponding to the first service logic segment is loaded into the FPGA, causing the FPGA to switch to the first service logic segment to process the received multiple service messages. After processing, the intermediate data is placed in buffer 1. Then, the bin file corresponding to the second service logic segment is loaded into the FPGA, causing the FPGA to switch to the second service logic segment and continue processing the data in buffer 1. After processing, the intermediate data is placed in buffer 2. Then, the bin file corresponding to the third service logic segment is loaded into the FPGA, causing the FPGA to switch to the third service logic segment and continue processing the data in buffer 2. After processing, the intermediate data is placed in buffer 3. Finally, the bin file corresponding to the fourth service logic segment is loaded into the FPGA, causing the FPGA to switch to the fourth service logic segment and continue processing the data in buffer 3. The processed data is then output.
[0140] Throughout the process, the CPU software only participated in the control part, consuming relatively few resources, and the FPGA part only required 1 / 4 of the original capacity.
[0141] For scenario three above, the business acceleration process can be found in [link to relevant documentation]. Figure 9 , Figure 9 A flowchart illustrating another business processing method provided in this application embodiment, wherein the executing entity of the method may be... Figure 1 The processing unit in the method includes the following steps.
[0142] In step 901, when the data processing conditions of any segment of business logic corresponding to the target service are met, access to the FPGA is stopped, and the FPGA's I / O is controlled to enter the holding state. The target service is a service that corresponds to multiple segments of serial business logic.
[0143] In step 902, the target configuration file for the target business under the target business logic is found from the set of configuration files stored in memory. The target business logic is this business logic.
[0144] In step 903, the FPGA in the online state is updated based on the target configuration file.
[0145] The implementation of this step can be found in step 203, and will not be repeated here.
[0146] In step 904, after a successful update, the FPGA is initialized, including restoring access to the FPGA and switching the FPGA's I / O state to a new I / O state.
[0147] In step 905, a preset identifier is added to the business data corresponding to the target business logic and stored in memory. The FPGA reads the business data containing the preset identifier from memory and executes the instructions corresponding to the business data according to the target business logic.
[0148] For scenario three above, the business interaction process can be found in [reference needed]. Figure 10 , Figure 10 This application provides a business interaction flowchart, in which both EFC_DRV and BSP are CPU-based operations, and the flowchart includes the following steps.
[0149] In step 1001, EFC_DRV detects data processing conditions that satisfy any segment of the business logic in the target service, where the target service is a service that corresponds to multiple segments of serial business logic.
[0150] These data processing conditions include situations such as the amount of business data reaching a set threshold, or the processing delay of business data reaching a delay threshold. Furthermore, in this case, one business logic segment corresponds to one configuration file.
[0151] In step 1002, EFC_DRV stops PCIe access to the FPGA.
[0152] In step 1003, EFC_DRV searches for the bin file corresponding to this business logic from the stored bin file set.
[0153] In step 1004, EFC_DRV sends the found bin file to the BSP.
[0154] In step 1005, the BSP stops accessing the FPGA's PCIe and configures the FPGA's I / O to enter a holding state.
[0155] In step 1006, the BSP updates the FPGA based on the bin file.
[0156] During the update process, the FPGA acts like a block of memory; you only need to write the bin file to the FPGA.
[0157] In step 1007, BSP returns the update result to EFC_DRV.
[0158] The update result can be either successful or failed.
[0159] In step 1008, EFC_DRV reinitializes the FPGA via the BSP.
[0160] When the update result is successful, the FPGA is reinitialized via BSP. After initialization, the FPGA can process data normally.
[0161] In step 1009, EFC_DRV adds a preset identifier to the business data corresponding to the target business logic and stores it in memory.
[0162] In step 1010, the FPGA reads service data containing preset identifiers from memory and executes the instructions corresponding to the service data according to the target service logic.
[0163] Based on the same technical concept, this application also provides a business processing device. The principle of the business processing device in solving the problem is similar to that of the above-mentioned business processing method. Therefore, the implementation of the business processing device can refer to the implementation of the business processing method, and the repeated parts will not be described again.
[0164] Figure 11 A schematic diagram of a business processing apparatus provided in this application embodiment includes:
[0165] The determination module 1101 is used to determine the target service logic to be switched to when the triggering conditions for processing the target service through the field programmable gate array (FPGA) are met.
[0166] The lookup module 1102 is used to look up the target configuration file of the target service under the target service logic from the stored configuration file set;
[0167] The update module 1103 is used to update the FPGA based on the target configuration file, so that the FPGA switches to the target business logic and processes the target business according to the target business logic.
[0168] In some embodiments, the target service is a service that includes multiple sub-services, and the triggering condition includes receiving a switching instruction for the target service, wherein the switching instruction contains a service logic identifier corresponding to each sub-service. The determining module 1101 is specifically used for:
[0169] The business logic corresponding to each sub-business is determined based on the business logic identifier corresponding to each sub-business.
[0170] The business logic corresponding to each of the various sub-businesses is determined as the target business logic.
[0171] In some embodiments, the lookup module 1102 is specifically used for:
[0172] Find the configuration file for each sub-service under the corresponding business logic from the configuration file set;
[0173] The configuration files corresponding to the various sub-services are determined as the target configuration file.
[0174] In some embodiments, the target service is multiple services, and the triggering condition includes receiving a switching instruction for the target service, wherein the switching instruction contains a service logic identifier corresponding to each service. The determining module 1101 is specifically used for:
[0175] The business logic corresponding to each business is determined based on the business logic identifier corresponding to each business.
[0176] The business logic corresponding to each of the various services is determined as the target business logic.
[0177] In some embodiments, the lookup module 1102 is specifically used for:
[0178] Find the configuration file for each service under the corresponding business logic from the configuration file set;
[0179] The configuration files corresponding to the various services are determined as the target configuration file.
[0180] In some embodiments, the target service is a service corresponding to multiple segments of serial service logic, and the triggering condition includes data processing conditions that satisfy any segment of the service logic. The determining module 1101 is specifically used for:
[0181] The business logic that meets the data processing conditions is identified as the target business logic.
[0182] In some embodiments, it further includes: a preprocessing module 1104, configured to:
[0183] After adding a preset identifier to the business data corresponding to the target business logic, the data is stored in memory. The FPGA reads the business data containing the preset identifier from the memory and executes the instructions corresponding to the business data according to the target business logic.
[0184] In some embodiments, the FPGA is in an online state, and the update processing module 1103 is further configured to:
[0185] Before updating the FPGA based on the target configuration file, access to the FPGA is stopped, and the FPGA's input / output I / O is controlled to enter a holding state.
[0186] After updating the FPGA, the FPGA is initialized, which includes restoring access to the FPGA and switching the FPGA's I / O state to a new I / O state.
[0187] The module division in this application embodiment is illustrative and only represents one logical functional division. In actual implementation, other division methods are possible. Furthermore, the functional modules in each embodiment of this application can be integrated into a single processor, exist as separate physical entities, or be integrated into a single module. Coupling between modules can be achieved through interfaces, typically electrical communication interfaces, but mechanical interfaces or other types of interfaces are also possible. Therefore, modules described as separate components may or may not be physically separate; they can be located in one place or distributed across different locations on the same or different devices. The integrated modules described above can be implemented in hardware or as software functional modules.
[0188] Having introduced the business processing method and apparatus according to exemplary embodiments of this application, we will now introduce an electronic device according to another exemplary embodiment of this application.
[0189] The following reference Figure 12 To describe an electronic device 130 implemented according to this embodiment of the present application. Figure 12 The electronic device 130 shown is merely an example and should not impose any limitations on the functionality and scope of use of the embodiments of this application.
[0190] like Figure 12 As shown, the electronic device 130 is presented in the form of a general-purpose electronic device. The components of the electronic device 130 may include, but are not limited to: at least one processor 131, at least one memory 132, and a bus 133 connecting different system components (including memory 132 and processor 131).
[0191] Bus 133 represents one or more of several bus structures, including a memory bus or memory controller, peripheral bus, processor, or local bus using any of the various bus structures.
[0192] The memory 132 may include a readable medium in the form of volatile memory, such as random access memory (RAM) 1321 and / or cache memory 1322, and may further include read-only memory (ROM) 1323.
[0193] The memory 132 may also include a program / utility 1325 having a set (at least one) of program modules 1324, including but not limited to: an operating system, one or more application programs, other program modules, and program data, each or some combination of these examples may include an implementation of a network environment.
[0194] Electronic device 130 can also communicate with one or more external devices 134 (e.g., keyboard, pointing device, etc.), and with one or more devices that enable a user to interact with electronic device 130, and / or with any device that enables electronic device 130 to communicate with one or more other electronic devices (e.g., router, modem, etc.). This communication can be performed via input / output (I / O) interface 135. Furthermore, electronic device 130 can also communicate with one or more networks (e.g., local area network (LAN), wide area network (WAN), and / or public networks, such as the Internet) via network adapter 136. As shown, network adapter 136 communicates with other modules used in electronic device 130 via bus 133. It should be understood that, although not shown in the figures, other hardware and / or software modules can be used in conjunction with electronic device 130, including but not limited to: microcode, device drivers, redundant processors, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.
[0195] In an exemplary embodiment, a storage medium is also provided, which, when executed by a processor of an electronic device, enables the electronic device to perform any of the aforementioned business processing methods. Optionally, the storage medium may be a non-transitory computer-readable storage medium, such as a ROM, random access memory (RAM), CD-ROM, magnetic tape, floppy disk, and optical data storage device.
[0196] In an exemplary embodiment, the electronic device of this application may include at least one processor and a memory communicatively connected to the at least one processor, wherein the memory stores a computer program that can be executed by the at least one processor, and when the computer program is executed by the at least one processor, it can cause the at least one processor to perform the steps of any business processing method provided in the embodiments of this application.
[0197] In an exemplary embodiment, a computer program product is also provided, which, when executed by an electronic device, enables the electronic device to implement any of the exemplary methods provided in this application.
[0198] Furthermore, computer program products may employ any combination of one or more readable media. A readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: electrical connections having one or more wires, portable disks, hard disks, RAM, ROM, erasable programmable read-only memory (EPROM), flash memory, optical fiber, compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.
[0199] The program product used for business processing in the embodiments of this application may be a CD-ROM and include program code, and may run on a computing device. However, the program product of this application is not limited to this. In this document, the readable storage medium may be any tangible medium that contains or stores a program, which may be used by or in conjunction with an instruction execution system, apparatus, or device.
[0200] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application.
[0201] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, then this application also includes such modifications and variations.
Claims
1. A business processing method, characterized in that, include: When the triggering conditions for processing the target service through a field-programmable gate array (FPGA) are met, the target service logic to be switched to is determined. From the stored set of configuration files, locate the target configuration file for the target service under the target service logic; Based on the target configuration file, the FPGA is updated to switch to the target business logic and the target business is processed according to the target business logic.
2. The method as described in claim 1, characterized in that, The target service is a service that includes multiple sub-services, and the triggering condition includes receiving a switching instruction for the target service, wherein the switching instruction contains a business logic identifier corresponding to each sub-service; Determining the target service logic to be switched to includes: The business logic corresponding to each sub-business is determined based on the business logic identifier corresponding to each sub-business. The business logic corresponding to each of the various sub-businesses is determined as the target business logic.
3. The method as described in claim 2, characterized in that, From the stored configuration file set, locate the target configuration file for the target service under the target service logic, including: Find the configuration file for each sub-service under the corresponding business logic from the configuration file set; The configuration files corresponding to the various sub-services are determined as the target configuration file.
4. The method as described in claim 1, characterized in that, The target service is multiple services, and the triggering condition includes receiving a switching instruction for the target service, wherein the switching instruction contains a business logic identifier corresponding to each service; Determining the target service logic to be switched to includes: The business logic corresponding to each business is determined based on the business logic identifier corresponding to each business. The business logic corresponding to each of the various services is determined as the target business logic.
5. The method as described in claim 4, characterized in that, From the stored configuration file set, locate the target configuration file for the target service under the target service logic, including: Find the configuration file for each service under the corresponding business logic from the configuration file set; The configuration files corresponding to the various services are determined as the target configuration file.
6. The method as described in claim 1, characterized in that, The target service is a service that corresponds to multiple segments of serial business logic, and the triggering conditions include data processing conditions that satisfy any segment of business logic. Determining the target service logic to be switched to includes: The business logic that meets the data processing conditions is identified as the target business logic.
7. The method according to any one of claims 1-6, characterized in that, Processing the target business according to the target business logic includes: After adding a preset identifier to the business data corresponding to the target business logic, it is stored in memory; The FPGA reads the service data containing the preset identifier from the memory and executes the instructions corresponding to the service data according to the target service logic.
8. The method according to any one of claims 1-6, characterized in that, The FPGA is in an online state. Before updating the FPGA's functionality based on the target configuration file, the following steps are also included: Stop accessing the FPGA; Control the FPGA's input / output I / O to enter a holding state; After updating the functionality of the FPGA, the following is also included: The FPGA is initialized, which includes restoring access to the FPGA and switching the FPGA's I / O state to a new I / O state.
9. An electronic device, characterized in that, include: At least one processor, and a memory communicatively connected to said at least one processor, wherein: The memory stores a computer program that can be executed by the at least one processor to enable the at least one processor to perform the method as described in any one of claims 1-8.
10. A computer program product, characterized in that, Includes a computer program that, when executed by a processor, implements the method of any one of claims 1-8.