Test system, configuration method and test method

By displaying the mapping relationship between backplane slots and boards in the interactive interface of the test system, and displaying the mapping relationship between motherboard slots and daughterboards for mother and daughter I/O boards, the inconvenience of wiring caused by the lack of information in the existing technology is solved, and a more intuitive and accurate test environment configuration is achieved.

CN122309255APending Publication Date: 2026-06-30KUNYI ELECTRONICS TECHNOLOGY (SHANGHAI) CO LTD

Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
KUNYI ELECTRONICS TECHNOLOGY (SHANGHAI) CO LTD
Filing Date
2025-11-19
Publication Date
2026-06-30

AI Technical Summary

Technical Problem

The existing testing system has limited information during configuration, leading to inconvenience in wiring and application.

Method used

By displaying the mapping relationship between backplane slots and boards in the interactive interface, and showing the mapping relationship between motherboard slots and daughterboards for mother and daughter I/O boards, more configuration basis is provided.

Benefits of technology

It improves the intuitiveness and accuracy of test environment configuration, reduces the possibility of misconfiguration, and provides sufficient basis for assembly, wiring and verification.

✦ Generated by Eureka AI based on patent content.

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  • Figure CN122309255A_ABST
    Figure CN122309255A_ABST
Patent Text Reader

Abstract

This application relates to a testing system, configuration method, and testing method. The configuration method includes: using a first interface element of an interactive interface to represent a backplane slot and the board connected thereto; if the board connected to the backplane slot is a parent-child I / O board, then using a second interface element of the interactive interface to represent the parent board slot and the child board connected thereto; the test physical channel of the child board in the parent-child I / O board is used to interact with the corresponding communication channel of the device under test or a test auxiliary device; the first interface element and the second interface element can at least be used to guide the user to configure the test environment.
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