External impedance identification and polymorphic address decoding circuit and polymorphic address decoding method

Abstract

This invention discloses an external impedance identification and multi-state address decoding circuit and method, belonging to the field of integrated circuit technology. To address the problems of low input pin utilization and limited address capacity in existing decoders, this invention includes: a power supply voltage divider unit that outputs multiple reference voltages; at least one external resistor identification unit that compares the reference voltages with the input pin voltages, distinguishes various external connection modes of the input pins, and outputs a comparison result signal; a logic unit that performs logic encoding on the comparison result signal and outputs the corresponding binary intermediate code; and a decoding unit that decodes the binary intermediate code and outputs an address selection signal. This invention expands the coded states of a single pin to five or more by identifying different external connection modes of the input pins, significantly increasing the number of decodeable addresses with the same number of pins, reducing the number of chip pins and packaging costs, and possessing good scalability.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and specifically to an off-chip impedance identification and polymorphic address decoding circuit and a polymorphic address decoding method. Background Technology

[0002] Logic circuits with decoding capabilities are typically called decoders. Their function is to convert input encoded signals with specific meanings into corresponding output signals, thereby selecting and activating a specific output from multiple output terminals. Decoders are widely used as fundamental logic units in digital systems and communication interfaces.

[0003] Taking I2C (Inter-Integrated Circuit) bus communication as an example, before a master device can interact with a specific slave device, it must first send the unique address code of that slave device. In order to address as many slave devices as possible with limited chip pin resources, the I2C bus system places high demands on the address decoding circuit, that is, it is expected to decode more address bits with fewer input pins.

[0004] Figure 1 This is a diagram of the most common binary decoder framework in existing technology. As shown in the figure, the working principle of this decoder is to convert n-bit binary input code into 2-bit binary code. n Each input signal has an independent output signal. For example, when n equals 2, it becomes the 2-to-4 line decoder shown in the figure, which can decode a 2-bit binary input signal into 4 high and low level output signals. Binary decoders have simple logic, but their drawback is that the number of outputs is exponentially related to the number of inputs by 2. Although the address space can be expanded by increasing the number of input pins, in integrated circuit design, the number of chip pins is strictly limited by package size, power consumption, and cost. Simply relying on increasing the number of pins to expand the address space would significantly increase chip area and packaging cost, making it an uneconomical solution.

[0005] To address the issue of low pin utilization in binary decoders, tri-state decoders capable of recognizing three input states have emerged in the current technology. Figure 2 This is a schematic diagram of a novel three-state decoder structure in the prior art. As shown in the figure, the input terminals of this novel three-state decoder circuit can not only recognize the traditional high and low levels, but also additionally recognize the "floating" state. By introducing three states—high, low, and floating—the number of encodeable states of a single input pin is increased from two to three, allowing n input pins to generate 3... nCompared to traditional binary decoders, tri-state decoders offer improved address decoding capabilities with the same number of input pins. For example, a tri-state decoder with two input pins can decode nine addresses, while a binary decoder with the same number of pins can only decode four. However, with the widespread application of I2C buses in IoT, industrial control, and other fields, the number of slave devices connected to a single bus is constantly increasing. The address capacity of tri-state decoders is gradually becoming insufficient to meet practical application needs. Furthermore, these decoders have poor scalability and cannot further improve address decoding capabilities without changing the circuit architecture.

[0006] In summary, existing address decoding circuits suffer from low input pin utilization, limited address capacity, and poor scalability. How to significantly improve the address decoding capability of the decoder under the premise of strictly limited input pin count has become a technical problem that urgently needs to be solved in this field. Summary of the Invention

[0007] To alleviate or partially alleviate the above-mentioned technical problems, the solution of the present invention is as follows: On one hand, this invention discloses an off-chip impedance identification and polymorphic address decoding circuit, comprising: The power supply voltage divider unit is used to divide the power supply voltage and output multiple reference voltages with different voltage values; At least one external resistor identification unit is connected to the power supply voltage divider unit to receive the reference voltage, compare the reference voltage with the voltage on an input pin to distinguish the various external connection modes of the input pin, and output the corresponding comparison result signal. A logic unit, connected to the external resistor identification unit, is used to receive the comparison result signal and perform logic encoding on the comparison result signal to output a binary intermediate code that corresponds one-to-one with the various external connection modes. A decoding unit, connected to the logic unit, is used to receive the binary intermediate code and decode the binary intermediate code to output an address selection signal.

[0008] In one embodiment, the off-chip resistor identification unit includes: A unity-gain operational amplifier has a non-inverting input terminal for receiving a first reference voltage and an output terminal connected to its inverting input terminal. The unity-gain operational amplifier clamps the voltage at one end of an internal resistor R0, causing the other end of the internal resistor R0 (i.e., the voltage at the input pin) to form different potentials depending on different external connection methods, which are then identified by the internal comparator. An internal resistor, one end of which is connected to the inverting input of the unity-gain operational amplifier, and the other end of which is connected to the input pin; Multiple comparators are provided, each with its first input terminal connected to the input pin to receive the voltage on the input pin, its second input terminal connected to different reference voltages output by the power supply voltage divider unit, and its output terminal outputting the comparison result signal.

[0009] In one embodiment, the various external connection modes of the input pin include at least the following five: - Directly connected to the power supply voltage; - Connect to the power supply voltage via an external pull-up resistor; - Suspended; - Connected to system ground via an external pull-down resistor; - Directly connected to the system ground.

[0010] In one embodiment, the reference voltage output by the power supply voltage divider unit includes at least: a first reference voltage, a second reference voltage, a third reference voltage, a fourth reference voltage, and a fifth reference voltage; The non-inverting input of the unity-gain operational amplifier is connected to the first reference voltage; The plurality of comparators includes a first comparator, a second comparator, a third comparator, and a fourth comparator; The second input terminals of the first comparator, the second comparator, the third comparator, and the fourth comparator are respectively connected to the second reference voltage, the third reference voltage, the fourth reference voltage, and the fifth reference voltage.

[0011] In one embodiment, the first reference voltage is equal to 0.5 times the power supply voltage; The second reference voltage is equal to 0.9 times the power supply voltage; The third reference voltage is equal to 0.6 times the power supply voltage; The fourth reference voltage is equal to 0.4 times the power supply voltage; The fifth reference voltage is equal to 0.1 times the power supply voltage.

[0012] In one embodiment, the binary intermediate code output by the logic unit is a 3-bit binary code, and the correspondence between the five external connection modes and the 3-bit binary code is as follows: When the input pin is directly connected to the power supply voltage, the logic unit outputs the first group of 3-bit binary code; When the input pin is connected to the power supply voltage through an external pull-up resistor, the logic unit outputs a second set of 3-bit binary code; When the input pin is left floating, the logic unit outputs the third group of 3-bit binary code; When the input pin is connected to the system ground via an external pull-down resistor, the logic unit outputs a fourth group of 3-bit binary code; When the input pin is directly connected to the system ground, the logic unit outputs the fifth group of 3-bit binary code.

[0013] In one embodiment, the number of the off-chip resistor identification unit, the logic unit, and the input pins are all n, where n is an integer greater than or equal to 2; The decoding unit is used to receive n sets of binary intermediate codes and decode them into address selection signals, the number of which is the nth power of the number of external connection modes.

[0014] In one embodiment, the logic unit includes a combinational logic circuit composed of multiple logic gates. The combinational logic circuit is used to receive the comparison result signal and output the binary intermediate code according to a preset truth table.

[0015] On the other hand, this invention discloses a polymorphic address decoding method, applied to the circuit as described in any of the preceding claims, comprising: The power supply voltage is divided by a power supply voltage divider unit to generate multiple reference voltages; The reference voltage is compared with the voltage on an input pin by an external resistor identification unit to distinguish the various external connection modes of the input pin and output the comparison result signal. The comparison result signal is logically encoded by a logic unit to generate a binary intermediate code that corresponds one-to-one with the various external connection modes. The binary intermediate code is decoded by the decoding unit, and an address selection signal is output.

[0016] In one embodiment, the off-chip resistor identification unit includes a unity-gain operational amplifier, an internal resistor, and multiple comparators; The polymorphic address decoding method further includes: The unity-gain operational amplifier clamps one end of the internal resistor to a first reference voltage. Connect the other end of the internal resistor to the input pin to generate a corresponding input voltage on the input pin according to the different external connection modes of the input pin; The input voltage is compared with the corresponding reference voltage using the plurality of comparators to generate the comparison result signal.

[0017] The technical solution of this invention has one or more of the following beneficial technical effects: (1) The invention expands the single-pin state into multiple states by identifying external impedance, which greatly reduces the number of pins and lowers the cost of chip design and packaging.

[0018] (2) By clamping one end of the internal resistor to the reference voltage through a unity gain operational amplifier and combining it with a multi-reference voltage comparator, the five external connection states of direct connection, pull-up, floating, pull-down and direct connection to ground can be accurately distinguished, so as to realize the reliable identification and quantification of external impedance.

[0019] (3) The internal 3-bit intermediate code represents five states, the logic encoding is flexible, and by increasing the number of comparators and reference voltages, it can be extended to seven-state, eight-state and other multi-state decoding. The circuit topology has good design scalability.

[0020] Furthermore, other beneficial effects of the present invention will be mentioned in the specific embodiments. Attached Figure Description

[0021] Figure 1 This is the most common binary decoder framework diagram in existing technology; Figure 2 This is a schematic diagram of a novel three-state decoder structure in the prior art; Figure 3 This is a structural diagram of a 2-input -25-output quinary decoder provided in an embodiment of the present invention; Figure 4 This is a circuit implementation framework diagram of an embodiment of the present invention; Figure 5 This is a schematic diagram of the external resistor connection method and voltage divider principle in an embodiment of the present invention; Figure 6 This is a logic unit circuit structure diagram of an embodiment of the present invention. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0023] To facilitate a clear description of the technical solutions in the embodiments of the present invention, the terms "first" and "second" are used to distinguish identical or similar items with essentially the same function and effect. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or execution order.

[0024] The term "multiple" refers to two or more.

[0025] This invention provides an external impedance identification and multi-state address decoding circuit, primarily applied in chip systems requiring a large number of address configurations, such as I2C communication interfaces. It aims to achieve decoding of more address bits with a limited number of input pins. By accurately identifying the connection state of external resistors, this invention increases the number of encodeable states of a single input pin from the existing two or three to more than five, significantly improving the address decoding capability of the decoder without increasing the number of input pins. This invention mainly includes a power supply voltage divider unit, an external resistor identification unit, a logic unit, and a decoding unit. The output of the power supply voltage divider unit is connected to the reference voltage input of the external resistor identification unit, the output of the external resistor identification unit is connected to the input of the logic unit, and the output of the logic unit is connected to the input of the decoding unit.

[0026] The following text uses a 2-input -25-output quinary decoder as an example, which increases the coded states of a single input pin to 5, to illustrate the concept and specific implementation of the present invention.

[0027] Figure 3 This is a structural diagram of a 2-input-25-output pentatonic decoder provided by an embodiment of the present invention. As shown in the figure, unlike traditional binary decoders or tri-state decoders, this embodiment not only identifies simple high / low or floating states on the input pins, but also accurately determines the different connection methods and impedance characteristics between the external circuit and the input pins through an external impedance identification unit. This expands the number of states that a single input pin can represent from the traditional 2 or 3 to 5. As shown in the figure, when two input pins (A0 and A1) with 5-state recognition capability are used together, the number of state combinations reaches 5×5, or 25. Therefore, without increasing the number of input pins, the number of address bits that can be decoded is significantly increased from 4 in a traditional 2-line to 4-line decoder and 9 in a tri-state decoder to 25, significantly improving the utilization efficiency of the chip pins. Y0-Y24 are the 25 address output terminals of the pentatonic decoder, each output terminal corresponding to a unique address code used to select the corresponding slave device.

[0028] Figure 4 This is a circuit implementation framework diagram of an embodiment of the present invention. As shown in the figure, the circuit mainly includes four functional units: a power supply voltage divider unit, an external resistor identification unit, a logic unit, and a decoding unit. The specific circuit structure, connection relationship, and working principle of each unit will be described in detail below.

[0029] The power supply voltage divider unit divides the power supply voltage VDD according to a preset ratio, outputting multiple stable reference voltages (vref) with defined ratios to the external resistor identification unit, providing a benchmark for subsequent voltage comparison. In this embodiment, the power supply voltage divider unit adopts a resistor series voltage divider structure, sequentially dividing the power supply voltage VDD to generate five reference voltages: 0.5 times the power supply voltage (0.5VDD), 0.9 times the power supply voltage (0.9VDD), 0.6 times the power supply voltage (0.6VDD), 0.4 times the power supply voltage (0.4VDD), and 0.1 times the power supply voltage (0.1VDD). The 0.5VDD reference voltage is output to a unity-gain operational amplifier (UAV) (also known as a buffer) in the external resistor identification unit, while the other four reference voltages are output to the inverting inputs of four comparators in the external resistor identification unit. Those skilled in the art should understand that the power supply voltage divider unit can also use a diode-connected MOSFET voltage divider structure or other equivalent voltage divider structures, as long as it can output stable reference voltages with the above-mentioned ratios, all of which fall within the scope of protection of this invention.

[0030] The external resistor identification unit is the core unit of this invention. It is used to accurately identify the external resistor connection status of the input pin by voltage comparison and convert the analog voltage signal into a level signal that can be processed by digital circuits. This unit includes a unity-gain operational amplifier (buffer), an internal resistor R0, and multiple comparators. The output terminal of the unity-gain operational amplifier is connected to its inverting input terminal to form a voltage follower, while its non-inverting input terminal is connected to a stable reference voltage. In this embodiment, the reference voltage is preferably 0.5 times the power supply voltage (0.5VDD). Based on the "virtual short" working principle of the operational amplifier, one end of the internal resistor R0 connected to the inverting input terminal of the unity-gain operational amplifier is precisely clamped at 0.5VDD voltage. The other end of the internal resistor R0 is connected to the chip's input pin, which is the address input pin of the decoder, and its voltage is denoted as vin.

[0031] Once the chip is powered on, users can connect the chip's input pins to the system power supply VDD, system ground VSS, or leave them floating, depending on application requirements. Figure 4In the diagram, B0-B4 represent the five single-channel state input ports of the decoding unit, corresponding to the five states of a single-channel five-state input. Specifically, the external connection methods include the following five cases: First, the input pin is directly connected to the system power supply VDD (direct connection to high level); second, the input pin is connected to the system power supply VDD through an external pull-up resistor (pull-up); third, the input pin is not connected to any external circuit and is in a floating state (floating); fourth, the input pin is connected to system ground VSS through an external pull-down resistor (pull-down); fifth, the input pin is directly connected to system ground VSS (direct connection to low level).

[0032] Figure 5 This is a schematic diagram of the external resistor connection method and voltage divider principle in an embodiment of the present invention. As shown in the figure, the general calculation formula for the input pin voltage vin is: vin = 0.5VDD + R0×(VX-0.5VDD) / (R+R0), Where VX is the voltage at the external connection terminal (taken as VDD or 0), and R can be R1 or R1', where R1 is the external pull-up resistor value and R1' is the external pull-down resistor value. When the input pin is directly connected to VDD or VSS, R is 0; when the input pin is connected to an external pull-up resistor, R is the corresponding external pull-up resistor value R1; when the input pin is connected to an external pull-down resistor, R is the corresponding external pull-down resistor value R1'; when the input pin is floating, no current flows through the internal resistor R0, and the vin voltage is always equal to 0.5VDD. Through the above voltage divider principle, when the input pin is connected to the external circuit in the above five different ways, it corresponds to five different input states, and each connection method will generate a unique and non-overlapping vin voltage range on the input pin.

[0033] Specifically, when the input pin is directly connected to the system power supply VDD, the vin voltage is pulled close to the system power supply VDD, but higher than 0.9VDD. When the input pin is connected to the system power supply VDD through an external pull-up resistor, the external pull-up resistor and the internal resistor R0 form a voltage divider circuit. Since one end of the internal resistor R0 is clamped at 0.5VDD, the vin voltage will be between 0.6VDD and 0.9VDD. When the input pin is floating, no current flows through the internal resistor R0, so the vin voltage is equal to 0.5VDD. In actual circuits, considering factors such as leakage current, its voltage range is defined between 0.4VDD and 0.6VDD. When the input pin is connected to the system ground VSS through an external pull-down resistor, the external pull-down resistor and the internal resistor R0 form a voltage divider circuit, and the vin voltage will be between 0.1VDD and 0.4VDD. When the input pin is directly connected to the system ground VSS, the vin voltage is pulled close to 0V, but lower than 0.1VDD. Using the voltage divider principle described above, the five different input states are converted into five non-overlapping voltage ranges, providing a foundation for subsequent state recognition.

[0034] To identify these five different voltage ranges, the off-chip resistor identification unit also includes multiple comparators, such as... Figure 4 The comparators shown are comp0, comp1, comp2, comp3, and comp4. One input of each comparator (e.g., the non-inverting input) is connected to a common input pin to receive the VIN voltage, while the other input (e.g., the inverting input) is connected to the respective reference voltages output by the power supply voltage divider unit. Specifically, the reference voltage for comparator comp0 is 0.5VDD, for comparator comp1 it is 0.9VDD, for comparator comp2 it is 0.6VDD, for comparator comp3 it is 0.4VDD, and for comparator comp4 it is 0.1VDD. Each comparator compares the VIN voltage with its corresponding reference voltage and outputs a high or low level signal representing the comparison result. In this embodiment, a high level is output when the voltage at the non-inverting input is higher than that at the inverting input, and a low level is output otherwise. For example, when the VIN voltage is higher than 0.9VDD, comparator comp1 outputs a high level; when the VIN voltage is lower than 0.1VDD, comparator comp4 outputs a low level, and so on. The combination of high and low levels output by this set of comparators actually constitutes a unique code for the five external connection states of the input pin.

[0035] The function of the logic unit is to receive multiple comparator result signals output by the external resistor identification unit, perform logical operations and processing on them, and finally output a set of standardized binary intermediate codes that are easy for subsequent circuits to process. In this embodiment, the intermediate code is preferably a 3-bit binary code to uniquely identify the aforementioned five input states.

[0036] Figure 6 This is the circuit structure diagram of the logic unit in the embodiment of the present invention. As shown in the figure, the logic unit is composed of multiple basic logic gate circuits, such as NOT gates, AND gates, OR gates, etc. In the figure, comp1_out to comp4_out are the output signals of the aforementioned comparators comp1 to comp4 (it should be noted that comp0 can be used as an auxiliary judgment or redundant check in this logic coding). The logic unit performs combinational logic design according to a preset truth table. In this embodiment, the correspondence between the 3-bit intermediate code and the input pin states is shown in Table 1: When vin > 0.9VDD, comparators comp1 to comp4 all output high levels, and the logic unit outputs the intermediate code 100, corresponding to the state where the input pin is connected to VDD; When 0.6VDD < vin < 0.9VDD, comparator comp1 outputs a low level, comp2 to comp4 output high levels, and the logic unit outputs the intermediate code 011, corresponding to the pull-up state of the input pin; When 0.4VDD < vin < 0.6VDD, comparators comp1 and comp2 output low levels, comp3 and comp4 output high levels, and the logic unit outputs the intermediate code 010, corresponding to the floating state of the input pin; When 0.1VDD < vin < 0.4VDD, comparators comp1 to comp3 output low levels, comp4 outputs a high level, and the logic unit outputs the intermediate code 001, corresponding to the pull-down state of the input pin; When vin < 0.1VDD, comparators comp1 to comp4 all output low levels, and the logic unit outputs the intermediate code 000, corresponding to the state where the input pin is connected to VSS.

[0037] Table 1: Input pin states corresponding to the 3-bit intermediate code

[0038] In this way, the logic unit converts the complex analog voltage comparison result into a simple digital signal, realizing the conversion and coding from the analog domain to the digital domain. It is worth emphasizing that this 3-bit intermediate code can theoretically represent up to 8 or 9 states. Therefore, the logic unit of the present invention has good scalability. If more voltage intervals are subdivided by adding comparators in the future, the structure of this logic unit can be slightly modified to support the coding of 7 states, 8 states or even more states.

[0039] The decoding unit receives multiple sets of 3-bit binary intermediate codes from one or more logic units, performs combined decoding, and generates corresponding address selection signals to select the target slave device. The decoding rule of the decoding unit follows a mapping relationship from quinary to multi-ary output. For an input pin and its corresponding logic unit, a set of 3-bit intermediate codes can be decoded to obtain five unique address codes. When the system contains n such input pins, the number of intermediate code sets received by the decoding unit is n (in other words, n is the number of input pins of the decoder), and the total number of addresses it can decode is five raised to the power of n (5^n). n ) . In this embodiment, refer to Figure 3 As shown, n is 2, therefore a total of twenty-five address codes can be obtained. The decoding unit can be implemented using digital circuit design methods well known to those skilled in the art. It can be implemented using AND gates, OR gate arrays, or programmable logic arrays. Alternatively, register-transfer level code can be written using hardware description languages ​​(such as Verilog or VHDL), and a specific gate-level circuit netlist can be generated through logic synthesis and placement and routing. Since its implementation method is relatively conventional, its internal transistor-level circuit details will not be elaborated here.

[0040] Specifically, the workflow of Embodiment 1 of this invention is as follows. When the system is powered on, the power supply voltage divider unit first operates, generating reference voltages of 0.5VDD, 0.9VDD, 0.6VDD, 0.4VDD, and 0.1VDD, and outputting them to the reference voltage input terminal of the corresponding comparator in the external resistor identification unit. Simultaneously, the unity-gain operational amplifier buffer inside the external resistor identification unit clamps the voltage at one end of the internal resistor R0 to 0.5VDD. At this time, the chip's input pin generates the corresponding VIN voltage on the input pin according to the actual connection method of the external user (directly connected to VDD, pull-up, floating, pull-down, or directly connected to VSS). The VIN voltage is simultaneously applied to the non-inverting inputs of all comparators, compared with the reference voltages at their respective inverting inputs, and outputs corresponding high and low level signals to the logic unit. After receiving the output signals from comparators comp1 to comp4, the logic unit performs calculations according to a preset logic relationship to generate the corresponding 3-bit binary intermediate code A<2:0> (A2, A1, A0, where A2 is the most significant bit and A0 is the least significant bit) and outputs it to the decoding unit. The decoding unit receives the 3-bit intermediate code groups corresponding to all input pins, performs combined decoding, and outputs a unique and valid address selection signal to select the corresponding slave device, completing the entire address decoding process.

[0041] It should be noted that this invention has strong scalability and is not limited to the above-described five-state address decoding embodiment. Those skilled in the art can, according to actual application needs, increase the number of voltage divider nodes in the power supply voltage divider unit and the number of comparators in the external resistor identification unit to more finely divide the voltage identification range of the input pins, thereby achieving 7-state, 8-state, or even more-state address decoding. Furthermore, since the logic unit uses a 3-bit intermediate code for encoding, it can support up to 9 different input states. Therefore, when expanding the input states, there is no need to modify the overall architecture of the logic unit; only the connection relationship of the internal logic gates needs to be adjusted. The decoding unit also only needs to adjust the decoding mapping relationship accordingly to adapt to the address decoding requirements of more states, further reducing the circuit modification cost.

[0042] In summary, this invention elevates traditional level-state identification to impedance network state identification by introducing off-chip impedance identification technology, achieving five-state differentiation on a single input pin. This not only significantly improves address decoding efficiency, reduces the number of chip pins, and lowers packaging costs, but also, because its core lies in voltage range comparison, it can be flexibly extended to more states by adding comparators and adjusting the reference voltage, demonstrating strong design flexibility and technological foresight.

[0043] To better illustrate the present invention, numerous specific details have been provided in the detailed embodiments described above. Those skilled in the art should understand that the present invention can be practiced even without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art have not been described in detail in order to highlight the main points of the present invention.

[0044] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. An off-chip impedance identification and polymorphic address decoding circuit, comprising: include: The power supply voltage divider unit is used to divide the power supply voltage and output multiple reference voltages with different voltage values; At least one external resistor identification unit is connected to the power supply voltage divider unit to receive the reference voltage, compare the reference voltage with the voltage on an input pin to distinguish the various external connection modes of the input pin, and output the corresponding comparison result signal. A logic unit, connected to the external resistor identification unit, is used to receive the comparison result signal and perform logic encoding on the comparison result signal to output a binary intermediate code that corresponds one-to-one with the various external connection modes. A decoding unit, connected to the logic unit, is used to receive the binary intermediate code and decode the binary intermediate code to output an address selection signal.

2. The off-chip impedance identification and multi-modal address decoding circuit of claim 1, wherein, The off-chip resistor identification unit includes: A unity-gain operational amplifier, whose non-inverting input is used to receive a first reference voltage, and whose output is connected to its inverting input. An internal resistor, one end of which is connected to the inverting input of the unity-gain operational amplifier, and the other end of which is connected to the input pin; Multiple comparators are provided, each with its first input terminal connected to the input pin to receive the voltage on the input pin, its second input terminal connected to different reference voltages output by the power supply voltage divider unit, and its output terminal outputting the comparison result signal.

3. The off-chip impedance identification and multi-modal address decoding circuit of claim 2, wherein, The input pins have at least the following five external connection modes: - Directly connected to the power supply voltage; - Connect to the power supply voltage via an external pull-up resistor; - Suspended; - Connected to system ground via an external pull-down resistor; - Directly connected to the system ground.

4. The off-chip impedance identification and multi-modal address decoding circuit of claim 3, wherein, The reference voltage output by the power supply voltage divider unit includes at least: a first reference voltage, a second reference voltage, a third reference voltage, a fourth reference voltage, and a fifth reference voltage; The non-inverting input of the unity-gain operational amplifier is connected to the first reference voltage; The plurality of comparators includes a first comparator, a second comparator, a third comparator, and a fourth comparator; The second input terminals of the first comparator, the second comparator, the third comparator, and the fourth comparator are respectively connected to the second reference voltage, the third reference voltage, the fourth reference voltage, and the fifth reference voltage.

5. The external impedance identification and polymorphic address decoding circuit according to claim 4, characterized in that: The first reference voltage is equal to 0.5 times the power supply voltage; The second reference voltage is equal to 0.9 times the power supply voltage; The third reference voltage is equal to 0.6 times the power supply voltage; The fourth reference voltage is equal to 0.4 times the power supply voltage; The fifth reference voltage is equal to 0.1 times the power supply voltage.

6. The off-chip impedance identification and multi-modal address decoding circuit of claim 4 or 5, wherein, The binary intermediate code output by the logic unit is a 3-bit binary code, and the correspondence between the five external connection modes and the 3-bit binary code is as follows: When the input pin is directly connected to the power supply voltage, the logic unit outputs the first group of 3-bit binary code; When the input pin is connected to the power supply voltage through an external pull-up resistor, the logic unit outputs a second set of 3-bit binary code; When the input pin is left floating, the logic unit outputs the third group of 3-bit binary code; When the input pin is connected to the system ground via an external pull-down resistor, the logic unit outputs a fourth group of 3-bit binary code; When the input pin is directly connected to the system ground, the logic unit outputs the fifth group of 3-bit binary code.

7. The external impedance identification and polymorphic address decoding circuit according to claim 1, characterized in that: The number of the external resistor identification unit, the logic unit, and the input pins are all n, where n is an integer greater than or equal to 2; The decoding unit is used to receive n sets of binary intermediate codes and decode them into address selection signals, the number of which is the nth power of the number of external connection modes.

8. The external impedance identification and polymorphic address decoding circuit according to claim 1, characterized in that: The logic unit includes a combinational logic circuit composed of multiple logic gates. The combinational logic circuit is used to receive the comparison result signal and output the binary intermediate code according to a preset truth table.

9. A method of multi-state address decoding, applied to the circuit of any one of claims 1 to 8, characterized in that, include: The power supply voltage is divided by a power supply voltage divider unit to generate multiple reference voltages; The reference voltage is compared with the voltage on an input pin by an external resistor identification unit to distinguish the various external connection modes of the input pin and output the comparison result signal. The comparison result signal is logically encoded by a logic unit to generate a binary intermediate code that corresponds one-to-one with the various external connection modes. The binary intermediate code is decoded by the decoding unit, and an address selection signal is output.

10. The method of claim 9, wherein, The off-chip resistor identification unit includes a unity-gain operational amplifier, an internal resistor, and multiple comparators; The polymorphic address decoding method further includes: The unity-gain operational amplifier clamps one end of the internal resistor to a first reference voltage. Connect the other end of the internal resistor to the input pin to generate a corresponding input voltage on the input pin according to the different external connection modes of the input pin; The input voltage is compared with the corresponding reference voltage using the plurality of comparators to generate the comparison result signal.

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