Inter-nuclear communication methods, devices, equipment, media and chips

Abstract

This disclosure proposes an inter-core communication method, apparatus, device, medium, and chip. The method includes: in response to receiving a target message for inter-core communication between a first processor core and a second processor core, locking an inter-core channel in a shared state, wherein the shared state characterizes the state of a communication channel usable by all processor cores; and performing inter-core communication of the target message through the locked inter-core channel, wherein the locked inter-core channel is used only for inter-core communication between the first and second processors. This eliminates the need to construct separate communication channels for each processor core requiring communication, reducing resource consumption during inter-core communication, lowering the possibility of information leakage and tampering during inter-core communication, improving information security during inter-core communication, and thus enhancing the security and stability of system operation.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, and in particular to an inter-core communication method, apparatus, device, medium, and chip. Background Technology

[0002] With the development of technology, the integration of chips is becoming higher and higher. Multiple processor cores can be integrated into a system-on-a-chip. In this scenario, it is necessary to rely on inter-core communication between the processor cores to achieve the normal operation of the system-on-a-chip. Therefore, the information security during inter-core communication between the processor cores is very important. Summary of the Invention

[0003] This disclosure aims to at least partially address one of the technical problems in the related art.

[0004] Therefore, the first aspect of this disclosure proposes an inter-core communication method.

[0005] The second aspect of this disclosure proposes an inter-nuclear communication device.

[0006] The third aspect of this disclosure proposes an electronic device.

[0007] The fourth aspect of this disclosure provides for a computer-readable storage medium.

[0008] The fifth aspect of this disclosure proposes a chip.

[0009] The first aspect of this disclosure proposes an inter-core communication method, comprising: in response to receiving a target message for inter-core communication between a first processor core and a second processor core, locking an inter-core channel in a shared state, wherein the shared state is used to characterize the state of a communication channel that can be used by each processor; and performing inter-core communication of the target message through the locked inter-core channel, wherein the locked inter-core channel is used only for inter-core communication between the first processor and the second processor.

[0010] A second aspect of this disclosure provides an inter-core communication device, comprising: a locking module, configured to lock an inter-core channel in a shared state in response to receiving a target message for inter-core communication between a first processor core and a second processor core, wherein the shared state characterizes the state of a communication channel that can be used by each processor; and a communication module, configured to perform inter-core communication of the target message through the locked inter-core channel, wherein the locked inter-core channel is used only for inter-core communication between the first processor and the second processor.

[0011] A third aspect of this disclosure provides an electronic device comprising: a processor; and a memory for storing executable instructions of the processor; wherein the processor is configured to execute instructions to implement the inter-core communication method as described in the first aspect above.

[0012] The fourth aspect of this disclosure provides a computer-readable storage medium that, when the instructions in the computer-readable storage medium are executed by a processor of an electronic device, enables the electronic device to perform the inter-core communication method as described in the first aspect above.

[0013] The fifth aspect of this disclosure provides a chip including one or more interface circuits and one or more processors; the interface circuits are configured to receive signals and send the signals to the processors, the signals including computer instructions stored in a memory, which, when executed by the processors, cause the chip to perform the inter-core communication method as described in the first aspect above.

[0014] The inter-core communication method and apparatus proposed in this disclosure, upon receiving a target message requiring inter-core communication between a first processor core and a second processor core, locks the inter-core channel in a shared state and performs inter-core communication of the target message through the locked inter-core channel. In this disclosure, after receiving the target message, the inter-core channel is locked, and inter-core communication between the first and second processor cores is performed through the locked inter-core channel. Adjusting the shared inter-core channel to a locked state before inter-core communication eliminates the need to construct separate communication channels for each processor core requiring communication, reducing resource consumption in inter-core communication. Since the locked inter-core channel is used only for inter-core communication between the first and second processor cores, the possibility of information leakage and tampering during inter-core communication is reduced, improving information security and thus enhancing the security and stability of system operation.

[0015] It should be understood that the description herein is not intended to identify key or essential features of the embodiments thereof, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0016] The above and / or additional aspects and advantages of this disclosure will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, in which:

[0017] Figure 1 This is a flowchart illustrating an embodiment of an inter-core communication method according to the present disclosure; Figure 2 This is a flowchart illustrating an inter-core communication method according to another embodiment of the present disclosure; Figure 3 This is a flowchart illustrating an inter-core communication method according to another embodiment of the present disclosure; Figure 4 This is a flowchart illustrating an inter-core communication method according to another embodiment of the present disclosure; Figure 5 This is a schematic diagram of the structure of an inter-core communication device according to an embodiment of the present disclosure; Figure 6 This is a schematic diagram of the structure of an electronic device according to an embodiment of the present disclosure; Figure 7 This is a schematic diagram of the structure of a chip according to an embodiment of the present disclosure. Detailed Implementation

[0018] Embodiments of this disclosure are described in detail below. Examples of these embodiments are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this disclosure, and should not be construed as limiting this disclosure.

[0019] The following description, with reference to the accompanying drawings, outlines an inter-core communication method, apparatus, device, medium, and chip according to embodiments of this disclosure.

[0020] Figure 1 This is a flowchart illustrating an embodiment of an inter-core communication method of this disclosure, as shown below. Figure 1 As shown, the method includes: S101, in response to receiving a target message for inter-core communication between the first processor core and the second processor core, the inter-core channel in the shared state is locked, wherein the shared state is used to characterize the state of the communication channel that can be used by each processor core.

[0021] In this embodiment of the disclosure, multiple processors can be deployed on the System on a Chip (SOC), and each processor can include multiple processor cores. In this scenario, the normal operation of the System on a Chip can be achieved based on the communication between the processor cores.

[0022] In this scenario, communication between processor cores can be defined as inter-core communication.

[0023] In this embodiment of the disclosure, the two processor cores that perform inter-core communication can be respectively designated as the first processor core and the second processor core. As an example, for instance... Figure 2 As shown, in Figure 2 The scenario shown includes n processor cores: P1, P2, ..., Pn. Processor core P1 and processor core Pn need to communicate via... Figure 2 If the inter-core communication interface shown is used for inter-core communication, then in this scenario, processor core P1 and processor core Pn can be identified as the first processor core and the second processor core, respectively.

[0024] In some possible implementations, the system-on-a-chip provides a communication channel shared by each processor core for inter-core communication. This communication channel can be defined as a shared inter-core channel, meaning that when the communication channel is idle, it is in a shared state.

[0025] In this scenario, when the first processor core and the second processor core need to communicate with each other, information exchange can be achieved based on this channel. The message that needs to be communicated between the first processor core and the second processor core can be identified as the target message.

[0026] In some possible implementations, an inter-core communication channel can be provided for communication between processor cores through an inter-core communication interface set in the system, and the communication status of the inter-core channel can be adjusted through the inter-core communication interface.

[0027] In a scenario where the first processor core is the sender of the target message and the second processor core is the receiver of the target message, when the first processor core can transmit the target message that needs to be communicated between the cores to the inter-core communication interface, the inter-core communication interface can determine that the first processor core and the second processor core in the current system need to communicate the target message between them. In this scenario, the inter-core communication interface can adjust the communication status of the inter-core channel in the shared state, lock the communication permission of the inter-core channel between the first processor core and the second processor core, and at the same time close the usage permission of the inter-core channel for other processor cores.

[0028] In other words, once locked, the inter-core channel enables inter-core communication between the first and second processor cores, but other processor cores in the system cannot access the inter-core channel.

[0029] S102, target message inter-core communication is performed through the locked inter-core channel, wherein the locked inter-core channel is only used for inter-core communication between the first processor and the second processor.

[0030] In this embodiment of the disclosure, the channel status of the inter-core channel can be adjusted through the inter-core communication interface, such as... Figure 2 As shown, in Figure 2 In the process, processor cores P1, P2, ..., Pn can communicate with each other via... Figure 2 The inter-core communication interface shown provides an inter-core channel for inter-core communication, which then enables inter-core communication. Figure 2 In the scenario shown, the state of the inter-core channel can be adjusted through this inter-core communication interface.

[0031] In other words, when inter-core communication is not required between processor cores P1, P2, ..., Pn, the inter-core channel is placed in a shared state. When inter-core communication is required between the first processor core P1 and the second processor core Pn, the inter-core channel is placed in a locked state that is only open to the first processor core P1 and the second processor core Pn, and access from other processor cores P2, P3, ..., Pn-1 is denied.

[0032] In this embodiment of the disclosure, the message used for communication between the first processor core and the second processor core can be identified as the target message. After the inter-core communication interface locks the inter-core channel, the first processor core and the second processor core can achieve inter-core communication of the target message through the locked inter-core channel.

[0033] The inter-core communication method proposed in this disclosure locks the shared inter-core channel when receiving a target message requiring inter-core communication between a first processor core and a second processor core, and then performs inter-core communication of the target message through the locked inter-core channel. In this disclosure, after receiving the target message, the inter-core channel is locked, and inter-core communication between the first and second processor cores is performed through the locked inter-core channel. Adjusting the shared inter-core channel to a locked state before inter-core communication eliminates the need to construct separate communication channels for each processor core requiring communication, reducing the resource consumption of inter-core communication. The locked inter-core channel is used only for inter-core communication between the first and second processor cores, reducing the possibility of information leakage and tampering during inter-core communication, improving the information security of inter-core communication, and thus improving the security and stability of system operation.

[0034] In the above embodiments, the locking of inter-core channels and inter-core communication of target messages can also be combined with... Figure 3 understand, Figure 3 This is a flowchart illustrating another embodiment of the inter-core communication method of this disclosure, as shown below. Figure 3 As shown, the method includes: S301, in response to receiving a target message for inter-core transmission between the first processor core and the second processor core, configure permissions for the first processor core and the second processor core to lock the inter-core channel in the shared state.

[0035] The shared state is used to characterize the state of the communication channel that can be used by each processor.

[0036] In some possible implementations, communication authorization is granted to at least some of the processor cores in the system before inter-core communication is performed, and inter-core communication is performed among the processor cores after communication authorization.

[0037] In this embodiment of the disclosure, the system may include multiple processor cores, wherein the inter-core communication interface can provide a channel for at least some of the processor cores to communicate with each other. In some possible implementations, the inter-core communication interface can obtain the processor core that needs to provide a communication channel and authorize it to communicate based on the communication authorization method in the related art. The authorized processor core can then use the inter-core channel provided by the inter-core communication interface to realize inter-core communication with other processor cores.

[0038] In this embodiment of the disclosure, when the inter-core communication interface receives a target message, the access permissions of each processor core to the inter-core channel can be configured, thereby locking the inter-core channel so that it only grants communication permissions to the first processor core and the second processor core.

[0039] In some possible implementations, access permissions for the inter-core channel are configured for the first processor core and the second processor core, and access permissions for the inter-core channel are denied for the remaining processor cores in the system, in order to lock the inter-core channel, wherein the remaining processor cores are the processor cores in the system other than the first processor core and the second processor core.

[0040] In this embodiment of the disclosure, the permission to allow a processor core to use the inter-core channel for inter-core communication can be defined as the permission to use the inter-core channel, and the permission to deny a processor core the right to use the inter-core channel so that it cannot use the inter-core channel for communication can be defined as the permission to deny access.

[0041] In this scenario, after receiving the target message, the inter-core communication interface can configure access permissions for the inter-core channel to the first processor core and the second processor core based on the communication channel access permission configuration method in related technologies. At the same time, it can configure denied access permissions for the remaining processor cores other than the first and second processor cores among the authorized processor cores. Thus, after the permission configuration, the inter-core channel is only open to the first and second processor cores, and other processor cores cannot use it, thereby realizing the switching of the inter-core channel from a shared state to a locked state.

[0042] S302 transmits the target message to the second processor core through the locked inter-core channel.

[0043] In some possible implementations, after the target message is transmitted to the receiving second processor core via the locked inter-core channel, a message reception response is received from the second processor core, and the message reception response is returned to the first processor core via the locked inter-core channel. The message reception response is sent after the second processor core has successfully verified the security of the target message.

[0044] In a scenario where the first processor core is the sender and the second processor core is the receiver, after the inter-core communication interface transmits the target message sent by the first processor core to the second processor core through a locked inter-core channel, the second processor core can return a corresponding response from the inter-core communication interface after receiving the target message, and this response can be identified as a message reception response.

[0045] In this scenario, after receiving the target message, the second processor core can perform security verification on the received target message based on the verification method in the relevant technology. When the target message passes the security verification, the second processor core can determine that the target message received is a message transmitted by the first processor core. In this scenario, the second processor core can generate corresponding response information based on the response information generation algorithm deployed on it, and determine the response information as the message reception response of the target message, and then transmit it to the inter-core communication interface through the locked inter-core channel.

[0046] In this scenario, once the inter-core communication interface receives the message reception response from the second processor core, it can transmit it to the first processor core through the locked inter-core channel.

[0047] It should be noted that once the first processor core receives the message reception response from the second processor core, it can be determined that the current inter-core communication between the first and second processor cores can end. In this scenario, the locked inter-core channel needs to be adjusted to restore it to a shared state.

[0048] In some possible implementations, in response to the permission cleanup task being triggered, the denied access permissions configured on the remaining processor cores in the system are cancelled to restore the locked inter-core channels to a shared state.

[0049] In this embodiment of the present disclosure, when the first processor core receives the message reception response returned by the second processor core, it can be determined that the state of the inter-core channel needs to be restored to the shared state. The task of restoring the inter-core channel to the shared state can be identified as a permission clearing task.

[0050] In some possible implementations, the permission clearing task is triggered in response to the first processor core receiving a message reception response to the target message, or in response to the second processor core timeout.

[0051] In other words, when the first processor core receives a message reception response from the second processor core, it can be determined that the permission clearing task of the inter-core channel has been triggered.

[0052] During inter-core communication, communication anomalies may occur. In this scenario, the response time of the second processor core can be used to determine whether a communication anomaly has occurred. That is, if the first processor core does not receive a message reception response within a set time, it can be determined that the second processor core has experienced a response timeout. In this scenario, in order to ensure the normal operation of the system, the locked inter-core channel can be restored to the shared state first.

[0053] In other words, when the second processor core times out, it can be determined that the permission clearing task has been triggered.

[0054] In this scenario, for the remaining processor cores in the system that are configured with denied access permissions, the denied access permissions configured for the remaining processor cores can be processed based on the permission cancellation method in related technologies to cancel the denied access permissions configured for the remaining processor cores. In this scenario, all authorized processor cores in the system can access the inter-core channel, thereby realizing the restoration of the inter-core channel to a shared state.

[0055] It should be noted that in the event of an anomaly in the target message communication process, the first processor core can attempt to send the target message again by restoring the shared state of the inter-core channel, or it can handle the situation based on other configured anomaly handling strategies, which are not specifically limited here.

[0056] The inter-core communication method proposed in this disclosure locks the inter-core channel through the permission configuration of each processor core after receiving the target message. This reduces the complexity of the inter-core channel locking operation and improves the locking efficiency and accuracy. Inter-core communication between the first processor core and the second processor core is carried out through the locked inter-core channel. Inter-core communication is performed after adjusting the shared inter-core channel to the locked state. There is no need to build a separate communication channel for each processor core that needs to communicate, which reduces the resource consumption of inter-core communication. The locked inter-core channel is only used for inter-core communication between the first processor core and the second processor core, which reduces the possibility of information leakage and information tampering during inter-core communication, improves the information security of inter-core communication, and thus improves the security and stability of system operation.

[0057] To better understand the above embodiments, it can be combined with Figure 4 , Figure 4 This is a flowchart illustrating another embodiment of the inter-core communication method of this disclosure, as shown below. Figure 4 As shown, the method includes: S401, the first processor core transmits the target message to the inter-core communication interface.

[0058] S402, the inter-core communication interface locks the inter-core channel, allowing only the first processor core and the second processor core to access it.

[0059] S403, the inter-core communication interface, transmits target messages to the second processor core.

[0060] S404, the second processor core, performs security verification of the target message.

[0061] S405, the inter-core processor core receives the message reception response of the target message returned by the second processor core.

[0062] S406, the inter-core communication interface transmits the message reception response of the target message to the first processor core.

[0063] S407: Clear permissions on the inter-core communication interface and restore the inter-core channel to a shared state.

[0064] like Figure 4 As shown, processor core P1 acts as the first processor core for sending the target message, and processor core P2 acts as the second processor core for receiving the target message. Processor core P1 can transmit the target message to processor core P2. Figure 4 The inter-core communication interface shown provides a shared inter-core channel for authorized processor cores in the system. After receiving the target message sent by P1, it can configure access permissions for processor cores P1 and P2, and configure denied access permissions for the remaining processor cores in the system, thereby locking the inter-core channel so that only processor cores P1 and P2 can access it.

[0065] like Figure 4 As shown, after the inter-core communication interface locks the inter-core channel, the target message can be transmitted to processor core P2 through the locked inter-core channel. After receiving the target message, processor core P2 can perform security verification on the received target message based on its pre-deployed security verification algorithm. When the target message passes the security verification, processor core P2 can generate a message receiving response corresponding to the target message and transmit the message receiving response of the target message to the inter-core communication interface through the locked inter-core channel. After receiving the message receiving response returned by processor core P2, the inter-core communication interface can transmit it to processor core P1 through the locked inter-core channel. After receiving the message receiving response, processor core P1 can determine that the target message has been successfully transmitted to processor core P2. In this scenario, it can be determined that the inter-core communication task between processor core P1 and processor core P2 has been completed.

[0066] like Figure 4 As shown, once the inter-core communication task between processor core P1 and processor core P2 is completed, the permission clearing task of the inter-core channel can be triggered. The inter-core communication interface can cancel the denied access permissions configured for other processor cores, thereby restoring the locked inter-core channel to a shared state for use in the next inter-core communication.

[0067] It should be noted that the inter-core communication interface mentioned above can be built based on the inter-core communication (IPC) mechanism in related technologies, or it can be built based on other mechanisms. No specific limitation is made here.

[0068] The inter-core communication method proposed in this disclosure locks the inter-core channel through the permission configuration of each processor core after receiving the target message. This reduces the complexity of the inter-core channel locking operation and improves the locking efficiency and accuracy. Inter-core communication between the first processor core and the second processor core is carried out through the locked inter-core channel. Inter-core communication is performed after adjusting the shared inter-core channel to the locked state. There is no need to build a separate communication channel for each processor core that needs to communicate, which reduces the resource consumption of inter-core communication. The locked inter-core channel is only used for inter-core communication between the first processor core and the second processor core, which reduces the possibility of information leakage and information tampering during inter-core communication, improves the information security of inter-core communication, and thus improves the security and stability of system operation.

[0069] Corresponding to the inter-core communication methods proposed in the above embodiments, an embodiment of this disclosure also proposes an inter-core communication device. Since the inter-core communication device proposed in this disclosure corresponds to the inter-core communication methods proposed in the above embodiments, the implementation methods of the above inter-core communication methods are also applicable to the inter-core communication device proposed in this disclosure, and will not be described in detail in the following embodiments.

[0070] Figure 5 This is a schematic diagram of the structure of an inter-core communication device according to an embodiment of the present disclosure, as shown below. Figure 5 As shown, the inter-core communication device 500 includes a locking module 51 and a communication module 52, wherein: Locking module 51 is used to lock the inter-core channel in the shared state in response to receiving a target message for inter-core communication between the first processor core and the second processor core, wherein the shared state is used to characterize the state of the communication channel that can be used by each processor. The communication module 52 is used for inter-core communication of target messages through a locked inter-core channel, wherein the locked inter-core channel is only used for inter-core communication between the first processor and the second processor.

[0071] In this embodiment of the disclosure, the locking module 51 is further configured to: in response to receiving a target message for inter-core transmission between the first processor core and the second processor core, configure permissions for the first processor core and the second processor core to lock the inter-core channel in the shared state.

[0072] In this embodiment of the disclosure, the locking module 51 is further configured to: configure access permissions for the inter-core channel for the first processor core and the second processor core, and configure denial access permissions for the inter-core channel for the remaining processor cores in the system, so as to lock the inter-core channel, wherein the remaining processor cores are the processor cores in the system other than the first processor core and the second processor core.

[0073] In this embodiment of the disclosure, the communication module 52 is further configured to: transmit the target message to the second processor core through the locked inter-core channel.

[0074] In this embodiment of the present disclosure, the communication module 52 is further configured to: receive a message reception response returned by the second processor core, and return the message reception response to the first processor core through the locked inter-core channel, wherein the message reception response is sent after the second processor core has passed the security verification of the target message.

[0075] In this embodiment of the disclosure, the apparatus further includes a recovery module, configured to: in response to the permission clearing task being triggered, cancel the denied access permissions configured on the remaining processor cores in the system, so as to restore the locked inter-core channel to a shared state.

[0076] In this embodiment of the disclosure, the recovery module is further configured to: determine that the permission clearing task has been triggered in response to the message receiving response of the first processor core receiving the target message, or the response of the second processor core timeout.

[0077] In this embodiment of the disclosure, the apparatus further includes an authorization module, configured to: authorize communication of at least some processor cores in the system before inter-core communication is performed, and to perform inter-core communication among the processor cores after communication authorization.

[0078] The inter-core communication device proposed in this disclosure, upon receiving a target message requiring inter-core communication between a first processor core and a second processor core, locks the inter-core channel in a shared state and performs inter-core communication of the target message through the locked inter-core channel. In this disclosure, after receiving the target message, the inter-core channel is locked, and inter-core communication between the first and second processor cores is performed through the locked inter-core channel. Adjusting the shared inter-core channel to a locked state before inter-core communication eliminates the need to construct separate communication channels for each processor core requiring communication, reducing the resource consumption of inter-core communication. The locked inter-core channel is used only for inter-core communication between the first and second processor cores, reducing the possibility of information leakage and tampering during inter-core communication, improving the information security of inter-core communication, and thus improving the security and stability of system operation.

[0079] To achieve the above embodiments, this disclosure also provides an electronic device, a computer-readable storage medium, and a computer program product.

[0080] Figure 6 This is a schematic diagram of the structure of an electronic device according to an embodiment of the present disclosure. For example, the electronic device 600 may be a vehicle, mobile phone, computer, digital broadcasting terminal, messaging device, game console, tablet device, medical device, fitness equipment, personal digital assistant, etc.

[0081] Reference Figure 6 The electronic device 600 may include one or more of the following components: processing component 602, memory 604, power component 606, multimedia component 608, audio component 610, input / output (I / O) interface 612, sensor component 614, and communication component 616.

[0082] Processing component 602 typically controls the overall operation of electronic device 600, such as operations associated with display, telephone calls, data communication, camera operation, and recording operations. Processing component 602 may include one or more processors 620 to execute instructions to complete all or part of the steps of the inter-core communication method described above. Furthermore, processing component 602 may include one or more modules to facilitate interaction between processing component 602 and other components. For example, processing component 602 may include a multimedia module to facilitate interaction between multimedia component 608 and processing component 602.

[0083] Memory 604 is configured to store various types of data to support the operation of electronic device 600. Examples of this data include instructions for any application or method operating on electronic device 600, contact data, phonebook data, messages, pictures, videos, etc. Memory 604 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as Static Random Access Memory (SRAM), Electrically Erasable Programmable Read-Only Memory (EEPROM), Erasable Programmable Read-Only Memory (EPROM), Programmable Read-Only Memory (PROM), Read-Only Memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.

[0084] Power component 606 provides power to various components of electronic device 600. Power component 606 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to electronic device 600.

[0085] Multimedia component 608 includes a screen that provides an output interface between electronic device 600 and user. In some embodiments, the screen may include a Liquid Crystal Display (LCD) and a Touch Panel (TP). If the screen includes a Touch Panel, the screen may be implemented as a touchscreen to receive input signals from the user. The Touch Panel includes one or more touch sensors to sense touches, swipes, and gestures on the Touch Panel. The touch sensors may sense not only the boundaries of touch or swipe actions but also the duration and pressure associated with the touch or swipe operation. In some embodiments, multimedia component 608 includes a front-facing camera and / or a rear-facing camera. When electronic device 600 is in an operating mode, such as a shooting mode or video mode, the front-facing camera and / or rear-facing camera may receive external multimedia data. Each front-facing camera and rear-facing camera may be a fixed optical lens system or have focal length and optical zoom capabilities.

[0086] Audio component 610 is configured to output and / or input audio signals. For example, audio component 610 includes a microphone configured to receive external audio signals when electronic device 600 is in an operating mode, such as call mode, recording mode, and voice recognition mode. The received audio signals may be further stored in memory 604 or transmitted via communication component 616. In some embodiments, audio component 610 also includes a speaker for outputting audio signals.

[0087] I / O interface 612 provides an interface between processing component 602 and peripheral interface modules, such as keyboards, click wheels, buttons, etc. These buttons may include, but are not limited to, home buttons, volume buttons, start buttons, and lock buttons.

[0088] Sensor assembly 614 includes one or more sensors for providing state assessments of various aspects of electronic device 600. For example, sensor assembly 614 may detect the on / off state of electronic device 600, the relative positioning of components such as the display and keypad of electronic device 600, changes in position of electronic device 600 or a component of electronic device 600, the presence or absence of user contact with electronic device 600, orientation or acceleration / deceleration of electronic device 600, and temperature changes of electronic device 600. Sensor assembly 614 may include a proximity sensor configured to detect the presence of nearby objects without any physical contact. Sensor assembly 614 may also include an optical sensor, such as a complementary metal-oxide-semiconductor (CMOS) or charge-coupled device image sensor, for use in imaging applications. In some embodiments, sensor assembly 614 may also include an accelerometer, gyroscope, magnetometer, pressure sensor, or temperature sensor.

[0089] Communication component 616 is configured to facilitate wired or wireless communication between electronic device 600 and other devices. Electronic device 600 can access wireless networks based on communication standards, such as WiFi, 4G, or 5G, or combinations thereof. In one exemplary embodiment, communication component 616 receives broadcast signals or broadcast-related information from an external broadcast management system via a broadcast channel. In one exemplary embodiment, communication component 616 also includes a Near Field Communication (NFC) module to facilitate short-range communication. For example, the NFC module may be implemented based on Radio Frequency Identification (RFID), Infrared Data Association (IrDA), Ultra-Wideband (UWB), Bluetooth, and other technologies.

[0090] In an exemplary embodiment, the electronic device 600 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to perform the inter-core communication method described above.

[0091] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory 604 including instructions, which can be executed by a processor 620 of an electronic device 600 to complete the aforementioned inter-core communication method. For example, the non-transitory computer-readable storage medium may be a read-only memory (ROM), a random access memory (RAM), a compact disc read-only memory (CD-ROM), magnetic tape, a floppy disk, and an optical data storage device, etc.

[0092] To implement the above embodiments, this disclosure also proposes a computer-readable storage medium storing computer program instructions thereon, which, when executed by a processor, implement the steps of the inter-core communication method provided in this disclosure.

[0093] Alternatively, the computer-readable storage medium may be ROM, random access memory (RAM), CD-ROM, magnetic tape, floppy disk, and optical data storage device, etc.

[0094] To implement the above embodiments, this disclosure also proposes a chip including an interface circuit and a processing circuit coupled to each other. The interface circuit is used to input or output signals, and the processing circuit is configured to implement the steps of the inter-core communication method provided in this disclosure.

[0095] Figure 7 This is a schematic diagram of the structure of a chip according to an embodiment of this disclosure. See also... Figure 7 The diagram shown is a schematic representation of the structure of chip 700, but it is not limited to this.

[0096] Chip 700 includes processing circuitry 701, which is configured to perform any of the above inter-core communication methods.

[0097] In some embodiments, chip 700 further includes one or more interface circuits 702. Optionally, interface circuit 702 is connected to memory 703, and interface circuit 702 can be used to receive signals from memory 703 or other devices, and interface circuit 702 can be used to send signals to memory 703 or other devices. For example, interface circuit 702 can read instructions stored in memory 703 and send the instructions to processing circuit 701.

[0098] In some embodiments, the interface circuit 702 performs at least one of the communication steps such as sending and / or receiving in the above method, and the processing circuit 701 performs other steps.

[0099] In some embodiments, the terms interface circuit, interface, transceiver pin, transceiver, etc., can be used interchangeably.

[0100] In some embodiments, chip 700 further includes one or more memories 703 for storing instructions. Optionally, all or part of the memories 703 may be located outside of chip 700.

[0101] To implement the above embodiments, this disclosure also proposes a computer program product, including a computer program that, when executed by a processor, implements the steps of the inter-core communication method provided in this disclosure.

[0102] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the following claims.

[0103] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.

Claims

1. A method of inter-core communication, the method comprising: The method comprises: locking an inter-core channel in a shared state in response to receiving a target message for inter-core communication between a first processor core and a second processor core, wherein the shared state is used to represent a state of the communication channel available to each processor core; inter-core communication of the target message through the locked inter-core channel, wherein the locked inter-core channel is only used for inter-core communication between the first processor and the second processor.

2. The method of claim 1, wherein, The method comprises: locking an inter-core channel in a shared state in response to receiving a target message for inter-core communication between a first processor core and a second processor core, wherein the shared state is used to represent a state of the communication channel available to each processor core; 3. The method of claim 2, wherein, The method comprises: locking an inter-core channel in a shared state in response to receiving a target message for inter-core communication between a first processor core and a second processor core, wherein the shared state is used to represent a state of the communication channel available to each processor core; 4. The method of claim 1, wherein, The method comprises: locking an inter-core channel in a shared state in response to receiving a target message for inter-core communication between a first processor core and a second processor core, wherein the shared state is used to represent a state of the communication channel available to each processor core; 5. The method of claim 4, wherein, The method comprises: locking an inter-core channel in a shared state in response to receiving a target message for inter-core communication between a first processor core and a second processor core, wherein the shared state is used to represent a state of the communication channel available to each processor core; 6. The method according to any one of claims 1-5, characterized in that, The method comprises: locking an inter-core channel in a shared state in response to receiving a target message for inter-core communication between a first processor core and a second processor core, wherein the shared state is used to represent a state of the communication channel available to each processor core; 7. The method of claim 6, wherein, The method further comprises: canceling the denial access permission configured by the remaining processor cores in the system to restore the locked inter-core channel to the shared state in response to the permission clearing task being triggered.

8. The method of claim 1, wherein, The method further comprises: determining that the permission clearing task is triggered in response to the first processor core receiving a message reception response of the target message or the second processor core responding timeout.

9. An inter-core communication device, comprising: The method further comprises: authorizing at least part of the processor cores in the system for communication before inter-core communication, and performing inter-core communication among the processor cores after communication authorization. The device comprises: A locking module is used to lock the inter-core channel in a shared state in response to receiving a target message for inter-core communication between a first processor core and a second processor core, wherein the shared state is used to characterize the state of the communication channel that can be used by each processor. A communication module is used for inter-core communication of the target message through the locked inter-core channel, wherein the locked inter-core channel is used only for inter-core communication between the first processor and the second processor.

10. The apparatus of claim 9, wherein, The locking module is also used for: In response to receiving the target message for inter-core transmission between the first processor core and the second processor core, permissions are configured for the first processor core and the second processor core to lock the inter-core channel in the shared state.

11. The apparatus of claim 10, wherein, The locking module is also used for: Configure access permissions for the inter-core channel to the first processor core and the second processor core, and configure denied access permissions for the inter-core channel to the remaining processor cores in the system, thereby locking the inter-core channel, wherein the remaining processor cores are the processor cores in the system other than the first processor core and the second processor core.

12. The apparatus of claim 9, wherein, The communication module is also used for: The target message is transmitted to the second processor core via the locked inter-core channel.

13. The apparatus of any one of claims 9-12, wherein, The device further includes a recovery module for: In response to the permission cleanup task being triggered, the denied access permissions configured on the remaining processor cores in the system are cancelled to restore the locked inter-core channels to the shared state.

14. An electronic device, comprising: include: processor; Memory used to store the processor's executable instructions; The processor is configured to execute instructions to implement the method as described in any one of claims 1-8.

15. A computer-readable storage medium, wherein when instructions in the computer-readable storage medium are executed by a processor of an electronic device, the electronic device is enabled to perform the method as described in any one of claims 1-8.

16. A chip, characterized by The device includes one or more interface circuits and one or more processors; the interface circuits are used to receive signals and send the signals to the processors, the signals including computer instructions stored in a memory, which, when executed by the processor, cause the chip to perform the steps of the method according to any one of claims 1-8.

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