Unified power format file generation method and system, electronic device and readable medium

Abstract

This invention provides a method, system, electronic device, and readable medium for generating a unified power format file, relating to the field of computer technology. In this method, during logical reorganization, a reorganized module-level file is obtained; the module-level file represents the hierarchical relationship between the added logically reorganized module and the underlying modules before logical reorganization. For any logically reorganized module, policy description information corresponding to the target underlying module is obtained to obtain description information to be updated; the target underlying module includes the underlying modules belonging to the next level of the logically reorganized module. The description information to be updated is updated to obtain target policy description information corresponding to the logically reorganized module, and a UPF file corresponding to the target policy description information is generated. Thus, by automatically generating UPF files corresponding to the target policy description information for logically reorganized modules, manual writing is eliminated, resulting in higher generation efficiency.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and in particular to a method, system, electronic device, and readable medium for generating a unified power format file. Background Technology

[0002] As chips integrate more and more functional blocks and become larger, a hierarchical design approach is often adopted, dividing the chip into at least two layers, with each layer corresponding to at least one module. Accordingly, when generating a unified power format (UPF) file for the chip, a corresponding UPF file is generated for each module. Furthermore, since level conversion and voltage domain isolation may be required between modules, low-power strategies (i.e., voltage control strategies) are designed for each module, generating a corresponding UPF file for that voltage control strategy.

[0003] In the backend processing stage, to optimize chip planning, the backend performs logical reorganization of modules. In related technologies, when generating a UPF file equivalent to the reorganized design level, it's necessary to manually write a UPF file corresponding to the voltage control strategy for each reorganized module. This approach suffers from inefficiency. Summary of the Invention

[0004] This invention provides a method, system, electronic device, and readable medium for generating a unified power format file, which can solve the problem of low efficiency.

[0005] To address the aforementioned problems, this invention discloses a method for generating a unified power format file, the method comprising: In the case of logical reorganization, the reorganized module hierarchy file is obtained; the module hierarchy file represents the hierarchical relationship between the added logically reorganized modules and the underlying modules when no logical reorganization was performed. For any of the aforementioned logical restructuring modules, obtain the strategy description information corresponding to the target underlying module to obtain the description information to be updated; the target underlying module includes the underlying module that belongs to the next level module of the logical restructuring module; The description information to be updated is updated to obtain the target policy description information corresponding to the logical reorganization module, and a UPF file corresponding to the target policy description information is generated.

[0006] On the other hand, embodiments of the present invention disclose a method for generating a unified power supply format file in an electronic design automation system, the method comprising: The low-power strategy information extracted from the original UPF file is marked as a user-defined attribute on the design object; the user-defined attribute is associated with and propagated to the design object during the logic reorganization process; After logical reorganization, identify the design objects marked with the low-power strategy information in the design file, and track the change information of the design objects after logical reorganization; Based on the change information and the low-power policy information marked by the design object, obtain the low-power policy information to be updated corresponding to the logic reorganization module, and update the low-power policy information to be updated to obtain the target low-power policy information of the logic reorganization module. Generate a UPF file corresponding to the target low-power strategy information, and based on the UPF file corresponding to the target low-power strategy information, generate a UPF file equivalent to the design layer after the logic reorganization.

[0007] On the other hand, embodiments of the present invention disclose an electronic design automation system, the system comprising: The input interface receives the original UPF file and the logically reassembled file; A graphical user interface engine configured to generate a user interface and trigger corresponding processing flows in response to user actions on the user interface. The processing engine is configured to mark the low-power policy information extracted from the original UPF file as a user-defined attribute to the design object; the user-defined attribute is associated with and propagated to the design object during the logic reorganization process; the design object marked with the low-power policy information is identified in the design file after logic reorganization, and the change information of the design object after logic reorganization is tracked; based on the change information and the low-power policy information marked on the design object, the low-power policy information to be updated corresponding to the logic reorganization module is obtained, and the low-power policy information to be updated is updated to obtain the target low-power policy information of the logic reorganization module; a UPF file corresponding to the target low-power policy information is generated, and a UPF file equivalent to the design level after logic reorganization is generated based on the UPF file corresponding to the target low-power policy information; The output interface outputs a UPF file that is equivalent to the design hierarchy after the logical reorganization.

[0008] In another aspect, embodiments of the present invention disclose an electronic device, including: a processor, a memory, a communication interface, and a communication bus, wherein the processor, the memory, and the communication interface communicate with each other through the communication bus; the memory is used to store at least one executable instruction, the executable instruction causing the processor to execute the aforementioned method.

[0009] This invention also discloses a machine-readable medium storing instructions that, when executed by one or more processors, cause the processors to perform the methods described above.

[0010] The embodiments of the present invention have the following advantages: The unified power format file generation method provided by the embodiments of the present invention, in the case of logical reorganization, obtains a reorganized module-level file; the module-level file represents the hierarchical relationship between the added logical reorganized module and each underlying module when no logical reorganization was performed. For any logical reorganized module, the policy description information corresponding to the target underlying module is obtained to obtain the description information to be updated; the target underlying module includes the underlying module belonging to the next level module of the logical reorganized module. The description information to be updated is updated to obtain the target policy description information corresponding to the logical reorganized module, and a UPF file corresponding to the target policy description information is generated. In this way, by automatically generating the UPF file corresponding to the target policy description information for the logical reorganized module, there is no need for manual writing, thus the generation efficiency is higher.

[0011] Furthermore, compared to manual coding, the UPF file corresponding to the voltage control strategy of the logic reorganization module can be obtained more quickly, thus avoiding development bottlenecks. It also avoids the errors that are prone to occur in manual coding. Attached Figure Description

[0012] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments of the present invention will be briefly introduced below.

[0013] Figure 1 This is a flowchart illustrating the steps of a method for generating a unified power format file according to an embodiment of the present invention. Figure 2 This is a schematic diagram of a low-power constraint file provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of an original module hierarchy file provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of a reorganized module hierarchy file provided in an embodiment of the present invention; Figure 5 This is a schematic diagram of a voltage control strategy defined in an original UPF file provided by an embodiment of the present invention; Figure 6 This is a schematic diagram of another voltage control strategy defined in the original UPF file provided in an embodiment of the present invention; Figure 7 This is a schematic diagram of another voltage control strategy defined in an original UPF file provided by an embodiment of the present invention; Figure 8 This is a schematic diagram of another voltage control strategy defined in an original UPF file provided by an embodiment of the present invention; Figure 9 This is a schematic diagram of a processing flow provided in an embodiment of the present invention; Figure 10 This is a schematic diagram of another processing flow provided by an embodiment of the present invention; Figure 11 This is a schematic diagram of a processing architecture provided by an embodiment of the present invention; Figure 12 This is a flowchart illustrating the steps of a method for generating a unified power format file in an electronic design automation system, as provided in an embodiment of the present invention. Figure 13 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention. Detailed Implementation

[0014] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

[0015] First, an application scenario related to this invention will be described. Currently, in chip design scenarios (e.g., chip power management systems, digital circuit design, etc.), front-end engineers design low-power constraint diagrams. Further, based on the low-power constraint diagrams, automated generation tools generate corresponding UPF files for each module in the diagrams. These low-power constraint diagrams employ low-power design techniques, such as using multi-threshold devices, power gating (PG), etc., to reduce the chip's static power consumption (e.g., reducing leakage power consumption), using integrated clock gating (ICG) units, multiple power supply voltages, dynamic voltage and frequency scaling (DVFS), adaptive voltage and frequency scaling (AVFS), multi-bit flip-flop units, etc., to reduce the chip's dynamic power consumption. Specifically, these low-power techniques can be used as power constraints to design the low-power constraint diagrams.

[0016] In the backend phase, based on information such as the UPF file provided by the frontend, layout planning is performed to complete the physical implementation. During layout planning, factors such as chip compatibility, manufacturing costs, and whether it is conducive to routing are considered. The modules are logically reorganized manually or with the help of automated synthesis tools (such as Electronic Design Automation (EDA) tools). For example, all second-level layers in the original design are adjusted to first-level layers, the original first-level layers are removed to flatten the original logic hierarchy, or the original first-level layers or other layers are combined into a new logic hierarchy, and the original first-level layers become second-level layers to construct a new logic hierarchy.

[0017] After logic reconfiguration, related technologies require manually writing UPF files corresponding to the voltage control strategies for the logic reconfiguration modules. When dealing with large-scale chips, multiple voltage domains, and numerous logic layers in the reconfiguration, this manual approach is extremely labor-intensive, inefficient, and prone to errors. Furthermore, during rapid iteration phases, frequent logic reconfigurations are necessary, and the manual approach cannot quickly obtain UPF files representing the voltage control strategies of the logic reconfiguration modules, creating a development bottleneck.

[0018] Therefore, embodiments of the present invention provide a method for generating a unified power format file, which will be described in detail below.

[0019] Figure 1 This is a flowchart illustrating the steps of a method for generating a unified power format file according to an embodiment of the present invention, as shown below. Figure 1 As shown, the method for generating a unified power format file may include the following steps: Step 101: In the case of logical reorganization, obtain the reorganized module hierarchy file; the module hierarchy file represents the hierarchical relationship between the added logically reorganized module and each underlying module when no logical reorganization was performed.

[0020] Step 102: For any of the aforementioned logical reorganization modules, obtain the strategy description information corresponding to the target underlying module to obtain the description information to be updated; the target underlying module includes the underlying module that belongs to the next level module of the logical reorganization module.

[0021] Step 103: Update the description information to be updated to obtain the target policy description information corresponding to the logical reorganization module, and generate the UPF file corresponding to the target policy description information.

[0022] In this embodiment of the invention, the module hierarchy file can be a reorganized logic architecture diagram file. The module hierarchy file can be manually generated by technicians. For example, it can be created based on the logic reorganization scheme and the logic architecture diagram file before reorganization (referred to as the original module hierarchy file). Alternatively, it can be automatically generated during the logic reorganization process using EDA tools (e.g., DesignCompiler or Genus tools). This embodiment of the invention does not limit this. Correspondingly, the reorganized logic architecture diagram file input by the user can be received to obtain the reorganized module hierarchy file. Alternatively, the reorganized logic architecture diagram file generated by the EDA tool can be read to obtain the reorganized module hierarchy file. The specific method of logic reorganization can be set as needed. For example, the lower-level modules corresponding to the same voltage domain in the original module hierarchy file can be divided into the same module. A voltage domain refers to the parts of a circuit with the same voltage level. Components within this domain operate under the same supply voltage, share the same power network, and can be power-managed independently of other voltage domains. The voltage domain corresponding to a module is the voltage domain used by that module; different modules may have the same voltage domain. Low-power constraint diagrams, also known as low-power constraint files or voltage domain design diagrams, are created by designers based on chip design requirements. As a graphical representation, voltage domain design diagrams describe the modules and voltage domains within a chip, as well as the hierarchical relationships between modules.

[0023] Figure 2 This is a schematic diagram of a low-power constraint file provided in an embodiment of the present invention, such as... Figure 2As shown, taking a scenario with four module levels as an example. The TOP module is the top-level module, and its corresponding voltage domain is a normally open domain of 0.8V. BlockA, BlockB, BlockC, and BlockD are the next-level modules after the TOP module. BlockA, BlockB, BlockC, and BlockD are at the same level, and their respective voltage domains are a normally open domain of 0.8V, a normally turn-off domain of 0.8V, a normally open domain of 0.8V, and a normally open domain of 0.8V. The next-level modules after BlockA include BlockA.1, BlockA.2, and BlockA.3, whose respective voltage domains are a normally open domain of 0.8V, a normally open domain of 0.8V, and a normally open domain of 0.6V. The next level module of Block A.2 includes Block A.2.1 and Block A.2.2. Each of Block A.2.1 and Block A.2.2 has a normally open voltage domain of 0.6V and a turn-off voltage domain of 0.8V. The next level module of Block C includes Block C.1 and Block C.2. Each of Block C.1 and Block C.2 has a normally open voltage domain of 0.6V and a turn-off voltage domain of 1.0V. The next level module of Block D includes Block D.1. Block D.1 has a turn-off voltage domain of 0.8V.

[0024] The control states for the 0.8V turn-off domains are identical; for example, all modules in the 0.8V turn-off domain are powered by the same power supply after being gated. The power gating control signals and switching states are also identical. The 0.6V normally open domain can be powered by a global 0.8V power supply converted to 0.6V via an LDO, supplying power to the modules in the corresponding 0.6V normally open domain. The 1.0V turn-off domain can be controlled by an external 1.0V independent power supply network via an internal power gating unit. In practical applications, modules corresponding to the same voltage domain can be labeled with the same color; for example, modules in the 0.8V turn-off domain are labeled red, those in the 0.6V normally open domain are labeled blue, and those in the 1.0V turn-off domain are labeled green. Modules in the 0.6V normally open domain have higher priority than modules in the 0.8V turn-off domain, and modules in the 0.8V turn-off domain have higher priority than modules in the 1.0V turn-off domain.

[0025] The original module hierarchy file can be obtained by expanding the low-power constraint file into a tree structure. Alternatively, the RTL code of the low-power constraint file can be used as input to an EDA tool, and the original module hierarchy file can be generated based on the code hierarchy output by the EDA tool. The bottom-level modules without logical reorganization refer to the bottom-level modules in the original module hierarchy file; these modules do not have sub-level modules. Figure 3 This is a schematic diagram of an original module hierarchy file provided in an embodiment of the present invention, such as... Figure 3 As shown, the next-level modules of the TOP module include BlockA, BlockB, BlockC, and BlockD. The next-level modules of BlockA include BlockA.1, BlockA.2, and BlockA.3. The next-level modules of BlockA.2 include BlockA.2.1 and BlockA.2.2. The next-level modules of BlockC include BlockC.1 and BlockC.2. The next-level module of BlockD includes BlockD.1. BlockA.1, BlockA.2.1, BlockA.2.2, BlockA.3, BlockB, BlockC.1, BlockC.2, and BlockD.1 do not have next-level modules. Therefore, the underlying modules without logical reorganization include BlockA.1, BlockA.2.1, BlockA.2.2, BlockA.3, BlockB, BlockC.1, BlockC.2, and BlockD.1.

[0026] Furthermore, a logical reorganization module refers to a newly added module in the original module hierarchy file. That is, a logically reorganized module can be a module that did not exist in the original module hierarchy file in the reorganized module hierarchy file, or a module whose name has been updated. For example, Figure 4 This is a schematic diagram of a reorganized module hierarchy file provided in an embodiment of the present invention, such as... Figure 4As shown, the next-level modules of the TOP module include Block I, Block II, and Block III. The next-level modules of Block I include Block A.1, Block A.2.2, Block B, and Block D.1. The next-level modules of Block II include Block A.2.1, Block C.1, and Block A.3. The next-level module of Block III includes Block C.2. This example considers voltage domain integrity, logically reorganizing modules within the same voltage domain to facilitate later routing. In this example, Block I is composed of four modules within the same voltage domain (Block A.1, Block A.2.2, Block B, and Block D.1), which is a 0.8V turn-off domain. Block II is composed of three modules within the same voltage domain (Block A.2.1, Block C.1, and Block A.3), which is a 0.6V normally-on domain. Block III consists of one module (Block C.2), which is a 1.0V turn-off domain. Block I, Block II, and Block III are logic reconfiguration modules. The underlying modules Block A.1, Block A.2.2, Block B, and Block D.1 are the next-level modules of logic reconfiguration module Block I, i.e., the target underlying modules of logic reconfiguration module Block I. The underlying modules Block A.2.1, Block C.1, and Block A.3 are the next-level modules of logic reconfiguration module Block II, i.e., the target underlying modules of logic reconfiguration module Block II. The underlying module Block C.2 is the next-level module of logic reconfiguration module Block III, i.e., the target underlying module of logic reconfiguration module Block III.

[0027] Since the logical reorganization module is a level above the target underlying module and is its parent module, the strategy description information corresponding to the target underlying module can be updated and used as the target strategy description information for the logical reorganization module. Accordingly, the target strategy description information corresponding to the logical reorganization module is output as a UPF file, thus obtaining the UPF file corresponding to the target strategy description information. The UPF file can be a code file; that is, a UPF file can also be called UPF code.

[0028] In summary, the unified power format file generation method provided by this invention, when performing logical reorganization, obtains a reorganized module-level file; the module-level file represents the hierarchical relationship between the added logically reorganized module and the underlying modules before logical reorganization. For any logically reorganized module, the strategy description information corresponding to the target underlying module is obtained to obtain description information to be updated; the target underlying module includes the underlying modules belonging to the next level module of the logically reorganized module. The description information to be updated is updated to obtain the target strategy description information corresponding to the logically reorganized module, and a UPF file corresponding to the target strategy description information is generated. Thus, by automatically generating the UPF file corresponding to the target strategy description information for the logically reorganized module, manual writing is unnecessary, resulting in higher generation efficiency.

[0029] Furthermore, compared to manual coding, the UPF file corresponding to the voltage control strategy of the logic reorganization module can be obtained more quickly, thus avoiding development bottlenecks. It also avoids the errors that are prone to occur in manual coding.

[0030] Optionally, the step of obtaining the strategy description information corresponding to the target underlying module in the embodiments of the present invention may specifically include: Step 1021: For any of the target underlying modules, based on the module name of the target underlying module, search for the strategy name of the voltage control strategy corresponding to the target underlying module from the relational representation information set, and use it as the strategy name to be searched; the relational representation information set is used to represent the correspondence between the module name of each underlying module and the voltage control strategy corresponding to each underlying module.

[0031] Step 1022: For any of the search strategies, based on the strategy name of the search strategy, search for the strategy description information of the search strategy from the strategy description information set; the strategy description information set includes the strategy description information of each voltage control strategy corresponding to each of the underlying modules.

[0032] The strategy description information corresponding to the underlying module describes the voltage control strategy set by that underlying module. For example, the voltage control strategy may include a level shifter strategy and an isolation strategy. In practical applications, when there is interaction between low-voltage domain signals and high-voltage domain signals between two modules, level shifting units are inserted at the voltage domain boundaries. For example, level shifting units are set in modules with higher priority to adjust the voltage of the voltage domain signals. For example, when a low-voltage domain signal is converted to a high-voltage domain signal, an L_H type level shifting unit needs to be set; when a high-voltage domain signal is converted to a low-voltage domain signal, an H_L type level shifting unit needs to be set. Accordingly, a level shifting strategy is set for the module with the level shifting unit, and this level shifting strategy is defined in the UPF file, i.e., a UPF file representing the level shifting strategy is added. For example, taking the signal output from BlockA.1 to BlockA.3 as an example, since the voltage of the voltage domain corresponding to BlockA.1 is higher than the voltage of the voltage domain corresponding to BlockA.3... Therefore, a level conversion strategy representing type H_L can be set for Block A.3, and an H_L type level conversion unit can be inserted into Block A.3. For the signal output from Block A.3 to Block A.1, since the voltage of the voltage domain corresponding to Block A.1 is higher than the voltage of the voltage domain corresponding to Block A.3, a level conversion strategy representing type L_H can be set for Block A.3, and an L_H type level conversion unit can be inserted into Block A.3.

[0033] Isolation control strategies are used to ensure that signals input to normally open or higher-priority power domains that are turn-off regions are clamped to a fixed state (e.g., clamped to a high or low level). For example, when there is interaction between turn-off region signals and normally open voltage domain signals between two modules, isolation units are inserted at the voltage domain boundaries; for example, isolation units are set in the higher-priority module. Accordingly, an isolation control strategy is set for the module with the isolation unit, and this isolation control strategy is defined in the UPF file, i.e., a UPF file representing the isolation control strategy is added. For example, if the voltage domain corresponding to Block A.1 is a turn-off region, and the power gating of Block A.1 is active, to ensure the normal operation of the voltage domain corresponding to Block A.3, which has direct signal interaction with Block A.1, an isolation control strategy can be set for Block A.3, and an isolation unit is inserted in Block A.3 to clamp the signal input to the voltage domain corresponding to Block A.3 from Block A.1 to a fixed state through a predefined special control signal.

[0034] In this embodiment of the invention, the voltage control strategies corresponding to each underlying module can be categorized to generate strategy description information for each underlying module's voltage control strategy, as well as relationship representation information characterizing the correspondence between the module name of the underlying module and the voltage control strategy corresponding to the underlying module. The relationship representation information of all underlying modules constitutes a relationship representation information set. The strategy description information of the voltage control strategies corresponding to all underlying modules constitutes a strategy description information set.

[0035] Specifically, a single relational representation in the relational representation information set represents the correspondence between the module name of a bottom-level module and the voltage control strategy corresponding to that bottom-level module. For example, a single relational representation includes the module name of a bottom-level module and the strategy name of the voltage control strategy corresponding to that bottom-level module. Accordingly, the module name of the target bottom-level module can be matched with the relational representation information in the relational representation information set to find the strategy name of the voltage control strategy corresponding to the target bottom-level module. The found strategy name can then be used as the strategy name of the searched strategy name corresponding to the target bottom-level module.

[0036] A single strategy description in the strategy description information set represents a voltage control strategy. Assuming there are m underlying modules, and these m modules correspond to n voltage control strategies, strategy description information can be generated for each of the n voltage control strategies. These n generated strategy description information sets constitute the strategy description information set. A single strategy description information can include the strategy name of a voltage control strategy and the field values ​​of specified fields within that voltage control strategy. Correspondingly, the strategy name of the strategy to be searched can be matched against the strategy description information in the strategy description information set to find the strategy description information for the target strategy. The strategy description information for the target strategy is the strategy description information corresponding to that target underlying module.

[0037] In this embodiment of the invention, by pre-generating a set of relational representation information and a set of strategy description information, for any target underlying module, based on the module name of the target underlying module, the strategy name of the voltage control strategy corresponding to the target underlying module is searched from the set of relational representation information, and used as the strategy name of the strategy to be searched. For any strategy to be searched, based on the strategy name of the strategy to be searched, the strategy description information of the strategy to be searched is searched from the set of strategy description information. In this way, by performing name matching on the pre-generated set of relational representation information and the set of strategy description information, the strategy description information corresponding to the target underlying module can be obtained, which can ensure the efficiency of obtaining the strategy description information to a certain extent.

[0038] Optionally, prior to step 1021, the embodiments of the present invention may further include the following steps: Step S21: For any of the underlying modules, obtain the strategy defined in the original UPF file that has the same module name as the underlying module, and use it as the voltage control strategy corresponding to the underlying module. Step S22: Generate relational representation information including the module name and the strategy name of the voltage control strategy corresponding to the underlying module; the generated relational representation information constitutes the relational representation information set.

[0039] Step S23: For any voltage control strategy of the underlying module, obtain the strategy name of the voltage control strategy and the field value of the specified field.

[0040] Step S24: Generate strategy description information including the field values ​​of the specified fields and the strategy name; the generated strategy description information constitutes the strategy description information set.

[0041] In this embodiment of the invention, a set of relation representation information can be generated through steps S21 to S22, and a set of strategy description information can be generated through steps S23 to S24.

[0042] Specifically, the original UPF file is the UPF file before logical reorganization. The voltage control strategy defined in the original UPF file can be a voltage control strategy in UPF file format. The code segment containing strategy setting statements in the original UPF file can be searched to obtain the voltage control strategy defined in that original UPF file. Strategy setting statements are statements used to set the voltage control strategy; for example, strategy setting statements can include `set_isolation` statements, `set_isolation_control` statements, and `set_level_shifter` statements, etc. Next, the strategy whose module name in the voltage control strategy defined in the original UPF file is the same as the module name of the underlying module is taken as the voltage control strategy corresponding to that underlying module. For example, the module name included in the voltage control strategy defined in the original UPF file is defined in the `domain` field of that voltage control strategy. For example, if the module name of the underlying module is `BlockA.1`, then the voltage control strategy whose `domain` field value includes `BlockA.1` can be taken as the voltage control strategy corresponding to that underlying module. The strategy name defined in the strategy setting statement of the voltage control strategy corresponding to that underlying module is obtained. For example, Figure 5 This is a schematic diagram of a voltage control strategy defined in an original UPF file according to an embodiment of the present invention, such as... Figure 5As shown, since the domain field value of this voltage control strategy includes the module name: BlockA.1, this voltage control strategy can be identified as the voltage control strategy corresponding to BlockA.1. Accordingly, the strategy name defined in the strategy setting statement of this voltage control strategy (iso_0 in this example) can be obtained. Figure 6 This is a schematic diagram of another voltage control strategy defined in the original UPF file provided in an embodiment of the present invention, such as... Figure 6 As shown, since the domain field value of this voltage control strategy includes the module name: BlockA.1, this voltage control strategy can be identified as the voltage control strategy corresponding to BlockA.1. Accordingly, the strategy name defined in the strategy setting statement of this voltage control strategy (iso_1 in this example) can be obtained. Figure 7 This is a schematic diagram of another voltage control strategy defined in an original UPF file provided by an embodiment of the present invention, such as... Figure 7 As shown, since the domain field value of this voltage control strategy includes the module name: BlockB, this voltage control strategy can be identified as the voltage control strategy corresponding to BlockB. Accordingly, the strategy name defined in the strategy setting statement of this voltage control strategy (iso_2 in this example) can be obtained. Figure 8 This is a schematic diagram of another voltage control strategy defined in an original UPF file provided by an embodiment of the present invention, such as... Figure 8 As shown, since the domain field value of this voltage control strategy includes the module name: BlockA.1, this voltage control strategy can be identified as the voltage control strategy corresponding to BlockA.1. Accordingly, the strategy name defined in the strategy setting statement of this voltage control strategy can be obtained (LS_BlockA3_to_BlockA1 in this example).

[0043] Furthermore, the module name of the underlying module and the strategy name of the voltage control strategy corresponding to the underlying module can be stored according to the first classification template to obtain the relationship representation information corresponding to the underlying module. For example, assuming the strategy name of the voltage control strategy corresponding to BlockA.1 includes iso_0, iso_1, and LS_BlockA3_to_BlockA1, then after writing to the first classification template, a relationship representation information can be classified for BlockA.1. For example, this relationship representation information can be represented as: powerDomainInfo(BlockA.1){iso_0 iso_1 LS_BlockA3_to_BlockA1}. Assuming the strategy name of the voltage control strategy corresponding to BlockB includes iso_2, then after writing to the first classification template, a relationship representation information can be classified for BlockB. For example, this relationship representation information can be represented as: powerDomainInfo(BlockB){iso_2}.

[0044] Furthermore, for any voltage control strategy corresponding to any underlying module, the field values ​​of specified fields in that voltage control strategy can be obtained. These specified fields are pre-defined by the developers. For example, for isolation control strategies, the specified fields may include the domain field, elements field, clamp_value field, isolation_signal field, and isolation_sense field. The domain field represents the voltage domain name corresponding to the module, the elements field represents the transmitted signal, the isolation_signal field represents the control signal, the isolation_sense field represents the control signal state, and the clamp_value field represents the clamp value. For level conversion strategies, the specified fields may include the domain field, elements field, and rule field. The rule field indicates the conversion type.

[0045] The strategy name and field values ​​of specified fields within the voltage control strategy can be stored according to the second classification template to obtain the strategy description information corresponding to the voltage control strategy. For example, for the iso_0 strategy, the strategy description information obtained after writing to the second classification template can be represented as: strategyInfo(iso_0){PD_BlockA.1 iso_ctrl0_A1 low {signal_A1_to_A3_group0} 0}. The field values ​​of the specified fields are set in a preset order (e.g., in this example, the preset order is domain field - isolation_signal field - isolation_sense field - elements field - clamp_value field).

[0046] Furthermore, the generated relation representation information can be added to the same set to obtain a relation representation information set, and the generated policy description information can be added to the same set to obtain a policy description information set.

[0047] In this embodiment of the invention, a strategy whose defined module name is the same as the module name of the underlying module is obtained from the original UPF file and used as the voltage control strategy corresponding to the underlying module. A relationship representation information set can be formed by generating relationship representation information including the module name and the strategy name of the voltage control strategy corresponding to the underlying module. The strategy name of the voltage control strategy and the field values ​​of specified fields are obtained. A strategy description information set can be formed by generating strategy description information including the field values ​​of the specified fields and the strategy name. This allows for efficient acquisition of the relationship representation information set and the strategy description information set, thus facilitating subsequent use.

[0048] Optionally, in this embodiment of the invention, the step of searching for the strategy name of the voltage control strategy corresponding to the target underlying module from the relational representation information set based on the module name of the target underlying module, and using it as the strategy name to be searched, may specifically include: Step 1021a: For any relation representation information in the relation representation information set, if the module name included in the relation representation information is the same as the module name of the target underlying module, then the strategy name defined in the relation representation information is used as the strategy name of the strategy to be searched.

[0049] In this embodiment of the invention, the module name of the target underlying module can be compared with the module names in each relation representation information in the relation representation information set. For example, the module name defined in the powerDomainInfo() part of the relation representation information can be extracted. This module name is then compared with the module name of the target underlying module. If they match, it indicates that the relation representation information corresponds to the target underlying module. Accordingly, the strategy name can be extracted from the relation representation information to obtain the strategy name of the strategy to be searched. For example, assuming the target underlying module is BlockA.1, the strategy names of the strategy to be searched corresponding to BlockA.1 can be extracted: iso_0, iso_1, and LS_BlockA3_to_BlockA1. Assuming the target underlying module is BlockB, the strategy name of the strategy to be searched corresponding to BlockB can be extracted: iso_2.

[0050] In this embodiment of the invention, by setting module names in the relation representation information, the strategy name of the strategy to be searched can be found by comparing the module name of the target underlying module with the module names included in each relation representation information, resulting in high search efficiency.

[0051] Optionally, in this embodiment of the invention, the step of searching for the strategy description information of the strategy to be searched from the strategy description information set based on the strategy name of the strategy to be searched may specifically include: Step 1022a: For any strategy description information in the strategy description information set, if the strategy name included in the strategy description information is the same as the strategy name of the strategy to be searched, then the strategy description information is used as the strategy description information of the strategy to be searched.

[0052] In this embodiment of the invention, the strategy name of the strategy to be searched can be compared with the strategy names in each strategy description information in the strategy description information set. For example, the strategy name defined in the strategyInfo() part of the strategy description information can be extracted. This strategy name is then compared with the strategy name of the strategy to be searched. If they match, it indicates that the strategy description information is the strategy description information corresponding to the strategy to be searched. Accordingly, this strategy description information can be determined as the strategy description information of the strategy to be searched. For example, assuming the strategy name of the strategy to be searched is iso_0, then strategyInfo(iso_0) {PD_BlockA.1 iso_ctrl0_A1 low {signal_A1_to_A3_group0} 0} can be determined as the strategy description information of the strategy to be searched.

[0053] In this embodiment of the invention, by setting a strategy name in the strategy description information, the strategy description information of the strategy to be searched can be obtained by comparing the strategy name of the strategy to be searched with the strategy names included in each strategy description information, resulting in high search efficiency.

[0054] Optionally, in this embodiment of the invention, before obtaining the strategy description information corresponding to the target underlying module, the following steps may be performed: Step S31: Traverse the modules in the module hierarchy file. If the currently traversed module is a logical reorganization module, then traverse the next level module of the logical reorganization module.

[0055] Step S32: Take the next level module of the current traversal as the target bottom level module.

[0056] Furthermore, the steps described above for obtaining the description information to be updated may include: after completing the traversal of the next level module of the logical reorganization module, using the obtained strategy description information as the description information to be updated.

[0057] In this embodiment of the invention, modules in the module hierarchy file can be traversed. If the original hierarchy file does not include the currently traversed module, then the currently traversed module is determined as a logical reorganization module. Further, the voltage domain corresponding to the logical reorganization module can be found from a preset correspondence between logical reorganization modules and voltage domains (hereinafter referred to as the first correspondence). Then, the underlying module corresponding to the voltage domain of the logical reorganization module is found from a preset correspondence between voltage domains and underlying modules (hereinafter referred to as the second correspondence), thereby obtaining the next-level module of the logical reorganization module. If the logical reorganization module does not have a next-level module, for example, if the logical reorganization module is obtained by renaming an existing underlying module (i.e., the logical reorganization module itself is an underlying module), then the strategy description information corresponding to the logical reorganization module can be directly used as the description information to be updated.

[0058] For example, assuming that in the first correspondence, the voltage domains corresponding to Block I, Block II, and Block III are PD0, PD1, and PD2 respectively, and in the second correspondence, PD0 corresponds to Block A.1, Block A.2.2, Block B, and Block D.1, PD1 corresponds to Block A.2.1, Block C.1, and Block A.3, and PD2 corresponds to Block C.2, then Block A.1, Block A.2.2, Block B, and Block D.1 can be identified as the next-level modules of Block I, Block A.2.1, Block C.1, and Block A.3 as the next-level modules of Block II, and Block C.2 as the next-level module of Block III. The second correspondence can be a predefined data structure, which can be predefined by developers based on low-power constraint diagrams and logic reconfiguration architecture diagrams, including voltage domain names and information such as the modules contained in those voltage domains. For example, this data structure can be represented as: designPDInfo { {PD0 {blockA.1 blockA.2.2 blockB blockD.1}} {PD1 { blockA.3 blockA.2.1 blockC.1}} {PD2 {blockC.2}} } Furthermore, the next-level modules of the logical reorganization module can be traversed, and the traversed next-level modules can be used as the target bottom-level modules. For example, taking Block I as an example, Block A.1 can be traversed first, and Block A.1 can be used as the target bottom-level module. After obtaining the strategy description information corresponding to Block A.1, the next next-level module can be traversed. For example, Block A.2.2 can be traversed, and Block A.2.2 can be used as the target bottom-level module. After obtaining the strategy description information corresponding to Block A.2.2, Block B can be traversed, and Block B can be used as the target bottom-level module. After obtaining the strategy description information corresponding to Block B, Block D.1 can be traversed, and Block D.1 can be used as the target bottom-level module. After obtaining the strategy description information corresponding to BlockD.1, the next level module of the logic reorganization module BlockI is traversed. Accordingly, the obtained strategy description information (e.g., the strategy description information corresponding to BlockA.1, BlockA.2.2, BlockB, and BlockD.1) can be used as the description information to be updated.

[0059] In this embodiment of the invention, modules in the module hierarchy file are traversed. If the currently traversed module is a logical reorganization module, then the next-level modules of the logical reorganization module are traversed. The next-level module is taken as the target bottom-level module. After completing the traversal of the next-level modules of the logical reorganization module, the obtained strategy description information is taken as the description information to be updated. In this way, by traversing the next-level modules of the logical reorganization module, omissions can be avoided, thereby ensuring the comprehensiveness of the obtained description information to be updated.

[0060] Optionally, in this embodiment of the invention, before setting the next level module being traversed as the target bottom-level module, the following steps may be performed: Step S41: For any of the underlying modules, if the voltage control strategy corresponding to the underlying module is not empty, then set a flag for the underlying module.

[0061] Accordingly, the step of taking the next level module of the current traversal as the target bottom level module may specifically include: step S32a, taking the next level module of the current traversal as the target bottom level module when the current level module of the current traversal is marked.

[0062] In this embodiment of the invention, for any underlying module, after generating relational representation information for that underlying module, the relational representation information can be marked for that underlying module in the reorganized module hierarchy file. For example, the relational representation information of the underlying module can be marked as custom attribute information for that underlying module using an EDA tool.

[0063] Furthermore, if the next-level module being traversed is marked, then that next-level module is taken as the target bottom-level module. This avoids unnecessary operations to obtain policy description information. Furthermore, the policy description information of the voltage control policy corresponding to the bottom-level module can also be marked. For example, the policy description information of the voltage control policy corresponding to the bottom-level module can be marked as custom attribute information using an EDA tool. Accordingly, when obtaining the policy description information of the target bottom-level module, the marked policy description information can be read directly to obtain the policy description information corresponding to the target bottom-level module, thus ensuring efficiency.

[0064] Optionally, in this embodiment of the invention, the step of updating the description information to be updated to obtain the target strategy description information corresponding to the logical reorganization module may specifically include: Step 1031: Replace the field values ​​in the description information to be updated with the corresponding reorganized field values.

[0065] Step 1033: Take all the description information to be updated with the same field value as a policy description information group, assign a policy name to the policy description information group, and merge it into a target policy description information based on the assigned policy name and the field values ​​in the policy description information group.

[0066] In this embodiment of the invention, the strategy description information corresponding to each target underlying module can be propagated to the logical reorganization module. For example, the strategy description information corresponding to each target underlying module can be marked for the logical reorganization module. Correspondingly, the strategy description information marked for the logical reorganization module can be used as description information to be updated. For instance, if BlockA.1, BlockA.2.2, BlockB, and BlockD.1 all have corresponding voltage control strategies (i.e., the corresponding voltage control strategies are not empty, and the original UPF file defines strategies with the same module names as these four underlying modules), the strategy description information corresponding to BlockA.1, BlockA.2.2, BlockB, and BlockD.1 can be marked to the BlockI module.

[0067] Furthermore, during logic reorganization, the tracing function of the EDA tool can be enabled to obtain the reorganized field value of a specific field. The specific field can be a field whose value will be affected by the logic reorganization. This specific field can be predefined by the developer, and this embodiment of the invention does not impose any restrictions on it. For example, the specific field may include a domain field, elements field, and isolation_signal field. The voltage domain name corresponding to the module in the specific field can be modified to the voltage domain name corresponding to the connected upper-level logic reorganization module, the module name can be modified to the module name of the connected upper-level logic reorganization module, or the signal above the signal represented by the specific field recorded by the EDA tool can be used as the reorganized field value of the specific field. For example, for any voltage control strategy, the voltage domain name corresponding to the module in the domain field value can be modified to the voltage domain name corresponding to the connected upper-level logic reorganization module to obtain the reorganized field value of the domain field. For example, the reorganized field values ​​corresponding to PD_BlockA.1 and PD_BlockB can be PD_0. Modify the module name in the `elements` field to the module name of the connected parent logical reassembly module, and use it as the reassembled value of the `elements` field. Alternatively, use the parent transmission signal of the transmission signal represented by the `elements` field recorded by the EDA tool as the reassembled value of the `elements` field. Use the parent control signal of the control signal represented by the `isolation_signal` field recorded by the EDA tool as the reassembled value of the `isolation_signal` field.

[0068] Assume the description information to be updated includes: strategyInfo(iso_0){PD_BlockA.1 iso_ctrl0_A1 low {signal_A1_to_A3_group0}0}, strategyInfo(iso_1) {PD_BlockA.1 iso_ctrl0_A1 low {signal_A1_to_A3_group1}1}, strategyInfo(iso_2) {PD_BlockB iso_ctrl1_B low {signal_B_to_BlockC1_group0}0}.

[0069] The recombined field values ​​for PD_BlockA.1 and PD_BlockB are PD0, for iso_ctrl0_A1 and iso_ctrl1_B is iso_ctrl_I, for signal_A1_to_A3_group1 and signal_B_to_BlockC1_group0 is signal_I_to_II_seg0, and for signal_A1_toA3_group1 is signal_I_to_II_seg1. Therefore, the updated description information includes: strategyInfo(iso_0){PD0 iso_ctrl_I low {signal_I_to_II_seg0}0}, strategyInfo(iso_1){PD0 iso_ctrl_I low {signal_I_to_II_seg1}1}, and strategyInfo(iso_2){PD0iso_ctrl_I low {signal_I_to_II_seg0}0}.

[0070] Since the replaced description information to be updated includes description information with consistent field values, merging can continue. The target strategy description information includes the merged description information, and may also include the replaced description information that has not been merged. Further, description information with consistent field values ​​can be grouped as a single strategy description information group, and this group can be categorized as a voltage control strategy of the logic reorganization module. For example, description information with consistent voltage domain, transmission signal, control signal, control signal state, and clamping state (i.e., clamping value) can be merged into a single target strategy description information, that is, merging description information with consistent field values ​​into a single target strategy description information. For example, strategyInfo(iso_0){PD0 iso_ctrl_I low {signal_I_to_II_seg0}0} and strategyInfo(iso_2){PD0iso_ctrl_I low{signal_I_to_II_seg0}0} can be merged. Specifically, a strategy name can be assigned to the strategy description information group composed of these two description information items. Different strategy description information groups are assigned different strategy names. For example, iso_0_I can be used as the assigned strategy name. The assigned strategy name and the field values ​​from the strategy description information group are written into the second classification template to obtain a target strategy description information. For example, the generated target strategy description information can be strategyInfo(iso_0_I){PD0 iso_ctrl_I low {signal_I_to_II_seg0}0}.

[0071] Figure 9 This is a schematic diagram of a processing flow provided by an embodiment of the present invention, such as... Figure 9 As shown, traversal can begin from the top-level module. It determines whether the currently traversed module is a logical reorganization module. If so, it checks if there are any untraversed lower-level modules within that logical reorganization module. If so, it traverses the lower-level modules. It checks if the untraversed lower-level modules are marked with a voltage control strategy. If marked, the strategy description information corresponding to that lower-level module is propagated to the logical reorganization module. If there are no untraversed lower-level modules, the strategy description information (i.e., the description information to be updated) propagated to the logical reorganization module is updated to obtain the target strategy information, and the corresponding UPF file is output. If there are no untraversed modules in the reorganized module hierarchy file, the process ends. If there are untraversed modules in the reorganized module hierarchy file, traversal continues, and the process returns to the step of determining whether the currently traversed module is a logical reorganization module. Figure 10 This is a schematic diagram of another processing flow provided by an embodiment of the present invention, such as... Figure 10 As shown, you can first define the preset voltage domain and its correspondence with the underlying modules, then classify the voltage control strategies corresponding to each underlying module, set tags for the underlying modules, and finally output the UPF file corresponding to the target strategy information.

[0072] It should be noted that, in this embodiment of the invention, relational representation information can also be generated for the logic reorganization module to facilitate the determination of the voltage control strategy corresponding to the logic reorganization module. For example, the module name of the logic reorganization module and all strategy names allocated when generating the target strategy description information for the logic reorganization module can be written into the first classification template to obtain the relational representation information of the logic reorganization module. For example, the relational representation information of BlockI can be: powerDomainInfo(BlockI){ iso_0_I ...} Since the logical reorganization process may cause changes in field values, in this embodiment of the invention, the field values ​​in the description information to be updated are replaced with the corresponding reorganized field values. Then, all the description information to be updated with the same field values ​​are grouped together as a strategy description information group, a strategy name is assigned to the strategy description information group, and based on the assigned strategy name and the field values ​​in the strategy description information group, they are merged into a single target strategy description information. In this way, by first replacing the field values, the accuracy of the generated target strategy description information is ensured.

[0073] Optionally, in this embodiment of the invention, the step of generating the UPF file corresponding to the target policy description information may specifically include: Step 1041: Write the policy name defined in the target policy description information into the name field of the preset file template, and write the values ​​of each field in the target policy description information into the corresponding fields of the preset file template to obtain the UPF file of the target policy description information.

[0074] In this embodiment of the invention, the preset file template can be predefined by the developer. For example, a preset file template can be set based on a voltage control strategy in UPF file format, and the preset file template follows UPF syntax. Accordingly, when the target strategy description information is a level conversion strategy description information, the field values ​​in the target strategy description information are written to the corresponding positions in the preset file template corresponding to the level conversion strategy. When the target strategy description information is an isolation control strategy description information, the field values ​​in the target strategy description information are written to the corresponding positions in the preset file template corresponding to the isolation control strategy.

[0075] For example, the preset file template corresponding to the level conversion strategy may include: set_isolation (strategy name) -domain (voltage domain name) -elements {transmit signals} -clamp_value (clamp value) -isolation_signal (control signal) -isolation_sense (control signal state) Here, `set_isolation` is the name field. For the target strategy description information: `strategyInfo(iso_0_I){ PD0 iso_ctrl_I low {signal_I_to_II_seg0}0}`, after writing the preset file template corresponding to the level conversion strategy, a UPF file of the target strategy description information (i.e., the target strategy in UPF file format) can be obtained. set_isolation iso_0_I -domain PD0 -elements signal_I_to_II_seg0 -clamp_value 0 -isolation_signal iso_ctrl_I -isolation_sense low In this embodiment of the invention, by writing the policy name defined in the target policy description information into the name field of the preset file template, and writing the values ​​of each field in the target policy description information into the corresponding fields of the preset file template, the UPF file of the target policy description information can be obtained, resulting in high code generation efficiency.

[0076] It should be noted that after logical reorganization, it is often necessary to adaptively regenerate the corresponding UPF files for each module. In one related technology, the original UPF file is manually modified according to the module hierarchy file to obtain the UPF files corresponding to each module after logical reorganization. When the chip scale is large, there are many voltage domains, and many reorganized logic layers, manual modification is time-consuming and extremely error-prone, making it impractical. Moreover, during rapid iteration, logical reorganization is required frequently, and manual modification cannot quickly update the UPF file, thus creating a development bottleneck. In this embodiment of the invention, a new power state table can be obtained. This new power state table is input by the user after modifying the power state table before logical reorganization based on the module hierarchy file. The new power state table adapts to the module hierarchy relationship after logical reorganization. For example, the original low-power constraint file can be converted into a low-power constraint file corresponding to the logical reorganization architecture, and the power state table can be modified based on the converted low-power constraint file. The power state table (PSD) records the various modules within the chip and their hierarchical relationships, as well as the various voltage domains and their hierarchical relationships. The PSD includes fields to facilitate subsequent information retrieval. For example, the PSD includes fields reflecting the relationships between modules and voltage domains, the hierarchical relationships between modules, and the power information of the power supplies used by each voltage domain. Furthermore, the new PSD can be input into an automated generation tool to obtain the corresponding UPF files for each module. This approach requires only manual updates to the PSD, minimizing manual editing, and allows for the automated and rapid generation of UPF files for each module after logical reconfiguration, thus shortening UPF file generation time and accelerating design iteration.

[0077] Furthermore, as chips integrate more and more functional blocks and become larger and larger, a hierarchical design approach is typically adopted to cope with ultra-large-scale chip designs. This involves dividing the chip into at least two module levels, one from bottom to top and the other from top to bottom. In this embodiment of the invention, by generating UPF files corresponding to each module, the hierarchical design scenario can be adapted, thereby meeting the needs of large-scale or ultra-large-scale chip designs.

[0078] Furthermore, in this embodiment of the invention, when updating the low-power constraint file and modifying the RTL code, resulting in an update of the module hierarchy and logical reorganization, the target policy description information corresponding to the reorganized module is automatically generated based on the reorganized module hierarchy file, resulting in a UPF file with policy description information adapted to the reorganized module hierarchy. For any logical reorganization, the above-mentioned unified power format file generation method can be executed after the logical reorganization to obtain a UPF file with policy description information adapted to the reorganized module hierarchy. Simultaneously, based on the power state table corresponding to the reorganized module hierarchy file, UPF files corresponding to each module are automatically generated. Thus, the UPF file based on the target policy description information and the UPF files corresponding to each module form a UPF file consistent with the reorganized architecture. The entire process does not require manual code editing by the user, making it applicable to very large-scale integrated circuit scenarios. During the iteration process of code versioning and logical reorganization, rapid updates of the UPF file can be achieved. Furthermore, since no manual editing by the user is required, the probability of errors can be reduced.

[0079] It should be noted that the unified power format file generation method provided by the present invention can be implemented in the form of an algorithm, and when the algorithm is executed, the processing logic of the unified power format file generation method can be executed. Figure 11 This is a schematic diagram of a processing architecture provided by an embodiment of the present invention, such as... Figure 11 As shown, the code generation algorithm can generate a UPF file (referred to as a policy UPF file) representing the target policy description information based on the original UPF file, the recombined module hierarchy file, and the module hierarchy file before recombining. The power state table is modified based on the low-power constraint file and the recombined module hierarchy file, and the corresponding UPF file for each module is generated based on the modified power state table. Finally, a UPF file is obtained, consisting of the UPF file representing the target policy description information and the corresponding UPF files for each module. In this embodiment of the invention, the algorithm automatically generates and recombines the UPF file for the target policy description information of the module hierarchy. Thus, in the event of errors, error correction can be achieved by finding and fixing errors in the algorithm code (debug).

[0080] Figure 12 This is a flowchart illustrating the steps of a method for generating a unified power format file in an electronic design automation system, as provided in an embodiment of the present invention. Figure 12 As shown, the method may include: Step 201: The low-power policy information extracted from the original UPF file is marked as a user-defined attribute on the design object; the user-defined attribute is associated with and propagated to the design object during the logic reorganization process.

[0081] Step 202: Identify the design objects marked with the low-power strategy information in the design file after logic reorganization, and track the change information of the design objects after logic reorganization.

[0082] Step 203: Based on the change information and the low-power policy information marked by the design object, obtain the low-power policy information to be updated corresponding to the logic reorganization module, and update the low-power policy information to be updated to obtain the target low-power policy information corresponding to the logic reorganization module.

[0083] Step 204: Generate a UPF file corresponding to the target low-power strategy information, and based on the UPF file corresponding to the target low-power strategy information, generate a UPF file equivalent to the design layer after the logic reorganization.

[0084] The design object can be a module in the original logical architecture diagram file before reorganization, including the aforementioned underlying modules. The low-power strategy can be the aforementioned voltage control strategy. For any design object, the low-power strategy information can be extracted from the original UPF file. The low-power strategy information can include a first structured data and a second structured data. Specifically, the first structured data can be the aforementioned powerDomainInfo, and the second structured data can be the aforementioned strategyInfo.

[0085] Specifically, low-power strategies whose module names match the module name of the design object can be extracted from the original UPF file and used as the low-power strategies corresponding to that design object. The module name of the design object and the strategy name of the corresponding low-power strategy are stored according to the first classification template to obtain the powerDomainInfo corresponding to the design object. Further, for any low-power strategy corresponding to the design object, the field value of a specified field in the low-power strategy can be obtained. The strategy name of the low-power strategy and the field value of the specified field in the low-power strategy can be stored according to the second classification template to obtain the strategyInfo corresponding to the design object. Assuming the strategy name of the low-power strategy corresponding to design object BlockB includes iso_2, then the first structured data of design object BlockB includes: powerDomainInfo(BlockB){iso_2}.

[0086] The second structured data of the design object, Block B, includes: strategyInfo(iso_2) {PD_BlockBiso_ctrl1_B low {signal_B_to_BlockC1_group0}0}. By marking, the originally loosely structured UPF file is organized into easily searchable structured data. For example, on the user interface, an EDA tool can be triggered to use the marking function to mark the low-power strategy information of the design object as a user-defined attribute. The marked low-power strategy information, as an attribute of the design object, is associated and bound to the design object. During logic reorganization, it is passed along with the topology changes of the design object. As the design object is adjusted, for example, moved or renamed, it always carries the bound low-power strategy information. For example, if Block B is moved to a submodule of another module or renamed, Block B still carries the bound structured data.

[0087] Furthermore, the tracing function of EDA tools can be used to query design objects marked with low-power policy information. Simultaneously, changes to the design objects after logical reorganization can be tracked. This change information includes name changes (including new names), path changes (representing the new parent module of the design object), and the reorganized field values ​​of specific fields in the low-power policy information marked on the design object. Accordingly, based on the change information and the low-power policy information marked on the design objects, the low-power policy information to be updated for the corresponding logical reorganization module can be obtained. This updated low-power policy information is then used to obtain the target low-power policy information for the logical reorganization module. The logical reorganization module can be a newly added design object or a renamed design object.

[0088] Furthermore, UPF files corresponding to the target low-power strategy information can be generated, and UPF files corresponding to each module in the reorganized logical architecture diagram file can be generated. After merging, a UPF file consistent with the reorganized architecture can be obtained, that is, a UPF file equivalent to the design hierarchy after logical reorganization can be obtained.

[0089] In summary, the present invention provides a method for generating a unified power supply format (UPF) file in an electronic design automation (EDA) system. Low-power policy information extracted from the original UPF file is used as a user-defined attribute to mark the design object; this user-defined attribute is propagated and associated with the design object during logic reorganization. After logic reorganization, the design object marked with low-power policy information is identified in the design file, and changes to the design object after logic reorganization are tracked. Based on the change information and the low-power policy information marked on the design object, the low-power policy information to be updated corresponding to the logic reorganization module is obtained, and the low-power policy information to be updated is updated to obtain the target low-power policy information for the logic reorganization module. A UPF file corresponding to the target low-power policy information is generated, and based on the UPF file corresponding to the target low-power policy information, a UPF file equivalent to the logic reorganized design level is generated. Thus, by automatically generating the UPF file corresponding to the target low-power policy information for the logic reorganization module, manual writing is eliminated, resulting in higher generation efficiency.

[0090] Furthermore, compared to manual coding, it allows for faster acquisition of the UPF file corresponding to the target low-power strategy information of the logic reorganization module, thus avoiding development bottlenecks. It also avoids the errors that are prone to occur in manual coding.

[0091] Optionally, the step of obtaining the low-power policy information to be updated corresponding to the logic reorganization module based on the change information and the low-power policy information marked by the design object may specifically include: Step 2031: Determine the design object marked with low power policy information as the target design object, and obtain the low power policy information of each target design object associated with the logic reorganization module as the low power policy information to be updated.

[0092] If the logical reorganization module does not have a lower-level module—for example, if the logical reorganization module is a renamed version of an existing lower-level module (i.e., the logical reorganization module itself is a lower-level module)—then the low-power policy information marked by this logical reorganization module can be directly obtained as the low-power policy information to be updated. If the logical reorganization module is a newly added module (i.e., it has a lower-level module), based on the path change information of each target design object, the parent module is identified as the target design object of this logical reorganization module, and the low-power policy information marked by these target design objects is obtained as the low-power policy information to be updated.

[0093] The steps described above for updating the low-power policy information to obtain the target low-power policy information of the logic reorganization module may specifically include: Step 2032: Based on the change information, determine the recombined field value corresponding to the field value in the low-power strategy information to be updated and replace it.

[0094] Step 2033: Generate the target low-power strategy information based on the replaced low-power strategy information.

[0095] In this embodiment of the invention, the recombined field value corresponding to a specific field in the low-power policy information to be updated can be found in the change information. If the corresponding recombined field value is found, the specific field is replaced with the corresponding recombined field value. The specific implementation of the replacement operation can refer to the implementation of the replacement operation in the previous embodiments, and will not be repeated here. It should be noted that if the logical recombination module is obtained by renaming the original underlying module, the original module name defined in the low-power policy information to be updated can also be modified to the new name recorded in the change information. After the replacement, all policy information with consistent field values ​​is merged to obtain the target low-power policy information. The specific implementation of the merging operation can refer to the implementation of the merging operation in the previous embodiments, and will not be repeated here. The technical effects achieved by steps 2031 to 2032 can refer to the relevant descriptions in the previous embodiments, and will not be repeated here.

[0096] Optionally, the step of generating the UPF file corresponding to the target low-power policy information may specifically include: Step 2041: Write the policy name defined in the target low power policy information into the name field of the preset file template, and write the values ​​of each field in the target low power policy information into the corresponding fields of the preset file template to obtain the UPF file corresponding to the target low power policy information.

[0097] The target low-power strategy information is the aforementioned target strategy description information. The specific implementation method of this step and the technical effects that can be achieved can be referred to the relevant descriptions in the aforementioned embodiments, and will not be repeated here.

[0098] This invention also provides an electronic design automation system, the system comprising: The input interface receives the original UPF file and the logically reassembled file; A graphical user interface engine configured to generate a user interface and trigger corresponding processing flows in response to user actions on the user interface. The processing engine is configured to mark the low-power policy information extracted from the original UPF file as a user-defined attribute to the design object; the user-defined attribute is associated with and propagated to the design object during the logic reorganization process; the design object marked with the low-power policy information is identified in the design file after logic reorganization, and the change information of the design object after logic reorganization is tracked; based on the change information and the low-power policy information marked on the design object, the low-power policy information to be updated corresponding to the logic reorganization module is obtained, and the low-power policy information to be updated is updated to obtain the target low-power policy information of the logic reorganization module; a UPF file corresponding to the target low-power policy information is generated, and a UPF file equivalent to the design level after logic reorganization is generated based on the UPF file corresponding to the target low-power policy information; The output interface outputs a UPF file that is equivalent to the design hierarchy after the logical reorganization.

[0099] The implementation method and technical effects of the operations performed by the electronic design automation system can be referred to the relevant description of the aforementioned method embodiment for generating a unified power format file in an electronic design automation system, and will not be repeated here.

[0100] Reference Figure 13 This is a schematic diagram of the structure of the electronic device provided in an embodiment of the present invention. For example... Figure 13 As shown, the electronic device includes: a processor, a memory, a communication interface, and a communication bus.

[0101] The processor, the memory, and the communication interface communicate with each other via the communication bus; the memory stores at least one executable instruction, which causes the processor to execute the method of the aforementioned embodiments. The executable instructions can form a program.

[0102] This invention provides a machine-readable medium storing instructions that, when executed by one or more processors, enable the processors to perform the methods described in the foregoing embodiments. The machine-readable medium may be one or more processors.

[0103] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0104] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, apparatus, or computer program products. Therefore, embodiments of the present invention can take the form of entirely hardware embodiments, entirely software embodiments, or embodiments combining software and hardware aspects. Furthermore, embodiments of the present invention can take the form of computer program products implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0105] It should be noted that all actions involving the acquisition of signals, information, or data in this application are carried out in compliance with the relevant data protection laws and policies of the country where the application is located, and with the authorization granted by the owner of the relevant device.

[0106] Embodiments of the present invention are described with reference to flowchart illustrations and / or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing terminal device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal device, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0107] These computer program instructions may also be stored in a computer-readable storage medium capable of directing a computer or other programmable data processing terminal device to operate in a predictive manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0108] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal equipment, causing a series of operational steps to be performed on the computer or other programmable terminal equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable terminal equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0109] Although preferred embodiments of the present invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the embodiments of the present invention.

[0110] Finally, it should be noted that in this paper, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0111] Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or terminal device. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or terminal device that includes said element.

[0112] The foregoing has provided a detailed description of a method for generating a unified power format file, a method for generating a unified power format file in an electronic design automation system, an electronic design automation system, an electronic device, and a machine-readable medium provided by the present invention. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A method for generating a unified power format file, characterized in that, The method includes: In the case of logical reorganization, the reorganized module hierarchy file is obtained; the module hierarchy file represents the hierarchical relationship between the added logically reorganized modules and the underlying modules when no logical reorganization was performed. For any of the aforementioned logical restructuring modules, obtain the strategy description information corresponding to the target underlying module to obtain the description information to be updated; the target underlying module includes the underlying module that belongs to the next level module of the logical restructuring module; The description information to be updated is updated to obtain the target policy description information corresponding to the logical reorganization module, and a UPF file corresponding to the target policy description information is generated.

2. The method according to claim 1, characterized in that, The acquisition of the strategy description information corresponding to the target underlying module includes: For any of the target underlying modules, based on the module name of the target underlying module, the strategy name of the voltage control strategy corresponding to the target underlying module is searched from the relational representation information set, and used as the strategy name to be searched; the relational representation information set is used to represent the correspondence between the module name of each underlying module and the voltage control strategy corresponding to each underlying module; For any of the searchable strategies, the strategy description information of the searchable strategy is searched from the strategy description information set based on the strategy name of the searchable strategy; the strategy description information set includes the strategy description information of each voltage control strategy corresponding to each of the underlying modules.

3. The method according to claim 2, characterized in that, The method further includes: For any of the underlying modules, a strategy whose defined module name is the same as the module name of the underlying module is obtained from the original UPF file and used as the voltage control strategy corresponding to the underlying module. Generate relational representation information including the module name and the strategy name of the voltage control strategy corresponding to the underlying module; the generated relational representation information constitutes the relational representation information set; For any voltage control strategy of the underlying module, obtain the strategy name of the voltage control strategy and the field value of the specified field; Generate policy description information that includes the field values ​​of the specified fields and the policy name; the generated policy description information constitutes the policy description information set.

4. The method according to claim 2, characterized in that, The step of searching for the strategy name of the voltage control strategy corresponding to the target underlying module from the relation representation information set, and using it as the strategy name of the strategy to be searched, includes: for any relation representation information in the relation representation information set, if the module name included in the relation representation information is the same as the module name of the target underlying module, then the strategy name defined in the relation representation information is used as the strategy name of the strategy to be searched. The step of searching for the strategy description information of the strategy to be searched from the strategy description information set based on the strategy name of the strategy to be searched includes: for any strategy description information in the strategy description information set, if the strategy name included in the strategy description information is the same as the strategy name of the strategy to be searched, then the strategy description information is used as the strategy description information of the strategy to be searched.

5. The method according to any one of claims 1-4, characterized in that, The method further includes: The modules in the module hierarchy file are traversed. If the currently traversed module is a logical reorganization module, then the next level of modules of the logical reorganization module is traversed. The next level module being traversed is taken as the target bottom level module; The method further includes: after completing the traversal of the next level module of the logical reorganization module, using the obtained strategy description information as the description information to be updated.

6. The method according to claim 5, characterized in that, The method further includes: For any of the underlying modules, if the voltage control strategy corresponding to the underlying module is not empty, then a flag is set for the underlying module; Accordingly, the step of taking the next level module of the current traversal as the target bottom level module includes: when the next level module of the current traversal is marked, taking the next level module of the current traversal as the target bottom level module.

7. The method according to claim 1, characterized in that, The step of updating the description information to be updated to obtain the target strategy description information corresponding to the logical reorganization module includes: Replace the field values ​​in the description information to be updated with the corresponding recombined field values; All description information to be updated with consistent field values ​​is grouped into a policy description information group. A policy name is assigned to the policy description information group, and based on the assigned policy name and the field values ​​in the policy description information group, they are merged into a single target policy description information.

8. The method according to claim 1, characterized in that, The generation of the UPF file corresponding to the target policy description information includes: Write the policy name defined in the target policy description information into the name field of the preset file template, and write the values ​​of each field in the target policy description information into the corresponding fields of the preset file template to obtain the UPF file of the target policy description information.

9. A method for generating a uniform power supply format file in an electronic design automation system, characterized in that, The method includes: The low-power strategy information extracted from the original UPF file is marked as a user-defined attribute on the design object; the user-defined attribute is associated with and propagated to the design object during the logic reorganization process; After logical reorganization, identify the design objects marked with the low-power strategy information in the design file, and track the change information of the design objects after logical reorganization; Based on the change information and the low-power policy information marked by the design object, obtain the low-power policy information to be updated corresponding to the logic reorganization module, and update the low-power policy information to be updated to obtain the target low-power policy information of the logic reorganization module. Generate a UPF file corresponding to the target low-power strategy information, and based on the UPF file corresponding to the target low-power strategy information, generate a UPF file equivalent to the design layer after the logic reorganization.

10. The method according to claim 9, characterized in that, The step of obtaining the low-power policy information to be updated corresponding to the logic reorganization module based on the change information and the low-power policy information marked by the design object includes: The design object marked with low power policy information is identified as the target design object, and the low power policy information of each target design object associated with the logic reorganization module is obtained as the low power policy information to be updated. The step of updating the low-power policy information to be updated to obtain the target low-power policy information of the logic reorganization module includes: Based on the change information, determine the recombined field value corresponding to the field value in the low-power strategy information to be updated and replace it; The target low-power strategy information is generated based on the replaced low-power strategy information.

11. The method according to claim 9, characterized in that, The generation of the UPF file corresponding to the target low-power strategy information includes: Write the policy name defined in the target low-power policy information into the name field of the preset file template, and write the values ​​of each field in the target low-power policy information into the corresponding fields of the preset file template to obtain the UPF file corresponding to the target low-power policy information.

12. An electronic design automation system, characterized in that, The system includes: The input interface receives the original UPF file and the logically reassembled file; A graphical user interface engine configured to generate a user interface and trigger corresponding processing flows in response to user actions on the user interface. The processing engine is configured to mark the low-power policy information extracted from the original UPF file as a user-defined attribute to the design object; the user-defined attribute is associated with and propagated to the design object during the logic reorganization process; the design object marked with the low-power policy information is identified in the design file after logic reorganization, and the change information of the design object after logic reorganization is tracked; based on the change information and the low-power policy information marked on the design object, the low-power policy information to be updated corresponding to the logic reorganization module is obtained, and the low-power policy information to be updated is updated to obtain the target low-power policy information of the logic reorganization module; a UPF file corresponding to the target low-power policy information is generated, and a UPF file equivalent to the design level after logic reorganization is generated based on the UPF file corresponding to the target low-power policy information; The output interface outputs a UPF file that is equivalent to the design hierarchy after the logical reorganization.

13. An electronic device, characterized in that, include: The processor, memory, communication interface, and communication bus are provided, wherein the processor, memory, and communication interface communicate with each other via the communication bus. The memory is used to store executable instructions that cause the processor to perform the method as described in any one of claims 1 to 11.

14. A machine-readable medium, characterized in that, It stores instructions that, when executed by one or more processors, cause the processors to perform the method as described in any one of claims 1 to 11.

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