A method for verifying a RAM read-modify-write zero-latency synchronization system and related devices

CN122311089APending Publication Date: 2026-06-30SUZHOU CENTEC COMM CO LTD
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
SUZHOU CENTEC COMM CO LTD
Filing Date
2026-04-09
Publication Date
2026-06-30

AI Technical Summary

Technical Problem

In integrated circuit design, the read and write process of RAM has a latency problem, which leads to inaccurate data modification and low read and write efficiency. Existing verification methods are difficult to effectively verify the logical function of a RAM read-modify-write zero-latency synchronous system.

Method used

By adding sequence numbers and classification labels when identifying the enable signals of the logic design under test, and by using dynamic message queues and dynamic mapping tables to merge messages of the same operation type, the input and output signals are monitored to complete the comparison verification, thus severing the strong dependency between the verification framework and the logic design under test.

Benefits of technology

It improves verification efficiency and versatility, ensures that the read and write performance improvement is as expected, reduces logical errors, and shortens the defect localization cycle.

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Abstract

This invention proposes a verification method and related equipment for a RAM read / write zero-latency synchronous system. The method involves adding a corresponding sequence number and classification label to the identified i-th enable signal, adding the i-th message to a dynamic message queue, and extracting the first N valid messages from the dynamic message queue. Based on a dynamic mapping table and the sequence numbers and classification labels of the first N valid messages, M messages that can be merged are identified and merged. The merged reference message is added to a reference queue. The verification is then determined based on the reference queue and the write instruction queue output by the DUT (Device Under Test). By monitoring enable signals and write instructions, the comparison verification is completed without needing to understand or steal complex internal signals of the DUT. The time slot interval label for continuous read / write operations separates the verification framework from the DUT, severing the strong dependency between the DUT and the verification framework, thereby greatly improving the versatility and efficiency of the verification device.
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