Method for establishing spice model of mom capacitor structure

Abstract

The application provides a method for establishing a SPICE model of a MOM capacitor structure, and belongs to the technical field of semiconductors. The method comprises the following steps: acquiring the number of layers A of a single-layer capacitor structure closest to a substrate in an interconnection structure and the number of layers B of a single-layer capacitor structure farthest from the substrate in the interconnection structure of the MOM capacitor structure; obtaining a bottom-layer coefficient of the MOM capacitor structure, obtaining a top-layer coefficient of the MOM capacitor structure; obtaining a middle-layer coefficient of the MOM capacitor structure; acquiring a bottom-layer capacitor model, a middle-layer capacitor model and a top-layer capacitor model, each of which comprises a size correction factor representing the planar size of the corresponding single-layer capacitor structure; and establishing a SPICE model, SPICE model = bottom-layer capacitor model * bottom-layer coefficient + middle-layer capacitor model * middle-layer coefficient + top-layer capacitor model * top-layer coefficient. The SPICE model established by the application can accurately represent the capacitance of the MOM capacitor structure.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, specifically to a method for establishing a SPICE model of a MOM capacitor structure. Background Technology

[0002] MOM (Metal-Oxide-Metal) capacitors are widely used components in semiconductor devices. They primarily utilize the capacitance between metal layers, and larger capacitance values ​​can be achieved by stacking multiple MOM capacitors. The advantage of this type of capacitor is that it can be implemented using existing metal interconnect processes, meaning that the MOM capacitor and interconnect structure can be completed simultaneously without adding additional photolithography layers.

[0003] As the size of semiconductor devices continues to shrink and the demand for capacitance per unit substrate area continues to increase (by stacking more single-layer capacitor structures), existing MOM capacitor models, which describe inter-finger capacitance, are finding it difficult to accurately express the capacitance value of MOM capacitor structures. Summary of the Invention

[0004] In view of this, this application aims to provide a method for establishing a SPICE model of a MOM capacitor structure, which can be used to accurately characterize the capacitance of the MOM capacitor structure.

[0005] The method for establishing a SPICE model of a MOM capacitor structure provided in this application, wherein the MOM capacitor structure is disposed in an interconnect structure on a substrate, including N monolayer capacitor structures stacked sequentially in a direction away from the substrate, wherein the N monolayer capacitor structures are located in N interconnect layers in the interconnect structure and each interconnect layer has one monolayer capacitor structure, where N is a positive integer, and the method includes: Obtain the number of interconnect layers A of the single-layer capacitor structure closest to the substrate in the interconnect structure and the number of interconnect layers B of the single-layer capacitor structure furthest from the substrate in the interconnect structure, where A and B are both positive integers and B≥A; Based on the number of layers A, the bottom layer coefficients of the MOM capacitor structure are obtained, and based on the number of layers B, the top layer coefficients of the MOM capacitor structure are obtained. Based on the bottom layer coefficients and the top layer coefficients, the middle layer coefficients of the MOM capacitor structure are obtained; Based on the corresponding single-layer capacitor structure, a bottom layer capacitor model, a middle layer capacitor model, and a top layer capacitor model are obtained. The bottom layer capacitor model, the middle layer capacitor model, and the top layer capacitor model all include a size correction factor that characterizes the planar dimensions of the corresponding single-layer capacitor structure. Establish a SPICE model of the MOM capacitor structure, wherein the SPICE model = the underlying capacitor model. The bottom layer coefficient + middle layer capacitance model The middle layer coefficient + top layer capacitance model The top-level coefficients.

[0006] Optionally, the steps of obtaining the bottom-level coefficients, the top-level coefficients, and the middle-level coefficients include: Determine whether the layer number A is 1. If yes, the bottom layer coefficient = 1; otherwise, the bottom layer coefficient = 0. Determine whether the number of layers B is 1. If yes, the top layer coefficient = 0; otherwise, the top layer coefficient = 1. The middle layer coefficient = the number of layers B - the number of layers A - the bottom layer coefficient The top-level coefficients.

[0007] Optionally, the bottom layer capacitor model, the middle layer capacitor model, and the top layer capacitor model all include a first capacitance value module representing the corresponding inter-finger capacitance, where the first capacitance value module equals the capacitance per unit length of the inter-finger capacitance. Interdigital length.

[0008] Optionally, the capacitance per unit length of the interfinal capacitor is equal to the capacitance per unit length of the reference interfinal capacitor. (1 + the corresponding size correction factor).

[0009] Optionally, the step of obtaining the capacitance per unit length of the reference interfinite capacitance includes: Obtain first sample data of the single-layer capacitor structure, wherein the interdigitated length of the single-layer capacitor structure in the first sample data is greater than or equal to a preset size. Based on the first sample data, a linear fit is performed to obtain the capacitance value per unit length of the reference interfinite capacitance.

[0010] Optionally, the step of obtaining the size correction factor includes: Obtain second sample data of the single-layer capacitor structure, wherein the interdigitated length of the single-layer capacitor structure in the second sample data is less than the preset size; The size correction factor is obtained by performing nonlinear fitting based on the first sample data and the second sample data.

[0011] Optionally, the size correction factor = α e ^ （β / lf） Where α and β are both correction terms and are both positive, and lf is the length of the interdigitated finger. e It is the natural logarithm.

[0012] Optionally, the steps of obtaining the bottom-layer capacitor model, the middle-layer capacitor model, and the top-layer capacitor model include: M test structures are established, and the M test structures are respectively labeled as the first test structure to the Mth test structure. The first test structure includes M stacked monolayer capacitor structures, wherein the monolayer capacitor structure closest to the substrate is located in the first interconnect layer. The second test structure includes M-1 stacked monolayer capacitor structures, wherein the monolayer capacitor structure closest to the substrate is located in the second interconnect layer. The Bth test structure includes MB stacked monolayer capacitor structures, wherein the monolayer capacitor structure closest to the substrate is located in the Bth interconnect layer. The B+1th test structure includes MB-1 stacked monolayer capacitor structures, wherein the monolayer capacitor structure closest to the substrate is located in the B+1th interconnect layer. M is a positive integer greater than or equal to 2, and M is greater than B. Subtracting the capacitance value of the second test structure from the capacitance value of the first test structure yields the capacitance value of the single-layer capacitor structure located in the first interconnect layer, thereby establishing the underlying capacitor model. Subtracting the capacitance value of the Bth test structure from the capacitance value of the second test structure yields the capacitance values ​​of the B-2 single-layer capacitor structures located in the middle layer of the interconnect structure, thereby establishing the middle layer capacitor model. Subtracting the capacitance value of the B+1 test structure from the capacitance value of the Bth test structure yields the capacitance value of the single-layer capacitor structure located in the Bth interconnect layer, thereby establishing the top-level capacitor model.

[0013] Optionally, the bottom-layer capacitor model, the middle-layer capacitor model, and the top-layer capacitor model all further include a second capacitance value module representing the corresponding fingertip capacitor, a third capacitance value module representing the corresponding first edge parasitic capacitor, and a fourth capacitance value module representing the corresponding second edge parasitic capacitor, wherein the second capacitance value module equals the capacitance value of a single fingertip capacitor. (Number of interdigitated fingers - 1), the third capacitance module is equal to the capacitance of the parasitic capacitance along the edge in the first direction, and the fourth capacitance module is equal to the capacitance of the parasitic capacitance along the edge in the second direction.

[0014] Optionally, multiple plugs are arranged close to the edge of the MOM capacitor structure along the first direction, and the third capacitance module is equal to the capacitance per unit length of the parasitic capacitance at the first edge. Interdigital length.

[0015] In summary, the unexpected effects of this application are as follows: Considering that the single-layer capacitor structures of the MOM capacitor structure are located in different interconnect layers, and that their environments and distances from the substrate vary, this application establishes layered (bottom, middle, and top) capacitor models. Each capacitor model is obtained based on the single-layer capacitor structure located in different interconnect layers within the interconnect structure. Bottom, middle, and top layer coefficients are obtained based on the layer position of each single-layer capacitor structure within the interconnect structure. By multiplying the corresponding layer's capacitor model with its corresponding coefficient, and then summing the capacitor models of each layer as a SPICE model, the established SPICE model of the MOM capacitor structure becomes more detailed and accurate. Furthermore, this application introduces size correction factors into the aforementioned bottom, middle, and top layer capacitor models to avoid accuracy issues caused by differences in capacitor size, making the model more flexible and accurate when applied to small-sized MOM capacitor structures. Attached Figure Description

[0016] Figure 1 This is a comparison table of theoretical and actual capacitance values ​​of the top-level capacitor obtained from existing capacitor models.

[0017] Figure 2 This is a schematic diagram comparing the theoretical and actual capacitance values ​​of the top-level capacitor obtained from the existing capacitor model.

[0018] Figure 3 This is a top view of a single-layer capacitor structure in a MOM capacitor structure.

[0019] Figure 4 This is a cross-sectional schematic diagram of a MOM capacitor structure.

[0020] Figure 5 This is a cross-sectional schematic diagram of a MOM capacitor structure.

[0021] Figure 6 A flowchart illustrating the method for establishing a SPICE model of a MOM capacitor structure according to an embodiment of this application.

[0022] Figure 7 This is a block diagram illustrating the acquisition of the bottom layer coefficients, middle layer coefficients, and top layer coefficients of a MOM capacitor structure according to an embodiment of this application.

[0023] Figure 8 This is a comparison table of the theoretical and actual capacitance values ​​of the top-layer capacitor obtained from the model established in this application.

[0024] Figure 9 This is a schematic diagram comparing the theoretical capacitance value and the actual capacitance value of the top layer capacitor obtained from the model established in this application.

[0025] In the attached figures: 100 - substrate; 201 - plug; M1 - first interconnect layer; M2 - second interconnect layer; M3 - third interconnect layer; M4 - fourth interconnect layer; M5 - fifth interconnect layer; M6 - sixth interconnect layer; 210 - first comb structure; 220 - second comb structure; 211 - first busbar; 212 - first electrode; 221 - second busbar; 222 - second electrode; C1 - first capacitance module; C2 - second capacitance module; C3 - third capacitance module; C4 - fourth capacitance module; X - first direction; Y - second direction; 310 - first single-layer capacitor structure; 320 - second single-layer capacitor structure; 330 - third single-layer capacitor structure; 340 - fourth single-layer capacitor structure; 350 - fifth single-layer capacitor structure; 360 - sixth single-layer capacitor structure. Detailed Implementation

[0026] SPICE (Simulation Program with Integrated Circuit Emphasis) models, as a type of device model used in the semiconductor field for circuit simulation, can be used to predict the actual performance of devices. The SPICE model of a MOM capacitor structure, as a model describing interdigital capacitance, in current mainstream modeling methods, mainly involves extracting the interdigital capacitance values ​​of different lengths in each layer, performing linear fitting, and then calculating the capacitance per unit length of a single interdigital finger to obtain the capacitance value of a multi-layer MOM capacitor. For example, in existing MOM capacitor models, capacitance C = number of single-layer capacitor structures. (Capacity per unit length of a single interdigitated finger) (Forked finger length lf + fingertip capacitance) Number of interdigitated fingers nf + other parasitic capacitances.

[0027] Figure 1 This is a comparison table of theoretical and actual capacitance values ​​of the top-level capacitor obtained from existing capacitor models. Figure 2 This is a schematic diagram comparing the theoretical and actual capacitance values ​​of the top-level capacitor obtained from an existing capacitor model. (Example:) Figure 1 and Figure 2As shown, the horizontal axis represents the interdigitation length in micrometers, and the vertical axis represents the capacitance value in volts (F). The red dashed line represents the theoretical capacitance value provided by the model, and the green dots represent the actual capacitance value. When the interdigitation length lf > 4 micrometers, the error between the theoretical and actual capacitance values ​​of the top layer capacitor obtained by the above MOM capacitor model is less than 1%. However, when the interdigitation length lf = 4 micrometers, the error reaches 4.4%. When the interdigitation length lf = 1 micrometer, the error reaches 14.4%. Therefore, it is easy to see that the above MOM capacitor model has low accuracy for smaller MOM capacitors, meaning that this MOM capacitor model cannot be used to describe smaller MOM capacitors.

[0028] In view of this, embodiments of this application provide a method for establishing a SPICE model of a MOM capacitor structure. The MOM capacitor structure is disposed in an interconnect structure on a substrate, including N single-layer capacitor structures stacked sequentially in a direction away from the substrate. The N single-layer capacitor structures are located in N interconnect layers of the interconnect structure, and each interconnect layer has one single-layer capacitor structure, where N is a positive integer. The method includes: obtaining the layer number A of the interconnect layer of the single-layer capacitor structure closest to the substrate and the layer number B of the interconnect layer of the single-layer capacitor structure furthest from the substrate, where A and B are both positive integers and B≥A; obtaining the bottom layer coefficients of the MOM capacitor structure based on the layer number A, and obtaining the top layer coefficients of the MOM capacitor structure based on the layer number B; obtaining the middle layer coefficients of the MOM capacitor structure based on the bottom layer coefficients and the top layer coefficients; obtaining the bottom layer capacitor model, the middle layer capacitor model, and the top layer capacitor model based on the corresponding single-layer capacitor structures, where the bottom layer capacitor model, the middle layer capacitor model, and the top layer capacitor model all include size correction factors representing the planar dimensions of the corresponding single-layer capacitor structures; and establishing a SPICE model of the MOM capacitor structure, where SPICE model = bottom layer capacitor model. Bottom layer coefficients + middle layer capacitance model Middle layer coefficient + top layer capacitance model Top-layer coefficients. An unexpected benefit of this application is that, considering the different environments and distances relative to the substrate within the interconnect layers of the MOM capacitor structure, each monolayer capacitor structure is located in a different interconnect layer. Therefore, this application establishes layered (bottom, middle, and top) capacitor models. Each capacitor model is obtained based on the monolayer capacitor structure located in different interconnect layers within the interconnect structure. Bottom, middle, and top-layer coefficients are obtained based on the layer position of each monolayer capacitor structure within the interconnect structure. By multiplying the corresponding layer's capacitor model with its corresponding coefficient, and then summing the capacitor models of each layer as a SPICE model, the established SPICE model of the MOM capacitor structure becomes more detailed and accurate. Furthermore, this application introduces size correction factors into the aforementioned bottom, middle, and top-layer capacitor models to avoid accuracy issues caused by differences in capacitor size, making the model more flexible and accurate when applied to small-sized MOM capacitor structures.

[0029] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0030] This application provides a method for establishing a SPICE model of a MOM capacitor structure. The MOM capacitor structure is located in an interconnect structure on a substrate. The MOM capacitor structure may include N single-layer capacitor structures stacked sequentially in a direction away from the substrate (i.e., from bottom to top). The N single-layer capacitor structures are located in N interconnect layers of the interconnect structure, and each interconnect layer has one single-layer capacitor structure. Each single-layer capacitor structure has the same layout design (same shape and size), and the N single-layer capacitor structures can be aligned in the longitudinal direction (vertical direction). For example, the interconnect structure includes M interconnect layers (i.e., the first to the Mth interconnect layers) arranged sequentially from bottom to top, and the N single-layer capacitor structures include the first to the Nth single-layer capacitor structures arranged sequentially from bottom to top. The first to the Nth single-layer capacitor structures each correspond one-to-one with the N interconnect layers of the interconnect structure. That is, the first single-layer capacitor structure is located in the i-th interconnect layer, the second single-layer capacitor structure is located in the (i+1)-th interconnect layer, and the Nth interconnect layer is located in the (i+N-1)-th interconnect layer. i, M, and N are all positive integers, and M is greater than or equal to the N single-layer capacitor structures and i is less than or equal to M.

[0031] Figure 3 This is a top view schematic diagram of a single-layer capacitor structure in a MOM capacitor structure. (Example:) Figure 3As shown, the single-layer capacitor structure can be in the form of an interdigitated structure, and may include a first comb structure 210 and a second comb structure 220 arranged opposite to each other. The first comb structure 210 includes a first busbar 211 connected to each other and four first electrodes 212. The second comb structure 220 includes a second busbar 221 connected to each other and four second electrodes 222. The first busbar 211 and the second busbar 221 extend along the first direction X and are arranged opposite to each other. The four first electrodes 212 and the four second electrodes 222 are alternately arranged between the first busbar 211 and the second busbar 221 along the first direction X. The portion of adjacent first electrodes 212 and second electrodes 222 facing each other (the intersection portion) constitutes an interdigital capacitor (first capacitance module C1). The length of adjacent first electrodes 212 and second electrodes 222 facing each other is the interdigital length lf. The portion of the first electrode 212 and the second busbar 221 that are spaced apart and the portion of the second electrode 222 and the first busbar 211 that are spaced apart and opposite to each other constitutes a fingertip capacitor (second capacitance module C2). Multiple plugs 201 are disposed on both sides of the single-layer capacitor structure along the first direction X, and are disposed adjacent to the outermost first electrode 212 and second electrode 222 of the capacitor. These plugs 201, together with the first electrode 212 and the second electrode 222, constitute a first edge parasitic capacitance (third capacitance module C3) along the first direction X. The first bus bar 211 and the second bus bar 221 are located on both sides of the single-layer capacitor structure along the second direction Y, and together with the substrate 100 or other structures in the interconnect structure, constitute a second edge parasitic capacitance (fourth capacitance module C4) along the second direction Y.

[0032] Figure 4 This is a cross-sectional schematic diagram of a MOM capacitor structure. Figure 4 As shown, the interconnect structure is located on the substrate 100. The MOM capacitor structure may include first to sixth single-layer capacitor structures 310~360 arranged sequentially from bottom to top. The first to sixth single-layer capacitor structures 310~360 correspond one-to-one with the first to sixth interconnect layers M1~M6 in the interconnect structure. That is, the first single-layer capacitor structure 310 is located in the first interconnect layer M1, the second single-layer capacitor structure 320 is located in the second interconnect layer M2, the third single-layer capacitor structure 330 is located in the third interconnect layer M3, the fourth single-layer capacitor structure 340 is located in the fourth interconnect layer M4, the fifth single-layer capacitor structure 350 is located in the fifth interconnect layer M5, and the sixth single-layer capacitor structure 360 ​​is located in the sixth interconnect layer M6. Plugs 201 are provided between the corresponding electrodes of adjacent single-layer capacitor structures for connection.

[0033] Figure 5 This is a cross-sectional schematic diagram of a MOM capacitor structure. Figure 5As shown, the MOM capacitor structure may include first to third single-layer capacitor structures 310 to 330 arranged sequentially from bottom to top. The first to third single-layer capacitor structures 310 to 330 correspond one-to-one with the third to fifth interconnect layers M3 to M5 in the interconnect structure. That is, the first single-layer capacitor structure 310 is located in the third interconnect layer M3, the second single-layer capacitor structure 320 is located in the fourth interconnect layer M4, and the third single-layer capacitor structure 330 is located in the fifth interconnect layer M5. The corresponding electrodes of adjacent single-layer capacitor structures are connected by plugs 201.

[0034] Figure 6 This is a flowchart illustrating a method for establishing a SPICE model of a MOM capacitor structure according to an embodiment of this application. Figure 6 As shown, an embodiment of this application provides a method for establishing a SPICE model of a MOM capacitor structure, including: S100: Obtain the number of interconnect layers A of the single-layer capacitor structure closest to the substrate in the interconnect structure and the number of interconnect layers B of the single-layer capacitor structure furthest from the substrate in the interconnect structure, where A and B are both positive integers and B≥A. S200: Based on the number of layers A, obtain the bottom layer coefficient of the MOM capacitor structure, and based on the number of layers B, obtain the top layer coefficient of the MOM capacitor structure; S300: Obtain the middle layer coefficient of the MOM capacitor structure based on the bottom layer coefficient and the top layer coefficient; S400: Obtain a bottom layer capacitor model, a middle layer capacitor model, and a top layer capacitor model based on the corresponding single-layer capacitor structure. The bottom layer capacitor model, the middle layer capacitor model, and the top layer capacitor model all include a size correction factor that characterizes the planar dimensions of the corresponding single-layer capacitor structure. S500: Establish the SPICE model of the MOM capacitor structure, where the SPICE model = the underlying capacitor model. The bottom layer coefficient + middle layer capacitance model The middle layer coefficient + top layer capacitance model The top-level coefficients.

[0035] Steps S100, S200, and S300 are used to obtain the bottom layer coefficients, middle layer coefficients, and top layer coefficients of the MOM capacitor structure. Due to differences in the environment and distance from the substrate of different interconnect layers within the interconnect structure, the same single-layer capacitor structure located on different interconnect layers has different capacitance values. Therefore, this application establishes a layered model based on the different positions of each single-layer capacitor structure in the interconnect structure within the MOM capacitor structure. The capacitance model of each layer is obtained based on the single-layer capacitor structure of the corresponding interconnect layer in the interconnect structure, and the coefficients of each layer are obtained. By multiplying the model of the corresponding layer by the coefficient of the corresponding layer, a SPICE model of the MOM capacitor structure is established to accurately obtain the capacitance value of the MOM capacitor structure.

[0036] Figure 7 This is a block diagram illustrating the acquisition of the bottom layer coefficients, middle layer coefficients, and top layer coefficients of a MOM capacitor structure according to an embodiment of this application. Figure 7 As shown, based on the position of each monolayer capacitor structure in the MOM capacitor structure within the interconnect structure, the layer number A of the interconnect layer in the interconnect structure for the monolayer capacitor structure closest to the substrate (the first monolayer capacitor structure) is obtained. It is then determined whether layer number A is 1. If yes, the bottom layer coefficient of the MOM capacitor structure is 1; otherwise, the bottom layer coefficient is 0. Next, the layer number B of the interconnect layer in the interconnect structure for the monolayer capacitor structure furthest from the substrate (the Nth monolayer capacitor structure) is obtained. It is then determined whether layer number B is 1. If yes, the top layer coefficient of the MOM capacitor structure is 0; otherwise, the top layer coefficient is 1. Finally, based on the bottom and top layer coefficients, the middle layer coefficient of the MOM capacitor structure is obtained: Middle layer coefficient = Layer number B - Layer number A - Bottom layer coefficient. Top-level coefficients.

[0037] In such Figure 4 In the example, the first single-layer capacitor structure is located on the first interconnect layer, and the sixth single-layer capacitor structure is located on the sixth interconnect layer. A=1, B=6, such that the bottom coefficient of this MOM capacitor structure is 1, the top coefficient is 1, and the middle coefficient is 6-1-1. 1 = 4.

[0038] In such Figure 5 In the example, the first single-layer capacitor structure is located on the third interconnect layer, the third single-layer capacitor structure is located on the fifth interconnect layer, A=3, B=5, such that the bottom coefficient of this MOM capacitor structure is 0, the top coefficient is 1, and the middle coefficient is 5-3-0. 1 = 2.

[0039] In some examples, the MOM capacitor structure includes only a first single-layer capacitor structure located in the first interconnect layer, where A=B=1, such that the bottom coefficient of the MOM capacitor structure is 1, the top coefficient is 0, and the middle coefficient is 1-1-1. 0 = 0.

[0040] In some examples, the MOM capacitor structure consists of only a first single-layer capacitor structure located on the third interconnect layer, where A=B=3, such that the bottom layer coefficient of the MOM capacitor structure is 0, the top layer coefficient is 1, and the middle layer coefficient is 3-3-0. 2=0.

[0041] In step S400, a bottom layer capacitor model, a middle layer capacitor model, and a top layer capacitor model are obtained based on the corresponding single-layer capacitor structure. Each of these models includes a size correction factor representing the planar dimensions of the corresponding single-layer capacitor structure. Specifically, each of the bottom, middle, and top layer capacitor models includes a first capacitance value module C1 representing the inter-finger capacitance, a second capacitance value module C2 representing the inter-finger capacitance, a third capacitance value module C3 representing the first edge parasitic capacitance, and a fourth capacitance value module C4 representing the second edge parasitic capacitance. The first capacitance value module C1 equals the capacitance per unit length of the inter-finger capacitance, Cfin. The interdigitation length lf, the second capacitance module C2 = the capacitance value Ctip of a single fingertip. (Number of interdigitated fingers nf-1), the third capacitance module C3 = capacitance per unit length of the first edge parasitic capacitance Cpa. Interdigital length lf.

[0042] Specifically, the underlying capacitance model = (Cfin_m1) lf+Ctip_m1) (nf-1)+Cpa_m1 lf+Cpb_m1, where Cfin_m1, Ctip_m1, Cpa_m1 and Cpb_m1 are respectively the capacitance value per unit length of the inter-finger capacitance, the capacitance value of a single fingertip capacitance, the capacitance value per unit length of the first edge parasitic capacitance, and the capacitance value of the edge parasitic capacitance along the second direction in the single-layer capacitor structure of the bottom interconnect layer (e.g., the first interconnect layer).

[0043] Middle layer capacitor model = (Cfin_mx lf+Ctip_mx) (nf-1)+Cpa_mx lf+Cpb_mx, where Cfin_mx, Ctip_mx, Cpa_mx and Cpb_mx are the capacitance per unit length of the inter-finger capacitance, the capacitance of a single fingertip capacitance, the capacitance per unit length of the first edge parasitic capacitance, and the capacitance of the edge parasitic capacitance along the second direction in the single-layer capacitor structure of the intermediate interconnect layer (e.g., the second to the (N-1)th interconnect layer).

[0044] Top-level capacitor model = (Cfin_mtop) (lf+Ctip_mtop) (nf-1)+Cpa_mtop lf+Cpb_mtop, where Cfin_mtop, Ctip_mtop, Cpa_mtop and Cpb_mtop are the capacitance per unit length of the inter-finger capacitance, the capacitance of a single fingertip capacitance, the capacitance per unit length of the first edge parasitic capacitance, and the capacitance of the edge parasitic capacitance along the second direction in the single-layer capacitor structure of the top interconnect layer (e.g., the Nth interconnect layer).

[0045] In this application, capacitance test structures located at different interconnect layers can be designed to obtain the parameters of the bottom, middle and top layer capacitance models, including Cfin, Ctip, Cpa and Cpb, to establish the corresponding capacitance models. For example, a first capacitance test structure is designed, including bottom, middle, and top layer capacitance models; a second capacitance test structure is designed, including middle and top layer capacitance models; and a third capacitance test structure is designed, including the top layer capacitance model. The capacitance of the bottom layer capacitance model is obtained by subtracting the second capacitance test structure from the first capacitance test structure, and thus the parameters of the bottom layer capacitance model are obtained, such as Cfin_m1, Ctip_m1, Cpa_m1, and Cpb_m1. The capacitance of the middle layer capacitance model is obtained by subtracting the third capacitance test structure from the second capacitance test structure, and thus the parameters of the middle layer capacitance model are obtained, such as Cfin_mx, Ctip_mx, Cpa_mx, and Cpb_mx. The capacitance of the top layer capacitance model is obtained through the third capacitance test structure, and thus the parameters of the top layer capacitance model are obtained, such as Cfin_mtop, Ctip_mtop, Cpa_mtop, and Cpb_mtop.

[0046] Specifically, M test structures are established, labeled as the first test structure, the second test structure, up to the Mth test structure, where M is a positive integer greater than or equal to 2, and M ≥ B. The first test structure comprises M stacked single-layer capacitor structures located in the first to Mth interconnect layers; the second test structure comprises M-1 stacked single-layer capacitor structures located in the second to Mth interconnect layers; the (N-1)th test structure comprises M-N+1 stacked single-layer capacitor structures located in the (N-1)th to Mth interconnect layers; the Nth test structure comprises MN stacked single-layer capacitor structures located in the Nth to Mth interconnect layers; and the (N+1)th test structure comprises... The test structure includes MN-1 stacked single-layer capacitor structures located in interconnect layers N+1 to M, respectively. The capacitance value of the first test structure is subtracted from the capacitance value of the second test structure to obtain the capacitance value of the single-layer capacitor structure located in the first interconnect layer, thereby establishing the bottom layer capacitor model. The capacitance value of the second test structure is subtracted from the capacitance value of the single-layer capacitor structure located in the first interconnect layer of the Nth test structure to obtain the capacitance value of the single-layer capacitor structure located in the second to N-1th interconnect layers, thereby establishing the middle layer capacitor model. The capacitance value of the Nth test structure is subtracted from the capacitance value of the N+1th test structure to obtain the capacitance value of the single-layer capacitor structure located in the Nth interconnect layer, thereby establishing the top layer capacitor model.

[0047] In one example, M=6, and the MOM capacitor and corresponding test structure can be found in [reference needed]. Figure 4 The bottom layer coefficient is set to 1, the middle layer coefficient to 4, and the top layer coefficient to 1. This includes the bottom, middle, and top layer capacitance models. The capacitance value of the first test structure is subtracted from the capacitance value of the second test structure to obtain the capacitance value of the first interconnect layer in the multilayer MOM structure, resulting in Cfin_m1, Ctip_m1, Cpa_m1, and Cpb_m1, thus establishing the bottom layer capacitance model. The capacitance value of the second test structure is subtracted from the capacitance value of the sixth test structure to obtain the sum of the capacitance values ​​of the second, third, fourth, and fifth interconnect layers in the multilayer MOM structure. The average value obtained by dividing this sum by the layer number 4 is used to calculate the capacitance value of each middle layer, resulting in Cfin_mx, Ctip_mx, Cpa_mx, and Cpb_mx, thus establishing the middle layer capacitance model. The capacitance value of the sixth test structure is used as the capacitance value of the sixth interconnect layer in the multilayer MOM structure, resulting in Cfin_mtop, Ctip_mtop, Cpa_mtop, and Cpb_mtop, thus establishing the top layer capacitance model.

[0048] In one example, M=6, and the MOM capacitor and corresponding test structure can be found in [reference needed]. Figure 5The bottom layer coefficient is 0, the middle layer coefficient is 2, and the top layer coefficient is 1, which includes the capacitance models of the middle and top layers. The capacitance value of the third test structure is subtracted from the capacitance value of the fifth test structure to obtain the sum of the capacitance values ​​of the third and fourth interconnect layers in the multilayer MOM structure. The average value obtained by dividing the sum of the capacitance values ​​by the layer number 2 is used to calculate the capacitance value of each layer in the middle layer to obtain Cfin_mx, Ctip_mx, Cpa_mx, and Cpb_mx, thereby establishing the middle layer capacitance model. The capacitance value of the fifth test structure is subtracted from the capacitance value of the sixth test structure to obtain the capacitance value of the fifth interconnect layer in the multilayer MOM structure to obtain Cfin_mtop, Ctip_mtop, Cpa_mtop, and Cpb_mtop, thereby establishing the top layer capacitance model.

[0049] It should be noted that this application also introduces a size correction factor into the above-mentioned capacitor models (including bottom, middle, and top layer capacitor models) and their corresponding parameters to correct accuracy issues caused by differences in capacitor size (planar size). In some embodiments, in the first to fourth capacitance modules of the above-mentioned capacitor models, since the capacitance value of the interdigital capacitor portion (first capacitance module) accounts for a much larger proportion of the total capacitance value of the MOM capacitor structure than the other three modules, the size correction factor can be associated only with the interdigital capacitor (first capacitance module) to simplify the model. In the first capacitance module (interdigital capacitor), the capacitance value per unit length Cfin of the interdigital capacitor = the capacitance value per unit length Cfin0 of the reference interdigital capacitor. (1 + size correction factor), where the size correction factor varies with the size of the MOM capacitor structure (single-layer MOM structure). The capacitance value Cfin0 per unit length of the reference inter-fin capacitance is not related to the size of the MOM capacitor structure. Of course, the size correction factor in the capacitor model of different layers (bottom layer, middle layer and top layer) can also be different. The size correction factor of each layer can be obtained from the sample data of multiple single-layer capacitor structures corresponding to each layer and located in the same interconnect layer.

[0050] In some examples, the steps for obtaining the capacitance value Cfin0 per unit length of the reference interfinite capacitor include: obtaining first sample data of a large-scale monolayer capacitor structure, wherein the interdigital length lf of the monolayer capacitor structure in the first sample data is greater than or equal to a preset size (the preset size is, for example, 4 micrometers); performing linear fitting based on the first sample data to obtain the capacitance value Cfin0 per unit length of the reference interfinite capacitor, wherein the capacitance value Cfin0 per unit length of the reference interfinite capacitor is not correlated with the interdigital length lf (or the correlation is weak).

[0051] Furthermore, the size correction factor can be set to α. e ^ （β / lf） α and β are both correction terms, and lf is the length of the interdigitated fingers. eLet be the natural logarithm, where α is used to adjust the relative magnitude of the size correction factor and the capacitance per unit length Cfin0 of the reference interdigital capacitance, and β is used to adjust the relationship between lf and α. When lf is small, i.e., when applied to small-sized MOM capacitor structures, the size correction factor has a larger correction effect, while when lf is large, i.e., when applied to large-sized MOM capacitor structures, the size correction factor has a smaller correction effect. In some examples, the steps of obtaining the size correction factor (i.e., α and β) include: obtaining second sample data of a small-sized monolayer capacitor structure, in which the interdigital length lf of the monolayer capacitor structure is less than a preset size (the preset size is, for example, 4 micrometers); performing nonlinear fitting based on the first and second sample data to obtain the correction terms (α and β) in the size correction factor, and adjusting α and β in combination with the actual range of lf, so that the size correction factor can simultaneously accommodate both large-sized and small-sized MOM capacitors.

[0052] Understandably, by designing multiple capacitor test structures of different sizes on corresponding interconnect layers, the parameters and corresponding size correction factors of capacitor models at different layers (bottom, middle, and top layers) can be obtained simultaneously. In some examples, for instance, multiple single-layer capacitor structures are designed as first test structures located on the first to sixth interconnect layers, with dimensions (interdigitation length lf) covering multiple sizes from large to small. Similarly, multiple single-layer capacitor structures are designed as second test structures located on the second to sixth interconnect layers, with dimensions (interdigitation length lf) covering multiple sizes from large to small. The dimensions of the multiple first test structures and the multiple second test structures correspond one-to-one. By subtracting the capacitance value of the corresponding second test structure from the capacitance value of the first test structure, the capacitance values ​​of multiple bottom-layer capacitor models of different sizes can be obtained. This allows for the acquisition of various parameters of the bottom-layer capacitor model, as well as size correction factors that accommodate capacitors of different sizes.

[0053] Figure 8 This is a comparison table of the theoretical and actual capacitance values ​​of the top-layer capacitor obtained from the model established in this application. Figure 9 This is a schematic diagram comparing the theoretical and actual capacitance values ​​of the top-layer capacitor obtained from the model established in this application. Figure 8 and Figure 9As shown, the horizontal axis represents the length of the interdigitated fingers in micrometers, and the vertical axis represents the capacitance value in volts (F). The red dashed line represents the theoretical capacitance value provided by the model, and the green dots represent the actual capacitance value. When the interdigitated finger length lf > 4 micrometers (i.e., 16 micrometers, 32 micrometers, and 64 micrometers), the error between the theoretical capacitance value and the actual capacitance value of the top layer capacitor obtained by the model established in this application is less than 1%. When the interdigitated finger length lf ≤ 4 micrometers, the error between the theoretical capacitance value and the actual capacitance value of the top layer capacitor obtained by the model established in this application is less than 0.5%. It can be seen that the theoretical capacitance value of the single-layer capacitor structure obtained by the model established in this application is basically consistent with the actual capacitance value and has high accuracy.

[0054] In summary, this application provides a method for establishing a SPICE model of a MOM capacitor structure. The MOM capacitor structure is disposed in an interconnect structure on a substrate, including N single-layer capacitor structures stacked sequentially in a direction away from the substrate. The N single-layer capacitor structures are located in N interconnect layers of the interconnect structure, and each interconnect layer has one single-layer capacitor structure, where N is a positive integer. The method includes: obtaining the layer number A of the interconnect layer of the single-layer capacitor structure closest to the substrate and the layer number B of the interconnect layer of the single-layer capacitor structure furthest from the substrate, where A and B are both positive integers and B≥A; obtaining the bottom layer coefficients of the MOM capacitor structure based on the layer number A, and obtaining the top layer coefficients of the MOM capacitor structure based on the layer number B; obtaining the middle layer coefficients of the MOM capacitor structure based on the bottom layer coefficients and the top layer coefficients; obtaining the bottom layer capacitor model, the middle layer capacitor model, and the top layer capacitor model based on the corresponding single-layer capacitor structures, where the bottom layer capacitor model, the middle layer capacitor model, and the top layer capacitor model all include size correction factors representing the planar dimensions of the corresponding single-layer capacitor structures; and establishing a SPICE model of the MOM capacitor structure, where SPICE model = bottom layer capacitor model. Bottom layer coefficients + middle layer capacitance model Middle layer coefficient + top layer capacitance model Top-layer coefficients. An unexpected benefit of this application is that, considering the different environments and distances relative to the substrate within the interconnect layers of the MOM capacitor structure, each monolayer capacitor structure is located in a different interconnect layer. Therefore, this application establishes layered (bottom, middle, and top) capacitor models. Each capacitor model is obtained based on the monolayer capacitor structure located in different interconnect layers within the interconnect structure. Bottom, middle, and top-layer coefficients are obtained based on the layer position of each monolayer capacitor structure within the interconnect structure. By multiplying the corresponding layer's capacitor model with its corresponding coefficient, and then summing the capacitor models of each layer as a SPICE model, the established SPICE model of the MOM capacitor structure becomes more detailed and accurate. Furthermore, this application introduces size correction factors into the aforementioned bottom, middle, and top-layer capacitor models to avoid accuracy issues caused by differences in capacitor size, making the model more flexible and accurate when applied to small-sized MOM capacitor structures.

[0055] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the systems disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple, and relevant parts can be referred to the method section.

[0056] It should also be noted that although preferred embodiments have been disclosed above, these embodiments are not intended to limit this application. Any person skilled in the art can make many possible variations and modifications to the technical solutions of this application, or modify them into equivalent embodiments, without departing from the scope of the technical solutions of this application. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of this application, without departing from the content of the technical solutions of this application, shall still fall within the scope of protection of the technical solutions of this application.

[0057] It should also be understood that, unless otherwise specified or indicated, the terms “first,” “second,” “third,” etc., in the specification are used only to distinguish the various components, elements, and steps in the specification, and not to indicate the logical or sequential relationships between the various components, elements, and steps.

[0058] Furthermore, it should be recognized that the terminology described herein is used only to describe particular embodiments and is not intended to limit the scope of this application. It must be noted that the singular forms “a” and “an” as used herein include plural bases unless the context clearly indicates the opposite. For example, a reference to “a step” or “an apparatus” means a reference to one or more steps or apparatuses, and may include secondary steps and secondary apparatuses. All conjunctions used should be understood in the broadest sense. Also, the word “or” should be understood as having the definition of logical “or”, not logical “exclusive OR”, unless the context clearly indicates the opposite. Furthermore, implementations of the methods and / or devices in the embodiments of this application may include performing selected tasks manually, automatically, or in combination.

Claims

1. A method for establishing a SPICE model of a MOM capacitor structure, characterized in that, The MOM capacitor structure is disposed in an interconnect structure on a substrate, comprising N monolayer capacitor structures stacked sequentially in a direction away from the substrate. The N monolayer capacitor structures are located in N interconnect layers of the interconnect structure, and each interconnect layer has one monolayer capacitor structure. N is a positive integer. The method for establishing the structure includes: Obtain the number of interconnect layers A of the single-layer capacitor structure closest to the substrate in the interconnect structure, and the number of interconnect layers B of the single-layer capacitor structure furthest from the substrate in the interconnect structure, where A and B are both positive integers and B≥A; Based on the number of layers A, the bottom layer coefficients of the MOM capacitor structure are obtained, and based on the number of layers B, the top layer coefficients of the MOM capacitor structure are obtained. Based on the bottom layer coefficients and the top layer coefficients, the middle layer coefficients of the MOM capacitor structure are obtained; Based on the corresponding single-layer capacitor structure, a bottom layer capacitor model, a middle layer capacitor model, and a top layer capacitor model are obtained. The bottom layer capacitor model, the middle layer capacitor model, and the top layer capacitor model all include a size correction factor that characterizes the planar dimensions of the corresponding single-layer capacitor structure. Establish a SPICE model of the MOM capacitor structure, wherein the SPICE model = the underlying capacitor model. The bottom layer coefficient + middle layer capacitance model The middle layer coefficient + top layer capacitance model The top-level coefficients.

2. The method for establishing the SPICE model of the MOM capacitor structure according to claim 1, characterized in that, The steps for obtaining the bottom layer coefficients, the top layer coefficients, and the middle layer coefficients include: Determine whether the layer number A is 1. If yes, the bottom layer coefficient = 1; otherwise, the bottom layer coefficient = 0. Determine whether the number of layers B is 1. If yes, the top layer coefficient = 0; otherwise, the top layer coefficient = 1. The middle layer coefficient = the number of layers B - the number of layers A - the bottom layer coefficient The top-level coefficients.

3. The method for establishing the SPICE model of the MOM capacitor structure according to claim 1, characterized in that, The bottom-layer capacitor model, the middle-layer capacitor model, and the top-layer capacitor model all include a first capacitance value module representing the corresponding interfinite capacitance, where the first capacitance value module equals the capacitance per unit length of the interfinite capacitance. Interdigital length.

4. The method for establishing the SPICE model of the MOM capacitor structure according to claim 3, characterized in that, The capacitance per unit length of the interfinite capacitor is equal to the capacitance per unit length of the reference interfinite capacitor. (1 + the corresponding size correction factor).

5. The method for establishing the SPICE model of the MOM capacitor structure according to claim 4, characterized in that, The steps for obtaining the capacitance per unit length of the reference interfinite capacitance include: Obtain first sample data of the single-layer capacitor structure, wherein the interdigitated length of the single-layer capacitor structure in the first sample data is greater than or equal to a preset size. Based on the first sample data, a linear fit is performed to obtain the capacitance value per unit length of the reference interfinite capacitance.

6. The method for establishing a SPICE model of a MOM capacitor structure according to claim 5, characterized in that, The steps for obtaining the size correction factor include: Obtain second sample data of the single-layer capacitor structure, wherein the interdigitated length of the single-layer capacitor structure in the second sample data is less than the preset size; The size correction factor is obtained by performing nonlinear fitting based on the first sample data and the second sample data.

7. The method for establishing a SPICE model of a MOM capacitor structure according to any one of claims 3 to 6, characterized in that, The size correction factor = α e ^ （β / lf） Where α and β are both correction terms and are both positive, and lf is the length of the interdigitated finger. e It is the natural logarithm.

8. The method for establishing a SPICE model of a MOM capacitor structure according to claim 1, characterized in that, The steps for obtaining the bottom-layer capacitor model, the middle-layer capacitor model, and the top-layer capacitor model include: M test structures are established, and the M test structures are respectively labeled as the first test structure to the Mth test structure. The first test structure includes M stacked monolayer capacitor structures, wherein the monolayer capacitor structure closest to the substrate is located in the first interconnect layer. The second test structure includes M-1 stacked monolayer capacitor structures, wherein the monolayer capacitor structure closest to the substrate is located in the second interconnect layer. The Bth test structure includes M-B+1 stacked monolayer capacitor structures, wherein the monolayer capacitor structure closest to the substrate is located in the Bth interconnect layer. The B+1th test structure includes MB stacked monolayer capacitor structures, wherein the monolayer capacitor structure closest to the substrate is located in the B+1th interconnect layer. M is a positive integer and M is greater than B, and B is a positive integer greater than or equal to 2. Subtracting the capacitance value of the second test structure from the capacitance value of the first test structure yields the capacitance value of the single-layer capacitor structure located in the first interconnect layer, thereby establishing the underlying capacitor model. Subtracting the capacitance value of the Bth test structure from the capacitance value of the second test structure yields the capacitance values ​​of the B-2 single-layer capacitor structures located in the middle layer of the interconnect structure, thereby establishing the middle layer capacitor model. Subtracting the capacitance value of the B+1 test structure from the capacitance value of the Bth test structure yields the capacitance value of the single-layer capacitor structure located in the Bth interconnect layer, thereby establishing the top-level capacitor model.

9. The method for establishing a SPICE model of a MOM capacitor structure according to claim 1, characterized in that, The bottom-layer capacitor model, the middle-layer capacitor model, and the top-layer capacitor model all further include a second capacitance value module representing the corresponding fingertip capacitor, a third capacitance value module representing the corresponding first edge parasitic capacitor, and a fourth capacitance value module representing the corresponding second edge parasitic capacitor, wherein the second capacitance value module equals the capacitance value of a single fingertip capacitor. (Number of interdigitated fingers - 1), the third capacitance module is equal to the capacitance of the parasitic capacitance along the edge in the first direction, and the fourth capacitance module is equal to the capacitance of the parasitic capacitance along the edge in the second direction.

10. The method for establishing a SPICE model of a MOM capacitor structure according to claim 9, characterized in that, Multiple plugs are arranged close to the edge of the MOM capacitor structure along the first direction, and the third capacitance module is equal to the capacitance per unit length of the parasitic capacitance at the first edge. Interdigital length.

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