Pixel driving circuit and display device

Abstract

This application discloses a pixel driving circuit and a display device, relating to the field of display technology. The pixel driving circuit includes a driving transistor, a capacitor assembly, a light-emitting element, a voltage sampling module, a light-emitting control module, an initialization module, and a reset module. The capacitor assembly includes a storage capacitor and a first capacitor connected in series between a first node and a second node. The storage capacitor and the first capacitor are connected to a third node. The gate of the driving transistor is connected to the first node, the source of the driving transistor is connected to the third node, and the drain of the driving transistor is connected to the light-emitting element. Thus, during the data writing stage, the data voltage applied to the second node by the voltage sampling module is divided by the storage capacitor and the first capacitor, thereby reducing the influence of the data voltage on the driving current output by the driving transistor during the light-emitting stage, expanding the voltage range of the data voltage, and thus effectively expanding the grayscale range, which is beneficial to improving the display performance of the display device.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a pixel driving circuit and display device. Background Technology

[0002] With the development of display technology, light-emitting display technologies such as active matrix organic light-emitting diode (AMOLED), silicon-based OLED (microOLED), and quantum dot light-emitting diode (QLED) have been widely used in smartphones, wearable devices, televisions and other fields due to their unique advantages such as high contrast, wide viewing angle, low power consumption and the ability to achieve flexible displays.

[0003] In traditional pixel circuits, analog programming voltage is typically written directly to the controlled terminal of the driver module, thereby driving the light-emitting element to emit light, which limits the display performance of the display device.

[0004] The above content is only used to help understand the technical solution of this application and does not represent an admission that the above content is prior art. Summary of the Invention

[0005] The main objective of this application is to provide a pixel driving circuit and a display device, which aims to improve the display performance of the display device.

[0006] To achieve the above objectives, this application proposes a pixel driving circuit, including a driving transistor, a capacitor assembly, a light-emitting element, a voltage sampling module, a light-emitting control module, an initialization module, and a reset module; the capacitor assembly includes a storage capacitor and a first capacitor connected in series between a first node and a second node; the storage capacitor and the first capacitor are connected to a third node;

[0007] The gate of the driving transistor is connected to the first node, the source of the driving transistor is connected to the third node, and the drain of the driving transistor is connected to the light-emitting element; the voltage sampling module is connected to the second node; the initialization module is connected to the first node; the light-emitting control module is connected to the third node; and the reset module is connected to the drain of the driving transistor.

[0008] In the data writing phase of each working cycle, the light emission control module is configured to float the third node, the voltage sampling module is configured to apply a data voltage to the second node, and the initialization module is configured to apply an initialization voltage to the first node, so as to configure the potential difference between the third node and the first node as a programming voltage related to the data voltage.

[0009] During the light emission phase of each working cycle, the light emission control module is configured to apply a first power supply voltage to the third node, the initialization module is configured to float the first node, and the voltage sampling module is configured to float the second node, so as to maintain the potential difference between the third node and the first node at the programming voltage.

[0010] In one embodiment, during the initialization phase of each operating cycle, the voltage sampling module is configured to apply a first fixed voltage to the second node, the initialization module is configured to apply the initialization voltage to the first node, and the light emission control module is configured to apply a first power supply voltage to the third node, such that the absolute value of the potential difference between the first node and the third node is greater than the absolute value of the threshold voltage of the driving transistor.

[0011] In one embodiment, during the threshold voltage compensation phase of each operating cycle, the voltage sampling module is configured to apply the first fixed voltage to the second node, the initialization module is configured to apply the initialization voltage to the first node, the light emission control module is configured to float the third node, and the reset module is configured to apply a reset voltage to the drain of the driving transistor, the reset voltage being less than the first power supply voltage, so that at the end of the threshold voltage compensation phase, the potential difference between the first node and the third node is equal to the threshold voltage of the driving transistor.

[0012] In one embodiment, the programming voltage is related to the data voltage and the threshold voltage of the driving transistor.

[0013] In one embodiment, the reset module is configured to be turned off during the initialization phase, the data writing phase, and the light emission phase.

[0014] In one embodiment, the light emission control module includes a first transistor, the gate of the first transistor is connected to a light emission control signal line, the first electrode of the first transistor is connected to a first power supply, and the second electrode of the first transistor is connected to the third node.

[0015] In one embodiment, the reset module includes a second transistor, the gate of the second transistor is connected to a reset signal line, the first terminal of the second transistor is connected to the gate of the driving transistor, and the second terminal of the second transistor is connected to a reset power supply.

[0016] In one embodiment, the initialization module includes a third transistor, the gate of which is connected to an initialization signal line, the first terminal of which is connected to the first node, and the second terminal of which is connected to an initialization power supply.

[0017] In one embodiment, the voltage sampling module includes a fourth transistor and a fifth transistor. The gate of the fourth transistor is connected to a first sampling signal line, the first terminal of the fourth transistor is connected to a data signal line, and the second terminal of the fourth transistor is connected to the second node. The gate of the fifth transistor is connected to a second sampling signal line, the first terminal of the fifth transistor is connected to a first fixed power supply, and the second terminal of the fifth transistor is connected to the second node.

[0018] In addition, to achieve the above objectives, this application also proposes a display device, including the pixel driving circuit, as well as a scanning circuit, a source driving circuit, and a light-emitting control circuit.

[0019] The scanning circuit is connected to the controlled terminal of the initialization module through an initialization signal line, and is connected to the two controlled terminals of the voltage sampling module through the first sampling signal line and the second sampling signal line, respectively.

[0020] The reset control circuit is connected to the controlled terminal of the reset module via a reset signal line;

[0021] The source drive circuit is connected to the sampling module via a data signal line;

[0022] The light-emitting control circuit is connected to the controlled terminal of the light-emitting control module via a light-emitting control signal line.

[0023] The pixel driving circuit proposed in this application divides the data voltage applied to the second node by the voltage sampling module through the storage capacitor and the first capacitor during the data writing stage. This reduces the impact of the data voltage on the driving current output by the driving transistor during the light emission stage, expands the voltage selection range of the data voltage, and thus effectively improves the grayscale expansion capability of the pixel driving circuit, which is beneficial to improving the display performance of the display device. Attached Figure Description

[0024] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0025] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 This is a schematic diagram of the circuit structure provided in one embodiment of the pixel driving circuit of this application;

[0027] Figure 2This is a schematic diagram of the circuit structure provided for another embodiment of the pixel driving circuit of this application;

[0028] Figure 3 This is a timing diagram of the pixel driving circuit of this application in a specific embodiment;

[0029] Figure 4 This is a schematic diagram of the current flow of the pixel driving circuit in the initialization phase of this application;

[0030] Figure 5 This is a schematic diagram of the current flow in the pixel driving circuit of this application during the threshold voltage compensation stage;

[0031] Figure 6 This is a schematic diagram of the current flow of the pixel driving circuit in this application during the data writing stage;

[0032] Figure 7 This is a schematic diagram of the current flow in the pixel driving circuit of this application during the brightness adjustment stage.

[0033] Explanation of icon numbers:

[0034] M1, driving transistor; 10, capacitor assembly; D1, light-emitting element; 20, voltage sampling module; 30, light-emitting control module; 40, initialization module; 50, reset module; CS, storage capacitor; C1, first capacitor; A, first node; B, second node; C, third node; Vref, initialization voltage; VDD, first power supply voltage; VSS, second power supply voltage; M2, first transistor; EM[n], light-emitting control signal line; M3, second transistor; INT[n], reset signal line; VAR, reset voltage; M5, third transistor; WS1[n], initialization signal line; M4, fourth transistor; M6, fifth transistor; WS2[n], first sampling signal line; DL[m], data signal line; WS3[n], second sampling signal line; VDIM, first fixed voltage; T1, initialization stage; T2, threshold voltage compensation stage; T3, data writing stage; T4, light-emitting stage.

[0035] The purpose, features, and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0036] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0037] In all embodiments of this application, the transistors used (e.g., driving transistor M1, first switching transistor, second switching transistor, third switching transistor, fourth transistor M4, and fifth transistor M6) can be thin-film transistors, field-effect transistors, silicon-based devices, TFT devices, or other devices with similar characteristics. In the embodiments of this application, to distinguish the two terminals of the transistor other than the gate, one terminal is referred to as the first terminal, and the other as the second terminal. In actual operation, the first terminal can be the drain, and the second terminal can be the source; or, the first terminal can be the source, and the second terminal can be the drain.

[0038] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. However, the term "connected" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0039] In traditional pixel circuits, the analog programming voltage is usually written directly into the gate of the driving transistor M1, which in turn drives the light-emitting element D1 to emit light, thus limiting the display performance of the display device.

[0040] To address the aforementioned problems, this application proposes a pixel driving circuit, with reference to... Figure 1The pixel driving circuit of this application embodiment includes a driving transistor M1, a capacitor assembly 10, a light-emitting element D1, a voltage sampling module 20, a light-emitting control module 30, an initialization module 40, and a reset module 50. The capacitor assembly 10 includes a storage capacitor CS and a first capacitor C1 connected in series between a first node A and a second node B. The storage capacitor CS and the first capacitor C1 are connected to a third node C. The gate G of the driving transistor M1 is connected to the first node A, the source S of the driving transistor M1 is connected to the third node C, and the drain of the driving transistor M1 is connected to the light-emitting element D1. The voltage sampling module 20 is connected to the second node B. The initialization module 40 is connected to the first node A. The light-emitting control module 30 is connected to the third node C. The reset module 50 is connected to the drain S of the driving transistor M1. In the data writing phase T3 of each working cycle, the light emission control module 30 is configured to float the third node C, the voltage sampling module 20 is configured to apply a data voltage Vdata to the second node B, and the initialization module 40 is configured to apply a reference voltage Vref to the first node A, so as to configure the potential difference between the third node C and the first node A as a programming voltage related to the data voltage; in the light emission phase T4 of each working cycle, the light emission control module 30 is configured to apply a first power supply voltage VDD to the third node C, the initialization module 40 is configured to float the first node A, and the voltage sampling module 20 is configured to float the second node B, so as to maintain the potential difference between the third node C and the first node A as the programming voltage.

[0041] In at least one embodiment of this application, a complete working cycle of the pixel driving circuit includes at least an initialization phase T1, a threshold voltage compensation phase T2, a data writing phase T3, and a light emission phase T4 performed sequentially.

[0042] In this embodiment, the voltage sampling module 20 is used to connect the data signal line DL[m] and the first fixed power supply. The data signal line DL[m] is used to transmit the data voltage Vdata, and the first fixed power supply is used to provide the first voltage VDIM. The voltage sampling module 20 is connected to the first plate of the first capacitor C1, and the connection point between the voltage sampling module 20 and the first capacitor C1 is the second node B. During the data writing phase T3 of each working cycle, the voltage sampling module 20 can open the path between the data signal line DL[m] and the first capacitor C1, so that the data signal line DL[m] applies the data voltage Vdata to the second node B through the voltage sampling module 20. During the initialization phase T1 of each working cycle, the voltage sampling module 20 can open the path between the first fixed power supply and the first capacitor C1, so that the first fixed voltage VDIM is applied to the second node B through the voltage sampling module 20.

[0043] In this embodiment, the capacitor assembly 10 includes a storage capacitor CS and a first capacitor C1 connected in series between the first node A and the second node B. The gate of the driving transistor M1 is connected to the first plate of the storage capacitor CS to form the first node A. The second plate of the storage capacitor CS and the first plate of the first capacitor C1 are connected to form the third node C. Since the voltage sampling module 20 and the second plate of the first capacitor C1 are connected to the second node B, the storage capacitor CS and the first capacitor C1 are connected in series to form a capacitor voltage divider circuit, which can perform voltage division processing on the data voltage Vdata transmitted by the data signal line DL[m]. Due to the addition of the first capacitor C1, the influence of the data voltage on the driving current output by the driving transistor M1 during the light-emitting stage T4 can be reduced, and the voltage range of the data voltage can be expanded. That is, a wider range of data voltage can be used to control the brightness of the light-emitting element D1, thereby allowing for finer brightness control, effectively expanding the grayscale range, and improving the display performance of the display device.

[0044] In this embodiment, the capacitance values ​​of the storage capacitor CS and the first capacitor C1 can be set to be equal, or they can be in a certain ratio, such as 1:2 or 1:3. The specific capacitance values ​​and the ratio of the storage capacitor CS to the first capacitor C1 can be optimized according to the specific circuit design requirements, and are not limited here. When the data voltage Vdata output by the data signal line DL[m] acts on the capacitor component 10, the voltage of the third node C can be precisely controlled due to the voltage division effect of the first capacitor C1 and the bootstrap effect of the storage capacitor CS. Since the first plate of the first capacitor C1 and the source S of the driving transistor M1 are both connected to the third node C, the above voltage control can further adjust the potential difference between the gate G and the source S of the driving transistor M1 during the non-light-emitting period.

[0045] In this embodiment, the light-emitting element D1 may include an organic light-emitting diode (OLED), a silicon-based OLED (microOLED), a quantum dot light-emitting diode (QLED), or other types of light-emitting elements D1. It emits light under the influence of the driving current provided by the driving transistor M1, and the corresponding brightness is directly determined by this driving current. In at least one embodiment of this application, the first electrode of the light-emitting element D1 is connected to the drain of the driving transistor M1, and the second electrode of the light-emitting element D1 is connected to a second power supply or grounded to form a complete current path. When the driving current increases, the brightness of the light-emitting element D1 increases accordingly; conversely, when the driving current decreases, the brightness decreases.

[0046] In this embodiment, the light-emitting control module 30 is connected to both the first power supply and the third node C. Specifically, the light-emitting control module is connected to both the first power supply and the source S of the driving transistor M1. The first power supply provides a first power supply voltage VDD, and the second power supply provides a second power supply voltage VSS. Together, they provide the necessary voltage difference for the light-emitting element D1 to emit light. In this embodiment, the light-emitting control module 30 can disconnect the connection between the first power supply and the driving transistor M1 during the threshold voltage compensation stage T2 and the data writing stage T3 to prevent the first power supply voltage VDD from affecting the source voltage of the driving transistor M1. Furthermore, during the light-emitting stage T4 and the initialization stage T1, the light-emitting control module 30 can reconnect the connection between the first power supply and the driving transistor M1 to control the application of the first power supply voltage VDD to the source of the driving transistor M1.

[0047] In this embodiment, the initialization module 40 is connected between the initialization power supply and the first node A. The initialization power supply can output a preset initial voltage value Vref to reset or initialize the voltage of the first node A. It can connect the initialization power supply and the first node A during the initialization phase T1, the threshold voltage compensation phase T2, and the data writing phase T3, and disconnect the connection during the light emission phase T4. When the initialization module 40 connects the channel between the initialization power supply and the first node A, the initialization power supply outputs the preset initial voltage Vref and writes it to the gate of the driving transistor M1. Through this process, the gate of the driving transistor M1 is forcibly pulled to a preset initial level, effectively clearing any residual charge or voltage from the previous light emission cycle, preventing any potential voltage shift or residual current from affecting subsequent operations, and ensuring that each pixel starts from the same starting point each time it is updated, thereby improving the display quality and uniformity of the entire display panel.

[0048] In this embodiment, the reset module 50 is connected between the reset power supply and the drain D (first electrode of the light-emitting element D1) of the driving transistor M1. The reset power supply provides a second fixed voltage VAR, which is less than the first power supply voltage VDD. Furthermore, the difference between the second fixed voltage VAR and the second power supply voltage VSS is less than the threshold voltage of the light-emitting element D1. In this embodiment, the reset module 50 connected to the drain of the driving transistor M1 enables the connection between the reset power supply and the drain D of the driving transistor M1 to be turned on during the threshold voltage compensation stage T2. When the reset module 50 turns on the connection between the reset power supply and the drain of the driving transistor M1, the second fixed voltage VAR is written into the drain D (first electrode of the light-emitting element D1) of the driving transistor M1.

[0049] In this embodiment, during the data writing stage T3, the pixel driving circuit performs voltage division processing on the data voltage Vdata applied to the second node B by the voltage sampling module 20 through the storage capacitor CS and the first capacitor C1. This reduces the impact of the data voltage Vdata on the driving current output by the driving transistor M1 during the light emission stage T4, expands the voltage range of the data voltage, and thus effectively expands the grayscale range, which is beneficial to improving the display performance of the display device.

[0050] In one feasible implementation, during the initialization phase T1 of each working cycle, the voltage sampling module 20 is configured to apply a first fixed voltage VDIM to the second node B, the initialization module 40 is configured to apply an initialization voltage Vref to the first node A, and the light emission control module 30 is configured to apply a first power supply voltage VDD to the third node C, so that the absolute value of the potential difference between the first node A and the third node C is greater than the absolute value of the threshold voltage Vth of the driving transistor M1.

[0051] During the threshold voltage compensation phase T2 of each working cycle, the voltage sampling module 20 continues to be configured to apply the first fixed voltage VDIM to the second node B, the initialization module 40 continues to be configured to apply the initialization voltage Vref to the first node A, the light emission control module 30 is configured to float the third node C, and the reset module 50 is configured to apply the reset voltage VAR to the drain of the driving transistor M1. At the beginning of the threshold voltage compensation phase T2, the voltage of the third node C is still the first power supply voltage VDD. Since the absolute value of the potential difference between the first node A and the third node C is greater than the absolute value of the threshold voltage Vth of the driving transistor M1, and the voltage of the drain D of the driving transistor M1 is now the reset voltage VAR, which is less than the first power supply voltage VDD, the driving transistor M1 is in the on state, and the third node C discharges to the reset power supply through the driving transistor M1. Until the potential difference between the first node A and the third node C is equal to the threshold voltage Vth of the driving transistor M1, the driving transistor M1 changes from the on state to the off state, and the threshold voltage compensation phase T2 ends.

[0052] During the data writing phase T3 of each working cycle, the voltage sampling module 20 connects the data signal line DL[m] to the first capacitor C1, enabling the data signal line DL[m] to output the data voltage Vdata to the second plate of the first capacitor C1 during the data writing phase T3. Since the voltage of this phase T3 differs from the first fixed voltage VDIM written to the second plate of the first capacitor C1 during the threshold voltage compensation phase T2, the voltage at the third node C will also change accordingly due to the voltage division by the capacitor component 10 compared to the voltage at the end of phase T2. Therefore, at the end of the data writing phase T3, the voltage at the third node C is related to the data voltage Vdata and the threshold voltage Vth of the driving transistor M1. At this time, the potential difference between the third node C and the first node A, i.e., the programming voltage, is also related to the data voltage Vdata and the threshold voltage Vth of the driving transistor M1.

[0053] During the light-emitting phase T4 of each working cycle, the voltage sampling module 20 is turned off, the light-emitting control module 30 is turned on, the initialization module 40 is turned off, and the driving transistor M1 is controlled by the programming voltage configured in phase T3 to provide a corresponding driving current so that the light-emitting element D1 produces the corresponding brightness.

[0054] In one feasible implementation, refer to Figures 2 to 7 The light emission control module 30 includes a first transistor M2, the gate of the first transistor M2 is connected to the light emission control signal line EM[n], the first electrode of the first transistor M2 is connected to the first power supply, and the second electrode of the first transistor M2 is connected to the third node C.

[0055] The reset module 50 includes a second transistor M3, the gate of which is connected to the reset signal line INT[n], the first terminal of which is connected to the gate of the driving transistor M1, and the second terminal of which is connected to the reset power supply. The initialization module 40 includes a third transistor M5, the gate of which is connected to the initialization signal line WS1[n], the first terminal of which is connected to the first node A, and the second terminal of which is connected to the initialization power supply.

[0056] The voltage sampling module 20 includes a fourth transistor M4 and a fifth transistor M6. The gate of the fourth transistor M4 is connected to the first sampling signal line WS2[n], the first terminal of the fourth transistor M4 is connected to the data signal line DL[m], and the second terminal of the fourth transistor M4 is connected to the second node B. The gate of the fifth transistor M6 is connected to the second sampling signal line WS3[n], the first terminal of the fifth transistor M6 is connected to the first fixed power supply VDIM, and the second terminal of the fifth transistor M6 is connected to the second node B.

[0057] by Figure 2The pixel driving circuit shown uses P-type transistors as an example. A complete working cycle includes at least the following sequentially performed stages: initialization stage T1, threshold voltage compensation stage T2, data writing stage T3, and light emission stage T4. The following is a detailed explanation of the process, using the attached diagram as an example. Figures 3-7 Please provide an explanation.

[0058] like Figure 4 As shown, and refer to Figure 3 When the pixel driving circuit is in the initialization stage T1, the light emission control signal transmitted by the light emission control line EM[n] is at a low level, the first transistor M2 is turned on, and the first power supply voltage VDD is written to the third node C; the reset signal transmitted by the reset signal line INT[n] is at a high level, and the second transistor M3 is turned off; the initialization signal transmitted by the initialization signal line WS1[n] is at a low level, the third transistor M5 is turned on, and the initialization voltage Vref is written to the first node A; the first sampling signal transmitted by the first sampling signal line WS2[n] is at a high level, and the fourth transistor M4 is turned off; the second sampling signal transmitted by the second sampling signal line WS3[n] is at a low level, the fifth transistor M6 is turned on, and the first fixed voltage VDIM is written to the second node B.

[0059] During the initialization phase T1, the gate G voltage of the driving transistor M1 is the voltage of the first node A, and the source S voltage of the driving transistor M1 is the voltage of the third node C. Because the absolute value of the difference between the initialization voltage Vref and the first power supply voltage VDD is greater than the absolute value of the threshold voltage Vth of the driving transistor M1, the driving transistor M1 is in the on state when the initialization phase T1 ends.

[0060] like Figure 5 As shown, and refer to Figure 3 When the pixel driving circuit is in the threshold voltage compensation stage T2, the light emission control signal transmitted by the light emission control line EM[n] is at a high level, the first transistor M2 is cut off, and the third node C is floating; the reset signal transmitted by the reset signal line INT[n] is at a low level, and the second transistor M3 is turned on; the initialization signal transmitted by the initialization signal line WS1[n] is at a low level, the third transistor M5 is turned on, and the initialization voltage Vref is written to the first node A; the first sampling signal transmitted by the first sampling signal line WS2[n] is at a high level, and the fourth transistor M4 is cut off; the second sampling signal transmitted by the second sampling signal line WS3[n] is at a low level, the fifth transistor M6 is turned on, and the first fixed voltage VDIM is written to the second node B.

[0061] During the threshold voltage compensation phase T2, the drain S voltage of the driving transistor M1 is configured as the reset voltage VAR. Since the reset voltage VAR is less than the first power supply voltage VDD, a voltage difference is formed between the source S and drain D of the driving transistor M1 when the threshold voltage compensation phase T2 begins, forming a conduction loop from the third node C to the reset power supply VAR. The third node C begins to discharge until the voltage at the third node C becomes Vref-Vth. At this time, since the difference between the gate G voltage (voltage at the first node A) and the source S voltage (voltage at the third node C) of the driving transistor M1 is equal to the threshold voltage Vth of the driving transistor M1, the driving transistor M1 changes from the on state to the off state. This process can be regarded as discharging the storage capacitor CS. At the end of the threshold voltage compensation phase T2, the voltage difference across the storage capacitor CS is Vth, that is, the storage capacitor CS stores the threshold voltage of the driving transistor M1.

[0062] It should be noted that the difference between the reset voltage VAR and the second power supply voltage VSS is less than the threshold voltage of the light-emitting element D1, so as to prevent the light-emitting element D1 from emitting light during this stage.

[0063] like Figure 6 As shown, and refer to Figure 3 When the pixel driving circuit is in the data writing stage T3, the light emission control signal transmitted by the light emission control line EM[n] is at a high level, the first transistor M2 is cut off, and the third node C is floating; the reset signal transmitted by the reset signal line INT[n] is at a high level, and the second transistor M3 is cut off; the initialization signal transmitted by the initialization signal line WS1[n] is at a low level, the third transistor M5 is turned on, and the initialization voltage Vref is written to the first node A; the first sampling signal transmitted by the first sampling signal line WS2[n] is at a low level, the fourth transistor M4 is turned on, and the data voltage Vdata transmitted by the data signal line DL[m] is written to the second node B; the second sampling signal transmitted by the second sampling signal line WS3[n] is at a high level, and the fifth transistor M6 is cut off.

[0064] During the data writing phase T3, the voltage of the second node B changes from the first fixed voltage VDIM during the threshold voltage compensation phase T2 to the data voltage Vdata. Since the voltage of the first node A remains at the initial voltage Vref, the voltage of the third node C also changes with the voltage of the second node B. The amount of change in the voltage of the second node B is related to the voltage change of the second node B and the voltage division ratio of the storage capacitor CS. Therefore, when the data writing phase T3 ends, the voltage of the third node C is the sum of the voltage during the threshold voltage compensation phase T2 and the change during this phase.

[0065] At this time, the programming voltage formed by the gate-source voltage difference of the driving transistor M1 is the difference between the voltage of the first node A and the voltage of the third node C. Therefore, this programming voltage will be related to the threshold voltage Vth and the data voltage Vdata of the driving transistor M1.

[0066] like Figure 7 As shown, and refer to Figure 3 When the pixel driving circuit is in the light-emitting stage T4, the light-emitting control signal transmitted by the light-emitting control line EM[n] is at a low level, the first transistor M2 is turned on, and the third node C is configured with the first power supply voltage VDD; the reset signal transmitted by the reset signal line INT[n] is at a high level, and the second transistor M3 is turned off; the initialization signal transmitted by the initialization signal line WS1[n] is at a high level, the third transistor M5 is turned off, and the first node A is floated; the first sampling signal transmitted by the first sampling signal line WS2[n] is at a high level, and the fourth transistor M4 is turned off; the second sampling signal transmitted by the second sampling signal line WS3[n] is at a high level, and the fifth transistor M6 is turned off.

[0067] During this light-emitting stage T4, the voltage at the third node C changes. Since the first node A is floating, based on the bootstrap effect of the storage capacitor CS, the gate-source voltage difference Vgs of the driving transistor M1 is still the programming voltage at stage T3. The conduction level of the driving transistor M1 is controlled by this programming voltage, based on the current formula when the driving transistor M1 is operating in the saturation region:

[0068] Idrive = K / 2 * (Vgs - Vth) 2

[0069] It can be seen that when Vgs equals the programming voltage, the driving current Idrive provided by the driving transistor M1 is only related to the data voltage Vdata and the voltage division coefficient of the storage capacitor CS and the first capacitor C1, and is independent of the threshold voltage of the driving transistor M1. This avoids the display unevenness problem caused by the threshold voltage drift of the driving transistor M1, and expands the voltage range of the data voltage, thereby effectively expanding the grayscale range and improving the display performance of the display device.

[0070] This application also provides a display device, including a pixel driving circuit, a scanning circuit, a source driving circuit, and a light emission control circuit; the scanning circuit is connected to the controlled terminal of the initialization module 40 through an initialization signal line WS1[n], and is connected to the two controlled terminals of the voltage sampling module 20 through a first sampling signal line WS2[n] and a second sampling signal line WS3[n], respectively; the reset control circuit is connected to the controlled terminal of the reset module 50 through a reset signal line INT[n]; the source driving circuit is connected to the sampling module through a data signal line DL[m]; and the light emission control circuit is connected to the controlled terminal of the light emission control module 30 through a light emission control signal line EM[n].

[0071] In this embodiment, by precisely controlling the timing of the reset control signal, initialization control signal, light emission control signal, first sampling signal, and second sampling signal, the scanning circuit, source driving circuit, reset control circuit, and light emission control circuit are coordinated to ensure that the pixel driving circuit can operate according to the predetermined timing sequence, thereby achieving precise control of each pixel. Compared with the prior art, the beneficial effects of the display device provided in this application are the same as those of the pixel driving circuit provided in the above embodiments, and will not be repeated here.

[0072] The above are only some embodiments of this application and do not limit the patent scope of this application. All equivalent structural transformations made under the technical concept of this application and using the contents of the specification and drawings of this application, or direct / indirect applications in other related technical fields, are included in the patent protection scope of this application.

Claims

1. A pixel driving circuit, characterized by comprising: It includes a driving transistor, a capacitor assembly, a light-emitting element, a voltage sampling module, a light-emitting control module, an initialization module, and a reset module; the capacitor assembly includes a storage capacitor and a first capacitor connected in series between the first node and the second node; the storage capacitor and the first capacitor are connected to the third node; The gate of the driving transistor is connected to the first node, the source of the driving transistor is connected to the third node, and the drain of the driving transistor is connected to the light-emitting element; the voltage sampling module is connected to the second node; the initialization module is connected to the first node; the light-emitting control module is connected to the third node; and the reset module is connected to the drain of the driving transistor. In the data writing phase of each working cycle, the light emission control module is configured to float the third node, the voltage sampling module is configured to apply a data voltage to the second node, and the initialization module is configured to apply an initialization voltage to the first node, so as to configure the potential difference between the third node and the first node as a programming voltage related to the data voltage. During the light emission phase of each working cycle, the light emission control module is configured to apply a first power supply voltage to the third node, the initialization module is configured to float the first node, and the voltage sampling module is configured to float the second node, so as to maintain the potential difference between the third node and the first node at the programming voltage.

2. The pixel driving circuit according to claim 1, characterized in that, During the initialization phase of each working cycle, the voltage sampling module is configured to apply a first fixed voltage to the second node, the initialization module is configured to apply the initialization voltage to the first node, and the light emission control module is configured to apply a first power supply voltage to the third node, so that the absolute value of the potential difference between the first node and the third node is greater than the absolute value of the threshold voltage of the driving transistor.

3. The pixel driving circuit of claim 2, wherein, During the threshold voltage compensation phase of each operating cycle, the voltage sampling module is configured to apply the first fixed voltage to the second node, the initialization module is configured to apply the initialization voltage to the first node, the light emission control module is configured to float the third node, and the reset module is configured to apply a reset voltage to the drain of the driving transistor, the reset voltage being less than the first power supply voltage, so that at the end of the threshold voltage compensation phase, the potential difference between the first node and the third node is equal to the threshold voltage of the driving transistor.

4. The pixel driving circuit of claim 3, wherein, The programming voltage is related to the data voltage and the threshold voltage of the driving transistor.

5. The pixel driving circuit of claim 4, wherein, The reset module is configured to be turned off during the initialization phase, the data writing phase, and the light emission phase.

6. The pixel driving circuit according to any one of claims 1 to 4, characterized by The light emission control module includes a first transistor, the gate of the first transistor is connected to the light emission control signal line, the first electrode of the first transistor is connected to a first power supply, and the second electrode of the first transistor is connected to the third node.

7. The pixel driving circuit of claim 6, wherein, The reset module includes a second transistor, the gate of which is connected to a reset signal line, the first terminal of which is connected to the gate of the driving transistor, and the second terminal of which is connected to a reset power supply.

8. The pixel driving circuit according to claim 7, characterized in that, The initialization module includes a third transistor, the gate of which is connected to an initialization signal line, the first terminal of which is connected to the first node, and the second terminal of which is connected to an initialization power supply.

9. The pixel driving circuit of claim 8, wherein, The voltage sampling module includes a fourth transistor and a fifth transistor. The gate of the fourth transistor is connected to a first sampling signal line, the first electrode of the fourth transistor is connected to a data signal line, and the second electrode of the fourth transistor is connected to the second node. The gate of the fifth transistor is connected to a second sampling signal line, the first electrode of the fifth transistor is connected to a first fixed power supply, and the second electrode of the fifth transistor is connected to the second node.

10. A display device, characterized by comprising: It includes the pixel driving circuit as described in any one of claims 1-9, as well as a scanning circuit, a source driving circuit, a reset control circuit, and a light emission control circuit; The scanning circuit is connected to the controlled terminal of the initialization module through an initialization signal line, and is connected to the two controlled terminals of the voltage sampling module through the first sampling signal line and the second sampling signal line, respectively. The reset control circuit is connected to the controlled terminal of the reset module via a reset signal line; The source drive circuit is connected to the sampling module via a data signal line; The light-emitting control circuit is connected to the controlled terminal of the light-emitting control module via a light-emitting control signal line.

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