storage device

Abstract

Embodiments of this disclosure relate to a storage device, comprising: at least one data line; a general-purpose memory coupled to the data line and configured to output read data to the data line via a general-purpose read operation during a cache load mode; a cache memory coupled to the data line and configured to write the read data as load data via a cache write operation during a cache load mode; and a controller configured to control the general-purpose read operation of the general-purpose memory and the cache write operation of the cache memory by generating and using an auto-strobe signal and an auto-column address signal during the cache load mode.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0200275, filed on December 30, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Various embodiments of this disclosure relate to semiconductor design techniques, and more specifically, to memory devices. Background Technology

[0004] Storage devices are broadly classified into volatile storage devices and non-volatile storage devices.

[0005] Volatile memory is a type of storage device that stores data only while powered on and loses the stored data when power is lost. Volatile memory includes static random access memory (SRAM) and dynamic random access memory (DRAM).

[0006] Non-volatile storage devices retain stored data even when power is off. Non-volatile storage devices can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), and flash memory.

[0007] As the integration of storage devices increases, the access time during read or write operations also increases. Summary of the Invention

[0008] Various embodiments of this disclosure relate to storage devices including cache memory.

[0009] According to one embodiment of this disclosure, a storage device may include: a general-purpose memory configured to perform a general-purpose read operation or a general-purpose write operation based on a first command signal, a first column address signal, and a row address signal; a cache memory configured to perform a cache read operation or a cache write operation based on a second command signal and a second column address signal; a comparator configured to compare a previous row address signal with a current row address signal and generate a comparison signal corresponding to the comparison result; a processor configured to generate a load control signal, a strobe signal, a column address signal, and a row address signal based on an activation signal, a flag signal, the current row address signal, and the comparison signal; and a control switch configured to generate a first command signal, a first column address signal, a second command signal, and a second column address signal based on the load control signal, the strobe signal, and the column address signal.

[0010] According to one embodiment of this disclosure, a storage device may include: at least one data line; a general-purpose memory coupled to the data line and configured to output read data to the data line via a general-purpose read operation during a cache load mode; a cache memory coupled to the data line and configured to write the read data as load data via a cache write operation during a cache load mode; and a controller configured to control the general-purpose read operation of the general-purpose memory and the cache write operation of the cache memory during a cache load mode by generating and using an auto-strobe signal and an auto-list address signal.

[0011] According to one embodiment of this disclosure, a storage device may include: a storage cell array; a cache memory; and a controller configured to: perform a normal read operation or a normal write operation on the storage cell array based on a first command signal, a first column address signal, and a row address signal; perform a cache read operation or a cache write operation on the cache memory based on a second command signal and a second column address signal; generate the first command signal and the first column address signal or generate the second command signal and the second column address signal during a cache mode; and generate the second command signal and the second column address signal, and then generate the first command signal and the first column address signal during a precharge mode. Attached Figure Description

[0012] Figure 1 This is a block diagram illustrating a storage device according to an embodiment of the present disclosure.

[0013] Figure 2 It is shown Figure 1 The block diagram of the controller is shown.

[0014] Figures 3 to 6 yes Figure 1 The timing diagram for the operation of the storage device is shown. Detailed Implementation

[0015] Various embodiments of the present disclosure will now be described in conjunction with the accompanying drawings to provide a detailed description of the embodiments of the present disclosure, enabling those skilled in the art to readily implement the technical spirit of the present disclosure.

[0016] It should be understood that when an element is described as being "connected" or "coupled" to another element, the connection may be direct or may be physically or electrically indirect through one or more intermediate elements. Furthermore, it should be understood that the terms "comprising," "including," "containing," and "comprise" as used in this specification do not exclude the presence of one or more other elements, but may further include or have one or more other elements, unless otherwise stated. Throughout the description of this specification, some components are described in the singular, but this disclosure is not limited thereto, and it should be understood that components may be formed in the plural.

[0017] Figure 1 This is a block diagram illustrating a storage device 100 according to an embodiment of the present disclosure.

[0018] refer to Figure 1 The storage device 100 may include a command decoder 110, an address latch 120, a flag latch 130, a data input / output (input / output) unit 140, a general-purpose memory 150, a cache memory 160, and a controller 170.

[0019] Command decoder 110 can generate internal command signal ICMD based on external command signal CMD. For example, internal command signal ICMD may include activation signal ACT, precharge signal PRE, read command signal RD, and write command signal WR.

[0020] Address latch 120 can generate internal address signal IADD based on external address signal ADD. For example, internal address signal IADD may include internal row address signal RADD and internal column address signal CADD.

[0021] Flag latch 130 can generate an internal flag signal ICFG based on an external flag signal CFG. For example, the internal flag signal ICFG can be activated during cache load mode.

[0022] The data input / output unit 140 can receive data CDT corresponding to externally written data and output internally written data to the data line GIO<0:D>. Furthermore, the data input / output unit 140 can receive internally read data transmitted via the data line GIO<0:D> and output data CDT corresponding to the internally read data. Hereinafter, regardless of the mode, the internally read data and internally written data transmitted via the data line GIO<0:D> will be referred to as "read data" and "write data," respectively.

[0023] The general-purpose memory 150 can be coupled to the data line GIO<0:D>. The general-purpose memory 150 can perform read, write, or write-back operations based on the first column command signal RDm or WRm, the first column address signal CADDm, and the row address signal RADDm. Hereinafter, the read operation of the general-purpose memory 150 is referred to as a "normal read operation", and the write operation of the general-purpose memory 150 is referred to as a "normal write operation".

[0024] During cache load mode, the general-purpose memory 150 can output read data to the data line GIO<0:D> via a normal read operation. For example, during cache load mode, the general-purpose memory 150 can read read data from a word line corresponding to the row address signal RADDm.

[0025] During cache mode following cache loading mode, the general-purpose memory 150 may or may not perform normal read or write operations.

[0026] The general-purpose memory 150 can perform a write-back operation during the precharge mode following cache mode. For example, during cache mode, a write-back operation can only be performed if the cache memory 160 preferentially performs a write operation.

[0027] For example, a general-purpose memory 150 may include a column decoder 151, a row decoder 153, and a memory cell array 155. The column decoder 151 may be coupled between the data line GIO<0:D> and the bit line BL<0:Y>. The column decoder 151 may select one of the bit lines BL<0:Y> based on a first column command signal RDm or WRm and a first column address signal CADDm. The column decoder 151 may transmit ordinary read data input through the selected bit line as read data to the data line GIO<0:D>. The column decoder 151 may transmit write data input through the data line GIO<0:D> as ordinary write data to the selected bit line. The row decoder 153 may be coupled to the word line WL<0:X>. The row decoder 153 may select one of the word lines WL<0:X> and activate the selected word line based on the row address signal RADDm. The memory cell array 155 may be coupled between the bit line BL<0:Y> and the word line WL<0:X>. The memory cell array 155 may include memory cells arranged in a two-dimensional or three-dimensional structure. The memory cells may be coupled between word lines WL<0:X> and bit lines BL<0:Y>. In some embodiments, the bit lines BL<0:Y> may extend parallel to each other in the column direction, while the word lines WL<0:X> may extend parallel to each other in the row direction. Each memory cell may be located at its respective intersection between the word line WL<0:X> and the bit line BL<0:Y>.

[0028] The cache memory 160 can be coupled to the data line GIO<0:D>. The cache memory 160 can perform read or write operations based on the second column command signal RDc or WRc and the second column address signal CADDc. Hereinafter, the read operation of the cache memory 160 is referred to as a "cache read operation", and the write operation of the cache memory 160 is referred to as a "cache write operation".

[0029] During cache load mode, cache memory 160 can write read data as load data via cache write operations. As described above, read data refers to data read from general memory 150 and output to data line GIO<0:D> during cache load mode.

[0030] During cache mode, cache memory 160 can read loaded data as read data and output the read data to the data line GIO<0:D> via a cache read operation. During cache mode, cache memory 160 can write written data as loaded data (i.e., overwrite) via a cache write operation.

[0031] During the precharge mode, the cache memory 160 can read loaded data as write data and output the write data to the data line GIO<0:D> via a cache read operation.

[0032] The controller 170 can generate a first column command signal RDm or WRm, a first column address signal CADDm, and a row address signal RADDm for controlling the general memory 150 based on the internal command signal ICMD, the internal address signal IADD, and the internal flag signal ICFG, and generate a second column command signal RDc or WRc and a second column address signal CADDc for controlling the cache memory 160.

[0033] During cache loading mode, controller 170 can generate a first read command signal RDm, a first column address signal CADDm, and a row address signal RADDm for controlling normal read operations of general memory 150, and generate a second write command signal WRc and a second column address signal CADDc for controlling cache write operations of cache memory 160. In other words, during cache loading mode, controller 170 can control normal read operations of general memory 150 and cache write operations of cache memory 160, such that normal read data read from general memory 150 is written to cache memory 160 as load data.

[0034] During cache mode following cache loading mode, when a read command corresponding to the target address is requested, controller 170 can generate a second read command signal RDc and a second column address signal CADDc instead of the first read command signal RDm and the first column address signal CADDm, causing loaded data to be read from cache memory 160 instead of ordinary memory 150. During cache mode, when a write command corresponding to the target address is requested, controller 170 can generate a second write command signal WRc and a second column address signal CADDc instead of the first write command signal WRm and the first column address signal CADDm, causing write data to be written to cache memory 160 instead of ordinary memory 150 as loaded data. In other words, during cache mode, when a read or write command corresponding to the target address is requested, controller 170 can control ordinary memory 150 not to perform ordinary read or write operations, and control cache memory 160 to perform cache read or cache write operations. During cached mode, when a read command corresponding to a normal address different from the target address is requested, controller 170 can by default generate a first read command signal RDm and a first column address signal CADDm, causing normal read data to be read from normal memory 150 as read data according to default settings. During cached mode, when a write command corresponding to a normal address is requested, controller 170 can generate a first write command signal WRm and a first column address signal CADDm, causing write data to be written to normal memory 150 as write data according to default settings. That is, during cached mode, when a read command or write command corresponding to a normal address is requested, controller 170 can control cache memory 160 not to perform cache read or cache write operations, and control normal memory 150 to perform normal read or normal write operations.

[0035] During the precharge mode following the cache mode, the controller 170 can generate a second read command signal RDc and a second column address signal CADDc for controlling cache read operations of the cache memory 160, and a first write command signal WRm and a first column address signal CADDm for controlling normal write operations of the general memory 150. That is, during the precharge mode, the controller 170 can control the general memory 150 and the cache memory 160 such that loaded data written to the cache memory 160 is written to the general memory 150 as write data. This can be a write-back operation.

[0036] Figure 2 It is shown Figure 1 The block diagram of controller 170 is shown.

[0037] refer to Figure 2The controller 170 may include a register 171, a comparator 173, a processor 175, and a control switch 177.

[0038] Register 171 can store the internal row address signal RADD as the previous row address signal PREV_RA based on the control signal CTRL. For example, during cache load mode, register 171 can store the internal row address signal RADD as the previous row address signal PREV_RA. The previous row address signal PREV_RA can correspond to the target address.

[0039] During cached mode, comparator 173 compares the previous row address signal PREV_RA with the internal row address signal RADD and generates a comparison signal EX corresponding to the comparison result. During precharge mode, comparator 173 compares the previous row address signal PREV_RA with the internal row address signal RADD and generates a comparison signal EX corresponding to the comparison result. During either cached or precharge mode, comparator 173 identifies the internal row address signal RADD as the current row address signal and compares the current row address signal with the previous row address signal PREV_RA. For example, when the comparison result indicates that the current row address signal is the same as the previous row address signal PREV_RA, comparator 173 can activate the comparison signal EX. When the comparison result indicates that the current row address signal is different from the previous row address signal PREV_RA, comparator 173 can deactivate the comparison signal EX.

[0040] Processor 175 can generate load control signal CC_LOAD, auto-strobe signal INT_CAS, auto-column address signal INT_CA, cache select signal SEL, cache mode signal CC_MODE, write-back control signal CC_WB, row address signal RADDm, and control signal CTRL based on activation signal ACT, precharge signal PRE, internal flag signal ICFG, internal row address signal RADD (i.e., current row address signal), and comparison signal EX.

[0041] For example, during cache load mode, processor 175 can activate the control signal CTRL, the load control signal CC_LOAD, and the cache mode signal CC_MODE based on the activation signal ACT and the internal flag signal ICFG. The control signal CTRL can be activated during the initial period of cache load mode. The load control signal CC_LOAD can be activated during the initial and intermediate periods of cache load mode. The cache mode signal CC_MODE can be activated during the last period of cache load mode. During cache load mode, processor 175 can generate a strobe signal INT_CAS and a self-list address signal INT_CA based on the load control signal CC_LOAD. During cache mode, processor 175 can continuously activate the cache mode signal CC_MODE and determine whether to activate the cache select signal SEL based on the comparison signal EX. For example, processor 175 can activate the cache select signal SEL based on the activated comparison signal EX and deactivate the cache select signal SEL based on the deactivated comparison signal EX. During precharge mode, processor 175 can activate the write-back control signal CC_WB based on the precharge signal PRE. For example, during precharge mode, processor 175 may activate the write-back control signal CC_WB only if a write operation to cache memory 160 is preferentially performed during cache mode. During precharge mode, processor 175 may generate an auto-strobe signal INT_CAS and an auto-list address signal INT_CA based on the write-back control signal CC_WB.

[0042] The control switch 177 can generate a first column command signal RDm or WRm and a first column address signal CADDm for controlling the general memory 150, or a second column command signal RDc or WRc and a second column address signal CADDc for controlling the cache memory 160, based on the read command signal RD, write command signal WR, internal column address signal CADD and output signals of the processor 175 such as CC_LOAD, INT_CAS, INT_CA, SEL, CC_MODE and CC_WB.

[0043] For example, during cache load mode, i.e., when the load control signal CC_LOAD is activated, control switch 177 can generate a first column command signal RDm or WRm and a first column address signal CADDm based on the auto-strobe signal INT_CAS and the auto-column address signal INT_CA, and then generate a second column command signal RDc or WRc and a second column address signal CADDc. During cache mode, i.e., when the cache mode signal CC_MODE is activated, control switch 177 can generate a first column command signal RDm or WRm and a first column address signal CADDm, or a second column command signal RDc or WRc and a second column address signal CADDc, based on the read command signal RD, the write command signal WR, the internal column address signal CADD, and the cache select signal SEL. During the precharge mode, i.e. when the write-back control signal CC_WB is activated, the control switch 177 can generate a second column command signal RDc or WRc and a second column address signal CADDc based on the auto-strobe signal INT_CAS and the auto-column address signal INT_CA, and then generate a first column command signal RDm or WRm and a first column address signal CADDm.

[0044] Below, for reference Figures 3 to 6 For those with Figure 1 and Figure 2 The operation of the storage device 100 with the above-described configuration will be described.

[0045] Figure 3 yes Figure 1 The timing diagram shows the operation of the storage device 100 according to the cache loading mode.

[0046] refer to Figure 3 The internal flag signal ICFG can be activated when the activation signal ACT is activated and the internal row address signal RADD is input. The internal flag signal ICFG can be generated by an external device (such as the host).

[0047] The general-purpose memory 150 can activate the word line WL<0:X> corresponding to the internal row address signal RADD based on the row address signal RADDm. <r1>The controller 170 can internally generate a strobe signal INT_CAS and an internal address signal INT_CA based on the internal flag signal ICFG, and generate a first read command signal RDm and a first column address signal CADDm based on the strobe signal INT_CAS and the internal address signal INT_CA. Then, the controller 170 can generate a second write command signal WRc and a second column address signal CADDc.

[0048] The general-purpose memory 150 can perform a general-purpose read operation based on the first read command signal RDm and the first column address signal CADDm. The cache memory 160 can perform a cache write operation based on the second write command signal WRc and the second column address signal CADDc. For example, when the general-purpose memory 150 sequentially reads general-purpose read data according to the first column address signal CADDm and provides the general-purpose read data as read data d0 to dc to the data lines GIO<0:D>, the cache memory 160 can sequentially write the read data d0 to dc as load data according to the second column address signal CADDc.

[0049] Controller 170 can store the internal row address signal RADD, which is input during cache loading mode, as the previous row address signal PREV_RA.

[0050] Figure 4 yes Figure 1 The timing diagram of the read operation of the storage device 100 according to the cache mode is shown.

[0051] refer to Figure 4 The controller 170 can compare the internal row address signal RADD, which is input along with the activation signal ACT, with the previous row address signal PREV_RA.

[0052] When the input internal row address signal RADD (i.e., the current row address signal) is the same as the previous row address signal PREV_RA, the controller 170 can access the cache memory 160 instead of the general-purpose memory 150. For example, the controller 170 can generate a second read command signal RDc and a second column address signal CADDc instead of a first read command signal RDm and a first column address signal CADDm. The cache memory 160 can provide load data to the data line GIO<0:D> as read data based on the second read command signal RDc and the second column address signal CADDc. In other words, when the input internal row address signal RADD is the same as the previous row address signal PREV_RA, the controller 170 can control the general-purpose memory 150 and the cache memory 160 to perform a cache read operation.

[0053] When the input internal row address signal RADD differs from the previous row address signal PREV_RA, the controller 170 can access the general-purpose memory 150 according to default settings. For example, the controller 170 can generate a first read command signal RDm and a first column address signal CADDm by default. The general-purpose memory 150 can provide normal read data to the data line GIO<0:D> based on the first read command signal RDm and the first column address signal CADDm. That is, when the input internal row address signal RADD differs from the previous row address signal PREV_RA, the controller 170 can control the general-purpose memory 150 and the cache memory 160 to perform a normal read operation.

[0054] As described above, according to embodiments of the present disclosure, during a read operation based on a cache mode, the access time (i.e., tRCD) can be significantly reduced when the controller 170 accesses the cache memory 160 instead of the ordinary memory 150, compared to when the controller 170 accesses the ordinary memory 150.

[0055] Figure 5 yes Figure 1 The timing diagram of the write operation of the storage device 100 according to the cache mode is shown.

[0056] refer to Figure 5 The controller 170 can compare the internal row address signal RADD, which is input along with the activation signal ACT, with the previous row address signal PREV_RA.

[0057] When the input internal row address signal RADD is the same as the previous row address signal PREV_RA, the controller 170 can access the cache memory 160 instead of the general-purpose memory 150. For example, the controller 170 can generate a second write command signal WRc and a second column address signal CADDc instead of a first write command signal WRm and a first column address signal CADDm. The second column address signal CADDc generated during a write operation can be the same as or different from the second column address signal CADDc generated during a read operation (i.e., c1 = c2 or c1 ≠ c2). The cache memory 160 can write the write data provided via the data line GIO<0:D> as load data (i.e., overwrite) based on the second write command signal WRc and the second column address signal CADDc. In other words, when the input internal row address signal RADD is the same as the previous row address signal PREV_RA, the controller 170 can control the general-purpose memory 150 and the cache memory 160 to perform a cache write operation.

[0058] When the input internal row address signal RADD differs from the previous row address signal PREV_RA, the controller 170 can access the general-purpose memory 150 according to default settings. For example, the controller 170 can generate a first write command signal WRm and a first column address signal CADDm by default. The general-purpose memory 150 can write the write data provided through the data line GIO<0:D> as general-purpose write data based on the first write command signal WRm and the first column address signal CADDm. In other words, when the input internal row address signal RADD differs from the previous row address signal PREV_RA, the controller 170 can control the general-purpose memory 150 and the cache memory 160 to perform a general-purpose write operation.

[0059] As described above, according to embodiments of this disclosure, during a write operation based on a cache mode, when the controller 170 accesses the cache memory 160 instead of the ordinary memory 150, the access time (e.g., tRCD) can be significantly reduced compared to when the controller 170 accesses the ordinary memory 150.

[0060] Figure 6 yes Figure 1 The timing diagram of the write-back operation of the storage device 100 shown is based on the precharge mode. For example, only when Figure 5 The write-back operation can only be performed when the cache write operation described in the document is executed first.

[0061] refer to Figure 6 The controller 170 can activate the write-back control signal CC_WB based on the precharge signal PRE. The controller 170 can internally generate a strobe signal INT_CAS and an internal address signal INT_CA based on the write-back control signal CC_WB. The controller 170 can generate a second read command signal RDc and a second column address signal CADDc based on the strobe signal INT_CAS and the internal address signal INT_CA, and then generate a first write command signal WRm and a first column address signal CADDm.

[0062] The cache memory 160 can perform cache read operations based on the second read command signal RDc and the second column address signal CADDc. The general-purpose memory 150 can perform general-purpose write operations based on the first write command signal WRm and the first column address signal CADDm. For example, when the cache memory 160 sequentially provides load data as read data d0 to dc to the data line GIO<0:D> according to the second column address CADDm, the general-purpose memory 150 can sequentially write the read data d0 to dc as general-purpose write data according to the first column address signal CADDm.

[0063] When the read data d0 to dc read from cache memory 160 is written to general memory 150, controller 170 can connect the word line WL corresponding to the internal row address signal RADD. <r1>Deactivation can thus terminate the precharge operation.

[0064] According to embodiments of this disclosure, since the command signal RD or WR is input immediately after the input activation signal ACT during the buffered mode, the time between the activation signal ACT and the command signal RD or WR (i.e., tRCD) can be minimized.

[0065] According to embodiments of this disclosure, a cache memory may be included in the storage device, which makes it possible to reduce the access time, i.e., tRCD, during read or write operations.

[0066] While the present invention has been described and illustrated with reference to specific embodiments, the disclosed embodiments are provided for descriptive purposes and are not intended to be limiting. Furthermore, it is worth noting that, as those skilled in the art will recognize from this disclosure, the embodiments of this disclosure can be implemented in various ways through substitutions, alterations, and modifications, all of which fall within the scope of the following claims. These embodiments can be combined to form other embodiments.

Claims

1. A storage device, comprising: A general-purpose memory that performs a normal read operation or a normal write operation based on a first command signal, a first column address signal, and a row address signal; A cache memory that performs cache read or cache write operations based on a second command signal and a second column address signal; A comparator compares the previous row address signal with the current row address signal and generates a comparison signal corresponding to the comparison result. The processor generates a load control signal, a strobe signal, a column address signal, and the row address signal based on the activation signal, the flag signal, the current row address signal, and the comparison signal; as well as A control switch generates the first command signal, the first column address signal, the second command signal, and the second column address signal based on the load control signal, the auto-gating signal, and the auto-column address signal.

2. The storage device according to claim 1, wherein: When the load control signal is activated, the control switch generates the first command signal and the first column address signal, and then generates the second command signal and the second column address signal. The ordinary memory performs the ordinary read operation based on the first command signal and the first column address signal, and The cache memory performs the cache write operation based on the second command signal and the second column address signal.

3. The storage device according to claim 1, wherein, During cache mode, The processor generates a cache mode signal and a selection signal, and The control switch generates the first command signal and the first column address signal or the second command signal and the second column address signal based on the cache mode signal and the selection signal.

4. The storage device according to claim 3, wherein, The processor activates the cache mode signal after deactivating the load control signal, and determines whether to activate the selection signal based on the comparison signal. When the selection signal is activated, the control switch generates the second command signal and the second column address signal.

5. The storage device according to claim 1, wherein: The processor generates a write-back control signal during precharge mode. When the write-back control signal is activated, the control switch generates the second command signal and the second column address signal, and then generates the first command signal and the first column address signal. The cache memory performs the cache read operation based on the second command signal and the second column address signal, and The ordinary memory performs the ordinary write operation based on the first command signal and the first column address signal.

6. The storage device according to claim 1, further comprising a register, the register storing the previous row address signal based on a control signal. in, The processor generates the control signal based on the flag signal.

7. A storage device, comprising: At least one data cable; A general-purpose memory, coupled to the data line, outputs read data to the data line via a normal read operation during cache load mode; A cache memory, coupled to the data line, writes the read data as load data via a cache write operation during the cache load mode; as well as A controller that controls the normal read operation of the normal memory and the cache write operation of the cache memory by generating and using a strobe signal and a self-list address signal during the cache loading mode.

8. The storage device according to claim 7, wherein, The controller: During a cache mode following the cache loading mode, when a read command for reading data is requested, controls the cache memory to read the loaded data from the cache memory according to the row address signal.

9. The storage device according to claim 7, wherein, The controller: During the cache mode following the cache loading mode, when a write command for writing data is requested, controls the cache memory to write the write data to the cache memory.

10. The storage device according to claim 9, wherein, The controller controls the cache memory and the general memory during the precharge mode following the cache mode, such that the write data is written to the general memory.

11. The storage device according to claim 7, wherein, The controller includes: A comparator compares the previous row address signal with the current row address signal and generates a comparison signal corresponding to the comparison result. The processor generates a load control signal, a strobe signal, a column address signal, and a row address signal based on an activation signal, a flag signal, the current row address signal, and the comparison signal; and A control switch that generates a first command signal, a first column address signal, a second command signal, and a second column address signal based on the load control signal, the auto-gating signal, and the auto-column address signal.

12. The storage device according to claim 11, wherein: When the load control signal is activated, the control switch generates the first command signal and the first column address signal, and then generates the second command signal and the second column address signal. The ordinary memory performs the ordinary read operation based on the row address signal, the first command signal, and the first column address signal, and The cache memory performs the cache write operation based on the second command signal and the second column address signal.

13. The storage device according to claim 11, wherein, During the cache mode following the aforementioned cache loading mode, The processor generates a cache mode signal and a selection signal, and The control switch generates the first command signal and the first column address signal or the second command signal and the second column address signal based on the cache mode signal and the selection signal.

14. The storage device according to claim 13, wherein, The processor activates the cache mode signal after deactivating the load control signal, and determines whether to activate the selection signal based on the comparison signal. When the selection signal is activated, the control switch generates the second command signal and the second column address signal.

15. The storage device according to claim 13, wherein: The processor generates a write-back control signal during a precharge mode following the cache mode. When the write-back control signal is activated, the control switch generates the second command signal and the second column address signal, and then generates the first command signal and the first column address signal. The cache memory performs a cache read operation based on the second command signal and the second column address signal, and The ordinary memory performs a normal write operation based on the first command signal and the first column address signal.

16. The storage device according to claim 11, wherein, The controller also includes a register that stores the previous row address signal based on control signals, and The processor generates the control signal based on the flag signal.

17. A storage device, comprising: Storage cell array; Cache memory; as well as Controller, the controller: Based on the first command signal, the first column address signal, and the row address signal, perform a normal read operation or a normal write operation on the storage cell array. The cache read operation or cache write operation is performed on the cache memory based on the second command signal and the second column address signal. During cache mode, the first command signal and the first column address signal are generated, or the second command signal and the second column address signal are generated, and During the precharge mode, the second command signal and the second column address signal are generated, and then the first command signal and the first column address signal are generated.

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