Clock signals provide circuits, methods, memories, electronic devices, and equipment.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- CHENGDU HAIGUANG INTEGRATED CIRCUIT DESIGN CO LTD
- Filing Date
- 2026-04-02
- Publication Date
- 2026-06-30
Smart Images
Figure CN122314036A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of memory technology, and more specifically, to a clock signal providing circuit, method, memory, electronic device, and apparatus. Background Technology
[0002] As the performance requirements of memory continue to increase, existing technologies add Glitch latch structures to memory to accelerate data reading speed, thereby meeting the timing requirements of high-performance scenarios.
[0003] However, while the glitch latch structure improves read speed, it also introduces additional power consumption. In actual chip design, the same memory is often instantiated multiple times in different operating environments. In some operating environments, read latency is not a primary concern; power consumption is more important.
[0004] Therefore, there is an urgent need for a solution that enables memory with a Glitch latch structure to switch between performance-priority mode and power-priority mode. Summary of the Invention
[0005] The purpose of this application is to provide a clock signal providing circuit, method, memory, electronic device and apparatus to solve the problem in the related art that the memory with the Glitch latch structure cannot switch between performance priority mode and power priority mode.
[0006] This application provides a clock signal providing circuit, including: The first delay circuit has its input terminal configured to receive the original input clock signal of the Glitch latch structure, which is used to delay the original input clock signal to obtain a delayed input clock signal; the phase of the delayed input clock signal is delayed compared to the phase of the original input clock signal, and the delay is less than half a clock cycle of the original input clock signal. The selector has a first input terminal configured to receive the original input clock signal, a second input terminal connected to the output terminal of the first delay circuit, and an output terminal configured to be connected to the clock input terminal of the Glitch latch structure in the memory. A control circuit, connected to the control terminal of the selector, is used to acquire scene feature information and control the selector to output the original input clock signal or the delayed input clock signal according to the scene feature information.
[0007] In the above implementation, scene feature information is acquired, and the selector is controlled to output either the original input clock signal or the delayed input clock signal based on this information. Since the selector's input is connected to the clock input of a Glitch latch structure configured to operate in memory, the operating clock of the Glitch latch structure can change according to the scene feature information. When the selector outputs the original input clock signal, the Glitch latch structure operates in normal mode, i.e., high-speed data readout with high power consumption. However, when the selector outputs the delayed input clock signal, the phase of the delayed input clock signal is delayed compared to the phase of the original input clock signal. Therefore, even when reading data 0, if the original data output is 1, the data output time from 1 to 0 will be determined by Gclk_AR, which is slower than the method determined by the data path SBL_AFZX. However, when continuously reading 1s, since the delay is less than half a clock cycle of the original input clock signal and greater than the phase difference between the memory's operating clock signal and the data signal acquired by the memory, the rising edge of the Glitch latch structure's operating clock will not coincide with the high level of the bus output data signal. Correspondingly, the output data of the Glitch latch structure will not produce glitches, thereby reducing power consumption. This allows the memory with the Glitch latch structure to switch between performance-priority mode and power-priority mode based on scene characteristic information.
[0008] Optionally, the scene feature information includes the operating clock signal of the memory; the control circuit includes a clock cycle determination circuit, a first input terminal configured to receive the operating clock signal of the memory, a second input terminal configured to receive a cycle threshold signal, and an output terminal connected to the control terminal of the selector; the clock cycle determination circuit is used to determine whether the clock cycle of the operating clock signal is greater than the cycle threshold signal; if the clock cycle of the operating clock signal is greater than the cycle threshold signal, the selector is controlled to output the delayed input clock signal; if the clock cycle of the operating clock signal is less than the cycle threshold signal, the selector is controlled to output the original input clock signal.
[0009] In the above implementation, by determining the relationship between the clock period of the operating clock signal and the period threshold signal, the current operating mode of the memory can be effectively identified, thereby determining whether it should adopt a performance-priority mode or a power-priority mode. Specifically, when the clock period of the operating clock signal is greater than the period threshold signal, it indicates that the memory is in a low-frequency operating mode. In this mode, the requirement for data read speed is lower, so the input clock signal can be delayed after the selector output, thereby achieving the effect of reducing the data read power consumption of the Glitch latch structure by sacrificing read speed.
[0010] When the clock period of the operating clock signal is less than the aforementioned period threshold, the memory is in a high-frequency operating mode. In this mode, the system is extremely sensitive to read timing and requires minimizing access latency. At this time, the selector outputs the undelayed raw input clock signal to ensure that the Glitch latch structure can complete data latching in the shortest possible time, meeting the setup time and timing convergence requirements in high-performance scenarios.
[0011] Optionally, the clock period determination circuit includes: The first AND gate has a first input configured to receive the working clock signal and a second input configured to receive a period threshold signal. When the clock period of the working clock signal is greater than the period threshold signal, the high level of the working clock signal and the high level of the period threshold signal overlap. The first AND gate is used to output a set pulse when the high level of the working clock signal and the high level of the period threshold signal overlap. The trigger has its set terminal connected to the output terminal of the first AND gate, and its output terminal connected to the control terminal of the selector; the reset terminal is configured to receive a reset signal.
[0012] In the above implementation, the first AND gate outputs a set pulse when the high level of the working clock signal coincides with the high level of the period threshold signal; and the high level of the working clock signal and the high level of the period threshold signal only coincide when the clock period of the working clock signal is greater than the period threshold signal. Therefore, the first AND gate only outputs a set pulse when the clock period of the working clock signal is greater than the period threshold signal. Correspondingly, the flip-flop only controls the selector to output a delayed input clock signal when the clock period of the working clock signal is greater than the period threshold signal, and controls the selector to output the original input clock signal when the clock period of the working clock signal is less than the period threshold signal. Thus, when the clock period of the memory's working clock signal is less than the period threshold signal, the memory with the Glitch latch structure can be accurately controlled to operate in a power-priority mode, and when the clock period of the memory's working clock signal is greater than the period threshold signal, the memory with the Glitch latch structure can be accurately controlled to operate in a performance-priority mode.
[0013] Optionally, the clock signal providing circuit further includes: a periodic threshold signal generating circuit, the input of which is configured to access the working clock signal of the memory; and the output of which is connected to the first input of the first AND gate. The periodic threshold signal generation circuit is used to process the working clock signal according to a preset clock period threshold to generate a periodic threshold signal; when the clock period of the working clock signal is greater than the clock period threshold, the high level of the working clock signal and the high level of the periodic threshold signal coincide; when the clock period of the working clock signal is less than the clock period threshold, the high level of the working clock signal and the high level of the periodic threshold signal do not coincide.
[0014] In the above implementation, a periodic threshold signal generation circuit processes the operating clock signal according to a preset clock cycle threshold to generate a periodic threshold signal. In this way, the periodic threshold signal can dynamically match the memory's operating clock signal, thereby accurately determining whether the current clock cycle of the memory's operating clock signal is in a high-frequency or low-frequency operating range. This provides a reliable basis for subsequently switching the memory with the Glitch latch structure to a performance-priority mode or a power-priority mode.
[0015] Optionally, the periodic threshold signal generation circuit includes: A duty cycle adjustment circuit, the input of which is configured to receive the working clock signal, is used to reduce the duty cycle of the working clock signal to obtain a narrowband clock signal; The second delay circuit has its input terminal connected to the output terminal of the duty cycle adjustment circuit, and its output terminal connected to the second input terminal of the first AND gate. The second delay circuit is used to delay the narrowband clock signal according to the clock period threshold to obtain the period threshold signal.
[0016] In the above implementation, a narrowband clock signal is obtained by reducing the duty cycle of the memory's operating clock signal using a duty cycle adjustment circuit. Then, a second delay circuit delays the narrowband clock signal based on a clock cycle threshold to obtain a cycle threshold signal. This allows for a cycle threshold signal that changes with the memory's operating clock signal, enabling accurate determination of whether the memory's operating clock signal's clock cycle is in a high-frequency or low-frequency operating range in subsequent processes.
[0017] Optionally, the duty cycle adjustment circuit includes: The third delay circuit has its input terminal configured to receive the working clock signal, and is used to delay the working clock signal to obtain a delayed working clock signal. The phase of the delayed working clock signal is delayed compared to the phase of the working clock signal, and the delay is less than half a clock cycle of the working clock signal. The input terminal of the first inverter is connected to the output terminal of the third delay circuit; The second AND gate has its first input connected to the output of the first inverter, its second input configured to receive the operating clock signal, and its output connected to the input of the second delay circuit.
[0018] In the above implementation process, the working clock signal of the memory is delayed by the third delay circuit, and the delayed working clock signal is inverted by the first inverter. Then, the working clock signal of the memory and the inverted delayed working clock signal are ANDed by the second AND gate. In this way, the duty cycle of the working clock signal of the memory can be adjusted to obtain an accurate narrowband pulse signal.
[0019] Optionally, the scene feature information includes ambient temperature, and the control circuit includes a temperature judgment circuit, with its input terminal configured to receive the ambient temperature and its output terminal connected to the control terminal of the selector; the temperature judgment circuit is used to control the selector to output the delayed input clock signal when the ambient temperature is greater than the ambient temperature threshold, and to control the selector to output the original input clock signal when the ambient temperature is less than the ambient temperature threshold.
[0020] In the above implementation, by judging the relationship between the ambient temperature and a preset ambient temperature threshold, the ambient temperature of the memory can be effectively determined, thereby dynamically selecting the memory's operating mode. Specifically, when the ambient temperature is higher than the threshold, the selector outputs a delayed input clock signal, thus reducing memory power consumption, heat generation, and the risk of thermal runaway. When the ambient temperature is lower than the threshold, it indicates that the memory has sufficient heat dissipation margin to withstand the additional heat generated by high-performance operation. Therefore, in this case, the selector can output the original input clock signal to achieve high-speed data reading through the glitch latch structure in the memory.
[0021] Optionally, the control circuit is a central processing unit.
[0022] In the above implementation process, by using the central processing unit as the control circuit, adjustments to the memory hardware structure can be reduced.
[0023] Optionally, the first delay circuit, the selector, the control circuit, and the Glitch latch structure are integrated into the memory.
[0024] In the above implementation, by integrating the first delay circuit, the selector, the control circuit, and the Glitch latch structure into the memory, the memory with the Glitch latch structure can switch between performance-priority mode and power-priority mode without modifying or minimizing the modification of the memory's external interface.
[0025] Optionally, the first delay circuit, the selector, and the Glitch latch structure are integrated into the memory; the control circuit is independently located outside the memory.
[0026] In the above implementation, by integrating the first delay circuit, the selector, and the Glitch latch structure into the memory, and setting the control circuit independently outside the memory, the area of the memory can be effectively reduced.
[0027] Secondly, this application provides a clock signal providing method, applied in a control circuit of the clock signal providing circuit as described above; the method includes: Acquire scene feature signals; Based on the scene feature signal, the selector is controlled to output the original input clock signal to the Glitch latch structure, or to output the delayed input clock signal.
[0028] Thirdly, this application provides a memory including a clock signal providing circuit as described above.
[0029] Fourthly, this application provides an electronic device, including a clock signal providing circuit as described above and a memory having a Glitch latch structure; wherein: The first delay circuit, the selector, the control circuit, and the Glitch latch structure are integrated into the memory; or, The first delay circuit, the selector, and the Glitch latch structure are integrated into the memory; the control circuit is independently located outside the memory.
[0030] Fifthly, this application provides an electronic device, including the electronic components described above. Attached Figure Description
[0031] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.
[0032] Figure 1(a) is a schematic diagram of the structure of an 8T SRAM; Figure 1(b) is a schematic diagram of the circuit structure for transferring data from the selected bit cell to the Glitch latch structure in 8T SRAM; Figure 1(c) is a schematic diagram of the LE module; Figure 1(d) is a schematic diagram of the circuit structure of the Glitch latch; Figure 1(e) shows the circuit structure with the Glitch latch structure operating in normal mode and the test circuit in a high-impedance state, with the test circuit omitted. Figure 2(a) shows the timing correspondence between the memory's working clock signal CCLK, the bus transmission data signal SBL_AFZX, the Glitch latch structure's working clock signal Gclk_AR, and the Glitch latch structure's output data RdData when the working clock signal of the Glitch latch structure is the original input clock signal and 0 is read continuously.
[0033] Figure 2(b) is a schematic diagram of the timing correspondence between the memory's working clock signal CCLK, the bus transmission data signal SBL_AFZX, the Glitch latch structure's working clock signal Gclk_AR, and the Glitch latch structure's output data RdData when the working clock signal of the Glitch latch structure is the original input clock signal and 1 is read continuously.
[0034] Figure 3(a) is a schematic diagram of a clock signal providing circuit provided in an embodiment of this application; Figure 3(b) is a schematic diagram of another clock signal providing circuit provided in an embodiment of this application; Figure 4 A schematic diagram of another clock signal providing circuit provided in an embodiment of this application; Figure 5 A schematic diagram of another clock signal providing circuit provided in an embodiment of this application; Figure 6 A schematic diagram of another clock signal providing circuit provided in an embodiment of this application; Figure 7 For based on Figure 6 The diagram shows the correspondence between the clock signal providing circuit shown, the memory's working clock signal CLK, the delayed working clock signal L1 output by the third delay circuit, the pulse signal L2 output by the first inverter, and the pulse signal CLKpr output by the second AND gate. Figure 8(a) is based on Figure 6 The clock signal providing circuit shown in the diagram illustrates the timing relationship between the pulse signal CLKprdly output by the second delay circuit, the memory's working clock signal CLK, the pulse signal S output by the first AND gate, and the pulse signal En output by the RS flip-flop. Figure 8(a) is based on Figure 6 The diagram shows the timing correspondence between the pulse signal CLKprdly output by the second delay circuit obtained by the clock signal providing circuit, the memory's working clock signal CLK, the pulse signal S output by the first AND gate, and the pulse signal En output by the RS flip-flop. Figure 9(a) shows the results based on Figure 6 The clock signal supply circuit shown is a schematic diagram illustrating the timing correspondence between the memory's working clock signal CCLK, the bus transmission data signal SBL_AFZX, the working clock signal of the Glitch latch structure, and the output data RdData of the Glitch latch structure when continuously reading 0. Figure 9(b) is based on Figure 6The clock signal providing circuit shown is a schematic diagram illustrating the timing correspondence between the memory's operating clock signal CCLK, the bus transmission data signal SBL_AFZX, the operating clock signal of the Glitch latch structure, and the output data RdData of the Glitch latch structure when continuously reading 1. Figure 9(c) is based on Figure 6 The clock signal providing circuit shown illustrates the timing relationship between the memory's operating clock signal CCLK, the bus transmission data signal SBL_AFZX, the operating clock signal of the Glitch latch structure, and the output data RdData of the Glitch latch structure during the read 1-read 0-read 1-read 0 scenarios.
[0035] Figure 10 A power consumption comparison diagram is obtained by using the Glitch latch structure in normal mode and by delaying the original input clock signal of the Glitch latch structure based on the clock signal providing circuit provided in this application. Figure 11 This is a flowchart illustrating a clock signal provision method provided in an embodiment of this application. Detailed Implementation
[0036] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings.
[0037] Memory including Glitch latch structure, such as 8T SRAM (Static Random-Access Memory), for example, as shown in Figure 1(a), 8T SRAM may include a control module, a decode and word line driver module (decode & drv), an array module (bitcell), an in-array data transfer module (LE), and a global data transfer module (IO & latch).
[0038] As shown in the output transmission data diagram in 1(b), in the 8T SRAM, the selected bitcell can send data into the corresponding LE module and transmit it outward through the global bit line Sbl_afzx (also known as GBL). The gray marked part is the Glitch latch structure, which is located in the IO module and is used to latch the data signal from the global bit line.
[0039] For example, for each bitcell, the bitcell includes a first NMOS transistor NM1, a second NMOS transistor NM2, a third NMOS transistor NM3, a fourth NMOS transistor NM4, a third inverter F3, and a fourth inverter F4.
[0040] The first NMOS transistor, NM1, has its source configured to connect to the bit line signal BLT, its gate configured to connect to the write word line select signal WWL, and its drain connected to the input of the third inverter F3 and the output of the fourth inverter F4.
[0041] The input terminal of the third inverter F3 is connected to the output terminal of the fourth inverter F4, and the output terminal of the third inverter F3 is connected to the input terminal of the fourth inverter F4 and the drain of the second NMOS transistor NM2.
[0042] The source of the second NMOS transistor NM2 is configured to be connected to BLT, and the gate is configured to be connected to WWL.
[0043] The input of the fourth inverter F4 is connected to the gate of the third NMOS transistor NM3.
[0044] The third NMOS transistor, NM3, has its source grounded, and its drain connected to the source of the fourth NMOS transistor, NM4.
[0045] The fourth NMOS transistor, NM4, has its gate connected to RWL and its drain connected to the LE module.
[0046] The LE module is marked in yellow-green in Figure 1(b). The detailed structural diagram of the LE module can be seen in Figure 1(c). The LE module includes a first PMOS transistor PM1, a second PMOS transistor PM2, a third PMOS transistor PM3, a fourth PMOS transistor PM4, a fifth PMOS transistor PM5, a fifth NMOS transistor NM5, and a second NAND gate Y2.
[0047] The first PMOS transistor PM1 has its gate configured to receive the charging enable signal Pch_arx, its source configured to receive the operating voltage, and its gate connected to the first input terminal of the second NAND gate Y2 and the drain of the fourth NMOS transistor NM4 in one of the bit cells.
[0048] The source of the second PMOS transistor PM2 is configured to be connected to the operating voltage, and its gate is connected to the output of the second NAND gate Y2.
[0049] The source of the third PMOS transistor PM3 is connected to the drain of the second PMOS transistor PM2, and its drain is connected to the drain of the fourth NMOS transistor NM4, as well as the first input terminal of the second NAND gate Y2.
[0050] The second NAND gate Y2 has its second input connected to the drain of the fourth NMOS transistor NM4 in another bit cell. Its output is connected to the gates of the fifth NMOS transistor NM5 and the fifth PMOS transistor PM5.
[0051] The fifth NMOS transistor, NM5, has its source grounded and its drain connected to the bus input of the Glitch latch structure via the bus Sbl_AFZX.
[0052] The drain of the fifth PMOS transistor PM5 is connected to the drain of the fifth NMOS transistor NM5, and is connected to the bus input of the Glitch latch structure through the bus Sbl_AFZX.
[0053] The fourth PMOS transistor, PM4, has its source configured to receive the operating voltage, its gate configured to receive the first state sustain signal Sblkpr_afx, and its drain connected to the source of the fifth PMOS transistor, PM5. The bus Sbl_AFZX also houses the sixth PMOS transistor PM6, the seventh PMOS transistor PM7, and the third NAND gate Y3.
[0054] The sixth PMOS transistor, PM6, has its drain connected to the bus Sbl_AFZX, its gate configured to connect to Sblkpr_afx, and its source configured to connect to the operating voltage.
[0055] The seventh PMOS transistor PM7 has its drain connected to the bus Sbl_AFZX, its source configured to receive the operating voltage, and its gate connected to the output of the third NAND gate Y3.
[0056] The third NAND gate Y3 has its first input connected to the bus Sbl_AFZX, and its second input configured to connect to the second state sustaining signal Jtsblkpen. Similarly, the second state sustaining signal Jtsblkpen is only used under specific test conditions and is not used in the scenario described in this application.
[0057] The Glitch latch structure is a special latch that combines two input data and clock circuit structures for both test mode and normal mode, taking into account speed and area considerations.
[0058] The circuit diagram of the Glitch latch structure is shown in Figure 1(d). The yellow highlighted section represents the input data structure used in the test mode of the Glitch latch structure. The blue highlighted section represents the data input structure used in the normal mode of the Glitch latch structure. When the Glitch latch structure is operating in normal mode, i.e., for data latching, the circuit in the yellow highlighted section is in a high-impedance state.
[0059] Therefore, the circuit structure of the Glitch latch structure operating in normal mode can be shown in Figure 1(e), including logic circuit, inverting hold circuit and first NAND gate.
[0060] The logic circuit includes the eighth PMOS transistor PM8, the sixth NMOS transistor NM6, and the seventh NMOS transistor NM7.
[0061] The gate of the eighth PMOS transistor PM8 is configured to be connected to the bus, and the source is configured to be connected to the operating voltage.
[0062] The drain of the sixth NMOS transistor NM6 is connected to the drain of the eighth PMOS transistor PM8, and its gate is configured to receive the working clock signal of the Glitchlatch structure.
[0063] The seventh NMOS transistor, NM7, has its gate configured to be connected to the bus, its source grounded, and its drain connected to the source of the sixth NMOS transistor, NM6.
[0064] The inverting hold circuit includes a second inverter F2, the input of which is connected to the drain of the eighth PMOS transistor PM8 and the drain of the sixth NMOS transistor NM6.
[0065] The inverting hold circuit may also include a ninth PMOS transistor PM9, a tenth PMOS transistor PM10, an eighth NMOS transistor NM8, and a ninth NMOS transistor NM9.
[0066] The ninth PMOS transistor PM9 has its source configured to be connected to the operating voltage and its gate configured to be connected to the output of the second inverter F2.
[0067] The source of the tenth PMOS transistor PM10 is connected to the drain of the ninth PMOS transistor PM9, and its gate is configured to receive the working clock signal Gclk_AR of the Glitchlatch structure. Its drain is connected to the input of the second inverter F2.
[0068] The eighth NMOS transistor, NM8, has its drain connected to the drain of the tenth PMOS transistor, PM10, and its gate is configured to be connected to the bus.
[0069] The ninth NMOS transistor, NM9, has its source grounded, its drain connected to the source of the eighth NMOS transistor, NM8, and its gate connected to the output of the second inverter, F2.
[0070] The first NAND gate Y1 has its first input connected to the output of the second inverter F2, its second input configured to connect to the bus SBL_AFZX, and its output used to output data RdData.
[0071] Based on the circuit structure diagram of the Glitch latch structure in Figure 1(e), if the working clock signal of the Glitch latch structure is the original input clock signal when continuously reading 0, the timing correspondence between the working clock signal CCLK of the memory, the data signal SBL_AFZX of the bus transmission, the working clock signal Gclk_AR of the Glitch latch structure, and the output data RdData of the Glitch latch structure can be shown in Figure 2(a).
[0072] Based on the circuit structure diagram of the Glitch latch structure in Figure 1(e), when reading 1 continuously, if the working clock signal of the Glitch latch structure is the original input clock signal, the timing correspondence between the working clock signal CCLK of the memory, the data signal SBL_AFZX of the bus transmission, the working clock signal Gclk_AR of the Glitch latch structure, and the output data RdData of the Glitch latch structure can be shown in Figure 2(b).
[0073] Because the output data RdData of the Glitch latch structure is initially constant at 0, it can be read immediately when reading data 0. When continuously reading 1s, the data SBL_AFZX transmitted from H→L can be directly output through the first input of the first NAND gate, which is fast. However, this comes at the cost of having to be set low before the next 1 read, resulting in an extra transition during continuous 1 outputs, creating a glitch. The inverting hold circuit also has an extra latching action, increasing read power consumption. As shown in Figure 2(b), when the high-level transition edge of Gclk_AR coincides with the high level of the data signal SBL_AFZX transmitted on the bus, RdData will be set low, i.e., a transition occurs.
[0074] In practical chip applications, the same memory is often instantiated multiple times in different operating environments. In some low-power scenarios, such as serving as a control register in a PMU (Power Management Unit), the memory is accessed very infrequently, only being read from or written to when the system state changes, such as entering sleep mode, waking up, or adjusting the voltage domain. Such operations do not have strict requirements for real-time performance; the focus is more on minimizing static and dynamic power consumption in standby or idle states.
[0075] Most existing low-power designs rely on dual-voltage domain designs or power gating, requiring the introduction of numerous voltage conversion devices or power gating transistors, resulting in significant area overhead. Furthermore, for the same memory, users are not given the option to prioritize either performance or power efficiency.
[0076] To enable memory with a glitch latch structure to switch between performance-priority and power-priority modes, this application provides a clock signal supply circuit. By adding additional circuitry to control the phase of the glitch latch structure's operating clock, the transition edge of the glitch latch structure's operating clock can be changed according to user requirements. This eliminates the glitch between consecutive 1 outputs when output speed requirements are not high, thereby reducing power consumption. However, when continuously reading data 0, if the original data output is 1, the data output time from 1 to 0 will be determined by the glitch latch structure's operating clock, which is slower than the method of determining it through the bus-output data signal SBL_AFZX.
[0077] Example 1 To address the issue that memories with Glitch latch structures cannot switch between performance-priority and power-priority modes, this application provides a clock signal providing circuit. Referring to Figure 3(a), which is a schematic diagram of a clock signal providing circuit provided in this application embodiment, it includes: a first delay circuit 101, a selector 102, and a control circuit 103.
[0078] The input terminal of the first delay circuit 101 is configured to receive the original input clock signal Gclk_AR_pre of the Glitch latch structure. The first delay circuit is used to delay the original input clock signal Gclk_AR_pre to obtain the delayed input clock signal. The phase of the delayed input clock signal is delayed compared to the phase of the original input clock signal, and the delay is less than half a clock cycle of the original input clock signal and greater than the phase difference between the working clock signal of the memory and the data signal acquired by the memory data acquisition.
[0079] In some embodiments, the first delay circuit may include a plurality of inverters connected in series.
[0080] The selector 102 has a first input terminal configured to receive the original input clock signal Gclk_AR_pre, a second input terminal connected to the output terminal of the first delay circuit, and an output terminal configured to connect to the clock input terminal of the Glitch latch structure in the memory.
[0081] For example, a gate could be a multiplexer.
[0082] The control circuit 103, connected to the control terminal of the selector 102, is used to acquire scene feature information and control the selector 102 to output the original input clock signal or the delayed input clock signal according to the scene feature information. The clock signal output by the selector is the working clock signal of the Glitch latch structure.
[0083] In one optional implementation of this application, the control circuit may be a CPU (Central Processing Unit). The central processing unit may be a processor core or a processor chip.
[0084] In another optional implementation of this application embodiment, the scene feature information may include the memory's operating clock signal. The control circuit 103 may be a clock cycle determination circuit. The first input terminal of the clock cycle determination circuit is configured to receive the memory's operating clock signal, the second input terminal is configured to receive a cycle threshold signal, and the output terminal is connected to the control terminal of the selector. The clock cycle determination circuit is used to determine whether the clock cycle of the operating clock signal is greater than the cycle threshold signal. If the clock cycle of the operating clock signal is greater than the cycle threshold signal, it controls the selector to output a delayed input clock signal; if the clock cycle of the operating clock signal is less than the cycle threshold signal, it controls the selector to output the original input clock signal.
[0085] In one exemplary embodiment of this alternative implementation, the clock cycle determination circuit may be a frequency determiner.
[0086] In another exemplary embodiment of this alternative implementation, as shown in FIG3(b), the clock cycle determination circuit 131 may include a first AND gate X1 and a flip-flop RS1.
[0087] The first input of the first AND gate is configured to receive the memory's operating clock signal CLK, and the second input of the first AND gate is configured to receive the period threshold signal CLKprsly. When the memory's operating clock signal CLK is greater than the period threshold signal CLKprsly, the high level of the memory's operating clock signal and the high level of the period threshold signal CLKprsly coincide. The first AND gate X1 is used to output a set pulse when the high level of the operating clock signal and the high level of the period threshold signal coincide.
[0088] The set terminal S of the trigger RS1 is connected to the output terminal of the first AND gate X1, and the output terminal Q is connected to the control terminal of the selector; the reset terminal R is configured to receive the reset signal Rst.
[0089] For example, the trigger could be an RS trigger.
[0090] Optionally, the control circuit may further include a periodic threshold signal generation circuit. The input of the periodic threshold signal generation circuit is configured to access the working clock signal of the memory, and its output is connected to the first input of the first AND gate. The periodic threshold signal generation circuit is used to process the working clock signal according to a preset clock period threshold to generate a periodic threshold signal. Specifically, when the clock period of the working clock signal is greater than the clock period threshold, the high level of the working clock signal and the high level of the periodic threshold signal coincide; when the clock period of the working clock signal is less than the clock period threshold, the high level of the working clock signal and the high level of the periodic threshold signal do not coincide.
[0091] Optionally, the periodic threshold signal generation circuit includes: a duty cycle adjustment circuit and a second delay circuit. Wherein: The input of the duty cycle adjustment circuit is configured to receive the working clock signal of the memory. The duty cycle adjustment circuit is used to reduce the duty cycle of the working clock signal of the memory to obtain a narrowband clock signal.
[0092] The input of the second delay circuit is connected to the output of the duty cycle adjustment circuit, and the output of the second delay circuit is connected to the second input of the first AND gate. The second delay circuit is used to delay the narrowband clock signal according to the clock period threshold to obtain the period threshold signal.
[0093] For example, the duty cycle adjustment circuit may include a third delay circuit, a first inverter, and a second AND gate. The input of the third delay circuit is configured to receive a working clock signal to delay the working clock signal, resulting in a delayed working clock signal whose phase is delayed by less than half a clock cycle of the working clock signal. The input of the first inverter is connected to the output of the third delay circuit. The first input of the second AND gate is connected to the output of the first inverter, the second input of the second AND gate is configured to receive the working clock signal, and the output of the second AND gate is connected to the input of the second delay circuit.
[0094] Optionally, the duty cycle adjustment circuit can be a monostable multivibrator, which generates a narrowband pulse signal by being triggered by the rising edge of the working clock signal.
[0095] In another optional implementation of the embodiments of this application, combined with Figure 4 As shown, the scene feature information includes ambient temperature. The control circuit 103 is a temperature judgment circuit 132. The input terminal is configured to receive the ambient temperature temp, and the output terminal is connected to the control terminal En of the selector. The temperature judgment circuit is used to control the selector to output a delayed input clock signal when the ambient temperature is greater than the ambient temperature threshold, and to control the selector to output the original input clock signal when the ambient temperature is less than the ambient temperature threshold.
[0096] In some embodiments, ambient temperature represents the ambient temperature of the environment in which the memory is located. The ambient temperature threshold can be 80°C. Correspondingly, when the ambient temperature of the environment in which the memory is located is greater than 80°C, the temperature judgment circuit controls the selector to output a delayed input clock signal. When the ambient temperature of the environment in which the memory is located is less than or equal to 80°C, the temperature judgment circuit controls the selector to output the original input clock signal.
[0097] In another optional implementation of this application embodiment, the scene feature information may include ambient temperature and the memory's operating clock signal. Combined with... Figure 5 As shown, the control circuit 103 may include a clock cycle determination circuit 131, a temperature determination circuit 132, and an OR gate 133. The output terminal of the clock cycle determination circuit 131 is connected to the first input terminal of the OR gate 133, the output terminal of the temperature determination circuit 132 is connected to the second output terminal of the OR gate 133, and the output terminal of the OR gate 133 is connected to the control terminal En of the selector 102. Correspondingly, the control circuit 103 is used to control the selector to output a delayed input clock signal when the clock cycle of the working clock signal is greater than the cycle threshold signal and / or the ambient temperature is greater than the ambient temperature threshold; and to control the selector to output the original input clock signal when the clock cycle of the working clock signal is less than the cycle threshold signal and the ambient temperature is less than the ambient temperature threshold.
[0098] Optionally, the first delay circuit, the gate, the control circuit, and the Glitch latch structure can be integrated into the memory.
[0099] Optionally, the first delay circuit, the selector, and the Glitch latch structure are integrated into the memory; the control circuit is independently located outside the memory.
[0100] The clock signal providing circuit provided in this application embodiment acquires scene feature information and controls the selector to output either the original input clock signal or the delayed input clock signal based on the scene feature information. Since the input terminal of the selector is connected to the clock input terminal of a Glitch latch structure configured to be in memory, the operating clock of the Glitch latch structure can change according to changes in the scene feature information. When the selector inputs the original input clock signal, the Glitch latch structure can operate in normal mode, i.e., high-speed data readout with high power consumption. However, when the selector outputs the delayed input clock signal, since the phase of the delayed input clock signal is delayed compared to the phase of the original input clock signal, even when reading data 0, if the original data output is 1, the data output time from 1 to 0 will be determined by Gclk_AR, which is slower than the method determined by the data path SBL_AFZX. However, when continuously reading 1s, since the delay is less than half a clock cycle of the original input clock signal and greater than the phase difference between the memory's operating clock signal and the data signal acquired by the memory, the rising edge of the Glitch latch structure's operating clock will not coincide with the high level of the data signal output from the bus. Consequently, the output data of the Glitch latch structure will not produce glitches, thus reducing power consumption. This allows the memory with the Glitch latch structure to switch between performance-priority mode and power-priority mode based on scene characteristic information.
[0101] Example 2 This application provides further illustrative examples based on Embodiment 1 described above. Combination Figure 6 As shown, the clock signal providing circuit includes: a first delay circuit D1, a two-way selector, and a control circuit. Wherein: The first delay circuit D1 has its input terminal configured to receive the original input clock signal Gclk_AR_pre from the Glitch latch structure. This delays the original input clock signal Gclk_AR_pre to obtain a delayed input clock signal. The phase of the delayed input clock signal is delayed compared to the phase of the original input clock signal, and the delay is less than half a clock cycle of the original input clock signal. The two-way selector has a first input configured to receive the original input clock signal Gclk_AR_pre, a second input connected to the output of the first delay circuit D1, and an output configured to connect to the clock input of the Glitch latch structure in the memory. The control terminal En of the two-way selector is connected to the control circuit. When the control circuit outputs a low-level signal, the two-way selector outputs the original input clock signal Gclk_AR_pre to the Glitch latch structure. When the control circuit outputs a high-level signal, the two-way selector outputs a delayed input clock signal to the Glitch latch structure.
[0102] The control circuit includes an RS flip-flop, a first AND gate X1, a second delay circuit D2, a second AND gate X2, a first inverter F1, and a third delay circuit D3. Wherein: The third delay circuit D3 has its input terminal configured to receive the memory's working clock signal CLK. It is used to delay the memory's working clock signal CLK to obtain a delayed working clock signal. The phase of the delayed working clock signal is delayed compared to the phase of the working clock signal, and the delay is less than half a clock cycle of the working clock signal.
[0103] The input of the first inverter F1 is connected to the output of the third delay circuit D3.
[0104] The second AND gate X2 has its first input connected to the output of the first inverter F1, its second input configured to access the memory's operating clock signal CLK, and its output connected to the input of the second delay circuit D2.
[0105] The output of the second delay circuit D2 is connected to the second input of the first AND gate X1. The second delay circuit D2 is used to delay the narrowband clock signal CLKpr output by the second AND gate X2 according to the clock period threshold to obtain the period threshold signal CLKprdly.
[0106] The first input of the first AND gate X1 is configured to connect to the memory's operating clock signal CLK, and its output is connected to the set input S of the flip-flop. The output terminal Q of the trigger is connected to the control terminal En of the selector; the reset terminal r is configured to receive the reset signal Rst.
[0107] For example, in combination Figure 7 As shown, the memory's operating clock signal CLK is as follows: Figure 7 As shown in CLK, the delay time of the third delay circuit is 20ps. Correspondingly, after the third delay circuit delays the working clock signal CLK, the resulting delayed working clock signal is as follows: Figure 7 As shown in L1, after the delayed working clock signal passes through the first inverter, the pulse signal output by the first inverter is as follows: Figure 7 As shown in L2, the second AND gate ANDs the working clock signal CLK with the pulse signal L2 output from the first inverter, resulting in the pulse signal CLKpr as shown in the diagram. Figure 7As shown in CLKpr.
[0108] If the delay duration of the second delay circuit is greater than half a clock cycle of the working clock signal but less than the entire clock cycle of the working clock signal, then the timing correspondence between the pulse signal CLKprdly output by the second delay circuit and the working clock signal CLK of the memory can be shown in Figure 8(a). The first AND gate performs an AND operation between the pulse signal CLKprdly output by the second delay circuit and the working clock signal CLK of the memory, and the resulting pulse signal can be shown as S in 8(a). Furthermore, the pulse signal output by the output terminal Q of the RS flip-flop can be shown as En in 8(a). In this way, the selector will output the original input clock signal.
[0109] If the delay duration of the second delay circuit is less than half a clock cycle of the working clock signal, the correspondence between the pulse signal CLKprdly output by the second delay circuit and the working clock signal CLK can be shown in Figure 8(b). The first AND gate performs a bitwise AND operation between the pulse signal CLKprdly output by the second delay circuit and the working clock signal CLK, and the resulting pulse signal can be shown as S in Figure 8(b). Furthermore, the pulse signal output by the output terminal Q of the RS flip-flop can be shown as En in Figure 8(b). In this way, the selector outputs the delayed input clock signal.
[0110] Based on the circuit diagram of the Glitch latch structure shown in Figure 1(d), when the selector outputs a delayed input clock signal, the operating clock signal of the Glitch latch structure is the delayed input clock signal. In the case of continuous reads of 0, the timing correspondence between the memory's operating clock signal CCLK, the bus transmission data signal SBL_AFZX, the Glitch latch structure's operating clock signal, and the output data RdData of the Glitch latch structure can be shown in Figure 9(a). That is, the bus output data signal SBL_AFZX clock is a high-level signal H. The data RdData is always a low-level signal L.
[0111] When reading 1 continuously, the timing correspondence between the memory's operating clock signal CCLK, the bus transmission data signal SBL_AFZX, the operating clock signal of the Glitch latch structure, and the output data RdData of the Glitch latch structure can be shown in Figure 9(b).
[0112] Combination Figure 10As shown in Figure 1(a), in the memory scenario where half of the I / O operations are continuously read as 1 and the other half are constantly read as 0 power, if the Glitch latch structure operates in normal mode, the power consumption generated in the memory shown in Figure 1(a) is as follows: Figure 10 The original circuit is shown in Figure 1(a). If the clock signal providing circuit provided in this application is used to delay the original input clock signal of the Glitch latch structure, the power consumption generated in the memory shown in Figure 1(a) is as follows. Figure 10 As shown, by delaying the original input clock signal of the Glitch latch structure using the clock signal providing circuit provided in this application, the power consumption during continuous 1 reading can be reduced.
[0113] In the case of reading 1-reading 0-reading 1-reading 0, the timing correspondence between the memory's working clock signal CCLK, the bus transmission data signal SBL_AFZX, the working clock signal of the Glitch latch structure, and the output data RdData of the Glitch latch structure can be shown in Figure 9(c).
[0114] Example 3 Based on the same inventive concept, combined with Figure 11 As shown, this application provides a clock signal providing method, applied in the control circuit of the clock signal providing circuit of the above embodiment; the method includes: Step S111: Obtain scene feature signals; Step S112: Control the selector to output the original input clock signal to the Glitch latch structure, or output the delayed input clock signal, according to the scene feature signal.
[0115] Optionally, the scene feature information includes the memory's operating clock signal. Correspondingly, controlling the selector to output the original input clock signal or the delayed input clock signal to the Glitch latch structure based on the scene feature signal includes: acquiring the memory's operating clock signal, determining whether the clock period of the operating clock signal is greater than a period threshold signal, and controlling the selector to output the delayed input clock signal to the Glitch latch structure if the clock period of the operating clock signal is greater than the period threshold signal; and controlling the selector to output the original input clock signal to the Glitch latch structure if the clock period of the operating clock signal is less than the period threshold signal.
[0116] Optionally, the scene feature information may include ambient temperature. Correspondingly, controlling the selector to output the original input clock signal or the delayed input clock signal to the Glitch latch structure based on the scene feature signal includes: acquiring the ambient temperature, determining whether the ambient temperature is greater than a preset ambient temperature threshold, controlling the selector to output the delayed input clock signal to the Glitch latch structure when the ambient temperature is greater than the ambient temperature threshold, and controlling the selector to output the original input clock signal to the Glitch latch structure when the ambient temperature is less than the ambient temperature threshold.
[0117] Example 4: Based on the same inventive concept, this embodiment provides a memory including the clock signal providing circuit of the above embodiment.
[0118] Based on the same inventive concept, this embodiment also provides an electronic device, including a clock signal providing circuit as described in the above embodiments and a memory having a Glitch latch structure; wherein: The first delay circuit, the selector, the control circuit, and the Glitch latch structure are integrated into the memory; or, The first delay circuit, the selector, and the Glitch latch structure are integrated into the memory; the control circuit is independently located outside the memory.
[0119] In some embodiments, electronic devices may be circuit boards, motherboards, control modules, graphics cards, memory modules, etc., which can be independently manufactured and sold, and can be combined with other electronic devices to form a complete electronic device.
[0120] Based on the same inventive concept, this embodiment also provides an electronic device, including the above-described electronic device.
[0121] Electronic devices can be, but are not limited to, mobile phones, computers, servers, wearable devices, etc.
[0122] In the embodiments of this application, the electronic device may also have more components, such as a display device, a signal input / output device, a battery, etc., but this is not a limitation.
[0123] Based on the same inventive concept, embodiments of this application also provide a computer-readable storage medium, such as a floppy disk, optical disk, hard disk, flash memory, USB flash drive, SD (Secure Digital Memory Card), MMC (Multimedia Card), etc., in which one or more programs implementing the above-described steps are stored. These one or more programs can be executed by one or more processors to implement the above-described clock signal providing method. Further details will not be elaborated here.
[0124] Based on the same inventive concept, this application also provides a computer program product. The computer program product includes a computer program that, when executed by a processor, implements the aforementioned clock signal providing method. Further details will not be elaborated here.
[0125] For example, a computer program product may be an installation package or a program package.
[0126] In the embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. Furthermore, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Additionally, the displayed or discussed mutual couplings, direct couplings, or communication connections may be through some communication interfaces; indirect couplings or communication connections between devices or units may be electrical, mechanical, or other forms.
[0127] Furthermore, the units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.
[0128] Furthermore, the functional modules in the various embodiments of this application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.
[0129] In this document, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, without necessarily requiring or implying any such actual relationship or order between these entities or operations.
[0130] In this article, "multiple" refers to two or more.
[0131] The above description is merely an embodiment of this application and is not intended to limit the scope of protection of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.
Claims
1. A clock signal providing circuit, characterized in that, include: The first delay circuit has its input terminal configured to receive the original input clock signal of the Glitch latch structure, which is used to delay the original input clock signal to obtain a delayed input clock signal. The phase of the delayed input clock signal is delayed compared to the phase of the original input clock signal, and the delay is less than half a clock cycle of the original input clock signal, and greater than the phase difference between the memory's working clock signal and the data signal acquired by the memory. The selector has a first input terminal configured to receive the original input clock signal, a second input terminal connected to the output terminal of the first delay circuit, and an output terminal configured to be connected to the clock input terminal of the Glitch latch structure in the memory. A control circuit, connected to the control terminal of the selector, is used to acquire scene feature information and control the selector to output the original input clock signal or the delayed input clock signal according to the scene feature information.
2. The clock signal providing circuit according to claim 1, characterized in that, The scene feature information includes the operating clock signal of the memory; the control circuit includes a clock cycle determination circuit, a first input terminal configured to receive the operating clock signal of the memory, a second input terminal configured to receive a cycle threshold signal, and an output terminal connected to the control terminal of the selector; the clock cycle determination circuit is used to determine whether the clock cycle of the operating clock signal is greater than the cycle threshold signal; if the clock cycle of the operating clock signal is greater than the cycle threshold signal, the selector is controlled to output the delayed input clock signal; if the clock cycle of the operating clock signal is less than the cycle threshold signal, the selector is controlled to output the original input clock signal.
3. The clock signal providing circuit according to claim 2, characterized in that, The clock cycle determination circuit includes: The first AND gate has a first input configured to receive the working clock signal and a second input configured to receive a period threshold signal. When the clock period of the working clock signal is greater than the period threshold signal, the high level of the working clock signal and the high level of the period threshold signal overlap. The first AND gate is used to output a set pulse when the high level of the working clock signal and the high level of the period threshold signal overlap. The trigger has its set terminal connected to the output terminal of the first AND gate, and its output terminal connected to the control terminal of the selector; the reset terminal is configured to receive a reset signal.
4. The clock signal providing circuit according to claim 3, characterized in that, Also includes: A periodic threshold signal generation circuit has its input terminal configured to receive the operating clock signal of the memory; its output terminal is connected to the first input terminal of the first AND gate. The periodic threshold signal generation circuit is used to process the working clock signal according to a preset clock period threshold to generate a periodic threshold signal; when the clock period of the working clock signal is greater than the clock period threshold, the high level of the working clock signal and the high level of the periodic threshold signal coincide; when the clock period of the working clock signal is less than the clock period threshold, the high level of the working clock signal and the high level of the periodic threshold signal do not coincide.
5. The clock signal providing circuit according to claim 4, characterized in that, The periodic threshold signal generation circuit includes: A duty cycle adjustment circuit, the input of which is configured to receive the working clock signal, is used to reduce the duty cycle of the working clock signal to obtain a narrowband clock signal; The second delay circuit has its input terminal connected to the output terminal of the duty cycle adjustment circuit, and its output terminal connected to the second input terminal of the first AND gate. The second delay circuit is used to delay the narrowband clock signal according to the clock period threshold to obtain the period threshold signal.
6. The clock signal providing circuit according to claim 5, characterized in that, The duty cycle adjustment circuit includes: The third delay circuit has its input terminal configured to receive the working clock signal, and is used to delay the working clock signal to obtain a delayed working clock signal. The phase of the delayed working clock signal is delayed compared to the phase of the working clock signal, and the delay is less than half a clock cycle of the working clock signal. The input terminal of the first inverter is connected to the output terminal of the third delay circuit; The second AND gate has its first input connected to the output of the first inverter, its second input configured to receive the operating clock signal, and its output connected to the input of the second delay circuit.
7. The clock signal providing circuit according to claim 1, characterized in that, The scene feature information includes ambient temperature. The control circuit includes a temperature judgment circuit, with its input terminal configured to receive the ambient temperature and its output terminal connected to the control terminal of the selector. The temperature judgment circuit is used to control the selector to output the delayed input clock signal when the ambient temperature is greater than the ambient temperature threshold, and to control the selector to output the original input clock signal when the ambient temperature is less than the ambient temperature threshold.
8. The clock signal providing circuit according to claim 1, characterized in that, The control circuit is a central processing unit.
9. The clock signal providing circuit according to any one of claims 1 to 8, characterized in that, The first delay circuit, the selector, the control circuit, and the Glitch latch structure are integrated into the memory.
10. The clock signal providing circuit according to any one of claims 1 to 8, characterized in that, The first delay circuit, the selector, and the Glitch latch structure are integrated into the memory; the control circuit is independently located outside the memory.
11. A method for providing a clock signal, characterized in that, The method is applied in a control circuit of a clock signal providing circuit as described in any one of claims 1-10; the method includes: Acquire scene feature signals; Based on the scene feature signal, the selector is controlled to output the original input clock signal to the Glitch latch structure, or to output the delayed input clock signal.
12. A memory, characterized in that, Includes the clock signal providing circuit as described in any one of claims 1-9.
13. An electronic device, characterized in that, Includes a clock signal providing circuit as described in any one of claims 1-10 and a memory having a Glitch latch structure; wherein: The first delay circuit, the selector, the control circuit, and the Glitch latch structure are integrated into the memory; or, The first delay circuit, the selector, and the Glitch latch structure are integrated into the memory; the control circuit is independently located outside the memory.
14. An electronic device, characterized in that, Including the electronic device as described in claim 13.