Memory cells and memory arrays

Abstract

Embodiments of the present application provide a storage unit and a storage array, and relate to the field of semiconductors. The storage unit comprises a spin-orbit torque layer and a magnetic tunnel junction, the magnetic tunnel junction being stacked on the spin-orbit torque layer; a top electrode of the magnetic tunnel junction is connected to a source line, a first end of the spin-orbit torque layer is connected to a bit line through a first switch tube, a second end of the spin-orbit torque layer is connected to the bit line through a second switch tube, a control end of the first switch tube is connected to a first word line, and a control end of the second switch tube is connected to a second word line. The complexity of the peripheral control circuit and the timing control of the storage unit is reduced.

Description

Technical Field

[0001] This application relates to the semiconductor field, and more particularly to a memory cell and a memory array. Background Technology

[0002] Magnetic random access memory (MRAM) has become one of the next-generation mainstream memories due to its non-volatility, high read / write speeds, and low power consumption. Among them, spin-orbit torque MRAM (SOT-MRAM) has significant advantages over traditional spin transfer torque MRAM (STT-MRAM), such as faster write speeds, higher durability, and separate read / write paths, thus showing great potential in high-performance storage and in-memory computing.

[0003] The write operation of a SOT-MRAM memory cell relies on applying current across the Spin-Orbit Torque (SOT) layer. Data is written by flipping the magnetization direction of the free layer through the spin-orbit torque effect. Furthermore, the direction of the current applied across the SOT layer controls whether the written data is "0" or "1". This writing method requires controlling the write current in two different directions, increasing the complexity of the external control circuitry. In addition, under Voltage-Controlled Magnetic Anisotropy (VCMA) scenarios, precise timing synchronization between the VCMA voltage and the SOT current is also required, further increasing the complexity of timing control. Summary of the Invention

[0004] This application provides a storage unit and a storage array, which reduces the complexity of the peripheral control circuit and timing control of the storage unit.

[0005] In a first aspect, embodiments of this application provide a storage unit, including: a spin-orbit matrix layer and a magnetic tunnel junction, wherein the magnetic tunnel junction is stacked on the spin-orbit matrix layer;

[0006] The top electrode of the magnetic tunnel junction is connected to the source line. The first end of the spin-orbit junction is connected to the bit line through a first switch. The second end of the spin-orbit junction is connected to the bit line through a second switch. The control terminal of the first switch is connected to the first word line, and the control terminal of the second switch is connected to the second word line.

[0007] In some embodiments, when writing data, the target switch is turned on, and the target switch is either the first switch or the second switch.

[0008] The write current flows from the bit line through the target switch to the source line, or the write current flows from the source line through the target switch to the bit line;

[0009] The first write current is used to write a first value, and the second write current is used to write a second value. The first write current and the second write current flow through the magnetic tunnel junction in the same direction.

[0010] In some embodiments, the first switch and the second switch are P-type metal-oxide-semiconductor field-effect transistors;

[0011] When writing data, the bit line is connected to the write pulse, and the source line is grounded; and,

[0012] When writing the first value, the first word line is active to control the first switch to be turned on, and the second word line is inactive to control the second switch to be turned off. The first write current flows from the bit line through the first switch to the source line.

[0013] When the second value is written, the second word line is enabled to control the second switch to be turned on, and the first word line is disabled to control the first switch to be turned off. The second write current flows from the bit line through the second switch to the source line.

[0014] In some embodiments, the first switch and the second switch are N-type metal-oxide-semiconductor field-effect transistors;

[0015] When writing data, the bit line is grounded, and the source line is connected to the write pulse; and,

[0016] When the first value is written, the second word line is enabled to control the second switch to be turned on, and the first word line is disabled to control the first switch to be turned off. The first write current flows from the source line through the second switch to the bit line.

[0017] When the second value is written, the first word line is enabled to control the first switch to be turned on, and the second word line is disabled to control the second switch to be turned off. The second write current flows from the source line through the first switch to the bit line.

[0018] In some embodiments, when reading data, the read current flows from the bit line to the source line, or the read current flows from the source line to the bit line;

[0019] When reading data, the first word line is active to control the first switch to turn on, and / or the second word line is active to control the second switch to turn on.

[0020] In some embodiments, the magnetic tunnel junction includes an insertion layer, the material of which is a metal or its compound with a work function greater than a preset threshold.

[0021] In some embodiments, the insertion layer is disposed between the barrier layer and the free layer of the magnetic tunnel junction, or the insertion layer is disposed between the free layer and the spin-orbit moment layer.

[0022] In some embodiments, the storage unit is a device with perpendicular magnetic anisotropy or an in-plane magnetic anisotropy.

[0023] Secondly, embodiments of this application provide a storage array, including: a plurality of storage units, wherein the storage units are the storage units described in the first aspect;

[0024] In the memory array, memory cells in the same column are connected to the same first word line, second word line, and source line, and memory cells in the same row are connected to the same bit line.

[0025] In some embodiments, when writing data, in the same row of storage cells, the first word line or the second word line connected to the storage cell to be written is valid, while the first word line and the second word line connected to the storage cell not to be written are invalid.

[0026] The write current flows from the bit line connected to the memory cell to be written to the source line connected to the memory cell to be written, or the write current flows from the source line connected to the memory cell to be written to the bit line connected to the memory cell to be written.

[0027] In the memory cell and memory array provided in this application embodiment, the two ends of the SOT layer of the memory cell are connected to the same bit line through a first switch and a second switch, respectively. The top electrode of the MTJ is connected to the source line. In this way, when writing data, the first value or the second value can be written by selecting the first switch or the second switch. Moreover, regardless of whether the first value or the second value is written, the write current flows from the bit line to the source line, or vice versa. That is to say, data writing can be achieved using a single write current path, thereby reducing the complexity of the peripheral control circuit. Furthermore, since the write current flowing through the MTJ when writing the first value and the second value can generate the VCMA effect, and the direction of the VCMA effect is consistent, the synergistic effect of SOT and VCMA can be achieved by writing to both ports of the memory cell and memory array in this application embodiment. There is no need to apply an additional VCMA voltage, and there is no timing synchronization problem between the VCMA voltage and the SOT current, which fundamentally reduces the complexity of timing control. Attached Figure Description

[0028] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0029] Figure 1 This is a schematic diagram of a SOT-MRAM memory cell in related technologies;

[0030] Figure 2 A schematic diagram of a storage unit provided in an embodiment of this application;

[0031] Figure 3 A schematic diagram of the write current of a memory cell provided in an embodiment of this application. Figure 1 ;

[0032] Figure 4 A schematic diagram of the write current of a memory cell provided in an embodiment of this application. Figure 2 ;

[0033] Figure 5 A schematic diagram of the write current of a memory cell provided in an embodiment of this application. Figure 3 ;

[0034] Figure 6 A schematic diagram of the RV characteristic curve of a memory cell provided in an embodiment of this application. Figure 1 ;

[0035] Figure 7 A schematic diagram of the write current of a memory cell provided in an embodiment of this application. Figure 4 ;

[0036] Figure 8 A schematic diagram of the RV characteristic curve of a memory cell provided in an embodiment of this application. Figure 2 ;

[0037] Figure 9 A schematic diagram of an insertion layer for a storage cell provided in an embodiment of this application. Figure 1 ;

[0038] Figure 10 A schematic diagram of an insertion layer for a storage cell provided in an embodiment of this application. Figure 2 ;

[0039] Figure 11 A schematic diagram of an insertion layer for a storage cell provided in an embodiment of this application. Figure 3 ;

[0040] Figure 12 A schematic diagram of an insertion layer for a storage cell provided in an embodiment of this application. Figure 4 ;

[0041] Figure 13 A schematic diagram of a storage array provided in an embodiment of this application. Figure 1 ;

[0042] Figure 14 A schematic diagram of data writing to a storage array provided in this application embodiment. Figure 1 ;

[0043] Figure 15 A schematic diagram of data reading from a storage array provided in this application embodiment. Figure 1 ;

[0044] Figure 16 A schematic diagram of data reading from a storage array provided in this application embodiment. Figure 2 ;

[0045] Figure 17 A schematic diagram of data writing to a storage array provided in this application embodiment. Figure 2 ;

[0046] Figure 18 A schematic diagram of data reading from a storage array provided in this application embodiment. Figure 3 ;

[0047] Figure 19 A schematic diagram of a storage array provided in an embodiment of this application. Figure 2 .

[0048] The accompanying drawings have illustrated specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to specific embodiments. Detailed Implementation

[0049] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application.

[0050] like Figure 1 The diagram shown is a schematic of a SOT-MRAM memory cell in related technologies. For example... Figure 1As shown, the memory cell includes an SOT layer 201 and a magnetic tunnel junction (MTJ) 202. The MTJ 202 is stacked on top of the SOT layer 201. One end of the SOT layer 201 is connected to the source line SL, and the other end of the SOT layer 201 is connected to the bit line BL through a switch transistor. The control terminal of the switch transistor is connected to the write word line WWL. The top electrode of the MTJ 202 is connected to the bit line BL through a switch transistor. The control terminal of the switch transistor is connected to the read word line RWL.

[0051] When writing data, the write word line WWL is enabled, and the voltage of the bit line BL and the source line SL is controlled to generate a write current between the two ends of the SOT layer 201. The write current flows from the bit line BL along the SOT layer 201 into the source line SL, or vice versa. The two different directions of the write current cause the memory cell to flip to two different storage states, used to write the data "0" or "1". This scheme increases the complexity of the external control circuit due to the existence of two independent and opposite write current paths.

[0052] Furthermore, based on the aforementioned SOT-MRAM memory cells, related technologies also include schemes that combine the VCMA effect to assist or dominate writing in order to reduce device power consumption. When writing data, in addition to controlling the write current generated in the SOT layer 201, a VCMA voltage needs to be applied across the MTJ202 to generate the VCMA effect in the MTJ202, promoting the reversal of the free layer magnetic moments in the MTJ202, thereby facilitating data writing. This scheme requires precise timing synchronization between the VCMA voltage and the SOT current, further increasing the complexity of timing control.

[0053] To address the aforementioned problems, this application proposes a storage unit, referring to... Figure 2 As shown, the memory cell includes an SOT layer 201 and an MTJ 202, with the MTJ 202 stacked on top of the SOT layer 201. The top electrode of the MTJ 202 is connected to the source line SL. The first end of the SOT layer 201 is connected to the bit line BL via a first switch Q1, and the second end of the SOT layer 201 is connected to the bit line BL via a second switch Q2. The control terminal of the first switch Q1 is connected to the first word line W0L, and the control terminal of the second switch Q2 is connected to the second word line W1L.

[0054] The first switch Q1 and the second switch Q2 can be metal-oxide-semiconductor field-effect transistors (MOSFETs), fin field-effect transistors (FinFETs), junction field-effect transistors (JFETs), bipolar junction transistors (BJTs), insulated gate bipolar transistors (IGBTs), etc. The specific types of the first switch Q1 and the second switch Q2 are not limited in the embodiments of this application.

[0055] When writing data, the target switch is turned on. The target switch is either the first switch Q1 or the second switch Q2. The write current flows from the bit line BL through the target switch to the source line SL, or the write current flows from the source line BL through the target switch to the bit line BL.

[0056] The first write current is used to write a first value, and the second write current is used to write a second value. The first write current and the second write current flow through the MTJ202 in the same direction. The first value is "0" and the second value is "1"; or, the first value is "1" and the second value is "0".

[0057] In some embodiments, when writing a first value, the first switch Q1 is turned on, and the first write current flows from the bit line BL through the first switch Q1 to the source line SL; when writing a second value, the second switch Q2 is turned on, and the second write current flows from the bit line BL through the second switch Q2 to the source line SL. The directions of the first write current and the second write current are as follows: Figure 3 As shown.

[0058] from Figure 3 It can be seen that when writing the first value and writing the second value, the directions of the first write current and the second write current are different in the SOT layer 201. That is to say, in this embodiment, different values ​​are still written based on the different current directions in the SOT layer 201. However, the difference from related technologies is that in this embodiment, both the first write current and the second write current flow from the bit line BL to the source line SL. The write current path is single, which means that whether writing the first value or the second value, it is only necessary to control the level of the bit line BL to be higher than the level of the source line SL, thereby reducing the complexity of the peripheral control circuit.

[0059] Furthermore, the first write current and the second write current flow through the MTJ202 in the same direction, that is, both the first write current and the second write current flow along... Figure 3 As shown, the current flows from bottom to top through the MTJ202. Both the first write current and the second write current can generate the VCMA effect, and the direction of the VCMA effect is consistent. During the data writing process, the VCMA effect of the first write current and / or the second write current can continuously promote the magnetic moment reversal of the free layer in the MTJ202. No additional VCMA voltage needs to be applied, and there is no timing synchronization problem between the VCMA voltage and the SOT current, which fundamentally reduces the complexity of timing control.

[0060] In some embodiments, when writing the first value, the second switch Q2 is turned on, and the first write current flows from the source line SL through the second switch Q2 to the bit line BL; when writing the second value, the first switch Q1 is turned on, and the second write current flows from the source line SL through the first switch Q1 to the bit line BL. The directions of the first and second write currents are as follows: Figure 4 As shown.

[0061] from Figure 4 It can be seen that, with Figure 3 Similarly, when writing the first value and the second value, the directions of the first write current and the second write current are different in the SOT layer 201. That is, different values ​​are still written based on the different current directions in the SOT layer 201. However, the difference from related technologies is that in this embodiment, both the first write current and the second write current flow from the source line SL to the bit line BL. The write current path is single, which means that whether writing the first value or the second value, it is only necessary to control the level of the source line SL to be higher than the level of the bit line BL, thereby reducing the complexity of the external control circuit.

[0062] Furthermore, the first write current and the second write current flow through the MTJ202 in the same direction, that is, the first write current and the second write current flow along... Figure 4 As shown, the current flows from top to bottom through the MTJ202. Both the first write current and the second write current can generate the VCMA effect, and the VCMA effect is in the same direction. During the data writing process, the VCMA effect of the first write current and / or the second write current can continuously promote the magnetic moment reversal of the free layer. No additional VCMA voltage needs to be applied, and there is no timing synchronization problem between the VCMA voltage and the SOT current, which fundamentally reduces the complexity of timing control.

[0063] In the memory cell of this embodiment, the two ends of the SOT layer 201 are connected to the same bit line BL through a first switch Q1 and a second switch Q2, respectively. The top electrode of the MTJ202 is connected to the source line SL. When writing data, the first value or the second value is written by selecting either the first switch Q1 or the second switch Q2. Regardless of whether the first value or the second value is written, the write current flows from the bit line BL to the source line SL, or vice versa. Data writing can be achieved through a single write current path, thereby reducing the complexity of the peripheral control circuit. Furthermore, since the write current flowing through the MTJ202 when writing the first value and the second value can generate the VCMA effect, and the direction of the VCMA effect promoting or inhibiting the flip is consistent, this embodiment of the application can achieve the synergistic effect of SOT and VCMA by writing to both ports of the memory cell. There is no need to apply an additional VCMA voltage, and there is no timing synchronization problem between the VCMA voltage and the SOT current, which fundamentally reduces the complexity of timing control.

[0064] Reference Figure 5 and Figure 6 As shown, Figure 5 The diagram illustrates the write current when one end of SOT layer 201 is grounded. Figure 6 The diagram illustrates the resistance-voltage (RV) characteristic curve of the memory cell when one end of the SOT layer 201 is grounded. Figure 6 The horizontal axis represents the amplitude of the write pulse applied to the source line SL, and the vertical axis represents the resistance of the MTJ202. When a positive pulse is applied, the write current flows from the source line SL to the bit line ground point GND; when a negative pulse is applied, the write current flows from the ground point GND to the source line SL. Figure 6 As shown in the RV characteristics, when a positive pulse is applied, the MTJ202 can switch from a low-resistance state to a high-resistance state as the amplitude of the applied positive pulse increases, thus achieving the first value writing; when a negative pulse is applied, the MTJ202 can switch from a high-resistance state to a low-resistance state as the amplitude of the applied negative pulse increases, thus achieving the second value writing.

[0065] Reference Figure 7 and Figure 8 As shown, Figure 7 The diagram illustrates the write current when the other end of SOT layer 201 is grounded. Figure 8 The diagram illustrates the RV characteristic curve of the memory cell when the other end of the SOT layer 201 is grounded. Figure 8 The horizontal axis represents the amplitude of the write pulse applied to the source line SL, and the vertical axis represents the resistance of the MTJ202. When a positive pulse is applied, the write current flows from the source line SL to the ground point GND; when a negative pulse is applied, the write current flows from the ground point GND to the source line SL. Figure 6 As shown in the RV characteristics, when a positive pulse is applied, the MTJ202 can switch from a high-resistance state to a low-resistance state as the amplitude of the applied positive pulse increases, thus achieving the second value writing; when a negative pulse is applied, the MTJ202 can switch from a low-resistance state to a high-resistance state as the amplitude of the applied negative pulse increases, thus achieving the first value writing.

[0066] Therefore, it can be seen that in the memory cell of this application, regardless of whether a positive pulse or a negative pulse is applied, the write current of two different values ​​written to the memory cell flows in the same direction in MTJ202. The write current flows from the source line SL to the ground point GND, or from the ground point GND to the source line SL. By controlling the grounding of different terminals of SOT layer 201, the write current flows in different directions in SOT layer 201, and different values ​​can be written.

[0067] In one implementation, refer to Figure 3 The following explanation will be based on the example of a P-type metal-oxide-semiconductor field-effect transistor (PMOS) with the first switch Q1 and the second switch Q2 as examples.

[0068] When writing data, the bit line BL is connected to the write pulse, and the source line SL is grounded. When writing the first value, the first word line W0L is active to control the first switch Q1 to turn on, and the second word line W1L is inactive to control the second switch Q2 to turn off. The first write current flows from the bit line BL through the first switch Q1 to the source line SL. When writing the second value, the second word line W1L is active to control the second switch Q2 to turn on, and the first word line W0L is inactive to control the first switch Q1 to turn off. The second write current flows from the bit line BL through the second switch Q2 to the source line SL.

[0069] Since the first switch Q1 and the second switch Q2 are PMOS transistors, when writing the first value, the first word line W0L is active (i.e., connected to a low level), and the second word line W1L is inactive (i.e., connected to a high level). At this time, the first write current flows from the bit line BL through the first switch Q1, SOT layer 201, and MTJ202 to the source line SL. The direction of the first write current in SOT layer 201 is... Figure 3 The direction from left to right in MTJ202 is... Figure 3 The process is from bottom to top; when writing the second value, the second word line W1L is active (i.e., connected to a low level), and the first word line W0L is inactive (i.e., connected to a high level). At this time, the second write current flows from the bit line BL through the second switch Q2, SOT layer 201, and MTJ202 to the source line SL. The direction of the second write current in SOT layer 201 is... Figure 3 The direction from right to left in MTJ202 is... Figure 3 From bottom to top.

[0070] When the first switch Q1 and the second switch Q2 are PMOS, since the first word line W0L is connected to a low level when writing the first value and the second word line W1L is connected to a low level when writing the second value, and at the same time the bit line BL is connected to the write pulse, that is, the bit line BL is connected to a high level, the gate-source voltage (Vgs) of the first switch Q1 and the second switch Q2 can always remain stable. This can avoid the interference of the source degradation effect of the first switch Q1 and the second switch Q2 on the data writing, thereby reducing the write error rate.

[0071] In one implementation, refer to Figure 4 The following explanation will be based on the example of an N-type metal-oxide-semiconductor field-effect transistor (NMOS) with the first switch Q1 and the second switch Q2 as examples.

[0072] When writing data, the bit line BL is grounded, and the source line SL is connected to the write pulse. When writing the first value, the second word line W1L is active to control the second switch Q2 to turn on, and the first word line W0L is inactive to control the first switch Q1 to turn off. The first write current flows from the source line SL through the second switch Q2 to the bit line BL. When writing the second value, the first word line W0L is active to control the first switch Q1 to turn on, and the second word line W1L is inactive to control the second switch Q2 to turn off. The second write current flows from the source line SL through the first switch Q1 to the bit line BL.

[0073] Since the first switch Q1 and the second switch Q2 are NMOS transistors, when writing the first value, the second word line W1L is active (i.e., connected to a high level), and the first word line W0L is inactive (i.e., connected to a low level). At this time, the first write current flows from the source line SL through MTJ202, SOT layer 201, and the second switch Q2 to the bit line BL. The direction of the first write current in MTJ202 is... Figure 4 The direction from top to bottom in SOT layer 201 is... Figure 4 From left to right; when writing the second value, the first word line W0L is active (i.e., connected to a high level), and the second word line W1L is inactive (i.e., connected to a low level). At this time, the second write current flows from the source line SL through MTJ202, SOT layer 201, and the first switch Q1 to the bit line BL. The direction of the second write current in MTJ202 is... Figure 4 The direction from top to bottom in SOT layer 201 is... Figure 4From right to left in the middle.

[0074] When the first switch Q1 and the second switch Q2 are NMOS, since the second word line W1L is connected to a high level when writing the first value and the first word line W0L is connected to a high level when writing the second value, while the bit line BL is always grounded, the gate-source voltage of the first switch Q1 and the second switch Q2 can always remain stable. This can avoid the interference of the source degradation effect of the first switch Q1 and the second switch Q2 on the data writing, thereby reducing the write error rate.

[0075] It should be noted that the amplitude of the write pulse when the first switch Q1 and the second switch Q2 are NMOS transistors can be the same as or different from the amplitude of the write pulse when the first switch Q1 and the second switch Q2 are PMOS transistors. The amplitude of the write pulse can be determined according to the actual circuit. In practical applications, the read / write margin can be adjusted by adjusting the resistance-area product (RA) of the MTJ202 and the resistance value of the SOT layer 201. The write margin is the difference between the breakdown voltage and the critical flip voltage of the MTJ202, and the read margin is the signal difference between the high-resistance state and the low-resistance state of the MTJ202. The lower the RA of the MTJ202, the larger the write margin, but the higher the voltage divider of the SOT layer 201, the smaller the read margin. Conversely, the higher the RA of the MTJ202, the smaller the write margin, but the lower the voltage divider of the SOT layer 201, the larger the read margin. Therefore, by adjusting the resistance-area product (RA) of the MTJ202 and the resistance value of the SOT layer 201, the write margin and read margin of the memory cell can be kept within an appropriate range. This avoids one of the write margin and read margin being too high, causing the other to be too low, thereby ensuring that the memory cell can be stably read and written.

[0076] Optionally, the storage unit in this embodiment can be a device with perpendicular magnetic anisotropy (PMA), such as... Figure 10 or Figure 12 As shown, the magnetic anisotropy of each magnetic layer within the memory cell is along a plane perpendicular to the plane of each film layer in the MTJ202. Alternatively, the memory cell can be a device with in-plane magnetic anisotropy (IMA), such as... Figure 9 or Figure 11 As shown, the magnetic anisotropy of each magnetic layer in the memory cell is parallel to the plane direction of each film layer in MTJ202.

[0077] When the memory cell is an IMA device, the VCMA effect generated by the write current in the MTJ202 when the write current direction is from bottom to top can promote the magnetic moment reversal of the free layer in the MTJ202. When the memory cell is a PMA device, the VCMA effect generated by the write current when the write current direction is from top to bottom can also promote the magnetic moment reversal of the free layer in the MTJ202. Therefore, when the memory cell is an IMA device, the first switch Q1 and the second switch Q2 can be selected as PMOS, and when the memory cell is a PMA device, the first switch Q1 and the second switch Q2 can be selected as NMOS, thereby ensuring that the write current can continuously promote the magnetic moment reversal of the free layer in the MTJ202 and reduce device power consumption.

[0078] Based on any of the above embodiments, when reading data, the bit line BL is connected to the read pulse, the source line SL is grounded, and the read current flows from the bit line BL to the source line SL; or, the source line SL is connected to the read pulse, the bit line BL is grounded, and the read current flows from the source line SL to the bit line BL; when reading data, the first word line W0L is active to control the first switch Q1 to turn on, and / or, the second word line W1L is active to control the second switch Q2 to turn on. That is, optionally, when reading data, for any of the above embodiments, the read current can flow from the bit line BL to the source line SL, and either the first switch Q1 or the second switch Q1 can be turned on, or both can be turned on. Optionally, when reading data, for any of the above embodiments, the read current can flow from the source line SL to the bit line BL, and either the first switch Q1 or the second switch Q1 can be turned on, or both can be turned on. Optionally, the amplitude of the read pulse can be lower than the amplitude of the write pulse.

[0079] Reference Figures 9 to 12 As shown, MTJ202 includes a free layer 2023, a barrier layer 2022, and a reference layer 2021 disposed away from the SOT layer 201. The magnetization direction of the free layer 2023 can be changed by external factors, has low coercivity, and is easy to flip. The reference layer 2021 provides a fixed magnetization direction as a comparison benchmark. Both the reference layer 2021 and the free layer 2023 are made of ferromagnetic materials, including at least one of cobalt iron boron, cobalt iron, iron boron, cobalt boron, and nickel iron. The reference layer 2021 and the free layer 2023 can be a single layer or multiple layers. The barrier layer 2022 can be made of an insulating material, such as an oxide, and can include at least one of aluminum oxide and magnesium oxide.

[0080] Based on any of the above embodiments, optionally, the MTJ202 may further include an insertion layer 2024. The material of the insertion layer 2024 is a metal or its compound with a work function greater than a preset threshold. The insertion layer 2024 is used to enhance the VCMA effect generated by the write current in the MTJ202. For example, the material of the insertion layer 2024 may be metals such as platinum (Pt) or iridium (Ir), or other metals or their compounds with high work functions or that can enhance the VCMA effect. In some implementations, the thickness of the insertion layer 2024 may be less than 0.3 nm, but this application embodiment does not limit this, and the thickness of the insertion layer 2024 can be set as needed.

[0081] Optional, refer to Figure 9 and Figure 10 As shown, the insertion layer 2024 can be positioned between the barrier layer 2022 and the free layer 2023 of the MTJ202. For example, Figure 9 The diagram illustrates that the memory cell is an IMA device. When the first switch Q1 and the second switch Q2 are PMOS, the insertion layer 2024 is disposed between the barrier layer 2022 and the free layer 2023. The left and right arrows in the reference layer 2021 and the free layer 2023 are used to indicate the magnetic moment direction. Figure 10 The diagram illustrates a memory cell using a PMA device. With the first switch Q1 and the second switch Q2 employing NMOS transistors, the insertion layer 2024 is positioned between the barrier layer 2022 and the free layer 2023. The up-down arrows in the reference layer 2021 and the free layer 2023 indicate the magnetic moment direction. Positioning the insertion layer 2024 between the barrier layer 2022 and the free layer 2023 of the MTJ202 enhances the VCMA effect and promotes magnetic moment reversal in the free layer 2023.

[0082] Optional, refer to Figure 11 and Figure 12 As shown, the insertion layer 2024 can be positioned between the free layer 2023 and the SOT layer 201 of the MTJ202. For example, Figure 11 The diagram illustrates that the memory cell is an IMA device. When the first switch Q1 and the second switch Q2 are PMOS, the insertion layer 2024 is disposed between the free layer 2023 and the SOT layer 201. The left and right arrows in the reference layer 2021 and the free layer 2023 are used to indicate the magnetic moment direction. Figure 12The diagram illustrates a memory cell using a PMA device. With the first switch Q1 and the second switch Q2 employing NMOS, the insertion layer 2024 is positioned between the free layer 2023 and the SOT layer 201. The up-down arrows in the reference layer 2021 and the free layer 2023 indicate the magnetic moment direction. Positioning the insertion layer 2024 between the free layer 2023 and the SOT layer 201 of the MTJ202 enhances the VCMA effect and promotes magnetic moment reversal in the free layer 2023.

[0083] Based on the above embodiments, this application provides a memory array comprising multiple memory cells, which are memory cells of any of the foregoing embodiments. Memory cells in the same column of the memory array are connected to the same first word line, second word line, and source line, and memory cells in the same row of the memory array are connected to the same bit line.

[0084] For example, refer to Figure 13 As shown, taking a 3x3 memory cell array as an example, the memory cells in each column from left to right are named column 0, column 1, and column 2, and so on. Similarly, the memory cells in each row from top to bottom are named row 0, row 1, and row 2, and so on. Specifically, each memory cell in column 0 is connected to the first word line W0L0, the second word line W1L0, and the source line SL0; each memory cell in column 1 is connected to the first word line W0L1, the second word line W1L1, and the source line SL1; and each memory cell in column 2 is connected to the first word line W0L2, the second word line W1L2, and the source line SL2. Each memory cell in row 0 is connected to bit line BL0; each memory cell in row 1 is connected to bit line BL1; and each memory cell in row 2 is connected to bit line BL2.

[0085] When writing data, in the same row of memory cells, the first word line or the second word line connected to the memory cell to be written is valid, while the first word line and the second word line connected to the memory cell not to be written are invalid; the write current flows from the bit line connected to the memory cell to be written to the source line connected to the memory cell to be written, or the write current flows from the source line connected to the memory cell to be written to the bit line connected to the memory cell to be written.

[0086] Taking NMOS as an example of the switching transistors in the memory array, refer to... Figure 14 Taking the 0th column of the 0th row of memory cells as the memory cell to be written, and the others as memory cells not to be written, in this case, the source line SL0 of the 0th column of memory cells is connected to a high level V. writeThe bit line BL0 of the 0th row memory cell is grounded, and the first word line W0L0 or the second word line W1L0 of the 0th column memory cell is active to write the first or second value; the first word line W0L1 and the second word line W1L1 of the 1st column memory cell, and the first word line W0L2 and the second word line W1L2 of the 2nd column memory cell are all inactive. The bit line BL1 of the 1st row memory cell, the bit line BL2 of the 2nd row memory cell, the source line SL1 of the 1st column memory cell, and the source line SL2 of the 2nd column memory cell can all be connected to a high level V. write .

[0087] When reading data, refer to Figure 15 The source line SL0 of the 0th column memory cell is grounded, and the bit line BL0 of the 0th row memory cell is connected to a high level V. read The first word line W0L0 and / or the second word line W1L0 of the 0th column memory cell are valid; the first word line W0L1 and the second word line W1L1 of the 1st column memory cell, and the first word line W0L2 and the second word line W1L2 of the 2nd column memory cell are invalid; the bit line BL1 of the 1st row memory cell, the bit line BL2 of the 2nd row memory cell, the source line SL1 of the 1st column memory cell, and the source line SL2 of the 2nd column memory cell can all be grounded.

[0088] Alternatively, when reading data, refer to Figure 16 The source line SL0 is connected to a high-level V. read Bit line BL0 is grounded, and the first word line W0L0 and / or the second word line W1L0 are active. The first word line W0L1 and the second word line W1L1 of the first column memory cell, and the first word line W0L2 and the second word line W1L2 of the second column memory cell are all inactive. The bit line BL1 of the first row memory cell, the bit line BL2 of the second row memory cell, the source line SL1 of the first column memory cell, and the source line SL2 of the second column memory cell can all be connected to a high level V. read .

[0089] Taking PMOS transistors as an example in the memory array, refer to... Figure 17 Taking the 0th column of the 0th row of memory cells as the memory cell to be written, and the others as memory cells not to be written, in this case, the source line SL0 of the 0th column of memory cells is grounded, and the bit line BL0 of the 0th row of memory cells is connected to a high level V. write The first word line W0L0 or the second word line W1L0 of the 0th column memory cell is valid to write the first value or the second value; the first word line W0L1 and the second word line W1L1 of the 1st column memory cell, and the first word line W0L2 and the second word line W1L2 of the 2nd column memory cell are all invalid; the bit line BL1 of the 1st row memory cell, the bit line BL2 of the 2nd row memory cell, the source line SL1 of the 1st column memory cell, and the source line SL2 of the 2nd column memory cell can all be grounded.

[0090] When reading data, refer to Figure 18 The source line SL0 of the 0th column memory cell is grounded, and the bit line BL0 of the 0th row memory cell is connected to a high level V. read The first word line W0L0 and / or the second word line W1L0 of the 0th column memory cell are valid; the first word line W0L1 and the second word line W1L1 of the 1st column memory cell, and the first word line W0L2 and the second word line W1L2 of the 2nd column memory cell are invalid; the bit line BL1 of the 1st row memory cell, the bit line BL2 of the 2nd row memory cell, the source line SL1 of the 1st column memory cell, and the source line SL2 of the 2nd column memory cell can all be grounded.

[0091] Optional, refer to Figure 19 As shown, the storage array in this embodiment further includes a column selection module 191 and a first power driver module 192 connected to the column selection module 191, a row selection module 193 and a second power driver module 194 connected to the row selection module 193. The first power driver module 192 is connected to the first word line, the second word line and the source line of each column storage cell, and the second power driver module 194 is connected to the bit line of each row storage cell. During the read and write operations of the storage array, the column selection module 191 controls the first power driver module 192 and the row selection module 193 controls the second power driver module 194 to generate corresponding level signals to realize data read and write operations in the aforementioned embodiments.

[0092] In the memory array of this embodiment, the two ends of the SOT layer of the memory cell are connected to the same bit line through a first switch and a second switch, respectively. The top electrode of the MTJ is connected to the source line. Thus, when writing data, either the first or second switch can be selected to write either a first or second value. Regardless of whether a first or second value is written, the write current flows from the bit line to the source line, or vice versa. This means that data writing can be achieved using a single write current path, reducing the complexity of the memory array's peripheral control circuitry. Furthermore, since the write current flowing through the MTJ when writing the first and second values ​​generates a VCMA effect, and the direction of the VCMA effect is consistent, this embodiment achieves the synergistic effect of SOT and VCMA by writing to both ports of the memory cell. No additional VCMA voltage is required, and there is no timing synchronization issue between the VCMA voltage and the SOT current, fundamentally reducing the complexity of the memory array's timing control.

[0093] Those skilled in the art will understand that all or part of the steps of the above embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it performs the steps of the above method embodiments; and the aforementioned storage medium includes various media capable of storing program code, such as ROM, RAM, magnetic disk, or optical disk.

[0094] Finally, it should be noted that other embodiments of the invention will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This invention is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein, and is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope.

Claims

1. A storage unit, characterized in that, include: A spin-orbit matrix layer and a magnetic tunnel junction, wherein the magnetic tunnel junction is stacked on top of the spin-orbit matrix layer; The top electrode of the magnetic tunnel junction is connected to the source line, the first end of the spin-orbit junction is connected to the bit line through the first switch, the second end of the spin-orbit junction is connected to the same bit line through the second switch, the control terminal of the first switch is connected to the first word line, and the control terminal of the second switch is connected to the second word line. When writing data, the target switch is turned on, and the target switch is either the first switch or the second switch. The write current flows from the bit line through the target switch to the source line, or the write current flows from the source line through the target switch to the bit line; The first write current is used to write a first value, and the second write current is used to write a second value. The first write current and the second write current flow through the magnetic tunnel junction in the same direction.

2. The storage unit according to claim 1, characterized in that, The first and second switching transistors are P-type metal-oxide-semiconductor field-effect transistors; When writing data, the bit line is connected to the write pulse, and the source line is grounded; and, When writing the first value, the first word line is active to control the first switch to be turned on, and the second word line is inactive to control the second switch to be turned off. The first write current flows from the bit line through the first switch to the source line. When the second value is written, the second word line is enabled to control the second switch to be turned on, and the first word line is disabled to control the first switch to be turned off. The second write current flows from the bit line through the second switch to the source line.

3. The storage unit according to claim 1, characterized in that, The first and second switching transistors are N-type metal-oxide-semiconductor field-effect transistors; When writing data, the bit line is grounded, and the source line is connected to the write pulse; and, When the first value is written, the second word line is enabled to control the second switch to be turned on, and the first word line is disabled to control the first switch to be turned off. The first write current flows from the source line through the second switch to the bit line. When the second value is written, the first word line is enabled to control the first switch to be turned on, and the second word line is disabled to control the second switch to be turned off. The second write current flows from the source line through the first switch to the bit line.

4. The storage unit according to claim 2 or 3, characterized in that, When reading data, the read current flows from the bit line to the source line, or the read current flows from the source line to the bit line; When reading data, the first word line is active to control the first switch to turn on, and / or the second word line is active to control the second switch to turn on.

5. The storage unit according to claim 1, characterized in that, The magnetic tunnel junction includes an insertion layer, the material of which is a metal or its compound with a work function greater than a preset threshold.

6. The storage unit according to claim 5, characterized in that, The insertion layer is disposed between the barrier layer and the free layer of the magnetic tunnel junction, or the insertion layer is disposed between the free layer and the spin-orbit moment layer.

7. The storage unit according to any one of claims 1-3, characterized in that, The storage unit is a device with vertical magnetic anisotropy or an in-plane magnetic anisotropy.

8. A storage array, characterized in that, include: Multiple storage units, wherein the storage unit is the storage unit according to any one of claims 1-7; In the memory array, memory cells in the same column are connected to the same first word line, second word line, and source line, and memory cells in the same row are connected to the same bit line.

9. The storage array according to claim 8, characterized in that, When writing data, in the same row of storage cells, the first word line or the second word line connected to the storage cell to be written is valid, while the first word line and the second word line connected to the storage cell not to be written are invalid. The write current flows from the bit line connected to the memory cell to be written to the source line connected to the memory cell to be written, or the write current flows from the source line connected to the memory cell to be written to the bit line connected to the memory cell to be written.

Images