An SRAM storage device, an SRAM access system, and a data access method.

Abstract

This disclosure relates to an SRAM storage device, an SRAM access system, and a data access method. The SRAM storage device includes: an SRAM array for storing data; a cache array comprising multiple cache units corresponding to each data access device; a prefetch controller for generating a target prefetch read request for a target data access device and sending the target prefetch read request to the SRAM array; and a data routing module for routing data output by the SRAM array according to the target prefetch read request to the target cache unit corresponding to the target data access device for caching, based on the device identifier of the target data access device. The cache array is also used to respond to a data access request sent by the target data access device by returning the target data cached in the target cache unit that matches the data access request to the target data access device. This reduces the SRAM array access latency perceived by the data access device and improves the data processing efficiency of the data access device.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit design, and more specifically, to an SRAM storage device, an SRAM access system, and a data access method. Background Technology

[0002] Static Random Access Memory (SRAM) is a key component in high-performance computing systems, widely used in processor caches, on-chip memory, and various embedded systems. With the continuous increase in processor clock speeds and the widespread adoption of multi-core parallel architectures, memory access efficiency has become a critical bottleneck restricting overall system performance.

[0003] In relevant technical solutions, SRAM read operations inherently involve multiple physical delays, including address transfer and decoding delays, word line charging and bit line discharging delays, sensitive amplifier amplification delays, and data output delays. These delays typically consume one or more system clock cycles, resulting in a significant wait time between address validity and data output validity. In high-performance computing architectures, especially in scenarios where the data prefetch destination is uncertain or concurrent access requests are frequent, this fixed delay period can directly block the processing pipeline, causing the processor to idle and wait throughout the entire fixed delay period of SRAM, increasing instruction latency and severely limiting system throughput and energy efficiency. Summary of the Invention

[0004] One object of this disclosure is to provide a new technical solution for SRAM storage devices that reduces the access latency of SRAM storage devices.

[0005] According to a first aspect of this disclosure, an SRAM storage device is provided, comprising: SRAM arrays are used to store data; A cache array, comprising cache units corresponding to multiple data access devices; A prefetch controller is configured to generate a target prefetch request for a target data access device and send the target prefetch request to the SRAM array; wherein the target data access device is any one or more of the plurality of data access devices, and the target prefetch request contains a device identifier of the target data access device; The data routing module is used to route the data output by the SRAM array according to the target prefetch request to the target cache unit corresponding to the target data access device for caching, based on the device identifier. The cache array is also used to respond to a data access request sent by the target data access device by returning the target data cached in the target cache unit that matches the data access request to the target data access device.

[0006] Optionally, the cache unit is configured to perform first-in-first-out management of the cached data to ensure that the data is transmitted sequentially.

[0007] Optionally, the data input terminal of the data routing module is connected to the data output terminal of the SRAM array, the data routing module has a data output terminal corresponding to each of the cache units, each data output terminal of the data routing module is connected to the data input terminal of the corresponding cache unit, and the data output terminal of the cache unit is connected to the corresponding data access device. The target cache unit is used to receive data access requests sent by the target data access device through the target connection path between the target cache unit and the target data access device, and to return the target data to the target data access device through the target connection path.

[0008] Optionally, the prefetch controller is configured to determine the predicted access address of the target data access device based on the access addresses of the historical access requests of the target data access device to the SRAM storage device and the prediction algorithm corresponding to the target data access device, and generate the target prefetch request based on the predicted access address.

[0009] Optionally, the prefetch controller is used to obtain the number of times the target data access device accesses the SRAM storage device within a set statistical period, adjust the prefetch depth of the target data access device according to the number of accesses, and generate the target prefetch read request according to the prefetch depth.

[0010] Optionally, the prefetch controller is used to detect whether the target data access device meets the corresponding prefetch triggering condition, and if the target data access device meets the corresponding prefetch triggering condition, it generates the target prefetch read request.

[0011] Optionally, the prefetch triggering conditions of the target data access device include any one or more of the following: The free space of the target cache unit is greater than or equal to the corresponding space threshold; The percentage of used space in the target cache unit is less than or equal to the corresponding percentage threshold; The time interval between the current time and the last time a prefetch request for the target data access device was generated is greater than or equal to a time threshold; Receives a prefetch command sent from an external source for the target data access device.

[0012] Optionally, the prefetch controller is configured to determine the prefetch step size of the target data access device based on the access address of the target data access device’s historical access requests to the SRAM storage device, and generate the target prefetch read request based on the prefetch step size.

[0013] According to a second aspect of this disclosure, an SRAM access system is provided, including a plurality of data access devices and an SRAM storage device as described in the first aspect of this disclosure; the data access devices are used to access the SRAM storage device.

[0014] Optionally, the SRAM access system further includes an on-chip network, through which the plurality of data access devices are connected to the SRAM storage device and access the SRAM storage device.

[0015] According to a third aspect of this disclosure, a data access method for an SRAM memory device is provided, comprising: Generate a target prefetch request for a target data access device; wherein the target data access device is any one or more of a plurality of data access devices connected to the SRAM storage device, and the target prefetch request contains a device identifier of the target data access device; Read the data stored in the SRAM array according to the target prefetch request; According to the device identifier, the data output by the SRAM array based on the target prefetch request is routed to the target cache unit corresponding to the target data access device for caching; In response to a data access request sent by the target data access device, the data cached in the target cache unit that matches the data access request is returned to the target data access device.

[0016] In the embodiments of this disclosure, a cache array consisting of multiple independent cache units is set between the SRAM array and multiple data access devices. Each cache unit forms a dedicated prefetch channel with a specific data access device. The prefetch controller generates a prefetch read request from the data access device based on a prediction algorithm. The data routing module routes the data read from the SRAM array to the corresponding dedicated cache unit according to the device identifier of the data access device, enabling the data access device to directly read data from the corresponding cache unit. In this way, the inherent access latency of the SRAM array is transformed into a background prefetch operation that can be covered by parallel computing, which can significantly reduce the SRAM array access latency perceived by the data access device, improve the data processing efficiency of the data access device, and reduce the idle waiting time of the data access device.

[0017] The features and advantages of the embodiments of this specification will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0018] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments of this specification and, together with their description, serve to explain the principles of these embodiments.

[0019] Figure 1 This is a schematic diagram of an SRAM storage device according to an embodiment of the present disclosure; Figure 2 This is a schematic diagram of an SRAM access system according to an embodiment of the present disclosure; Figure 3 This is a flowchart illustrating the data access method of the SRAM storage device according to this embodiment. Detailed Implementation

[0020] Various exemplary embodiments of this specification will now be described in detail with reference to the accompanying drawings.

[0021] The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit the embodiments of this specification or their application or use.

[0022] It should be noted that similar labels and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be discussed further in subsequent figures.

[0023] From a digital design perspective, a complete SRAM read operation is not a simple instantaneous data retrieval process, but a complex physical process with a fixed timing path and involving the coordinated operation of multiple stages. When the data access device issues a read command, the data stored in the SRAM cannot be retrieved and used immediately. Instead, it must go through multiple consecutive physical and logical processing stages. Each stage inevitably introduces a corresponding delay. These multi-stage delays are superimposed and together constitute the total delay of the SRAM read operation, directly determining the upper limit of SRAM read performance and having a profound impact on the operating efficiency of the entire digital system.

[0024] Specifically, the latency of SRAM read operations mainly stems from four key and consecutive stages. The latency characteristics of each stage are interconnected and mutually influential, and cannot be analyzed independently. The first stage is the address transmission and decoding latency. The input address signal needs to be transmitted to the SRAM through the interconnection network inside the SRAM chip. Subsequently, the row address decoder decodes the address signal to determine the location of the target memory cell. This process introduces the interconnection latency of signal transmission, as well as the gate latency caused by multi-level combinational logic circuits. Moreover, this latency increases significantly with the increase of SRAM capacity and the continuous expansion of array size, becoming one of the important factors restricting SRAM read speed.

[0025] The second stage involves word line charging and bit line discharging delays, which are the core source of the overall SRAM read latency. The activated word line after decoding is essentially a global conductor with high parasitic resistance and capacitance. It needs time to charge to an effective level before it can effectively activate the target memory cell. Subsequently, the selected memory cell turns on, discharging the heavily loaded bit line capacitor, thus establishing a small voltage difference across the bit line pair. This voltage difference characterizes the data information stored within the memory cell. It is worth noting that this capacitor charging and discharging process is constrained by inherent physical laws. Its speed is determined by the characteristics of the integrated circuit process, the design parameters of the memory cell itself, and the array size, making it difficult to significantly reduce through conventional digital logic optimization methods. This is the core challenge in SRAM read latency optimization.

[0026] The third stage is the amplification delay of the sensitive amplifier. Since the tiny voltage difference established on the bit line cannot be directly used for subsequent data transmission and processing, a high-precision, high-gain sensitive amplifier must accurately detect this tiny voltage difference and amplify it to the full amplitude digital logic level in order to meet the requirements of subsequent data transmission. The enable timing, response speed, and output signal establishment and stabilization time of the sensitive amplifier together constitute the inherent delay of this stage, and its performance directly affects the accuracy and timeliness of SRAM data reading.

[0027] The fourth stage is the data output delay. The stable digital data, after being amplified by the sensitive amplifier, needs to be processed by the final data selection circuit and output drive circuit inside the chip before it can be transmitted to the I / O port of the SRAM for the central processing unit or other main control devices to read. This stage also introduces a certain logic delay and signal transmission delay, which further increases the total time spent reading the SRAM.

[0028] In actual digital system operation, for digital system designers, the SRAM read latency resulting from the superposition of the above-mentioned multiple stages manifests as a definite but time-consuming wait period between the effective address signal and the effective data output. This wait period typically consumes one or more system clock cycles. In current high-performance computing architectures, especially in application scenarios where the data prefetch destination is uncertain and concurrent access requests are frequent, this fixed latency period can directly block the digital system's processing pipeline, leading to increased instruction latency and severely limiting system throughput and energy efficiency.

[0029] More importantly, in the traditional SRAM access mode, the data demand of the data consumer (i.e., the data access device) is forced to be synchronized with the data readiness of the SRAM. This strong synchronization mechanism makes it impossible for the processor to perform effective calculations within the fixed delay period of the SRAM, and it can only idle and wait, resulting in a serious waste of processor resources and further exacerbating the bottleneck of digital system performance improvement.

[0030] Currently, most industry optimization solutions for SRAM read latency are limited to single-stage, localized improvements. For example, they might only optimize the response speed of the sensitivity amplifier or only optimize word line routing to reduce parasitic parameters. These solutions fail to fully consider the correlation and coupling relationships between timing paths at each latency stage, resulting in significant bottlenecks in SRAM read performance improvement and an inability to meet the high demands of current high-performance digital systems for memory read speeds. Furthermore, as integrated circuit technology continues to evolve towards advanced small nodes, SRAM capacity and array size are constantly increasing, making latency issues at each stage increasingly prominent and further restricting the overall performance improvement of digital systems.

[0031] Therefore, clarifying the multi-stage physical process of SRAM read operations and the generation mechanism and influencing factors of delays in each stage, sorting out the intrinsic correlation of each delay stage, and solving the pain point of processor idling and waiting in the traditional access mode have become the key prerequisites for optimizing SRAM read performance, breaking through performance bottlenecks, and improving the operating efficiency and energy efficiency of digital systems. It also provides important technical support for the design and improvement of subsequent SRAM read timing control schemes.

[0032] <First Embodiment> This embodiment provides an SRAM storage device, such as Figure 1 As shown, the SRAM storage device 100 may include an SRAM array 110, a cache array 120, a prefetch controller 130, and a data routing module 140.

[0033] SRAM array 110 is used to store data.

[0034] The cache array 120 includes cache units corresponding to multiple data access devices.

[0035] The prefetch controller 130 is used to generate a target prefetch request for a target data access device and send the target prefetch request to the SRAM array; wherein the target data access device is any one or more of a plurality of data access devices, and the target prefetch request contains a device identifier of the target data access device.

[0036] The data routing module 140 is used to route the data output by the SRAM array according to the target prefetch request to the target cache unit corresponding to the target data access device for caching, based on the device identifier.

[0037] The cache array 120 is also used to return data cached in the target cache unit that matches the data access request to the target data access device in response to a data access request sent by the target data access device.

[0038] The capacity of SRAM array 110 can be configured according to application requirements, such as 64KB, 128KB, 256KB, 512KB, 1MB, or 2MB. SRAM array 110 adopts a standard SRAM cell array structure, including a cell array, row address decoder, column address decoder, sensitive amplifier, and data output driver circuitry. The address input of SRAM array 110 receives the address signal from the prefetch request from prefetch controller 130, and the data output is connected to the data input of data routing module 140. The read latency of SRAM array 110 includes address transmission and decoding latency, word line charging and bit line discharging latency, sensitive amplifier amplification latency, and data output latency.

[0039] The cache array 120 includes multiple independent cache units, each of which corresponds to a data access device.

[0040] The number of cache units in cache array 120 can be the same as the number of data access devices. For example, when N data access devices (including data access device 0, data access device 1, data access device 2, ..., data access device N-1) need to access the SRAM storage device in an SRAM access system, cache array 120 contains N cache units, denoted as cache unit 0, cache unit 1, cache unit 2, ..., cache unit N-1, and each cache unit is bound to a corresponding numbered data access device.

[0041] Data access devices can be processor cores, graphics processing units, digital signal processors, direct memory access controllers, or other functional modules that need to access SRAM. Each data access device has a unique device identifier.

[0042] Each data access device's data read interface is connected to the data output terminal of its corresponding cache unit. When a target data access device needs to read data, it initiates a data access request to the corresponding target cache unit. Upon receiving the data access request, the target cache unit outputs the target data matching the data access request from its stored data to the target data access device through its data output terminal. The latency of the data access device reading data is only the access latency of the corresponding cache unit, which is significantly lower than the latency of directly accessing the SRAM array.

[0043] After receiving a target prefetch request, the SRAM array performs a read operation based on the access address in the request. The SRAM read operation sequentially goes through several stages, including address transfer decoding, word line charging and bit line discharging, sensitive amplifier signal amplification, and data output driving. The access address is decoded by the row address decoder and column address decoder. After decoding, the activated word line is charged to an effective level. The selected memory cell is turned on and discharges the bit line capacitor, establishing a small voltage difference on the bit line pair. The sensitive amplifier detects and amplifies the small voltage difference on the bit line to a full-amplitude digital logic level. The amplified stable data is then sent to the SRAM data output terminal through the data selection and output driving circuit.

[0044] When the prefetch controller 130 generates a prefetch request from the target data access device and initiates an SRAM read operation, any data access device can normally execute its own computing tasks or read the prefetched data. The SRAM read operation is performed in the background and does not block the normal operation of any data access device. After the SRAM read delay, the data output terminal of the SRAM array outputs the read data, which is routed to the target cache unit corresponding to the target data access device through the data routing module 140, completing the data prefetch.

[0045] In some examples, the data routing module 140 receives data output from the SRAM array and a device identifier of the target data access device provided by the prefetch controller 130. Based on the device identifier, the data routing module 140 determines the target cache cell in the cache array. The data routing module 140 routes the data received at the data input terminal to the data input terminal of the target cache cell, and simultaneously generates a write enable signal to control the target cache cell to perform a write operation.

[0046] In some embodiments, the data routing module 140 may include an address decoding unit and a data selection unit. The address decoding unit generates a cache unit selection signal based on the device identifier of the target data access device, and the data selection unit routes the data output from the SRAM array to the corresponding target cache unit based on the cache unit selection signal. The data input terminal of the data selection unit is connected to the data output terminal of the SRAM array to receive data read from the SRAM. The control terminal of the data selection unit is connected to the data output terminal of the address decoding unit to receive the cache unit selection signal. The data selection unit includes multiple data output terminals, each of which is connected to the data input terminal of a cache unit in the cache array.

[0047] The device identifier of the data access device can be encoded in binary. For example, a 2-bit device identifier can support 4 data access devices, encoded as 00, 01, 10, and 11 respectively. The address decoding unit performs a decoding operation based on the received device identifier, generating buffer unit selection signals. These buffer unit selection signals are in one-hot code form, meaning that only one of the multiple selection signals is high, while the rest are low. The high-level signal indicates the buffer unit to be selected. For example, when the device identifier of the target data access device is 00, the address decoding unit generates buffer unit selection signals sel0=1, sel1=0, sel2=0, and sel3=0, indicating the selection of buffer unit 0; when the device identifier of the target data access device is 01, it generates sel0=0, sel1=1, sel2=0, and sel3=0, indicating the selection of buffer unit 1. The address decoding unit can be implemented using combinational logic circuits. For example, a 2-to-4 decoder circuit can be used to decode the 2-bit device identifier into 4 buffer unit selection signals.

[0048] The data selection unit routes the data received at the data input terminal to the corresponding buffer unit connected to the data output terminal based on the buffer unit selection signal. For example, when the buffer unit selection signal is sel0=1, sel1=0, sel2=0, and sel3=0, the data selection unit routes the data output from the SRAM array to the data input terminal of buffer unit 0 connected to data output terminal 0, and the data is written to buffer unit 0. The data selection unit can be implemented using a multiplexer circuit, such as a 1-4 data distributor circuit, which distributes the input data to one of the four data output terminals according to the buffer unit selection signal.

[0049] The data routing module may also include a write enable signal generation circuit. This circuit generates a write enable signal for the corresponding target cache unit based on the cache unit selection signal. For example, when the cache unit selection signal sel0=1, it generates a write enable signal wr_en0=1 for cache unit 0, instructing cache unit 0 to perform a write operation. The write enable signal is then sent from the write enable output of the data routing module to the write enable input of the corresponding target cache unit.

[0050] Through the cooperation of the address decoding unit and the data selection unit, the data routing module can accurately route data read from SRAM to the corresponding cache unit based on the device identifier of the target data access device. This architecture can efficiently implement data routing and distribution, support the parallel operation of multiple cache units, and ensure that prefetched data is accurately distributed to the corresponding cache unit.

[0051] In the embodiments of this disclosure, a cache array consisting of multiple independent cache units is set between the SRAM array and multiple data access devices. Each cache unit forms a dedicated prefetch channel with a specific data access device. The prefetch controller generates a prefetch read request from the data access device based on a prediction algorithm. The data routing module routes the data read from the SRAM array to the corresponding dedicated cache unit according to the device identifier of the data access device, enabling the data access device to directly read data from the corresponding cache unit. In this way, the inherent access latency of the SRAM array is transformed into a background prefetch operation that can be covered by parallel computing, which can significantly reduce the SRAM array access latency perceived by the data access device, improve the data processing efficiency of the data access device, and reduce the idle waiting time of the data access device.

[0052] In this embodiment, the cache array adopts a parallel architecture of multiple cache units, which has strong overall scalability. In practical applications, the number of cache units can be flexibly increased to adapt to the concurrent transmission needs of more data access devices. The overall data throughput performance of the system can be improved almost linearly with the increase of the number of data access devices, effectively meeting the on-chip data interaction scenarios of multiple nodes and high concurrency.

[0053] In some embodiments, the cache unit is configured to perform first-in-first-out (FIFO) management of the cached data so that the data is transmitted sequentially.

[0054] In this embodiment, each cache unit adopts a standard first-in-first-out queue structure, including a write pointer, a read pointer, a storage unit array, and an empty / full status flag.

[0055] When the data routing module 140 transmits the prefetch data output by the SRAM array 110 to the target cache unit, the write pointer of the target cache unit points to the currently writable storage location. After the data is written, the write pointer is automatically incremented by 1 to point to the next free storage location. If the storage queue of the target cache unit is full (full status flag is set to 1), the writing is paused until data is read from the target cache unit and the free storage location is released.

[0056] When the target data access device sends a data access request to the target cache unit, the read pointer points to the earliest written data in the storage queue (i.e., the first data), and outputs the data to the target data access device. After the data is read, the read pointer is automatically incremented by 1, pointing to the next data to be read. If the target cache unit's storage queue is empty (empty status flag is set to 1), a signal indicating "data not ready" is fed back to the target data access device.

[0057] By synchronizing read and write pointers and providing real-time feedback on empty / full status indicators, the system ensures that data cached in the cache unit is transmitted to the corresponding data access device in a first-in, first-out (FIFO) order. This prevents errors in data access device operations due to out-of-order data, while also guaranteeing data transmission continuity and improving data reading accuracy. Prefetched data, cached in the cache unit, can be output according to the read requirements of the data access device. Combined with the prefetch mechanism, this reduces the idle waiting time of the data access device, improving resource utilization and data processing efficiency.

[0058] In some embodiments, the data input terminal of the data routing module 140 is connected to the data output terminal of the SRAM array 110. The data routing module 140 has an output terminal corresponding to each cache unit. Each data output terminal of the data routing module 140 is connected to the data input terminal of the corresponding cache unit, and the data output terminal of the cache unit is connected to the corresponding data access device. The target cache unit is used to receive a data access request sent by the target data access device through the target connection path between the target cache unit and the target data access device, and in response to the data access request, return the target data to the target data access device through the target connection path.

[0059] In this embodiment, the data output terminal of each cache unit is directly connected to the corresponding data access device, forming a dedicated connection path. This connection path is a bidirectional transmission path, used on one hand for the cache unit to receive data access requests sent by the corresponding data access device, and on the other hand for the cache unit to return matching data to the corresponding data access device, realizing efficient bidirectional data interaction. Moreover, each connection path is independent of the others and does not interfere with each other.

[0060] In this embodiment, the cache unit directly receives data access requests from the corresponding data access device and returns data through a dedicated connection path, which shortens the data interaction path. Combined with the prefetching mechanism, it further reduces the waiting time of the data access device, improves the resource utilization of the data access device, and enhances the system throughput. Moreover, the cache unit and the data access device use a dedicated bidirectional connection path, which effectively avoids interference and mistransmission during data transmission, improving the accuracy and stability of data transmission. Each connection path works independently, supporting parallel access by multiple data access devices, avoiding data conflicts and port arbitration delays when multiple computing units concurrently access the SRAM storage device, and ensuring the stability of prefetching efficiency.

[0061] In some embodiments, the prefetch controller is configured to determine the predicted access address of the target data access device based on the access address of the target data access device’s historical access requests to the SRAM storage device and the prediction algorithm corresponding to the target data access device, and generate a target prefetch request based on the predicted access address.

[0062] In this embodiment, the prefetch controller incorporates multiple address flow prediction algorithms. Each algorithm is adapted to different memory access scenarios of different data access devices (such as sequential access, step-by-step access, and random access scenarios) and is pre-bound to each data access device to achieve precise adaptation between the data access device and the prediction algorithm. The correspondence between the device and the address flow prediction algorithm can be flexibly adjusted according to the actual computing scenario of the data access device to cover the prediction requirements of different memory access modes.

[0063] For example, data access device 1 performs continuous computation tasks, and address access is sequential, so it can be bound to a sequential address flow prediction algorithm; data access device 2 performs fixed-step computation tasks, and address access is at fixed intervals, so it can be bound to a step-size address flow prediction algorithm; data access device 3 performs complex logical operations, and address access is associative, so it can be bound to an associative address flow prediction algorithm; data access device 4 performs random computation tasks, and address access has no obvious pattern, so it can be bound to a stream-mode address flow prediction algorithm.

[0064] The sequential address flow prediction algorithm is based on the principle of spatial locality of program data access, that is, consecutively accessed addresses are often located in adjacent address spaces. The core logic is: analyze the historical access address sequence, extract the address increment / decrement pattern (e.g., historical addresses are 0x00000000, 0x00000004, 0x00000008, with an increment step of 4), determine the address change trend, and then predict the next / multiple access addresses (e.g., predicted addresses are 0x0000000C, 0x00000010). This algorithm has low hardware overhead, is suitable for continuous address access scenarios, and can achieve a prefetch accuracy of over 90%. It is suitable for computational tasks involving continuous data storage and sequential reading, such as large-scale data scanning and linear operations.

[0065] The core logic of the step-size address flow prediction algorithm is as follows: Analyze the historical access address sequence, calculate the difference (step size) between two adjacent access addresses, and determine that the step size is fixed when the step size is consistent for K1 consecutive accesses. Based on the fixed step size and the latest access address, predict the subsequent access address (e.g., if the historical addresses are 0x00000000, 0x00000008, 0x00000010, the step size is 8, the latest address is 0x00000010, and the predicted addresses are 0x00000018, 0x00000020). This algorithm needs to use an access prediction table to record access address and step size information, adapt to fixed-step address access scenarios, such as array traversal and loop operations, and the prefetch accuracy can reach over 88%. The hardware implementation difficulty is moderate, balancing accuracy and resource consumption.

[0066] The core logic of the associated address flow prediction algorithm is as follows: analyze the historical access address sequence, mine the association relationship between different addresses (such as after accessing address A, address B and address C will inevitably be accessed), establish an address association mapping table, and when accessing address A is detected, directly predict that address B and address C will be accessed subsequently. This algorithm uses the association between memory access addresses for prefetching, which is suitable for complex logical operation scenarios, such as multi-parameter collaborative operation and branch instruction execution. The prefetch accuracy can reach more than 85%, and it can effectively deal with the address access requirements that are not continuous but have fixed associations.

[0067] The core logic of the stream-mode address flow prediction algorithm is as follows: it uses the flow identification buffer to record the memory access addresses within a certain period of time, identifies the flow characteristics of address access (i.e., the pattern of addresses accessed by the program within a certain period of time), and predicts the subsequent access addresses based on the flow characteristics. This algorithm does not require a preset step size or correlation relationship, and is suitable for scenarios where address access has no obvious fixed pattern but has short-term flow characteristics, such as random data sampling and complex condition judgment operations. The prefetch accuracy can reach more than 80%, effectively reducing the invalid prefetch overhead in random access scenarios and avoiding cache pollution.

[0068] In some examples, the prefetch controller can also monitor all data access requests initiated by each data access device to the SRAM storage device through the corresponding cache unit, collect and store the access addresses of the historical access requests of each data access device, forming an independent historical access address sequence for each data access device; the collected address information includes the complete physical access address (e.g., it can be 32 bits, adapted to the address space of the SRAM array), and records the access timestamp of each address for subsequent address flow prediction algorithm analysis; the storage depth of the historical address sequence is configurable (e.g., it can be set to 128 entries, or it can be adjusted according to system requirements), and adopts a first-in-first-out management method. When the storage capacity reaches the upper limit, it automatically overwrites the earliest access address to ensure the timeliness of historical data, which conforms to the principle of temporal locality of program data access, that is, the address that has been accessed recently is more likely to be accessed later.

[0069] The prefetch controller can call the address flow prediction algorithm corresponding to the target data access device, read the historical access address sequence of the target data access device, and analyze the access patterns of the historical addresses through the algorithm (combining the characteristics of historical address value changes, access time order, and frequency of repeated access) to determine 1 to N predicted access addresses that the target data access device may initiate access to in the future (N is the prefetch depth of the target data access device).

[0070] After the prefetch controller determines the predicted access address, it selects a number of predicted access addresses that match the prefetch depth of the target data access device and generates a target prefetch read request. The target prefetch read request contains the device identifier of the target data access device and the predicted access address. The target prefetch read request is then sent to the control terminal of the SRAM array to prefetch the data stored at the predicted access address into the target cache unit.

[0071] In addition, the prefetch controller can also record the predicted access address, the corresponding prediction algorithm, and the actual access address of the subsequent data access device for each prefetch, in order to optimize the accuracy of the address flow prediction algorithm and continuously improve the rationality of prefetching.

[0072] In this embodiment, a prefetch algorithm is independently configured for each data access device. The predicted access address is determined based on the access address of the historical access requests of each data access device and the corresponding prediction algorithm. Data is then prefetched based on the predicted access address and cached in the corresponding cache unit. This can improve the accuracy of the predicted access address, reduce invalid prefetch overhead, avoid cache pollution, and also avoid invalid prefetching and bandwidth waste caused by a unified prefetch algorithm, thereby improving the effective utilization of SRAM array bandwidth and the overall system energy efficiency.

[0073] In some embodiments, the prefetch controller is configured to acquire the number of times the target data access device accesses the SRAM storage device within a set statistical period, adjust the prefetch depth of the target data access device according to the number of accesses, and generate a target prefetch read request according to the prefetch depth of the target data access device.

[0074] The prefetch depth of each data access device can be configured independently, and the prefetch depth of different cache units can be the same or different.

[0075] Prefetch depth is the maximum amount of data that the prefetch controller sets individually for each data access device in an SRAM storage device, allowing for single prefetching. Too small a prefetch depth can lead to rapid depletion of cached data, causing data access devices to wait; too large a prefetch depth, on the other hand, results in redundant and wasted cache resources and increases the overhead of SRAM reads and data routing.

[0076] The prefetch controller counts the number of times the target data access device accesses the SRAM memory device within a set statistical period. The access count can be calculated using a sliding window method, for example, counting the access count over the last 1000 clock cycles. Based on the access count, the prefetch depth of the target data access device is dynamically adjusted. When the access count is high, it indicates frequent data demand from the target data access device; increasing the prefetch depth ensures that the corresponding target cache unit can cache enough prefetched data, reducing the waiting time of the target data access device, reducing the number of prefetch operations, and improving prefetch efficiency. When the access count is low, it indicates that the data demand from the target data access device is moderate; decreasing the prefetch depth avoids wasting cache resources in the corresponding target cache unit by prefetching too much invalid data, thus reducing SRAM bandwidth usage.

[0077] In this embodiment, a first mapping data reflecting the mapping relationship between the number of accesses and the prefetch depth can be preset; based on the number of accesses of the data access device and the first mapping data, the prefetch depth corresponding to the number of accesses is obtained and used as the prefetch depth of the data access device.

[0078] The first mapping data can be the first mapping function, or the first lookup table, etc., and is not limited here.

[0079] For the first mapping function, the dependent variable is the prefetch depth and the independent variable is the number of accesses. Thus, by substituting the number of accesses of the data access device into the first mapping function, the prefetch depth corresponding to the number of accesses can be obtained, which can be used as the prefetch depth of the data access device.

[0080] For the first lookup table, the prefetch depth corresponding to the number of accesses of the data access device can be found in the first lookup table and used as the prefetch depth of the data access device. If the number of accesses cannot be found directly in the first lookup table, two values ​​adjacent to the number of accesses can be found, and the prefetch depth corresponding to the number of accesses of the data access device can be obtained by interpolation based on these two values ​​and the prefetch depths corresponding to these two values, and used as the prefetch depth of the data access device.

[0081] In this embodiment, the prefetch controller generates a prefetch read request for the data access device based on the prefetch depth of the data access device. Then, the bit width of the data output by the SRAM array in response to the prefetch read request matches the corresponding prefetch depth.

[0082] In this embodiment, the prefetch depth of the data access device is dynamically adjusted according to the number of accesses, which can achieve a precise match between prefetch resources and the needs of the data access device. Data access devices with high-frequency access correspond to a larger prefetch depth to avoid insufficient prefetching and idling waiting of the data access device; data access devices with low-frequency access or no access correspond to a smaller prefetch depth or pause prefetching to avoid wasting cache resources and invalid prefetching overhead, thereby improving cache resource utilization and system energy efficiency.

[0083] In some embodiments, the prefetch controller is used to detect whether the target data access device meets the corresponding prefetch triggering condition, and if the target data access device meets the corresponding prefetch triggering condition, it generates a target prefetch read request.

[0084] The prefetch triggering conditions for the target data access device are used to determine when to initiate a prefetch operation for that device, and are the core mechanism for the prefetch controller to achieve efficient prefetching. The prefetch triggering conditions for different data access devices can be the same or different, and the prefetch controller can flexibly configure the prefetch triggering conditions for each data access device according to the application scenario.

[0085] In this embodiment, prefetching is initiated only when the target data access device meets the corresponding prefetch triggering conditions, avoiding meaningless prefetching when the target cache unit has limited free space, reducing the invalid occupation of cache resources, and avoiding the additional access pressure on the SRAM array caused by frequent invalid prefetching. This allows cache resources to prioritize serving actual computing needs and improves the resource utilization efficiency of the cache and SRAM array.

[0086] In some embodiments, the prefetch triggering condition corresponding to the target data access device includes any one or more of the following: The free space of the target cache unit is greater than or equal to the corresponding space threshold; The percentage of used space in the target cache unit is less than or equal to the corresponding percentage threshold; The time interval between the current time and the last time a prefetch request was generated from the target data access device is greater than or equal to a time threshold; Received a prefetch command sent from an external source for the target data access device.

[0087] In embodiments where the prefetch triggering condition for the target cache unit includes that the free space of the target cache unit is greater than or equal to the corresponding space threshold, the space threshold can be pre-set based on the target cache unit. For example, the space threshold can be, but is not limited to, 1kB. This ensures that the prefetched data has sufficient cache space for storage, avoiding cache overflow.

[0088] In embodiments where the prefetch triggering condition corresponding to the target cache unit includes the use space percentage of the target cache unit being less than or equal to the corresponding percentage threshold, the percentage threshold can be pre-set based on the target cache unit. For example, the percentage threshold can be, but is not limited to, 70%. By inferring free space from used space, this adapts to scenarios where cached data changes dynamically, avoiding false triggers caused by fluctuations in free space.

[0089] In embodiments where the prefetch triggering condition corresponding to the target data access device includes the time interval between the current time and the last time a prefetch request for the target data access device was generated being greater than or equal to a time threshold, the time threshold can be preset according to the target data access device. For example, the time threshold can be, but is not limited to, 500ns. This condition is suitable for time-sensitive scenarios, avoiding excessive cache resource consumption and excessive SRAM array access pressure caused by frequent prefetching in a short period of time, while ensuring the timeliness of prefetched data and avoiding cache pollution caused by prefetched data not being accessed for a long time.

[0090] In embodiments where the prefetch triggering condition for the target data access device includes receiving a prefetch command sent from an external source, the target data access device is forced to determine that it meets the corresponding prefetch triggering condition and initiate the prefetch process, regardless of whether the target data access device meets any of the aforementioned prefetch triggering conditions. This condition is adapted to special scenarios such as sudden computations and urgent data readings, ensuring the enforceability of external commands and overcoming the limitations of conventional triggering conditions.

[0091] This embodiment uses two core conditions—free space threshold and used space percentage threshold—to dual-verify cache storage capacity. This ensures that prefetching is initiated only when the cache has sufficient free resources, avoiding issues such as unstored prefetched data, cache overflow, and data corruption. This guarantees the stability and security of the prefetching process while maximizing the utilization of free cache resources and improving cache storage efficiency. Introducing a prefetch interval threshold restricts repeated prefetching to the same data access device within a short period, effectively reducing invalid access pressure on the SRAM array, lowering the probability of cache resources being occupied by frequently prefetched data, and preventing cache pollution caused by long-term idle prefetched data. It also ensures the timeliness of prefetched data, achieving precise matching between prefetch frequency and system operation rhythm, balancing prefetch efficiency and resource consumption. Using the receipt of external prefetch commands as one of the trigger conditions complements cache state conditions. This satisfies the on-demand prefetching needs of regular operation scenarios while adapting to special scenarios such as burst operations and urgent data readings. It breaks the limitations of a single trigger condition, allowing the prefetch logic to flexibly respond to the overall system operation needs and improve the versatility of the solution.

[0092] In some embodiments, the prefetch controller is configured to determine the prefetch step size of the target data access device based on the access address of the target data access device’s historical access requests to the SRAM storage device, and also generate a corresponding prefetch read request based on the prefetch step size.

[0093] In this embodiment, differentiated step-size analysis logic can be adopted for the access scenarios of the target data access device to adapt to the diversity of address access. The access scenarios of the target data access device can be any one of sequential access scenarios, fixed step-size access scenarios, dynamic step-size access scenarios, and random access scenarios.

[0094] When the target data access device is accessed sequentially, the increasing / decreasing pattern of its historical access address sequence can be analyzed. The difference between two adjacent access addresses (i.e., the initial step size) can be calculated. When the step size is consistent for K1 consecutive accesses and the address change trend remains increasing or decreasing, this step size is set as the prefetch step size for the target data access device. If the step size changes in subsequent access addresses, the step size for the K1 consecutive accesses is recalculated, and the prefetch step size is dynamically updated. Here, K1 is a positive integer pre-set according to the application scenario or specific requirements.

[0095] When the target data access device operates on a fixed-step access scenario, the difference between adjacent addresses in the historical access address sequence of the target data access device can be calculated. The step size with the highest frequency of occurrence and a consecutive occurrence count of ≥K2 can be selected as the prefetch step size for the target data access device. If multiple high-frequency step sizes are present, the step size corresponding to the most recent access can be selected based on the access timestamp. Here, K2 is a positive integer pre-set according to the application scenario or specific requirements.

[0096] When the target data access device operates on a dynamic step-size access scenario, the most recent K3 historical access addresses of the target data access device can be collected. The step size of adjacent addresses can be calculated, and the average of these step sizes can be used as the prefetch step size for the target data access device. For every additional K4 historical access addresses of the target data access device, the average value is recalculated, and the prefetch step size is dynamically adjusted to ensure that the predicted step size matches the address access pattern. Here, K3 and K4 are positive integers pre-set according to the application scenario or specific requirements; K3 and K4 can be the same or different.

[0097] When the access scenario of the target data access device is a random access scenario, if the historical access address of the target data access device does not have an obvious step size pattern (the fluctuation range of the difference between adjacent addresses is greater than or equal to the set fluctuation threshold), the prefetch step size of the target data access device is set to a default step size, and the adaptability of the prefetch step size is optimized by combining the address flow prediction algorithm.

[0098] In this embodiment, the prefetch step size of the target data access device is dynamically adjusted based on the historical access address of the target data access device, adapting to the address access patterns of different computing scenarios (sequential, fixed step size, dynamic step size, random access), making the predicted access address more in line with the actual access habits of the data access device, improving prefetch accuracy, reducing invalid prefetch overhead, avoiding cache pollution, while improving cache resource utilization and data access efficiency, reducing invalid access pressure on the SRAM array, and extending hardware lifespan.

[0099] <Second Embodiment> This disclosure also provides an SRAM access system, such as... Figure 2 As shown, the SRAM access system 200 may include a plurality of data access devices 210 and an SRAM storage device 100 as described in any of the foregoing embodiments. The data access devices 210 are used to access the SRAM storage device 100.

[0100] In this embodiment, the data access device may be a processor core, a graphics processing unit, a digital signal processor, a memory access controller, or other functional modules that need to access SRAM.

[0101] Each data access device operates independently, initiating data access requests to the SRAM storage device in parallel. The memory access requirements and address access patterns of each device differ, adapting to the parallel computing needs of various scenarios. Each data access device 210 has a data access interface directly connected to the corresponding cache unit data output in the SRAM storage device 100, forming a dedicated bidirectional access path. This interface is used to send data access requests (including access address and access type) and receive data returned by the SRAM storage device 100, avoiding data transmission interference when multiple data access devices access data in parallel. The data access device 210 can also record its own access history, working with the prefetch controller of the SRAM storage device 100 to collect historical access addresses. It can also receive external control commands to adjust its access frequency and access priority.

[0102] In this embodiment, multiple data access devices and SRAM storage devices can work in parallel and collaboratively. Each data access device can directly read prefetched data from its corresponding cache unit, which can balance the access needs of multiple data access devices, reduce the idle waiting time of data access devices, and improve the parallel access capability and overall throughput of the SRAM access system.

[0103] In some examples, the SRAM access system can be an integrated circuit chip, a system-on-a-chip (SoC), or a computer device.

[0104] In some embodiments, the SRAM access system 200 may further include an on-chip network, and the data access device 210 is connected to the SRAM storage device 100 via the on-chip network and accesses the SRAM storage device 100 via the on-chip network.

[0105] The Network-on-Chip (NoC) adopts a mesh topology to adapt to the parallel transmission requirements of multiple data access devices. It features low latency, high bandwidth, and scalability. The core is used to connect multiple data access devices and SRAM storage devices to achieve high-speed and orderly data transmission. The NoC incorporates routing nodes, transmission links, and an arbitrator. The routing nodes are used to parse device identifiers and address information in the data to achieve accurate data routing. The transmission links use bidirectional differential signal transmission, with each link having a transmission rate of up to 200MHz, ensuring high-speed and stable data transmission. The arbitrator is used to sort the access requests transmitted in parallel according to the access priority of the data access devices, prioritizing the forwarding of requests from high-priority data access devices to avoid data transmission congestion and balance the access latency of each data access device.

[0106] Each data access device's on-chip network interface (CNIC) is connected one-to-one with the CNIC's data access device port. The CNIC's storage device port is directly connected to the SRAM storage device's CNIC interface, forming the first connection path from each data access device to the CNIC. This first connection path uses a bidirectional data bus, supporting the data access device sending access requests to the CNIC and the CNIC returning data to the data access device. The CNIC's storage device port is also directly connected to the SRAM storage device's CNIC interface, forming the second connection path from the CNIC to the SRAM storage device. This second connection path also uses a bidirectional data bus, supporting the CNIC forwarding all data access requests from the data access devices to the SRAM storage device and the SRAM storage device returning data to the CNIC, thus meeting the data transmission requirements when multiple data access devices access data in parallel.

[0107] In this embodiment, by setting up an on-chip network as the data transmission hub between the data access device and the SRAM storage device, the connection complexity between multiple data access devices and the SRAM storage device can be simplified. The mesh topology enables parallel forwarding of access requests from multiple data access devices, avoiding data transmission congestion, reducing access latency, and improving the stability and reliability of data transmission. Furthermore, the on-chip network has excellent scalability; additional data access devices or cache units can be added through reserved ports without reconstructing the entire system and connection links, significantly reducing the hardware overhead and design complexity of system expansion and improving the versatility and flexibility of the SRAM access system.

[0108] <Third Embodiment> This disclosure also provides a data access method for an SRAM storage device, such as... Figure 3 As shown, the method may include the following steps S310 to S340: Step S310: Generate a target prefetch request for the target data access device; wherein the target data access device is any one or more of a plurality of data access devices connected to the SRAM storage device, and the target prefetch request contains the device identifier of the target data access device.

[0109] In some embodiments, the cache unit is configured to perform first-in-first-out (FIFO) management of the cached data so that the data is transmitted sequentially.

[0110] In some embodiments, generating a target prefetch request for a target data access device includes: determining a predicted access address of the target data access device based on the access address of the target data access device’s historical access requests to the SRAM storage device and a prediction algorithm corresponding to the target data access device, and generating a target prefetch request based on the predicted access address.

[0111] In some embodiments, the number of times a data access device accesses an SRAM storage device within a set statistical period is obtained, the prefetch depth corresponding to the target data access device is adjusted according to the number of accesses, and a corresponding prefetch read request is generated according to the prefetch depth.

[0112] In some embodiments, the prefetch step size of the target data access device is set according to the access address of the historical access request initiated by the target data access device to the SRAM storage device, and a target prefetch read request is generated according to the prefetch step size.

[0113] In some embodiments, it is detected whether the target data access device meets the corresponding prefetch triggering condition, and if the target data access device meets the corresponding prefetch triggering condition, a target prefetch read request is generated.

[0114] In some embodiments, the prefetching triggering conditions of the target data access device include any one or more of the following: The free space of the target cache unit is greater than or equal to the corresponding space threshold; The percentage of used space in the target cache unit is less than or equal to the corresponding percentage threshold; The time interval between the current time and the last time a prefetch request was generated from the target data access device is greater than or equal to a time threshold; Received a prefetch command sent from an external source for the target data access device.

[0115] Step S320: Read the data stored in the SRAM array according to the target prefetch request.

[0116] Step S330: Based on the device identifier, the data output by the SRAM array according to the target prefetch request is routed to the target cache unit corresponding to the target data access device for caching.

[0117] Step S340: In response to the data access request sent by the target data access device, the data cached in the target cache unit that matches the data access request is returned to the target data access device.

[0118] In some embodiments, steps S320 and S340 can be executed in parallel.

[0119] In this embodiment, the data to be read by the target data access device is prefetched into the corresponding target cache unit. When the target data access device needs to read the data, the data is directly read from the corresponding cache unit. The inherent access latency of the SRAM array is transformed into a background prefetch operation that can be covered by parallel computing. This can significantly reduce the SRAM array access latency perceived by the data access device, improve the data processing efficiency of the data access device, and reduce the idle waiting time of the data access device.

[0120] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0121] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and apparatuses according to various embodiments of this specification. In this regard, each block in a flowchart or block diagram may represent a module, unit, or part of a circuit. In some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented in hardware that performs the specified function or action, or in a combination of dedicated hardware and computer instructions. It will be known to those skilled in the art that implementation in hardware, implementation in software, and implementation in a combination of software and hardware are equivalent.

[0122] Various embodiments of this specification have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or improvement of the technology in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. An SRAM storage device, characterized in that, include: SRAM arrays are used to store data; A cache array, comprising cache units corresponding to multiple data access devices; A prefetch controller is configured to generate a target prefetch request for a target data access device and send the target prefetch request to the SRAM array; wherein the target data access device is any one or more of the plurality of data access devices, and the target prefetch request contains a device identifier of the target data access device; The data routing module is used to route the data output by the SRAM array according to the target prefetch request to the target cache unit corresponding to the target data access device for caching, based on the device identifier. The cache array is also used to respond to a data access request sent by the target data access device by returning the target data cached in the target cache unit that matches the data access request to the target data access device.

2. The SRAM storage device according to claim 1, characterized in that, The cache unit is configured to perform first-in-first-out (FIFO) management of the cached data to ensure that the data is transmitted sequentially.

3. The SRAM storage device according to claim 1, characterized in that, The data input terminal of the data routing module is connected to the data output terminal of the SRAM array. The data routing module has a data output terminal corresponding to each cache unit. Each data output terminal of the data routing module is connected to the data input terminal of the corresponding cache unit. The data output terminal of the cache unit is connected to the corresponding data access device. The target cache unit is used to receive data access requests sent by the target data access device through the target connection path between the target cache unit and the target data access device, and to return the target data to the target data access device through the target connection path.

4. The SRAM storage device according to claim 1, characterized in that, The prefetch controller is used to determine the predicted access address of the target data access device based on the access address of the target data access device’s historical access requests to the SRAM storage device and the prediction algorithm corresponding to the target data access device, and to generate the target prefetch read request based on the predicted access address.

5. The SRAM storage device according to claim 1, characterized in that, The prefetch controller is used to obtain the number of times the target data access device accesses the SRAM storage device within a set statistical period, adjust the prefetch depth of the target data access device according to the number of accesses, and generate the target prefetch read request according to the prefetch depth.

6. The SRAM storage device according to claim 1, characterized in that, The prefetch controller is used to detect whether the target data access device meets the corresponding prefetch triggering condition, and generates the target prefetch read request when the target data access device meets the corresponding prefetch triggering condition.

7. The SRAM storage device according to claim 6, characterized in that, The prefetching triggering conditions of the target data access device include any one or more of the following: The free space of the target cache unit is greater than or equal to the corresponding space threshold; The percentage of used space in the target cache unit is less than or equal to the corresponding percentage threshold; The time interval between the current time and the last time a prefetch request for the target data access device was generated is greater than or equal to a time threshold; Receives a prefetch command sent from an external source for the target data access device.

8. The SRAM storage device according to claim 1, characterized in that, The prefetch controller is used to determine the prefetch step size of the target data access device based on the access address of the target data access device’s historical access requests to the SRAM storage device, and generate the target prefetch read request based on the prefetch step size.

9. An SRAM access system, characterized in that, It includes multiple data access devices and an SRAM storage device as described in any one of claims 1 to 8; the data access devices are used to access the SRAM storage device.

10. The SRAM access system according to claim 9, characterized in that, The SRAM access system also includes an on-chip network, through which the plurality of data access devices are connected to the SRAM storage device and access the SRAM storage device.

11. A data access method for an SRAM storage device, characterized in that, include: Generate a target prefetch request for a target data access device; wherein the target data access device is any one or more of a plurality of data access devices connected to the SRAM storage device, and the target prefetch request contains a device identifier of the target data access device; Read the data stored in the SRAM array according to the target prefetch request; According to the device identifier, the data output by the SRAM array based on the target prefetch request is routed to the target cache unit corresponding to the target data access device for caching; In response to a data access request sent by the target data access device, the data cached in the target cache unit that matches the data access request is returned to the target data access device.

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