FTTR-based port self-immunization method, system and device

Abstract

The application discloses a port self-immunization method, system and device based on FTTR. The method comprises the following steps: monitoring the transient interference characteristics on the differential lines of the LAN port in real time, distinguishing electrostatic discharge type, electromagnetic interference type and mixed type interference through RC circuits with different time constants; selecting corresponding terminal resistance values and common-mode choke array according to the interference type by a hardware finite state machine, and performing switching; monitoring the bit error rate of the PHY chip after switching, if the bit error rate increases, backtracking and trying other parameter combinations, if the bit error rate does not increase, maintaining until the interference disappears; and restoring the default combination after the interference disappears. The application can realize nanosecond-level response of port self-immunization without occupying CPU resources, and greatly reduces the failure rate caused by electrostatic discharge and electromagnetic interference.

Description

Technical Field

[0001] This application relates to the field of communication network technology, specifically to a port self-immunity method, system, and device based on FTTR. Background Technology

[0002] FTTR equipment extends network signals to each room via optical fiber, with its LAN port handling high-speed data connections to user terminal devices. In actual operation, the following problems arise: In dry environments, when users plug and unplug network cables, static electricity from the human body is discharged through the network port, generating common-mode spikes with amplitudes ranging from tens to hundreds of volts and widths on the nanosecond scale on the differential lines; the starting and stopping of household appliances such as microwave ovens and air conditioners generate electromagnetic pulses with frequencies ranging from several megahertz to hundreds of megahertz, which couple into the network cable, causing common-mode voltage fluctuations and differential-mode overshoot.

[0003] Existing passive hardware protection solutions involve fixing transient voltage suppressors, common-mode chokes, and ferrite beads at the front end of the LAN port. The electrical parameters of these components are fixed at the factory, and their effectiveness decreases once the electrostatic discharge intensity exceeds the design range or the electromagnetic interference spectrum changes. Furthermore, fixed parameters struggle to accommodate the interference characteristics of different scenarios, often resulting in a trade-off between protection capability and signal integrity: too much protection attenuates normal signals, while too little protection fails to block interference. Another approach is software-based intelligent early warning solutions, which predict faults by collecting time-series data such as voltage and temperature and combining it with machine learning models. However, this approach suffers from inference latency in the hundreds of milliseconds and memory consumption exceeding megabytes, making it difficult to deploy on resource-constrained FTTR control chips (such as ARM Cortex-M4, with approximately 128KB of RAM and a clock speed of around 200MHz). Moreover, the accuracy of the warnings is greatly affected by the randomness of interference, making it impossible to simultaneously reduce false alarm and false negative rates. Crucially, it can only indicate potential faults, not actively prevent them.

[0004] In terms of electrostatic discharge and electromagnetic interference protection for the LAN port of FTTR equipment, hardware solutions with fixed parameters are difficult to simultaneously suppress wide-range interference and maintain signal integrity; software early warning solutions are even less able to balance low resource consumption, real-time response, and proactive defense. Summary of the Invention

[0005] This application proposes a port self-immunity method, system, and device based on FTTR. It distinguishes the type of interference by using two RC circuits with different time constants, and then executes a reverse adjustment strategy by a hardware finite state machine. This solves the problem that existing technologies cannot simultaneously achieve nanosecond-level real-time response, zero CPU resource consumption, and adaptive interference protection.

[0006] To achieve the above objectives, this application provides a port self-immunity method based on FTTR for use in FTTR devices, comprising: real-time monitoring of the characteristics of transient interference on the differential line of a LAN port, and using a first RC circuit and a second RC circuit with different preset time constants to distinguish the interference type; the interference type includes at least electrostatic discharge interference, electromagnetic interference, and mixed interference; a hardware finite state machine selects the corresponding terminating resistor value and common-mode choke array according to the interference type and performs a switching; the common-mode choke array includes at least a first choke and a third choke, the preset inductance value of the first choke being less than the preset inductance value of the third choke; wherein, when the interference type is electrostatic discharge interference, the hardware finite state machine reduces the terminating resistor value to below the default terminating resistor value and switches the common-mode choke array to the first choke; when the interference type is electromagnetic ... If the value increases above the default terminating resistance value, the common-mode choke array is switched to the third choke. When the interference type is mixed interference, the hardware finite state machine sets the terminating resistance value to a preset intermediate value between the default terminating resistance value and the terminating resistance value under electrostatic discharge interference, and switches the common-mode choke array to a parallel connection of the first and third chokes. After switching, the bit error rate of the PHY chip is monitored. If the bit error rate increases, it reverts to the terminating resistance value and common-mode choke array used before the switch, and attempts to switch to another different set of terminating resistance values ​​and common-mode choke arrays. If all attempts at parameter combinations of terminating resistance values ​​and common-mode choke arrays fail, a hardware warning signal is issued. If the bit error rate does not increase, the current terminating resistance value and common-mode choke array are maintained. The characteristics of the transient interference are monitored. When the characteristics of the transient interference are detected to disappear, the terminating resistance and common-mode choke array are restored to the default combination.

[0007] Optionally, the first RC circuit has a first preset time constant, and the second RC circuit has a second preset time constant. The first preset time constant is smaller than the second preset time constant. The first RC circuit is sensitive to narrow pulses with a width smaller than the first preset time constant, and the second RC circuit is sensitive to wide pulses with a width greater than the second preset time constant. When the common-mode spike amplitude exceeds a preset threshold, and the first RC circuit outputs a valid pulse while the second RC circuit does not output a valid pulse, it is determined to be electrostatic discharge interference. When the differential-mode overshoot amplitude exceeds a preset threshold or the common-mode repetitive fluctuation is detected, and both the first RC circuit and the second RC circuit output valid pulses with continuous repetitive characteristics, it is determined to be electromagnetic interference. When both the first RC circuit and the second RC circuit output valid pulses, and the determination conditions for both electrostatic discharge interference and electromagnetic interference are met simultaneously, it is determined to be mixed interference.

[0008] Optionally, the common-mode choke array further includes a second choke, wherein the preset inductance value of the second choke is an intermediate value between the preset inductance value of the first choke and the preset inductance value of the third choke; when the hardware finite state machine is in a normal state, the common-mode choke array is the second choke.

[0009] Optionally, before monitoring the bit error rate of the PHY chip after switching, the method further includes setting the bit error rate of the PHY chip monitored before switching as a first bit error rate, and setting the bit error rate of the PHY chip monitored after waiting for a preset time period after switching as a second bit error rate; if the increase of the second bit error rate relative to the first bit error rate exceeds a preset threshold, it is determined that the bit error rate has increased; if the increase of the second bit error rate relative to the first bit error rate is less than or equal to the preset threshold, it is determined that the bit error rate has not increased.

[0010] Optionally, restoring the terminating resistor and common-mode choke array to the default combination after detecting the disappearance of transient interference specifically includes, within a preset time window, if no transient interference is detected, the hardware finite state machine uses a step-by-step adjustment method to restore the terminating resistor and common-mode choke array to the default combination.

[0011] This application also provides a port self-immunity system based on FTTR for FTTR devices, comprising: a common-mode choke array connected to a LAN port differential line, including at least a first choke and a third choke, wherein the inductance value of the first choke is less than the inductance value of the third choke, and the common-mode choke array further including a selection switch; a programmable terminating resistor network connected between a PHY chip and an RJ45 interface for dynamically adjusting the terminating resistance of the LAN port differential line; a transient interference detection unit connected to the LAN port differential line for detecting transient interference characteristics; the transient interference detection unit includes a first RC circuit and a second RC circuit with different preset time constants for distinguishing interference types, wherein the interference types include at least electrostatic discharge interference, electromagnetic interference, and mixed interference; and a hardware finite state machine, the input of which is connected to the transient interference detection unit, and the output of which is connected to the programmable terminating resistor network and the common-mode choke array; the hardware finite state machine is used to select the corresponding terminating resistor value and the common-mode choke array according to the interference type and perform switching; wherein, when the interference type is electrostatic discharge... When the interference type is electromagnetic interference, the terminating resistance value is reduced to below the default terminating resistance value, and the common-mode choke array is switched to the first choke. When the interference type is electromagnetic interference, the terminating resistance value is increased to above the default terminating resistance value, and the common-mode choke array is switched to the third choke. When the interference type is mixed interference, the terminating resistance value is set to a preset intermediate value between the default terminating resistance value and the terminating resistance value under electrostatic discharge interference, and the common-mode choke array is switched to a parallel connection of the first and third chokes. The hardware finite state machine also reads the bit error rate of the PHY chip through the management interface. If the bit error rate increases, it reverts to the terminating resistor value and choke coil used before the switch and attempts to switch to another set of parameters. If all attempts to switch the parameter combinations of terminating resistor values ​​and common-mode choke coil array fail, a hardware warning signal is issued. If the bit error rate does not increase, the current parameters are maintained until the characteristics of transient interference disappear. The hardware finite state machine is also used to restore the terminating resistor and common-mode choke coil array to the default combination after the transient interference detection unit detects that the characteristics of transient interference have disappeared.

[0012] Optionally, the first RC circuit has a first preset time constant, and the second RC circuit has a second preset time constant. The first preset time constant is smaller than the second preset time constant. The first RC circuit is sensitive to narrow pulses with a width smaller than the first preset time constant, and the second RC circuit is sensitive to wide pulses with a width greater than the second preset time constant. The transient interference detection unit is configured to: determine electrostatic discharge interference when the common-mode spike amplitude exceeds a preset threshold and the first RC circuit outputs a valid pulse while the second RC circuit does not output a valid pulse; determine electromagnetic interference when the differential-mode overshoot amplitude exceeds a preset threshold or the common-mode repetitive fluctuation is detected, and both the first RC circuit and the second RC circuit output valid pulses with continuous repetition; determine mixed interference when both electrostatic discharge interference and electromagnetic interference are simultaneously satisfied; the common-mode choke array further includes a second choke, the inductance value of which is between the inductance values ​​of the first choke and the third choke; when the hardware finite state machine is in a normal state, the common-mode choke array switches to the second choke.

[0013] Optionally, the hardware finite state machine is configured as follows: the bit error rate read from the PHY chip before the switch is taken as the first bit error rate, and the bit error rate read from the PHY chip after waiting for a preset time period after the switch is taken as the second bit error rate; if the increase of the second bit error rate relative to the first bit error rate exceeds a preset threshold, it is determined that the bit error rate has increased; if the increase is less than or equal to the preset threshold, it is determined that the bit error rate has not increased. The hardware finite state machine is also configured to: when no transient interference is detected within a preset time window, gradually adjust the terminating resistor and common-mode choke array to restore them to the default combination.

[0014] Optionally, the states of the hardware finite state machine include at least: a normal state, an electrostatic discharge suppression state, an electromagnetic interference suppression state, a mixed interference suppression state, and a warning state; when the transient interference detection unit identifies electrostatic discharge interference, the hardware finite state machine enters the electrostatic discharge suppression state; when the transient interference detection unit identifies electromagnetic interference, the hardware finite state machine enters the electromagnetic interference suppression state; when the transient interference detection unit simultaneously identifies both electrostatic discharge interference and electromagnetic interference, the hardware finite state machine enters the mixed interference suppression state; when the hardware finite state machine issues a hardware warning signal, the hardware finite state machine enters the warning state.

[0015] This application also provides an FTTR device, including the FTTR-based port self-immune system as described above.

[0016] The port self-immunity method, system, and device based on FTTR provided in this application have the following beneficial effects: 1. By using two RC circuits with different time constants to distinguish between narrow electrostatic discharge pulses and wide electromagnetic interference pulses, and by adding a hardware finite state machine to perform reverse regulation (reducing the resistance during electrostatic discharge and increasing the resistance during electromagnetic interference), the port can actively adapt to different interference characteristics, significantly reducing the sudden failure rate caused by electrostatic discharge and electromagnetic interference. 2. All logic is implemented by a hardware state machine, which does not consume CPU time. For example, the memory increase is within a few hundred bytes and the response time is in the hundreds of nanoseconds. Therefore, it can be deployed on resource-constrained FTTR main control chips, while meeting the real-time protection requirements at the nanosecond level. The response time values ​​mentioned here are just examples; other nanosecond-level times can achieve the same purpose. 3. By adopting a bit error rate feedback closed-loop mechanism, the PHY bit error rate is monitored after adjustment. If it deteriorates, it automatically reverts to the previous parameter combination and tries another combination. In this way, the port can correct itself when the adjustment fails. Only when all combinations fail will a hardware warning signal be issued. This reduces the software warning task from complex fault prediction to simple adjustment effectiveness monitoring, reducing the reliance on machine learning models. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic block diagram of the FTTR port autoimmune system structure used in the embodiments of this application.

[0019] Figure 2 This is a schematic diagram of the circuit principle of the switchable common-mode choke array in this application.

[0020] Figure 3 This is a schematic diagram of the circuit principle of the programmable terminating resistor network in this application.

[0021] Figure 4 This is a schematic diagram of the transient interference detection unit in this application.

[0022] Figure 5 This is a flowchart illustrating the port self-immunity method in this application. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings. The described embodiments should not be regarded as limitations on this application. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0024] Unless otherwise defined, all technical and scientific terms used in the embodiments of this application have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used in the embodiments of this application is for the purpose of describing the embodiments of this application only and is not intended to limit this application.

[0025] Before providing a further detailed description of the embodiments of this application, the nouns and terms involved in the embodiments of this application will be explained, and the nouns and terms involved in the embodiments of this application shall be interpreted as follows.

[0026] (1) In this application, the default combination refers to the terminating resistor value and common mode choke selection configured at the factory of the FTTR equipment. For example, the terminating resistor is 100 ohms and the choke is the second choke.

[0027] (2) The default terminating resistance value in this application refers to the terminating resistance value under the default combination.

[0028] (3) The management interface in this application refers to the communication interface that can access the internal registers of the PHY chip to read the bit error rate statistics, including but not limited to the MDIO interface.

[0029] (4) The nanosecond time in this application refers to a time of less than 1 microsecond, and the specific value can be less than 100 nanoseconds, such as 50 nanoseconds, 80 nanoseconds, etc.

[0030] like Figure 5 As shown in the embodiments of this application, the port self-immunity method based on FTTR is used for FTTR devices and mainly includes the following four steps.

[0031] Step A involves real-time monitoring of transient interference characteristics on the LAN port differential line, and using a first RC circuit and a second RC circuit with different preset time constants to distinguish the interference type. The interference types include at least electrostatic discharge (ESD) interference, electromagnetic interference (EMI) interference, and mixed interference. Specifically, the first RC circuit has a first preset time constant, and the second RC circuit has a second preset time constant. The first preset time constant is smaller than the second preset time constant. The first RC circuit is sensitive to narrow pulses with a width smaller than the first preset time constant, and the second RC circuit is sensitive to wide pulses with a width greater than the second preset time constant. When the common-mode spike amplitude exceeds a preset threshold, and the first RC circuit outputs a valid pulse while the second RC circuit does not output a valid pulse, it is determined to be ESD interference. When the differential-mode overshoot amplitude exceeds a preset threshold or the common-mode repetitive fluctuation is detected, and both the first RC circuit and the second RC circuit output valid pulses with continuous repetition, it is determined to be EMI interference. When the conditions for both ESD interference and EMI interference are met simultaneously, it is determined to be mixed interference. For example, if the first time constant is 10 nanoseconds and the second time constant is 100 nanoseconds, then the first RC circuit is sensitive to narrow pulses with a width less than 10 nanoseconds, and the second RC circuit is sensitive to wide pulses with a width greater than 100 nanoseconds. When the first RC circuit outputs an active signal while the second RC circuit has no output, it is determined to be electrostatic discharge interference; when both are active and the repetition frequency is higher than 1 kHz (continuous repetition characteristic), it is determined to be electromagnetic interference; when both conditions are met simultaneously, it is determined to be mixed interference.

[0032] By utilizing first and second RC circuits with different preset time constants, combined with threshold detection of common-mode spike amplitude and differential-mode overshoot amplitude, electrostatic discharge interference, electromagnetic interference, and mixed interference can be classified within nanoseconds. This classification process is entirely implemented by hardware logic, without consuming CPU time, which helps provide real-time and accurate interference type identification results for subsequent hardware finite state machines. This allows the LAN port of the FTTR device to perform differentiated parameter adjustments before interference causes permanent damage. Simultaneously, the ability of step A to determine mixed interference helps avoid the failure of a single suppression mode or frequent state switching in complex interference scenarios, improving the adaptability of the FTTR device's LAN port in multi-source interference environments.

[0033] Step B: The hardware finite state machine selects the corresponding terminating resistor value and common-mode choke array according to the interference type, and performs the switching within nanoseconds. The common-mode choke array includes at least a first choke and a third choke, wherein the preset inductance value of the first choke is smaller than the preset inductance value of the third choke; wherein: When the interference type is electrostatic discharge, the hardware finite state machine reduces the terminating resistance value to below the default terminating resistance value and switches the common-mode choke array to the first choke; the first choke is used to suppress narrow electrostatic discharge pulses; When the interference type is electromagnetic interference, the hardware finite state machine will increase the terminating resistance value to a value higher than the default terminating resistance value and switch the common-mode choke array to the third choke; the third choke is used to suppress low-frequency conducted interference or broadband electromagnetic interference. When the interference type is mixed interference, the hardware finite state machine sets the terminating resistance value to a preset intermediate value between the default terminating resistance value and the terminating resistance value under electrostatic discharge interference, and switches the common-mode choke array to the parallel connection of the first choke and the third choke; the parallel connection of the two can provide balanced common-mode rejection capability over a wide frequency range.

[0034] Furthermore, the common-mode choke array also includes a second choke, the preset inductance value of which is an intermediate value between the preset inductance value of the first choke and the preset inductance value of the third choke. When the hardware finite state machine is in a normal state (e.g., no interference, restoration to the default combination after interference disappears, regression to the default combination after adjustment failure, or warning lock), the common-mode choke array is the second choke.

[0035] The hardware finite state machine is implemented using combinational logic and registers, without involving the execution of software instructions. The aforementioned switching action is completed during the duration of the interference pulse, enabling the adjustment of protection parameters before the interference causes permanent damage, and achieving differentiated reverse adjustment for different types of interference.

[0036] By utilizing the response of a hardware finite state machine (typically on the nanosecond level), parameter switching is ensured to be completed before electrostatic discharge or electromagnetic interference surges reach the sensitive nodes of the PHY chip, preventing communication interruption due to transient overvoltage or signal degradation. The reverse adjustment strategy (electrostatic discharge resistance reduction, electromagnetic interference resistance increase) breaks through the traditional protection approach of increasing impedance to limit current, while optimizing energy dissipation and signal integrity. Multi-stage choke switching and parallel configuration enable the port to achieve targeted common-mode suppression in narrow pulse, wideband conducted, and mixed interference scenarios, expanding the spectrum coverage of adaptive protection.

[0037] The following example illustrates this process using a default terminating resistor value of 100 ohms, a preset inductance value of 10 to 20 microhenries for the first choke, a preset inductance value of 50 to 80 microhenries for the second choke, and an inductance value of 150 to 250 microhenries for the third choke. When the interference type is electrostatic discharge (ESD), the hardware finite state machine outputs a control word that reduces the resistance value of the programmable terminating resistor network to below the default terminating resistor value (e.g., from the default 100 ohms to 85 ohms) and switches the common-mode choke array to the first choke (e.g., using an inductance value of 15 microhenries). When the interference type is electromagnetic interference (EMI), the hardware finite state machine increases the terminating resistor value to above the default terminating resistor value (e.g., to 110 ohms) and switches the common-mode choke array to the third choke (e.g., using an inductance value of 200 microhenries). When the interference type is mixed interference, the hardware finite state machine enters a mixed interference suppression state and switches the common-mode choke array to a parallel connection between the first and third chokes. For example, the first choke coil is 15 microhenries, the third choke coil is 200 microhenries, and the equivalent inductance after parallel connection is approximately 14 microhenries (calculation formula: 15 × 200 ÷ (15 + 200) = 3000 ÷ 215 ≈ 13.95 μH). The equivalent inductance after parallel connection is lower than the inductance of the first choke coil alone, but it still maintains high-frequency suppression characteristics. At the same time, due to the addition of the third choke coil, it also provides a certain common-mode attenuation capability in the low-frequency range. This parallel configuration enables the common-mode choke coil array to provide a balanced suppression effect over a wide frequency range under mixed interference types. The switching action is completed during the duration of the interference pulse. In actual implementation, the time from detection to completion of switching is usually less than 100 nanoseconds, and sometimes even less than 50 nanoseconds.

[0038] Step C: Monitor the bit error rate (BER) of the PHY chip after the switch. If the BER increases, i.e., the CRC error frame count or spurious carrier event count recorded by the PHY chip increases compared to before the switch, then revert to the terminating resistor value and common-mode choke array used before the switch (parameter combination before the switch), and attempt to switch to another set of terminating resistor values ​​and common-mode choke arrays (another set of parameter combinations). If all attempts with different terminating resistor values ​​and common-mode choke array parameter combinations (including but not limited to parameter combinations corresponding to electrostatic discharge interference, electromagnetic interference, and mixed interference) fail, a hardware warning signal is issued. If the BER does not increase (i.e., remains unchanged or decreases), then maintain the current terminating resistor value and common-mode choke array (current parameter combination). The purpose of this step is to verify the adjustment effect and automatically correct it in case of failure.

[0039] Specifically, the hardware finite state machine reads the bit error rate (BER) statistics register of the PHY chip through a management interface (e.g., the MDIO interface), including a spurious carrier event counter and a cyclic redundancy check (CRC) error frame counter. Before switching, it reads the first BER; after switching, it waits for a preset time period (e.g., 10 milliseconds) and then reads the second BER. If the increase in the second BER relative to the first BER exceeds a preset threshold (e.g., 5 frames), it is determined that the BER has increased. The hardware finite state machine first restores the parameters to the combination before switching, and then selects another set of parameter combinations that have not yet been tried based on the current interference type for switching. If the increase does not exceed the preset threshold, it is determined that the BER has not increased, the current combination is maintained, and a timer is started to wait for the interference to disappear.

[0040] By employing a bit error rate feedback loop, adaptive verification of the adjustment effect is achieved, preventing port performance degradation due to improper parameters. When adjustment fails, it automatically rolls back and attempts alternative solutions, triggering a hardware warning only after all combinations fail, helping to minimize CPU intervention frequency. Furthermore, this feedback mechanism is entirely implemented by a hardware state machine, generating no software interrupts and maintaining the overall advantage of nanosecond-level response.

[0041] Step D: Continue monitoring the characteristics of the transient interference. Once the transient interference characteristics disappear, restore the terminating resistor and common-mode choke array to their default combination, thereby restoring the nominal performance of the LAN port after the interference is eliminated. The hardware finite state machine continuously receives the output signal from the transient interference detection unit. When no transient interference characteristics are detected within a preset time window (e.g., after a timer expires and there is no new trigger signal), the hardware finite state machine uses a step-by-step adjustment method to restore the terminating resistor and common-mode choke to their default combination, for example, adjusting the resistance by 2 ohms every 10 milliseconds to avoid signal reflection caused by parameter abrupt changes.

[0042] Through a gradual recovery mechanism, signal reflection and eye diagram closure caused by parameter abrupt changes are avoided, ensuring that the LAN port smoothly transitions to normal operation after interference disappears without manual intervention. In steps A through D, step A's pulse width classification via dual RC circuits enables step B to execute differentiated reverse adjustment strategies (electrostatic discharge resistance reduction, electromagnetic interference resistance increase); step C's bit error rate feedback allows the adjustment parameters in step B to be verified and corrected; and step D's automatic recovery ensures the LAN port returns to normal operation without manual intervention after interference disappears. If any feature is missing, such as the dual RC circuit differentiation in step A, nanosecond-level interference type identification cannot be achieved; if the bit error rate feedback in step C is missing, automatic reverting in case of adjustment failure is impossible, potentially causing the LAN port to operate under unsuitable parameter combinations for extended periods, thus increasing the bit error rate.

[0043] This application also provides a port self-immunity system based on FTTR for FTTR devices, such as... Figure 1 As shown, it includes a common-mode choke array, a programmable terminating resistor network, a transient interference detection unit, and a hardware finite state machine.

[0044] The common-mode choke array is connected to the LAN port differential line and includes at least a first choke and a third choke. The inductance value of the first choke is less than that of the third choke. The common-mode choke array also includes a selection switch. Preferably, the first RC circuit has a first preset time constant, and the second RC circuit has a second preset time constant. The first preset time constant is smaller than the second preset time constant. The first RC circuit is sensitive to narrow pulses with a width smaller than the first preset time constant, and the second RC circuit is sensitive to wide pulses with a width greater than the second preset time constant. The transient interference detection unit is configured to: determine electrostatic discharge interference when the common-mode spike amplitude exceeds a preset threshold and the first RC circuit outputs a valid pulse while the second RC circuit does not output a valid pulse; determine electromagnetic interference when the differential-mode overshoot amplitude exceeds a preset threshold or the common-mode repetitive fluctuation is detected, and both the first RC circuit and the second RC circuit output valid pulses with continuous repetition; determine mixed interference when both electrostatic discharge interference and electromagnetic interference are simultaneously satisfied; the common-mode choke array further includes a second choke, the inductance value of which is between the inductance values ​​of the first choke and the third choke; when the hardware finite state machine is in a normal state, the common-mode choke array switches to the second choke.

[0045] like Figure 2 As shown, the common-mode choke array includes a first choke, a second choke, a third choke, a first selection switch, a second selection switch, a third selection switch, and a selection signal line from the hardware finite state machine. The differential signal from the PHY side is connected to the RJ45 side after passing through the selection switch to the corresponding choke. By default, the second selection switch is closed, and the first and third selection switches are open. The hardware finite state machine controls the on / off state of each selection switch through the selection signal line to connect the corresponding choke to the differential path or achieve parallel connection according to the interference type.

[0046] A programmable terminating resistor network is connected in series between the PHY chip of the FTTR device's main control chip and the RJ45 interface to dynamically adjust the terminating resistors of the LAN port differential lines. For example... Figure 3As shown, the programmable terminating resistor network includes a fixed base resistor and multiple parallel fine-tuning resistor branches. Each fine-tuning resistor branch consists of a switch and a fine-tuning resistor connected in series. Switch 1 and fine-tuning resistor 1 are connected in series to form the first fine-tuning resistor branch; switch 2 and fine-tuning resistor 2 are connected in series to form the second fine-tuning resistor branch; switch 3 and fine-tuning resistor 3 are connected in series to form the third fine-tuning resistor branch; and switch 4 and fine-tuning resistor 4 are connected in series to form the fourth fine-tuning resistor branch. The LAN port differential line is led out from the PHY side, passes through this network, and connects to the RJ45 side. The hardware finite state machine controls the on / off state of each switch through resistor control codes, thereby selecting different fine-tuning resistor branches to be connected or disconnected. When a switch is closed, the corresponding fine-tuning resistor is connected in parallel with the fixed base resistor, and the total resistance value decreases accordingly; when the switch is open, the fine-tuning resistor branch is removed from the network. By controlling the number of connected fine-tuning resistors, the total resistance can be adjusted in steps within a preset range. The resistance control code is directly output by the hardware finite state machine without software decoding, ensuring that the resistance value is switched within nanoseconds.

[0047] A transient interference detection unit is connected to the LAN port differential line to detect the characteristics of transient interference. The transient interference detection unit includes a first RC circuit and a second RC circuit with different preset time constants to distinguish interference types, which at least include electrostatic discharge interference, electromagnetic interference, and mixed interference. In such cases... Figure 4 In one specific embodiment, the transient interference detection unit includes common-mode voltage extraction resistors (R1 and R2), a high-speed comparator, a programmable threshold voltage source, a first RC circuit, a second RC circuit, a differential-mode overshoot detection circuit, and a pulse classification logic gate. The LAN port differential lines are connected to the common-mode voltage extraction resistors, and the extracted common-mode voltage is compared with the programmable threshold voltage source by the high-speed comparator. The comparator's output is simultaneously fed into the first RC circuit and the second RC circuit, which have different time constants. The first RC circuit is sensitive to narrow pulses, while the second RC circuit is sensitive to wide pulses. The differential-mode overshoot detection circuit directly extracts the differential-mode overshoot signal from the differential lines. Based on the outputs of the first RC circuit, the second RC circuit, and the differential-mode overshoot detection circuit, the pulse classification logic gate comprehensively determines the interference type (electrostatic discharge, electromagnetic interference, or mixed type) and outputs the corresponding interference type identification signal to the hardware finite state machine.

[0048] The input of the hardware finite state machine is connected to the transient interference detection unit, and its output is connected to the programmable terminating resistor network and the common-mode choke array. The hardware finite state machine is used to select the corresponding terminating resistor value and common-mode choke array according to the interference type and perform switching; wherein: When the interference type is electrostatic discharge interference, the terminating resistance value is reduced to below the default terminating resistance value, and the common mode choke array is switched to the first choke. When the interference type is electromagnetic interference, the terminating resistance value is increased to a value higher than the default terminating resistance value, and the common mode choke array is switched to the third choke. When the interference type is mixed interference, the terminating resistance value is set to a preset intermediate value between the default terminating resistance value and the terminating resistance value under electrostatic discharge interference, and the common mode choke array is switched to the parallel connection of the first choke and the third choke.

[0049] The hardware finite state machine also reads the bit error rate (BER) of the PHY chip through the PHY chip's management interface. If the BER increases, it reverts to the terminating resistor and choke values ​​used before the switch and attempts to switch to another set of parameters. If all attempts at different terminating resistor and common-mode choke array parameter combinations fail, a hardware warning signal is issued. If the BER does not increase, the current parameters are maintained until the transient interference characteristics disappear. Furthermore, when the transient interference detection unit detects the disappearance of transient interference characteristics, the hardware finite state machine restores the terminating resistor and common-mode choke array to the default combination.

[0050] This application's system achieves a closed-loop end-to-end system for interference detection, type differentiation, parameter selection, switching execution, bit error rate feedback, parameter backoff, and recovery through a hardware finite state machine. The transient interference detection unit, programmable terminating resistor network, common-mode choke array, and hardware finite state machine work together: the transient interference detection unit converts interference characteristics into digital signals and differentiates between electrostatic discharge (ESD), electromagnetic interference (EMI), and mixed interference; the hardware finite state machine selects the corresponding resistor value and choke combination based on this signal, performing reverse adjustment (reducing resistance for ESD and switching to the first choke, increasing resistance for EMI and switching to the third choke, and taking the intermediate resistance value for mixed interference and connecting the first and third chokes in parallel); the management interface provides bit error rate feedback for closed-loop verification. If any module is missing, such as the lack of a parallel choke configuration for mixed interference, balanced suppression under dual interference cannot be provided; if the bit error rate backoff mechanism is missing, it may operate with an unsuitable parameter combination for an extended period when adjustment fails. This design enables the LAN port to autonomously complete a full-type immune response from narrow pulse ESD to broadband conduction of EMI without CPU intervention. Through a closed-loop hardware system, the system of this application significantly reduces interference response time without consuming CPU resources; the combination of multi-level parallel chokes and reverse resistor adjustment covers the full spectrum of interference from narrow pulses to wideband conduction, which helps to significantly reduce the failure rate of LAN ports caused by ESD / EMI.

[0051] like Figure 4As shown, the time constants of the first RC circuit and the second RC circuit are set to 10 nanoseconds and 100 nanoseconds, respectively. The first RC circuit produces an effective output for narrow electrostatic discharge pulses with a width of less than 10 nanoseconds; the second RC circuit produces an effective output for wide electromagnetic interference pulses with a width of more than 100 nanoseconds. When the first RC circuit outputs an effective signal but the second RC circuit has no output, it is determined to be electrostatic discharge interference; when both outputs are effective and the repetition frequency is higher than 1 kHz, it is determined to be electromagnetic interference; when both outputs are effective and both of the above conditions are met, it is determined to be mixed interference. This classification method does not require an analog-to-digital converter and is implemented entirely by hardware comparators and logic gates, with a delay of less than 10 nanoseconds. In addition, the common-mode choke array includes a first choke, a second choke, and a third choke. The inductance value of the second choke (e.g., 65 microhenries) is between that of the first choke (e.g., 15 microhenries) and the third choke (e.g., 200 microhenries). Under normal conditions, the hardware finite state machine switches the selector switch to the second choke to provide basic common-mode rejection that is suitable for most home environments. Nanosecond-level classification of interference types is achieved by utilizing the physical differences in pulse width, and a wide spectral range from high-frequency narrow pulses to low-frequency conduction is covered by stepped inductance values.

[0052] Preferably, the hardware finite state machine is configured to: use the bit error rate (BER) of the PHY chip read before the switch as the first BER, and use the BER of the PHY chip read after waiting for a preset time period as the second BER; if the increase of the second BER relative to the first BER exceeds a preset threshold, it is determined that the BER has increased; if the increase is less than or equal to the preset threshold, it is determined that the BER has not increased; the hardware finite state machine is further configured to: when no transient interference characteristics are detected within a preset time window, use a gradual adjustment method to restore the terminating resistor and common-mode choke array to the default combination.

[0053] Specifically, the hardware finite state machine reads the PHY's CRC error counter through the MDIO interface. The preset time period is set to 10 milliseconds, and the preset threshold is 5 error frames. If the error frame count within 10 milliseconds after the switch minus the error frame count within 10 milliseconds before the switch is greater than 5, the bit error rate is determined to have increased. The state machine then performs a rollback and tries another set of parameters (e.g., rolling back from the electrostatic discharge suppression state to the default state and then trying the electromagnetic interference suppression state). If the increase is less than or equal to 5, the bit error rate is determined not to have increased, and the current parameters are maintained. After the interference disappears, the state machine waits for a preset time window (e.g., determined by a timer). If no new triggers occur within the window, gradual recovery begins: the terminating resistor is adjusted by 2 ohms every 10 milliseconds, and the choke is switched back to the second choke using the default combination. This design uses quantified bit error rate changes as an objective criterion for adjustment effectiveness and avoids signal reflection during the recovery process through a gradual approach.

[0054] Preferably, the states of the hardware finite state machine include at least: a normal state, an electrostatic discharge suppression state, an electromagnetic interference suppression state, a mixed interference suppression state, and a warning state; when the transient interference detection unit identifies electrostatic discharge interference, the hardware finite state machine enters the electrostatic discharge suppression state; when the transient interference detection unit identifies electromagnetic interference, the hardware finite state machine enters the electromagnetic interference suppression state; when the transient interference detection unit simultaneously identifies electrostatic discharge interference and electromagnetic interference, the hardware finite state machine enters the mixed interference suppression state; when the hardware finite state machine issues a hardware warning signal, the hardware finite state machine enters the warning state, at which time the hardware finite state machine locks the default combination and generates a hardware interrupt.

[0055] Preferably, the five states of the hardware finite state machine are S0 (normal state), S1 (electrostatic discharge suppression state), S2 (electromagnetic interference suppression state), S3 (mixed interference suppression state), and S4 (warning state). From S0, if an electrostatic discharge trigger signal is received, it transitions to S1; if an electromagnetic interference trigger signal is received, it transitions to S2; if both are received simultaneously, it transitions to S3. In S1, if electromagnetic interference characteristics are detected simultaneously, it escalates to S3; in S2, if electrostatic discharge characteristics are detected simultaneously, it escalates to S3. Each suppression state has a timer (100 milliseconds for S1, 1 second for S2, and 500 milliseconds for S3). If no new trigger occurs after the timeout, it returns to S0. When the hardware finite state machine attempts to switch parameter combinations in S1, S2, or S3, it reads the PHY bit error rate through the management interface. If all possible parameter combinations result in an increased bit error rate, the state machine transitions to S4 (warning state), sets the warning register, and generates a hardware interrupt signal to notify the CPU to perform software-level fault handling. In state S4, the programmable terminating resistor network and common-mode choke array are locked to the default combination, no longer responding to the characteristic trigger signals of transient interference, until the CPU writes a clear instruction and the state machine returns to state S0. This design achieves a one-to-one mapping between interference types and suppression states, avoiding parameter selection errors caused by state ambiguity, providing dedicated suppression configurations for mixed interference, and outputting an early warning when hardware adaptive adjustment fails completely, thus reducing upper-level software tasks to simple early warning responses.

[0056] This application also provides an FTTR device, including the FTTR-based port self-immunity system described above. This device integrates the aforementioned system into the LAN port path of the FTTR device, located between the PHY and RJ45 interface of the main control chip. This allows existing FTTR devices to acquire port self-immunity capabilities without modifying the upper-layer software; only low-cost components such as the programmable terminating resistor network, common-mode choke array, transient interference detection unit, and hardware finite state machine need to be added to the printed circuit board.

[0057] The technical solution of this application will be clearly and completely described below with reference to the accompanying drawings and specific embodiments. In actual deployment, the appropriate solution can be selected according to the network topology. The described embodiments are only some embodiments of this application, and not all embodiments.

[0058] like Figure 1 As shown, Embodiment 1 of this application provides a port self-immunity system based on FTTR, including a common-mode choke array, a programmable terminating resistor network, a transient interference detection unit, and a hardware finite state machine. The common-mode choke array includes a first choke (inductance value, for example, 15 microhenries, selectable within the range of 10 to 20 microhenries), a second choke (inductance value, for example, 65 microhenries, selectable within the range of 50 to 80 microhenries), and a third choke (inductance value, for example, 200 microhenries, selectable within the range of 150 to 250 microhenries). Each set of chokes is connected to the LAN port differential line via an analog switch with low on-resistance (e.g., less than 5 ohms). The total resistance adjustment range of the programmable terminating resistor network is, for example, 80 ohms to 120 ohms, with a step size, for example, 2 ohms (other step sizes such as 1 ohm or 4 ohms can also be selected). The transient interference detection unit includes a first RC circuit (time constant, for example, 10 nanoseconds), a second RC circuit (time constant, for example, 100 nanoseconds), and two high-speed comparators. The hardware finite state machine is implemented using combinational logic and registers, containing five states (S0, S1, S2, S3, S4) and three timers (e.g., T1 = 100 milliseconds, T2 = 1 second, T3 = 500 milliseconds). The hardware finite state machine is connected to the PHY chip's management bus via the MDIO interface, and reads the cyclic redundancy check (CRC) error counter every 10 milliseconds.

[0059] The complete workflow of this embodiment is as follows: In normal state S0, the terminating resistor is at its default value (e.g., 100 ohms), and the common-mode choke array selects the second choke. When the transient interference detection unit detects that the common-mode spike amplitude exceeds a preset threshold (e.g., 50 volts, which can be adjusted according to the PHY chip's tolerance capability), and the first RC circuit output is valid while the second RC circuit is invalid, it is determined to be electrostatic discharge interference. The hardware finite state machine switches from S0 to S1 within a nanosecond time (e.g., 50 nanoseconds): the control word of the programmable terminating resistor network is adjusted to a resistor corresponding to a value lower than the default value (e.g., 85 ohms), and the analog switch is switched to the first choke. The purpose of this adjustment is to utilize the reduced terminating resistor to shunt electrostatic discharge energy and to utilize the high-frequency suppression characteristics of the first choke to attenuate narrow pulses. After the switch, the state machine waits for a preset time period (e.g., 10 milliseconds), reads the PHY's error counter through the MDIO interface as the second bit error rate, and compares it with the first bit error rate read before the switch. If the increase does not exceed a preset threshold (e.g., 5 frames), the bit error rate is determined not to have increased, and S1 is maintained until T1 times out. If the increase exceeds the preset threshold, the bit error rate is determined to have increased, and the state immediately reverts to S0 (restoring the default resistor and second choke), then attempts to enter S2 (electromagnetic interference suppression state). If S2 also causes the bit error rate to increase, the state machine continues to try S3 (mixed interference suppression state). If S3 still causes the bit error rate to increase, it is determined that all possible parameter combinations have failed, and the state machine transitions to S4 (warning state), setting the warning register and pulling the hardware interrupt line high. In S4, the programmable terminating resistor network and common-mode choke array are locked to the default combination (e.g., 100 ohms, second choke), and no longer respond to transient interference trigger signals until the CPU writes a clear instruction through the management interface, after which the state machine returns to S0.

[0060] When the transient interference detection unit simultaneously identifies both electrostatic discharge (ESD) and electromagnetic interference (EMI) (e.g., both the first and second RC circuits output valid pulses and simultaneously meet both judgment conditions), the state machine enters state S3 (mixed interference suppression state), sets the terminating resistor to an intermediate value between the default value and the ESD suppression value (e.g., 90 ohms), and simultaneously connects the first and third chokes (in parallel). In state S3, a bit error rate monitoring and fallback mechanism is also executed: if the bit error rate increases after switching to the parallel configuration, it falls back to state S0 and attempts S1 and S2 sequentially; if all fail, it also transitions to state S4.

[0061] When the interference disappears and the corresponding timer expires, if the state machine is in state S1, S2, or S3 and no warning is triggered, a gradual adjustment method (e.g., adjusting by 2 ohms every 10 milliseconds) is used to gradually restore the terminating resistor to its default value, and the choke is switched back to the second choke, then the process returns to S0. All logic in the above process is implemented in hardware, without consuming CPU time, and the memory increase is less than 100 bytes. The CPU is only awakened when it receives a hardware interrupt S4, reads the warning register to determine if the adaptive adjustment has completely failed (e.g., PHY aging), and reports to the cloud platform to notify operations and maintenance. The purpose of this design is to enable the FTTR device's LAN port to autonomously cope with electrostatic discharge, electromagnetic interference, and mixed interference, requiring software intervention only when the hardware adaptive capability is exhausted, thus downgrading the warning task from complex fault prediction to simple adjustment effectiveness monitoring.

[0062] It should be noted that the specific values ​​listed in this embodiment (such as inductance value, resistance value, time constant, threshold, timer duration, etc.) are only illustrative examples. Those skilled in the art can select other equivalent values ​​according to the actual application scenario (such as the electrical specifications of different PHY chips, the intensity and spectrum distribution of different interference sources), which will not affect the implementation of the technical solution of this application.

[0063] This application also provides Embodiment Two. The main difference from Embodiment One lies in the implementation of the programmable terminating resistor network. The programmable terminating resistor network uses a digital potentiometer chip (e.g., a 7-bit digital potentiometer with non-volatile memory, a resistance range of 80 ohms to 120 ohms, and a step resolution of less than 1 ohm) instead of a metal-oxide-semiconductor field-effect transistor switching array. A hardware finite state machine writes control words to the digital potentiometer via an I2C bus or serial peripheral interface to adjust the terminating resistor. This implementation has high digital potentiometer integration and simple peripheral circuitry, but the adjustment speed is slightly slower (typical switching time is 1 microsecond to 5 microseconds), still much faster than software warning schemes (millisecond level), and is suitable for scenarios where switching speed requirements are not extremely stringent. The implementation of other modules (common-mode choke array, transient interference detection unit, hardware finite state machine) is the same as in Embodiment One. This embodiment provides an alternative with higher component integration to reduce printed circuit board area.

[0064] Example 3 provides a simplified port self-immunity system based on FTTR, containing only the essential features defined in claim 6: a common-mode choke array, a programmable terminating resistor network, a transient interference detection unit, and a hardware finite state machine. The hardware finite state machine reads the PHY bit error rate through a management interface and determines whether to maintain, roll back, or switch parameter combinations based on the bit error rate. In this example, the programmable terminating resistor network supports only two levels of adjustment (e.g., a default of 100 ohms and an electrostatic discharge suppression state of 85 ohms); the common-mode choke array contains only two chokes (e.g., a first choke of 15 microhenries and a second choke of 65 microhenries); the transient interference detection unit distinguishes between electrostatic discharge and electromagnetic interference using only two RC circuits (it does not handle mixed interference separately, prioritizing electrostatic discharge when mixed); the hardware finite state machine contains only three states (normal, electrostatic discharge suppression, and electromagnetic interference suppression), and the recovery process directly jumps back to the default combination (without gradual adjustment). The purpose of this simplified solution is to achieve basic port self-immunity capabilities with the lowest hardware cost, suitable for product models that are extremely cost-sensitive and have relatively simple interference scenarios.

[0065] As can be seen from the above, this application has at least the following technical effects: (1) By using a transient interference detection unit with two RC circuits of different time constants to distinguish between narrow electrostatic discharge pulses and wide electromagnetic interference pulses in real time, and by using a hardware finite state machine to execute a reverse adjustment strategy (reducing the terminal resistance to below the default value during electrostatic discharge and increasing the terminal resistance to above the default value during electromagnetic interference), this application can complete parameter switching during the duration of the interference pulse, so that the LAN port can actively adapt to different interference characteristics, which helps to significantly reduce the sudden failure rate caused by electrostatic discharge and electromagnetic interference. (2) All the logic of this application (including interference detection, type differentiation, parameter selection, switching execution, bit error rate reading, backoff judgment, parameter recovery, and early warning generation) is implemented by a hardware finite state machine and combinational logic circuits. It does not rely on the CPU to execute software instructions and occupies very little memory. Therefore, it can be deployed on resource-constrained FTTR main control chips, and at the same time, it can achieve a real-time response at the nanosecond level from the occurrence of interference to the completion of adjustment. This response time is much faster than the duration of the electrostatic discharge pulse itself, and can complete the protection before the interference causes permanent damage. (3) The hardware finite state machine reads the bit error rate statistics (including CRC error frame count and spurious carrier event count) of the PHY chip through the management interface, and compares the bit error rate changes before and after the adjustment: if the bit error rate increases, it reverts to the parameter combination before the switch and tries another set of parameter combinations; if the bit error rate does not increase, it maintains the current combination until the interference disappears; a hardware warning signal is issued only when all parameter combinations cause the bit error rate to increase. This mechanism reduces the task of the upper-layer software from fault prediction to adjustment effectiveness monitoring, so that the FTTR device can achieve port fault management without deploying complex machine learning models; (4) The programmable terminating resistor network uses a fixed base resistor and multiple parallel switches to control the fine-tuning resistor, which can achieve fine step adjustment; the common-mode choke array includes a first choke, a second choke, and a third choke, with their inductance values ​​increasing sequentially. This application can reduce the terminating resistance to shunt transient energy during electrostatic discharge and increase the terminating resistance to increase signal swing margin during electromagnetic interference. At the same time, it selects the corresponding choke according to the interference spectrum (the first choke is selected for narrow pulses, the second choke for intermediate frequency electromagnetic interference, the third choke for low frequency conduction, and the first and third chokes are connected in parallel for mixed interference), thereby providing targeted common-mode suppression in a wide frequency range, which helps to avoid the contradiction between protection strength and signal integrity in fixed parameter schemes; (5) The hardware finite state machine includes multiple timers (with different durations corresponding to different suppression states) and a gradual recovery mechanism. This application can maintain the protection parameters during the duration of interference, and restore the default combination after the interference disappears. During the recovery process, the resistance value changes gradually, which helps to avoid signal reflection and eye diagram closure caused by parameter abrupt changes, and realizes a seamless and smooth transition of the LAN port state; (6) The hardware finite state machine includes a normal state, an electrostatic discharge suppression state, an electromagnetic interference suppression state, and a mixed interference suppression state. When the transient interference detection unit simultaneously identifies two types of interference, it enters the mixed interference suppression state (the terminating resistor is set to an intermediate value between the default value and the electrostatic discharge suppression value, and is connected in parallel to the first choke coil and the third choke coil). This application can cope with complex interference scenarios where electrostatic discharge and broadband electromagnetic interference coexist, avoid parameter oscillations caused by frequent switching between two single suppression states, and enable the LAN port to maintain a low bit error rate under dual interference.

[0066] The above descriptions are merely embodiments of this application. Commonly known technical solutions or characteristics are not described in detail here. It should be noted that those skilled in the art can make various modifications and improvements without departing from the technical solution of this application. These modifications and improvements should also be considered within the scope of protection of this application, and will not affect the effectiveness of the application or the practicality of the patent. The scope of protection claimed in this application should be determined by the content of its claims, and the specific embodiments described in the specification can be used to interpret the content of the claims.

Claims

1. A port self-immunity method based on FTTR, characterized in that, For FTTR devices, including: The characteristics of transient interference on the differential line of the LAN port are monitored in real time, and the interference types are distinguished by using a first RC circuit and a second RC circuit with different preset time constants; the interference types include at least electrostatic discharge interference, electromagnetic interference, and mixed interference. A hardware finite state machine selects the corresponding terminating resistor value and common-mode choke array based on the interference type and performs the switching. The common-mode choke array includes at least a first choke and a third choke, with the preset inductance value of the first choke being less than the preset inductance value of the third choke. Specifically, when the interference type is electrostatic discharge interference, the hardware finite state machine reduces the terminating resistor value to below the default terminating resistor value and switches the common-mode choke array to the first choke. When the interference type is electromagnetic interference, the hardware finite state machine increases the terminating resistor value to above the default terminating resistor value and switches the common-mode choke array to the third choke. When the interference type is mixed interference, the hardware finite state machine sets the terminating resistor value to a preset intermediate value between the default terminating resistor value and the terminating resistor value under electrostatic discharge interference, and switches the common-mode choke array to a configuration where the first and third chokes are connected in parallel. After switching, monitor the bit error rate of the PHY chip. If the bit error rate increases, revert to the terminating resistor value and common-mode choke array used before the switch, and attempt to switch to another set of different terminating resistor values ​​and common-mode choke arrays. If all attempts to combine terminating resistor values ​​and common-mode choke array parameters fail, a hardware warning signal is issued. If the bit error rate does not increase, maintain the current terminating resistor value and common-mode choke array. Continue monitoring the characteristics of the transient interference. Once the characteristics of the transient interference disappear, restore the terminating resistor and common-mode choke array to the default combination.

2. The method according to claim 1, characterized in that, include: The first RC circuit has a first preset time constant, and the second RC circuit has a second preset time constant. The first preset time constant is smaller than the second preset time constant. The first RC circuit is sensitive to narrow pulses with a width smaller than the first preset time constant, and the second RC circuit is sensitive to wide pulses with a width greater than the second preset time constant. When the common-mode spike amplitude exceeds a preset threshold, and the first RC circuit outputs a valid pulse while the second RC circuit does not output a valid pulse, it is determined to be electrostatic discharge interference. When the differential-mode overshoot amplitude exceeds a preset threshold or the common-mode repetitive fluctuation is detected, and both the first RC circuit and the second RC circuit output valid pulses with continuous repetitive characteristics, it is determined to be electromagnetic interference. When the determination conditions for both electrostatic discharge interference and electromagnetic interference are met simultaneously, it is determined to be mixed interference.

3. The method according to claim 1, characterized in that, include: The common-mode choke array further includes a second choke, wherein the preset inductance value of the second choke is an intermediate value between the preset inductance value of the first choke and the preset inductance value of the third choke. When the hardware finite state machine is in the normal state, the common-mode choke array is the second choke.

4. The method according to claim 1, characterized in that, include: Before monitoring the bit error rate of the PHY chip after switching, the method further includes setting the bit error rate of the PHY chip monitored before switching as the first bit error rate, and setting the bit error rate of the PHY chip monitored after waiting for a preset time period after switching as the second bit error rate. If the increase in the second bit error rate relative to the first bit error rate exceeds a preset threshold, it is determined that the bit error rate has increased; if the increase in the second bit error rate relative to the first bit error rate is less than or equal to the preset threshold, it is determined that the bit error rate has not increased.

5. The method according to claim 1, characterized in that, include: The step of restoring the terminating resistor and common-mode choke array to the default combination after detecting the disappearance of transient interference specifically includes, within a preset time window, if no transient interference is detected, the hardware finite state machine uses a step-by-step adjustment method to restore the terminating resistor and common-mode choke array to the default combination.

6. A port-based self-immune system based on FTTR, characterized in that, For FTTR devices, including: A common-mode choke array, connected to a LAN port differential line, includes at least a first choke and a third choke, wherein the inductance value of the first choke is less than the inductance value of the third choke, and the common-mode choke array also includes a selection switch; A programmable terminating resistor network is connected between the PHY chip and the RJ45 interface to dynamically adjust the terminating resistor of the LAN port differential lines. A transient interference detection unit, connected to the LAN port differential line, is used to detect the characteristics of transient interference; the transient interference detection unit includes a first RC circuit and a second RC circuit with different preset time constants, used to distinguish the interference type, which includes at least electrostatic discharge interference, electromagnetic interference and mixed interference; A hardware finite state machine, whose input is connected to the transient interference detection unit and whose output is connected to the programmable terminating resistor network and the common-mode choke array; The hardware finite state machine is used to select the corresponding terminating resistor value and common-mode choke array according to the interference type and perform switching. Specifically, when the interference type is electrostatic discharge interference, the terminating resistor value is reduced to below the default terminating resistor value, and the common-mode choke array is switched to the first choke. When the interference type is electromagnetic interference, the terminating resistor value is increased to above the default terminating resistor value, and the common-mode choke array is switched to the third choke. When the interference type is mixed interference, the terminating resistor value is set to a preset intermediate value between the default terminating resistor value and the terminating resistor value under electrostatic discharge interference, and the common-mode choke array is switched to a parallel connection of the first and third chokes. The hardware finite state machine also reads the bit error rate of the PHY chip through the management interface. If the bit error rate increases, it will fall back to the terminating resistor value and choke coil used before the switch and try to switch to another set of parameters. If all attempts to switch the parameter combination of terminating resistor value and common mode choke coil array fail, a hardware warning signal will be issued. If the bit error rate does not increase, the current parameters will be maintained until the characteristics of transient interference disappear. The hardware finite state machine is also used to restore the terminating resistor and common-mode choke array to the default combination after the transient interference detection unit detects that the characteristics of the transient interference have disappeared.

7. The system according to claim 6, characterized in that, The first RC circuit has a first preset time constant, and the second RC circuit has a second preset time constant. The first preset time constant is smaller than the second preset time constant. The first RC circuit is sensitive to narrow pulses with a width smaller than the first preset time constant, and the second RC circuit is sensitive to wide pulses with a width greater than the second preset time constant. The transient interference detection unit is configured to: determine electrostatic discharge interference when the common-mode spike amplitude exceeds a preset threshold and the first RC circuit outputs a valid pulse while the second RC circuit does not output a valid pulse; determine electromagnetic interference when the differential-mode overshoot amplitude exceeds a preset threshold or the common-mode repetitive fluctuation is detected, and both the first RC circuit and the second RC circuit output valid pulses with continuous repetition; determine mixed interference when both electrostatic discharge interference and electromagnetic interference are simultaneously satisfied. The common-mode choke array further includes a second choke, the inductance of which is between that of the first choke and the third choke; when the hardware finite state machine is in a normal state, the common-mode choke array switches to the second choke.

8. The system according to claim 6, characterized in that, The hardware finite state machine is configured such that the bit error rate of reading the PHY chip before the switch is taken as the first bit error rate, and the bit error rate of reading the PHY chip after waiting for a preset time period after the switch is taken as the second bit error rate. If the increase in the second bit error rate relative to the first bit error rate exceeds a preset threshold, it is determined that the bit error rate has increased; if the increase is less than or equal to the preset threshold, it is determined that the bit error rate has not increased. The hardware finite state machine is also configured to: when no transient interference is detected within a preset time window, gradually adjust the terminating resistor and common-mode choke array to restore them to the default combination.

9. The system according to claim 6, characterized in that, The hardware finite state machine has at least the following states: normal state, electrostatic discharge suppression state, electromagnetic interference suppression state, mixed interference suppression state, and warning state. When the transient interference detection unit identifies electrostatic discharge interference, the hardware finite state machine enters the electrostatic discharge suppression state. When the transient interference detection unit identifies electromagnetic interference, the hardware finite state machine enters the electromagnetic interference suppression state. When the transient interference detection unit simultaneously identifies both electrostatic discharge interference and electromagnetic interference, the hardware finite state machine enters the mixed interference suppression state. When the hardware finite state machine issues a hardware warning signal, the hardware finite state machine enters the warning state.

10. An FTTR device, characterized in that, Includes the FTTR-based port self-immune system as described in any one of claims 6 to 9.

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