Cloud-native IPv6 subnet routing dynamic publishing method and system

Abstract

The present disclosure provides a cloud-native IPv6 subnet routing dynamic publishing method and system, the method comprising: obtaining a routing change event of an IPv6 subnet, determining an external network identifier associated with the routing change event, and determining a corresponding logical slot in a reference count slot pool of shared memory, the low bit of each physical slot containing a mode code and an allocation mark; analyzing the mode code to determine the current aggregation mode, and calculating the effective count bit width of the logical slot in the physical slot based on the current aggregation mode to obtain the current reference count of the logical slot in one memory access; performing an atomic increment or decrement operation on the current reference count to trigger the announcement or revocation of the corresponding route of the IPv6 subnet. The present disclosure can ensure the extremely high memory efficiency of reference count storage in the scenario of dynamic publishing of million-level IPv6 subnet routes, and meet the unlimited bit width expansion demand of extreme reference count without destroying self-containment.

Description

Technical Field

[0001] This invention belongs to the field of computer storage technology, and in particular relates to a method and system for dynamically publishing cloud-native IPv6 subnet routes. Background Technology

[0002] In a cloud-native IPv6 subnet routing dynamic publishing system based on OpenStack Neutron, the execution layer needs to maintain reference count snapshots for each GoBGP instance corresponding to an external network to determine the timing of route announcements and revocations. When the number of cloud platform tenants and the scale of IPv6 subnet routing entries reach millions or more, traditional reference counting storage solutions face significant challenges. Typically, such solutions use fixed-width slots combined with an independent hash index table. The index table records metadata such as the physical location, width, and validity of each logical counting unit. Under this architecture, as the number of snapshots surges, the index table itself consumes a large amount of shared memory. Simultaneously, the index query process involves lock contention and multiple random memory accesses, leading to increased location latency and thus blocking the route publishing pipeline. More seriously, storing the count value and metadata separately cannot guarantee atomic updates in high-concurrency route oscillation scenarios, easily causing incorrect route revocations or duplicate announcements, directly threatening network stability. Therefore, there is an urgent need for a reference counting management solution that can maintain extremely low memory overhead and nanosecond-level location latency while ensuring the atomicity of high-concurrency updates in scenarios involving millions of subnet route publishing entries. Summary of the Invention

[0003] This disclosure provides a cloud-native IPv6 subnet route dynamic publishing method and system, which improves object reuse hit rate and significantly reduces the creation of new objects while ensuring low-latency acquisition of active areas, thereby reducing garbage collection frequency and memory fragmentation. At the same time, it enables timely removal of low-value objects and avoids invalid memory occupation.

[0004] This disclosure provides a method for dynamically publishing cloud-native IPv6 subnet routes, including: Obtain the routing change event of the IPv6 subnet, determine the external network identifier associated with the routing change event, and based on the external network identifier, determine the corresponding logical slot in the reference counting slot pool of shared memory. The reference counting slot pool consists of multiple 64-bit physical slots. The low bits of each physical slot contain a self-verifying mode code and an allocation flag. The mode code indicates the aggregation mode of the logical slots within the physical slot, and the allocation flag indicates whether the physical slot has any allocated logical slots. Based on the logical identifier of the logical slot, the low bit of the physical slot where it is located is read, the mode code is parsed to determine the current aggregation mode, and the bit offset and effective count bit width of the logical slot in the physical slot are calculated based on the current aggregation mode, so as to obtain the current reference count of the logical slot in one memory access. An atomic increment / decrement operation is performed on the current reference count. Depending on whether the incremented / decremented count value changes from zero to a positive number or from a positive number to zero, an announcement or revocation of the route corresponding to the IPv6 subnet is triggered.

[0005] Optionally, the mode code includes: single-body 8-bit mode, dual-body 16-bit mode, quad-body 32-bit mode, and full-width 64-bit mode. In the full-width 64-bit mode, when the high bit of a physical slot is set as a recursive node marker, the physical slot acts as a recursive node, and its counting area is used to store the offset pointing to the next level physical slot.

[0006] Optionally, in the single 8-bit mode, the physical slot is divided into eight 8-bit logical slots. The lower two bits of each 8-bit logical slot are mode identifiers, the third bit from the lower number is an allocation marker, and the fourth to eighth bits are five valid count bits.

[0007] Optionally, when the current aggregation mode is a full-width 64-bit mode and the high-order bits are identified as the recursive node marker, parsing the mode code to determine the current aggregation mode, and calculating the bit offset and effective count bit width of the logical slot within the physical slot based on the current aggregation mode, further includes: The offset of the next level physical slot is parsed from the counting area of ​​the physical slot; The low bit of the next-level physical slot is read based on the offset to determine the next-level aggregation mode; Repeat the above parsing and offset reading process until the non-recursive physical slot is reached to obtain the final effective count bit width and actual reference count.

[0008] Optionally, the method further includes: When the count value of a logical slot in the current aggregation mode reaches the upper limit of the effective count bit width of the mode, check whether the logical slots adjacent to the logical slot in the same physical slot are free. If idle, the mode code of the physical slot is modified to the next-level aggregation mode through an atomic comparison and swap operation, and the logical slot is merged with the adjacent logical slot into a logical slot with a wider bit width. At the same time, the count value is merged and written into the merged count area.

[0009] Optionally, the method further includes: when the count value of the merged logical slot decays to below a preset ratio of the upper limit of the effective count bit width of the next-level aggregation mode, the mode code of the physical slot is restored to the previous-level aggregation mode through an atomic comparison and exchange operation, and the logical slot is split into multiple logical slots that conform to the previous-level aggregation mode, and the corresponding count value is written to each of the split logical slots.

[0010] Optionally, the method further includes: When a logical slot is in full-width 64-bit mode and the count value exceeds a preset threshold, a new physical slot is allocated in the reference count slot pool. Write the current count value into the count area of ​​the new physical slot, and set the mode code of the new physical slot to full-width 64-bit mode with the high bits not containing the recursive node marker. The mode code of the original physical slot is kept in full-width 64-bit mode, while its high bits are set as recursive node markers, and the offset of the new physical slot relative to the original physical slot is written into the counting area of ​​the original physical slot.

[0011] Optionally, triggering the announcement or revocation of the route corresponding to the IPv6 subnet further includes: If the count value changes from zero to a positive number after the increment or decrement, a BGP route advertisement message is sent to the core switch; If the count value changes from positive to zero after the increment or decrement, a BGP route cancellation message is sent to the core switch.

[0012] Optionally, the method further includes: during system initialization, setting all physical slots in the reference counting slot pool to single-unit 8-bit mode, and setting the allocation flag of each physical slot to zero.

[0013] The second aspect of this disclosure provides a cloud-native IPv6 subnet routing dynamic publishing system, including: The event acquisition module is used to acquire routing change events of IPv6 subnets, determine the external network identifier associated with the routing change event, and determine the corresponding logical slot in the reference counting slot pool of shared memory based on the external network identifier. The reference counting slot pool consists of multiple 64-bit physical slots. The low bits of each physical slot contain a self-verifying mode code and an allocation flag. The mode code indicates the aggregation mode of the logical slots in the physical slot, and the allocation flag indicates whether the physical slot has any allocated logical slots. The reference count management module is used to read the low bits of the physical slot where the logical slot is located according to the logical identifier of the logical slot, parse the mode code to determine the current aggregation mode, and calculate the bit offset and effective count bit width of the logical slot in the physical slot based on the current aggregation mode, so as to obtain the current reference count of the logical slot in one memory access. The route publishing module is used to perform atomic increment / decrement operations on the current reference count, and trigger the announcement or revocation of the route corresponding to the IPv6 subnet based on whether the count value changes from zero to a positive number or from a positive number to zero after the increment / decrement.

[0014] As can be seen from the above technical solution, by constructing a reference counting slot pool consisting of 64 physical slots, with the low bits of each slot carrying a self-verifying mode code and an allocation flag, the aggregation bit width information and validity status of logical slots are directly embedded in the data storage unit. When it is necessary to locate and update the reference count of a logical slot, it is only necessary to calculate the position of the physical slot based on the logical identifier of the logical slot. The current aggregation mode can be obtained synchronously by reading the low bits of the slot in a single memory operation, thereby completing the real-time parsing of bit offset and effective count bit width. The entire process does not require accessing any external index table. This inline encoding mechanism makes the location operation only a single memory access and a few bit operations in most cases, reducing the average location latency from hundreds of nanoseconds to less than ten nanoseconds. At the same time, since the mode code, allocation flag, and count value are located in the same atomic word, the atomic increment and decrement operations on the count value naturally cover the concurrent state switching during mode changes, ensuring strong consistency of increment, decrement, aggregation, and split operations under lock-free conditions. Ultimately, the incremented or decremented count accurately reflects the snapshot's reference status. Its change from zero to positive or from positive to zero is used to precisely trigger the announcement or revocation of the corresponding IPv6 subnet route, thereby achieving low latency, high throughput, and high reliability of dynamic route publishing in a large-scale cloud environment.

[0015] Furthermore, this disclosure introduces a recursive self-verifying expansion mechanism when aggregation within physical slots cannot meet extreme counting requirements. This mechanism allows physical slots to be transformed into recursive nodes by marking high-bit values ​​in the full-width mode indicated by the pattern code. Each node stores the offset of the next-level physical slot, thus linking multiple physical slots into a larger logical counting space. The key to this expansion method is that the recursive structure and the basic mode share the same self-verifying encoding framework. After recognizing the recursive marker, the positioning algorithm only needs to jump along the offset, ultimately completing the counting positioning within a non-recursive physical slot. At the implementation level, mode switching, aggregation splitting, and the establishment and dismantling of recursive links are all constrained within a single or ordered atomic comparison and exchange operation, without the need for additional locks or global coordination mechanisms. These technical features support each other, forming a unified self-verifying system from conventional reference counting management to extreme capacity expansion. Its overall operation and internal logic are not found in existing publicly available technologies. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a flowchart of a cloud-native IPv6 subnet routing dynamic publishing method according to an embodiment of this disclosure; Figure 2 This is a flowchart illustrating a cloud-native IPv6 subnet routing dynamic publishing method in an embodiment of this disclosure, which describes parsing the mode code to determine the current aggregation mode and calculating the bit offset and effective count bit width of the logical slot within the physical slot based on the current aggregation mode. Figure 3 This is one of the flowcharts of a cloud-native IPv6 subnet routing dynamic publishing method in this disclosure embodiment; Figure 4 This is the second flowchart of a method for dynamically publishing cloud-native IPv6 subnet routes in an embodiment of this disclosure; Figure 5 This is a flowchart illustrating the triggering of the announcement or revocation of the corresponding route for the IPv6 subnet in a cloud-native IPv6 subnet dynamic publishing method according to an embodiment of this disclosure; Figure 6 This is a schematic diagram of a cloud-native IPv6 subnet routing dynamic publishing system in an embodiment of this disclosure. Detailed Implementation

[0018] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not limiting, in order to provide a thorough understanding of the embodiments of this disclosure. However, those skilled in the art will understand that this disclosure may also be implemented in other embodiments without such specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this disclosure with unnecessary detail.

[0019] In cloud-native IPv6 subnet route dynamic deployment scenarios, traditional reference counting storage solutions have evolved along two paths. One path uses fixed-width slots, such as pre-allocating 64 bits for each reference count. While the implementation logic is straightforward, this leads to significant memory waste under millions of subnet route snapshots, as the actual reference count values ​​in many snapshots are far less than the maximum that bit width can represent. The other path attempts to compress storage through dynamic management, typically by maintaining a separate index table or metadata area outside the data area to record the bit width and location of each counting unit. While this approach improves memory utilization, it introduces indirect addressing overhead and complexity in concurrency control. In systems with stringent high concurrency and low latency requirements, such as route deployment, latency jitter and lock contention from index queries are unacceptable. Furthermore, separating metadata updates from count values ​​introduces the risk of inconsistent state, potentially leading to false route announcements or revocations.

[0020] In view of this, this disclosure provides a method for dynamically publishing cloud-native IPv6 subnet routes, such as... Figure 1 As shown, it includes: Step S100: Obtain the routing change event of the IPv6 subnet, determine the external network identifier associated with the routing change event, and determine the corresponding logical slot in the reference counting slot pool of shared memory based on the external network identifier. The reference counting slot pool consists of multiple 64-bit physical slots. The low bits of each physical slot contain a self-verifying mode code and an allocation flag. The mode code indicates the aggregation mode of the logical slots in the physical slot, and the allocation flag indicates whether the physical slot has an allocated logical slot. Step S200: Based on the logical identifier of the logical slot, read the low bit of the physical slot where it is located, parse the mode code to determine the current aggregation mode, and calculate the bit offset and effective count bit width of the logical slot in the physical slot based on the current aggregation mode, so as to obtain the current reference count of the logical slot in one memory access. Step S300: Perform an atomic increment / decrement operation on the current reference count, and trigger the announcement or cancellation of the route corresponding to the IPv6 subnet based on whether the count value changes from zero to a positive number or from a positive number to zero after the increment / decrement.

[0021] In the embodiments of this disclosure, a reference counting slot pool with self-contained interpretive information is constructed. The aggregation mode code and allocation flag of the logical slot are directly encoded in the low bits of the 64-bit physical slot, making each physical slot a self-verifying unit. When it is necessary to read or update the reference count of a logical slot, the aggregation mode of the physical slot and the specific offset and bit width of the logical slot can be obtained simultaneously through a single memory access based solely on the physical address calculated from the logical identifier, completely eliminating the dependence on external index tables. The difficulty in conceiving this mechanism lies in the requirement to start from the distribution of scenario data, confirm the range of the vast majority of reference counts, then solidify this statistical regularity into a multi-granularity partitioning rule for physical slots, and further place the metadata describing the partition and the count value itself in the same atomic operation domain. This design, which deeply integrates storage structure, addressing logic, and concurrency control, represents a reconstruction of the reference counting management problem in a specific scenario.

[0022] In this embodiment, the process of obtaining routing change events for IPv6 subnets is achieved through a long-connection subscription mechanism with the cloud platform's virtual network management component. The virtual network management component maintains a state database of all virtual network resources. When the state of any resource related to IPv6 subnet routing changes, it automatically generates a standardized event message and pushes it to all servers that have subscribed to that event type. The types of routing change events cover all operations on the cloud platform that may affect the reachability of IPv6 subnets, specifically including IPv6 subnet creation, IPv6 subnet deletion, IPv6 subnet binding to a virtual router interface, IPv6 subnet unbinding to a virtual router interface, adding a virtual router external gateway, deleting a virtual router external gateway, enabling a virtual router interface, disabling a virtual router interface, and switching the high availability state of a virtual router. Each routing change event message uses a structured data format, including a unique event identifier, an event timestamp, an event type code, a unique resource identifier, a tenant identifier associated with the resource, and extended attribute fields related to the event. The extended attribute field explicitly carries the external network identifier associated with the IPv6 subnet. The external network identifier is a globally unique string identifier on the cloud platform, used to distinguish different public network egress resources, different virtual routing forwarding domains, and different tenant-specific external networks.

[0023] In this embodiment, determining the corresponding logical slot in the reference-counting slot pool of shared memory based on the external network identifier first requires maintaining a mapping table between the external network identifier and the logical slot. This mapping table is stored in the system's local memory and implemented using a hash table data structure, with the external network identifier as the key and the logical identifier of the logical slot as the value. When the event acquisition module receives a new routing change event, it first extracts the external network identifier from the event's extended attribute field, and then queries the mapping table using this external network identifier as the key. If a corresponding logical identifier is found in the mapping table, it is directly used for subsequent counting update operations. If no corresponding logical identifier is found in the mapping table, it indicates that the external network is being used for the first time, and a new free logical slot needs to be allocated from the reference-counting slot pool. The process of allocating a new logical slot involves traversing the physical slots in the reference-counted slot pool, finding the first physical slot with an allocation mark of 1 and an available logical slot, or finding the first available physical slot with an allocation mark of 0, allocating one of the logical slots to the external network, and then adding the correspondence between the external network identifier and the newly allocated logical identifier to the mapping table.

[0024] In this embodiment, the reference-counted slot pool is a contiguous physical memory space allocated by the system in the shared memory region of the operating system during the initialization phase. The size of the shared memory region can be flexibly set through the system configuration file. The configured size needs to be calculated based on the maximum number of external networks planned for the cloud platform, typically estimated at 8 bytes per external network, with some redundancy reserved. The shared memory region is evenly divided into multiple 64-bit physical slots. Each physical slot has a unique physical address in the shared memory, and there is a fixed linear correspondence between the physical address and the physical slot index. The lower 3 bits of each 64-bit physical slot are predefined as a self-verifying metadata region, where bit 0 is the allocation flag, and bits 1 and 2 are the pattern code. The allocation flag is a binary bit. When the value of the allocation flag is 0, it indicates that all logical slots corresponding to the physical slot are in an idle state and are not used by any external network. When the value of the allocation flag is 1, it indicates that at least one logical slot in the physical slot has been allocated and used. The mode code consists of two binary bits, which are used to indicate the aggregation mode of the logical slots inside the physical slot. Different mode code values ​​correspond to different logical slot division methods and bit widths of individual logical slots.

[0025] In this embodiment, to read the low-order bits of the physical slot based on the logical identifier of the logical slot, the index of the physical slot where the logical slot is located needs to be calculated first using the logical identifier. The logical identifier is a continuously increasing integer starting from 0, and the system assigns a unique logical identifier to each allocated logical slot. For the default single-unit 8-bit mode, each 64-bit physical slot can accommodate 8 logical slots. Therefore, the index of the physical slot can be obtained by dividing the logical identifier by 8 and taking the integer part. The sub-slot index of the logical slot within the physical slot can be obtained by taking the remainder of the logical identifier by 8. After calculating the physical slot index, the system can calculate the starting physical address of the physical slot in shared memory by multiplying the physical slot index by 8 bytes. Then, the system reads the 64-bit data at this physical address through direct memory access and temporarily stores the read 64-bit data in the processor's general-purpose register. The operation of reading physical slot data is an atomic memory read operation, ensuring that the read data is complete and that intermediate state data is not read.

[0026] In this embodiment, parsing the pattern code to determine the current aggregation mode involves extracting the first and second bit values ​​from the read 64-bit data to form a two-bit pattern code. Then, according to a predefined correspondence table between pattern codes and aggregation modes, the current aggregation mode of the physical slot is determined. The correspondence between pattern codes and aggregation modes is fixed: pattern code 00 corresponds to a single-entity 8-bit mode, pattern code 01 corresponds to a dual-entity 16-bit mode, pattern code 10 corresponds to a quad-entity 32-bit mode, and pattern code 11 corresponds to a full-width 64-bit mode. After determining the current aggregation mode, the system needs to recalculate the bit offset and effective count bit width of the logical slot within the physical slot based on the current aggregation mode. Different aggregation modes correspond to different numbers of logical slots and different bit widths per logical slot; therefore, the calculation methods for bit offset and effective count bit width also differ. For example, in dual-body 16-bit mode, each physical slot can accommodate 4 logical slots. Therefore, the sequence number of a logical slot within a physical slot is obtained by taking the logical identifier modulo 4, with the bit offset being the sequence number multiplied by 16 bits, resulting in an effective count width of 14 bits. In quad-body 32-bit mode, each physical slot can accommodate 2 logical slots. The logical slot sequence number is obtained by taking the logical identifier modulo 2, with the bit offset being the sequence number multiplied by 32 bits, resulting in an effective count width of 30 bits. In full-width 64-bit mode, each physical slot can only accommodate 1 logical slot. The logical slot sequence number is fixed at 0, the bit offset is 0 bits, and the effective count width is 61 bits.

[0027] In this embodiment, through the above calculation process, the system only needs to perform one physical memory access operation to obtain the current reference count value of the logical slot. This is because all metadata information used to locate the logical slot is stored in the low bits of the physical slot itself, without needing to access any external index table or metadata storage structure. Compared with the traditional independent index table scheme, this design reduces the number of memory accesses in the location process from more than two to one, greatly reducing memory access latency. At the same time, since there is no need to maintain an external index table, it also saves a large amount of memory space occupied by the index table, improving the utilization of memory resources. In addition, since the metadata and the count value are stored in the same 64-bit atomic word, all modification operations on the logical slot can be completed through a single atomic comparison and exchange instruction, ensuring the atomicity of the operation and the consistency of the data.

[0028] In this embodiment, atomic increment / decrement operations are performed on the current reference count using atomic compare-swap instructions provided by the processor architecture. Atomic compare-swap instructions are atomic operation instructions commonly supported by modern processors. Their basic principle is to compare the value in memory with a target value. If they are equal, the value in memory is updated to the new value, and success is returned; otherwise, the value in memory is not updated, and failure is returned. When performing an atomic increment / decrement operation, the system first reads the current count value of the logical slot and calculates the target count value after the increment / decrement. Then, it calls the atomic compare-swap instruction to compare the count value in memory with the read current count value. If they are equal, the count value in memory is updated to the target count value. If the atomic compare-swap instruction returns failure, it means that the count value of the logical slot has been modified by another process or thread during the time between reading the current count value and performing the update operation. In this case, the system will reread the current count value, recalculate the target count value, and call the atomic compare-swap instruction again to attempt the update until the update is successful. This lock-free concurrency control mechanism based on atomic comparison and exchange instructions avoids the lock contention and context switching overhead of traditional locking mechanisms, greatly improving system performance in high-concurrency scenarios.

[0029] In this embodiment, the system triggers the advertisement or revocation of routes corresponding to the IPv6 subnet based on whether the count value changes from zero to a positive number or from a positive number to zero after the increment / decrement operation. After each successful atomic increment / decrement operation, the system compares the count values ​​before and after the operation. If the count value before the increment / decrement is 0 and the count value after the increment / decrement is positive, it indicates that the external network corresponding to the logical slot has changed from having no active IPv6 subnet routes to having active IPv6 subnet routes. In this case, the system needs to trigger a route advertisement operation to publish all active IPv6 subnet routes under this external network to the core switch. If the count value before the increment / decrement is positive and the count value after the increment / decrement is 0, it indicates that the external network corresponding to the logical slot has changed from having active IPv6 subnet routes to having no active IPv6 subnet routes. In this case, the system needs to trigger a route revocation operation to remove all IPv6 subnet routes under this external network from the core switch. If both the count values ​​before and after the increment / decrement are positive or both are 0, it indicates that the routing status of the external network has not changed substantially, and no routing operation needs to be triggered. This triggering mechanism ensures that routing messages are only sent when there is a fundamental change in the routing state, greatly reducing unnecessary network traffic and the processing load on core switches, while also avoiding routing oscillation problems.

[0030] In an optional embodiment, the mode code includes: single-body 8-bit mode, dual-body 16-bit mode, quad-body 32-bit mode, and full-width 64-bit mode. In full-width 64-bit mode, when the high bit of a physical slot is set as a recursive node marker, the physical slot acts as a recursive node, and its counting area is used to store the offset pointing to the next level physical slot.

[0031] In this embodiment, the mode code occupies the first and second bits of a 64-bit physical slot, totaling two bits, which can represent four different numerical combinations, corresponding to four different aggregation modes. These four aggregation modes cover all possible scenarios from low to high reference counts. The system can dynamically switch aggregation modes based on the actual reference count of the logical slot to achieve optimal memory utilization and processing performance. The single-slot 8-bit mode is the system's default aggregation mode, and all physical slots are set to single-slot 8-bit mode during system initialization. In single-slot 8-bit mode, the 64-bit physical slot is evenly divided into eight independent 8-bit logical slots, each occupying eight consecutive bits. This mode is suitable for scenarios with low reference counts, maximizing memory utilization; one physical slot can simultaneously store reference counts from eight different external networks.

[0032] In this embodiment, the dual-body 16-bit mode is suitable for scenarios with medium reference count values. In the dual-body 16-bit mode, the 64-bit physical slot is evenly divided into four independent 16-bit logical slots, each occupying 16 consecutive bits. Compared to the single-body 8-bit mode, the dual-body 16-bit mode has a larger effective count bit width per logical slot, allowing for the storage of larger reference count values, but the number of logical slots that a physical slot can accommodate is reduced to four. The quad-body 32-bit mode is suitable for scenarios with high reference count values. In the quad-body 32-bit mode, the 64-bit physical slot is evenly divided into two independent 32-bit logical slots, each occupying 32 consecutive bits. In this mode, the effective count bit width per logical slot is further increased, allowing for the storage of higher reference count values, but the number of logical slots that a physical slot can accommodate is reduced to two. The full-width 64-bit mode is suitable for scenarios with very high reference count values. In the full-width 64-bit mode, the entire 64-bit physical slot is used as a single logical slot, occupying all 64 bits. In this mode, the effective count bit width of a single logical slot is the largest, which can store very high reference count values, but a physical slot can only hold 1 logical slot.

[0033] In this embodiment of the disclosure, in full-width 64-bit mode, the high-bit region of a physical slot can be configured as a recursive node marker. The recursive node marker occupies bits 61, 62, and 63 of the physical slot, a total of three bits. When these three bits are set to a specific numerical combination, the physical slot is no longer used as a regular counting slot, but as a recursive node. As a recursive node, the counting area of ​​the physical slot no longer stores reference count values, but instead stores offset information pointing to the next-level physical slot. The offset information occupies bits 32 to 60 of the physical slot, a total of 29 bits, and is a signed integer representing the index offset of the next-level physical slot relative to the current recursive node's physical slot. Using the offset information, the system can calculate the index of the next-level physical slot, and thus calculate the physical address of the next-level physical slot. The setting of the recursive node marker allows the system to overcome the bit width limitation of a single 64-bit physical slot, linking multiple physical slots together to form a larger logical counting space, meeting the storage requirements of extremely high count values. Since only a very small number of external networks require such a high reference count in a real cloud platform operating environment, the setting of recursive node markers will not have a significant impact on the overall performance of the system.

[0034] Optionally, in single-unit 8-bit mode, the physical slot is split into eight 8-bit logical slots. The lower two bits of each 8-bit logical slot are the mode identifier, the third bit from the lower number is the allocation mark, and the fourth to eighth bits are five valid count bits.

[0035] In this embodiment, when the physical slot is in single-slot 8-bit mode, each 8-bit logical slot is divided according to a uniform bit layout. Bits 0 and 1 of each 8-bit logical slot are mode identifiers, whose values ​​match the mode code value of the physical slot, used to help confirm the aggregation mode of the logical slot. In single-slot 8-bit mode, the mode identifier value of each logical slot is 00. Bit 2 of each 8-bit logical slot is an allocation flag, whose value indicates whether the logical slot has been allocated. When the allocation flag value is 1, it indicates that the logical slot has been allocated to an external network and is in an occupied state. When the allocation flag value is 0, it indicates that the logical slot is in an idle state and can be allocated to a new external network. Bits 3 to 8 of each 8-bit logical slot are valid count bits, a total of 5 bits, specifically used to store the reference count value of the logical slot. The 5 valid count bits can represent values ​​from 0 to 31; therefore, the maximum reference count value that a single logical slot can store in single-slot 8-bit mode is 31.

[0036] In this embodiment, the bit layout design was determined after fully considering the actual data characteristics of the IPv6 routing and publishing scenario on the cloud platform. Analysis of actual operational data from multiple large operator cloud platforms revealed that over 90% of external networks have a reference count value not exceeding 31. Therefore, the default mode is set to a single 8-bit mode, with each logical slot providing 5 valid count bits, which can meet the storage needs of most scenarios. Simultaneously, the mode identifier and allocation flag are embedded in each 8-bit logical slot, ensuring that each logical slot itself contains complete state information without relying on external metadata structures. This design not only improves memory utilization but also simplifies the management and maintenance of logical slots. When checking whether a logical slot is idle, only the second allocation flag of that logical slot needs to be read; no other information needs to be accessed. When confirming the aggregation mode of a logical slot, only the 0th and 1st mode identifier bits of that logical slot need to be read; the mode code of the entire physical slot does not need to be read.

[0037] In some alternative embodiments, such as Figure 2 As shown, when the current aggregation mode is a full-width 64-bit mode and the high-order bits are identified as recursive node markers, parsing the mode code determines the current aggregation mode, and calculating the bit offset of the logical slot within the physical slot and the effective count bit width based on the current aggregation mode further includes: Step S201: Extract the offset of the next level physical slot from the counting area of ​​the physical slot; Step S202: Read the low bits of the next-level physical slot based on the offset to determine the next-level aggregation mode; Step S203: Repeat the above parsing and offset reading process until the non-recursive physical slot is reached to obtain the final effective count bit width and actual reference count.

[0038] In this embodiment, when the system reads the lower 3 bits of a physical slot and parses the mode code to be 11 (i.e., a full-width 64-bit mode), it further checks the bit values ​​from bits 61 to 63 of the physical slot to determine if a recursive node marker exists. If the values ​​of these three bits are equal to the predefined recursive node marker value, it indicates that the physical slot is a recursive node, and the system automatically enters the recursive addressing process. First, the system extracts the offset value of the next-level physical slot from bits 32 to 60 of the physical slot. The offset value is a signed integer; a positive number indicates that the next-level physical slot is after the current physical slot, and a negative number indicates that the next-level physical slot is before the current physical slot. Then, the system calculates the index of the next-level physical slot based on the index of the current physical slot and the offset value. The calculation method is that the index of the next-level physical slot is equal to the index of the current physical slot plus the offset value. After calculating the index of the next-level physical slot, the system uses this index to calculate the physical address of the next-level physical slot, and reads the lower 3 bits of the information of the next-level physical slot to parse out the corresponding aggregation mode.

[0039] In this embodiment, if the mode code of the next-level physical slot is still 11 and there is a recursive node marker in the high bits, the system will repeat the offset parsing and physical slot reading steps to continue addressing the next-level physical slot. This process will continue until a regular physical slot with a mode code other than 11, or a mode code of 11 but no recursive node marker in the high bits, is reached. Upon reaching the regular physical slot, the system calculates the bit offset and effective count bit width of the logical slot within the physical slot according to the aggregation mode corresponding to that physical slot, extracts the actual reference count value, and completes the count reading operation in the recursive scenario. The number of steps in the recursive addressing process is proportional to the length of the recursive chain. Since only a very small number of logical slots need to use recursive expansion, the length of the recursive chain is usually very short, generally not exceeding two levels. Therefore, the number of memory accesses increased by the recursive addressing process is very limited and will not have a significant impact on the overall performance of the system.

[0040] In this embodiment, the recursive addressing process shares most of the code logic with the conventional location process, requiring only the addition of offset parsing and jump steps when a recursive node marker is detected. This design greatly simplifies the system's implementation complexity and reduces code redundancy and the possibility of errors. Simultaneously, all memory read operations during recursive addressing are direct physical address accesses, eliminating the need for hash calculations or index lookups, thus maintaining high access speed. Furthermore, the construction and modification of recursive nodes are accomplished through atomic comparison and swap instructions, ensuring the consistency and stability of the recursive chain structure and preventing broken chains or circular references.

[0041] In some alternative embodiments, such as Figure 3 As shown, the method also includes: Step S211: When the count value of a logical slot in the current aggregation mode reaches the upper limit of the effective count bit width of the mode, check whether the logical slots adjacent to the logical slot in the same physical slot are free. Step S212: If idle, modify the mode code of the physical slot to the next level aggregation mode through an atomic comparison and exchange operation, merge the logical slot with the adjacent logical slot into a logical slot with a wider bit width, and simultaneously merge the count value into the merged count area.

[0042] In this embodiment, when the count value of a logic slot in the current aggregation mode reaches the upper limit of the effective count bit width that the mode can support, the system automatically triggers an aggregation operation. The upper limit of the effective count bit width is determined by the number of effective count bits in the aggregation mode. For example, in single-body 8-bit mode, the effective count bits are 5, and the upper limit is 31. In dual-body 16-bit mode, the effective count bits are 13, and the upper limit is 8191. In quad-body 32-bit mode, the effective count bits are 29, and the upper limit is 536870911. In full-width 64-bit mode, the effective count bits are 61, and the upper limit is 2305843009213693951. When the system performs an atomic addition operation, it first checks whether the current count value has reached the upper limit of the mode. If the current count value is equal to the upper limit, the atomic addition operation will fail, and the system will trigger an aggregation operation to attempt to expand the bit width of the logic slot.

[0043] In this embodiment, after triggering the aggregation operation, the system first checks whether the logical slots adjacent to the logical slot within the same physical slot are in an idle state. The method for checking whether adjacent logical slots are idle is to read the allocation flag value of the adjacent logical slots; if the allocation flag value is 0, it indicates that the adjacent logical slot is idle. Since the aggregation operation merges two adjacent small-width logical slots into one large-width logical slot, it is necessary to ensure that adjacent logical slots are idle to avoid overwriting valid data in other logical slots. In single-body 8-bit mode, the aggregation operation needs to merge two adjacent 8-bit logical slots, therefore it is necessary to check whether the next sequential logical slot is idle. In dual-body 16-bit mode, the aggregation operation needs to merge two adjacent 16-bit logical slots, therefore it is necessary to check whether the next sequential logical slot is idle. In quad-body 32-bit mode, the aggregation operation needs to merge two adjacent 32-bit logical slots, therefore it is necessary to check whether the next sequential logical slot is idle.

[0044] In this embodiment, if adjacent logical slots are idle, the system prepares the modified physical slot data required for the aggregation operation. In the modified physical slot data, the mode code is changed to the value corresponding to the next-level aggregation mode. For example, when aggregating from a single-entity 8-bit mode to a dual-entity 16-bit mode, the mode code is changed from 00 to 01. The count values ​​of the original logical slot and adjacent logical slots are merged into a larger count value and stored in the merged count area. The allocation flag of the merged adjacent logical slots is set to 1, indicating that the logical slot has been merged and occupied. Then, the system calls an atomic comparison swap instruction to compare the physical slot data in memory with the currently read physical slot data. If they are equal, the physical slot data in memory is updated to the modified data, and the aggregation operation succeeds. If they are not equal, it indicates that the physical slot has been modified by another process, the aggregation operation fails, and the system rereads the physical slot data and attempts aggregation again. Since the atomic comparison swap operation is a single-instruction cycle operation, the entire aggregation process can be completed in a very short time, and the atomicity of the operation is guaranteed. After the aggregation operation is completed, all subsequent accesses to the logical slot will be calculated according to the new aggregation mode. The upper-layer module does not need to be aware of the change in the underlying storage mode, and the aggregation process is completely transparent to the upper layer.

[0045] In some optional embodiments, the method further includes: when the count value of the merged logical slot decays to below a preset ratio of the upper limit of the effective count bit width of the next-level aggregation mode, restoring the mode code of the physical slot to the previous-level aggregation mode through an atomic comparison and exchange operation, and splitting the logical slot into multiple logical slots that conform to the previous-level aggregation mode, and writing the corresponding count value to each of the split logical slots.

[0046] In this embodiment, the system automatically triggers a split operation when the reference count of a logical slot after a merging operation gradually decreases. The trigger condition for the split operation is that the reference count of the merged logical slot decays to below a preset percentage of the upper limit of the effective count bit width of the next-level aggregation mode. The preset percentage can be set through the system configuration file, and is usually set to 80%. The purpose of setting the preset percentage is to introduce a hysteresis interval to avoid frequent fluctuations in the reference count near the boundary value of the aggregation mode, which would cause the system to frequently perform aggregation and split operations, thereby reducing unnecessary system overhead and maintaining the stability of the system's operating state. For example, when a logical slot is split from a dual-body 16-bit mode back to a single-body 8-bit mode, the trigger condition is that the reference count drops to below 80% of the upper limit value of 31 for the single-body 8-bit mode, which is below 25. The system will only trigger the split operation when the reference count drops to below 25, rather than splitting immediately as soon as the reference count drops below 31. In this way, even if the reference count fluctuates frequently between 25 and 31, it will not lead to frequent mode switching.

[0047] In this embodiment, after triggering the split operation, the system prepares the modified physical slot data required for the split operation. In the modified physical slot data, the mode code is restored to the value corresponding to the previous aggregation mode. For example, when splitting from a dual-body 16-bit mode back to a single-body 8-bit mode, the mode code is changed from 01 to 00. The large-width logical slot is split into multiple small-width logical slots. The original count value is allocated to the counting area of ​​the first logical slot after the split, and the allocation flags of the other split logical slots are set to 0, indicating that they are in an idle state. Then, the system calls the atomic comparison and swap instruction to compare the physical slot data in memory with the currently read physical slot data. If the two are equal, the physical slot data in memory is updated to the modified data, and the split operation is successful. If the two are not equal, it means that the physical slot has been modified by other processes, the split operation fails, and the system will reread the physical slot data and try to split again. After the split operation is completed, all subsequent accesses to the logical slot will be calculated according to the new aggregation mode, and the upper-layer module does not need to be aware of the change in the underlying storage mode. The free logical slots released by the splitting operation can be allocated to other new external networks, improving the utilization of memory resources.

[0048] In some alternative embodiments, such as Figure 4 As shown, the method also includes: Step S221: When the logical slot is in full-width 64-bit mode and the count value exceeds the preset threshold, allocate a new physical slot in the reference count slot pool; Step S222: Write the current count value into the count area of ​​the new physical slot, and set the mode code of the new physical slot to full-width 64-bit mode with the high bits not containing the recursive node marker. Step S223: Keep the mode code of the original physical slot in full-width 64-bit mode, set its high bits as a recursive node marker, and write the offset of the new physical slot relative to the original physical slot into the counting area of ​​the original physical slot.

[0049] In this embodiment, when a logical slot is in full-width 64-bit mode and the count value exceeds a preset threshold, the system automatically triggers a recursive expansion operation. The preset threshold is set to a value close to the upper limit of the effective counting bit width in full-width 64-bit mode, typically set to 90% of the upper limit value, reserving a certain safety margin to prevent overflow caused by a sudden increase in the count value. When the count value exceeds the preset threshold, the system checks whether there are any free logical slots within the physical slot that can be used for merging and expansion. Since the entire physical slot is already used as a single logical slot in full-width 64-bit mode, and there are no other free logical slots to merge, the system cannot further expand the bit width through internal aggregation and can only meet the storage requirements of larger count values ​​through recursive expansion.

[0050] In this embodiment of the disclosure, after triggering the recursive expansion operation, the system first allocates a new free physical slot in the reference counting slot pool. The process of allocating a new physical slot involves traversing the physical slots in the reference counting slot pool and finding a free physical slot with an allocation flag of 0. If no free physical slot with an allocation flag of 0 is found, a physical slot with an allocation flag of 1 but with available logical slots is found, and one of these logical slots is allocated. After allocating a new physical slot, the system initializes the physical slot to a full-width 64-bit normal mode, sets its mode code to 11, and does not set the recursive node flag in the high bits. Then, the system writes the count value of the current logical slot into the counting area of ​​the new physical slot. Next, the system prepares the modified data of the original physical slot, keeping the mode code of the original physical slot at 11, setting bits 61 to 63 of the original physical slot as the recursive node flag, and writing the offset of the new physical slot relative to the original physical slot into bits 32 to 60 of the original physical slot. Finally, the system calls the atomic comparison swap instruction to update the original physical slot data in memory with the modified data, thus completing the construction of the recursive node.

[0051] In this embodiment, after the recursive expansion operation is completed, the original physical slot becomes the first node of the recursive chain, and the new physical slot becomes the second node of the recursive chain. The actual count value is stored in the new physical slot. Subsequent accesses to this logical slot will be located in the new physical slot through a recursive addressing process. If the count value continues to grow beyond the preset threshold of the new physical slot, the system can continue to allocate new physical slots to the recursive chain, achieving infinite expansion of the logical slot width. When the count value drops to a level that can be accommodated in the previous physical slot, the system triggers a recursive contraction operation. The recursive contraction operation is the reverse of the recursive expansion operation. The system migrates the count value in the last physical slot to the previous physical slot, clears the recursive node marker of the previous physical slot, and releases the last physical slot back to the idle slot pool. The recursive contraction operation is also completed through atomic comparison and exchange instructions, ensuring the atomicity of the operation and the consistency of the data.

[0052] In some alternative embodiments, such as Figure 5 As shown, triggering the announcement or revocation of a route corresponding to an IPv6 subnet further includes: Step S301: If the count value changes from zero to a positive number after the increment / decrement, a BGP route advertisement message is sent to the core switch; Step S302: If the count value changes from positive to zero after the increment / decrement, a BGP route cancellation message is sent to the core switch.

[0053] In this embodiment, the system triggers a route advertisement operation when the reference count changes from zero to a positive number. The route advertisement operation is executed by the route publishing module. The route publishing module first queries the system's internal routing information database to obtain information on all active IPv6 subnets under the external network corresponding to the logical slot. The routing information database stores detailed information on all IPv6 subnets in the cloud platform, including the subnet network address prefix, subnet prefix length, subnet gateway address, subnet tenant, and subnet status information. Then, the route publishing module generates a route advertisement message based on the obtained IPv6 subnet information. The route advertisement message uses a standard routing protocol format and includes a network layer reachability information field, which carries the network address prefix and prefix length of the IPv6 subnet. The route advertisement message also includes a next-hop address field, which carries the IPv6 address of the gateway device in the cloud platform responsible for forwarding traffic from the external network.

[0054] In this embodiment, the route advertising module encapsulates the generated route advertisement message into a data packet conforming to the standard routing protocol specification and sends it to the core switch device through a pre-established routing protocol session. Upon receiving the route advertisement message, the core switch device verifies and processes the message, adding the route entry from the message to its own routing table. The core switch device then propagates this route entry to other routing devices in the network, thereby enabling connectivity between the IPv6 subnet and the entire external network. When the reference count value changes from positive to zero, the system triggers a route revocation operation. The route advertising module generates a route revocation message containing the network address prefixes and prefix length information for all IPv6 subnets that need to be revoked. The route advertising module sends the route revocation message to the core switch device. Upon receiving the route revocation message, the core switch device deletes the corresponding route entry from its own routing table and notifies other routing devices in the network to revoke the route entry, thereby terminating the connectivity between the IPv6 subnet and the external network.

[0055] In some optional embodiments, the method further includes setting all physical slots in the reference counting slot pool to single-unit 8-bit mode and setting the allocation flag of each physical slot to zero during system initialization.

[0056] In this embodiment, the system initialization process is executed when the system service starts, and is used to complete all the preparatory work required for system operation. First, the system calls the shared memory creation function provided by the operating system to allocate a contiguous memory space in the operating system's shared memory region as the storage area for the reference-counted slot pool. The size of the shared memory is specified by parameters in the system configuration file, in bytes, and must be an integer multiple of 8 bytes. When allocating shared memory, the system sets access permissions, allowing only system service processes and authorized worker node processes to perform read and write operations, preventing unauthorized processes from accessing and modifying data in the shared memory. After allocating the shared memory space, the system initializes all bytes in the shared memory space to zero, ensuring that no residual old data affects the normal operation of the system.

[0057] In this embodiment, the system divides the shared memory space into multiple 64-bit physical slots, each corresponding to a 64-bit aligned address in the shared memory. The system then sets the mode code of all physical slots to 00 (the value corresponding to the single 8-bit mode) and sets the allocation flag of all physical slots to 0. After initialization, all physical slots are in single 8-bit mode, and all logical slots are idle and ready for allocation. Next, the system initializes the mapping table between external network identifiers and logical slots, creating an empty hash table structure. Then, the system initializes the event subscription mechanism, establishing a long connection with the cloud platform's virtual network management component and subscribing to all event types related to IPv6 subnet routing. Finally, the system initializes the routing protocol session, establishing a routing protocol connection with the core switch device to complete parameter negotiation and session establishment. If any errors occur during system initialization, the system will record error logs and automatically exit, waiting for maintenance personnel to troubleshoot and restart. After initialization, the system enters normal operation and can begin processing routing change events.

[0058] Another aspect of this disclosure provides a cloud-native IPv6 subnet routing dynamic publishing system, such as... Figure 6 As shown, it includes: Event acquisition module 10 is used to acquire routing change events of IPv6 subnet, determine the external network identifier associated with the routing change event, and determine the corresponding logical slot in the reference counting slot pool of shared memory based on the external network identifier. The reference counting slot pool consists of multiple 64-bit physical slots. The low bits of each physical slot contain a self-verifying mode code and an allocation flag. The mode code indicates the aggregation mode of the logical slots in the physical slot, and the allocation flag indicates whether the physical slot has an allocated logical slot. The reference counting management module 20 is used to read the low bits of the physical slot where the logical slot is located according to the logical identifier of the logical slot, parse the mode code to determine the current aggregation mode, and calculate the bit offset and effective count bit width of the logical slot in the physical slot based on the current aggregation mode, so as to obtain the current reference count of the logical slot in one memory access. The route publishing module 30 is used to perform atomic increment / decrement operations on the current reference count. Depending on whether the incremented / decremented count value changes from zero to a positive number or from a positive number to zero, it triggers the announcement or revocation of the corresponding route for the IPv6 subnet.

[0059] It should be noted that the specific embodiments of the cloud-native IPv6 subnet route dynamic publishing method based on the cloud-native IPv6 subnet route dynamic publishing system in this disclosure have been described in detail in the above method process, and will not be repeated here.

[0060] In this embodiment, the cloud-native IPv6 subnet routing dynamic publishing system adopts a modular, layered architecture design, consisting of three independent functional modules: an event acquisition module 10, a reference counting management module 20, and a route publishing module 30. These three modules communicate through well-defined internal interfaces, achieving a loosely coupled design that facilitates independent development, testing, upgrades, and maintenance. The event acquisition module 10 is the system's input module, responsible for interacting with the cloud platform's virtual network management component, receiving route change events pushed by the virtual network management component, and parsing and preprocessing the events. The event acquisition module 10 internally includes an event subscription unit 11, an event parsing unit 12, and a logical slot matching unit 13. The event subscription unit 11 is responsible for implementing the event subscription protocol with the virtual network management component, establishing and maintaining a long connection with the virtual network management component, and receiving event messages pushed by the virtual network management component. The event parsing unit 12 is responsible for parsing the received raw event messages into a standardized event structure within the system and extracting key information fields from the events. The logical slot matching unit 13 is responsible for finding or allocating the corresponding logical slot based on the external network identifier in the event, and passing the standardized event and logical identifier to the reference count management module 20.

[0061] In this embodiment, the reference counting management module 20 is the core processing module of the system, responsible for managing all physical and logical slots in the reference counting slot pool, and providing core functions such as reference counting read, update, aggregation, splitting, and recursive expansion. The reference counting management module 20 provides a unified reference counting operation interface. Upper-layer modules only need to pass in the logical identifier and increment / decrement amount through this interface to complete the reference count update operation, without needing to understand the underlying storage structure and implementation details. The reference counting management module 20 internally includes a positioning calculation unit 21, an atomic operation unit 22, a mode switching unit 23, and a recursive management unit 24. The positioning calculation unit 21 is responsible for implementing the logical slot positioning algorithm, calculating the corresponding physical slot address and bit offset based on the logical identifier, parsing the mode code and effective count bit width, and extracting the reference count value. The atomic operation unit 22 is responsible for encapsulating the atomic comparison and exchange instructions provided by the processor, providing atomic counting read, write, and update operations, ensuring data consistency in concurrent scenarios. The mode switching unit 23 is responsible for detecting changes in the count value of the logical slot, triggering aggregation and splitting operations, and completing the atomic switching of the physical slot mode. The recursive management unit 24 is responsible for detecting recursive nodes, executing the recursive addressing process, and handling recursive expansion and contraction operations.

[0062] In this embodiment, the route advertising module 30 is the system's output module, responsible for interacting with core network devices to complete route announcement and revocation operations. The route advertising module 30 internally includes a route information database 31, a route message generation unit 32, a route protocol session unit 33, and a route status management unit 34. The route information database 31 stores detailed information and route status information for all IPv6 subnets in the cloud platform, providing data support for route message generation. The route message generation unit 32 is responsible for generating route announcement and route revocation messages conforming to standard formats based on the reference count change status and data in the route information database. The route protocol session unit 33 is responsible for implementing standard routing protocols, establishing and maintaining routing protocol sessions with the core switch, sending generated route messages to the core switch, and receiving routing protocol messages sent by the core switch. The route status management unit 34 is responsible for maintaining the status information of all currently published route entries, enabling rapid restoration of the route advertising status based on the status information during system restarts or fault recovery.

[0063] By constructing a reference counting slot pool consisting of 64 physical slots, with the low bits of each slot carrying a self-verifying mode code and an allocation flag, the aggregation bit width information and validity status of logical slots are directly embedded in the data storage unit. When it is necessary to locate and update the reference count of a logical slot, it is only necessary to calculate the position of its physical slot based on the logical identifier of the logical slot. The current aggregation mode can be obtained synchronously by reading the low bits of the slot in a single memory operation, thereby completing the real-time parsing of bit offset and valid count bit width. The entire process does not require accessing any external index table. This inline encoding mechanism makes the location operation only a single memory access and a few bit operations in most cases, reducing the average location latency from hundreds of nanoseconds to less than ten nanoseconds. At the same time, since the mode code, allocation flag, and count value are located in the same atomic word, the atomic increment and decrement operations on the count value naturally cover the concurrent state switching during mode changes, ensuring strong consistency of increment, decrement, aggregation, and split operations under lock-free conditions. Ultimately, the incremented or decremented count accurately reflects the snapshot's reference status. Its change from zero to positive or from positive to zero is used to precisely trigger the announcement or revocation of the corresponding IPv6 subnet route, thereby achieving low latency, high throughput, and high reliability of dynamic route publishing in a large-scale cloud environment.

[0064] For example, a provincial-level telecom operator's cloud platform deploys the cloud-native IPv6 subnet routing dynamic publishing system described in this disclosure. This cloud platform hosts over 5,000 enterprise tenants, manages over 500,000 IPv6 subnets, and has a worker node cluster consisting of 32 worker nodes. During system operation, tenant A, a large internet company, creates an IPv6 subnet on the cloud platform to host its core business, with the subnet prefix 2409:8a12:1234:: / 48. Tenant A binds this subnet to its dedicated virtual router and configures the virtual router with an external network gateway for its public network exit. Upon detecting this operation, the virtual network management component generates a route change event of type "Router Interface Added" and pushes this event to the event acquisition module.

[0065] In this embodiment, after the event subscription unit of the event acquisition module receives the route change event, the event parsing unit parses the event message and extracts the event type code, resource unique identifier, tenant identifier, and external network identifier. The external network identifier is the tenant's dedicated public network exit identifier, with a value of ext-net-tenant-a-12345. The logical slot matching unit 13 queries the mapping table using ext-net-tenant-a-12345 as the key and finds that this external network is being used for the first time, with no corresponding record in the mapping table. Therefore, the logical slot matching unit 13 sends a logical slot allocation request to the reference counting management module 20. The reference counting management module 20 traverses the reference counting slot pool, finds the physical slot with index 100, whose allocation flag is 1, and the third logical slot is idle. The reference counting management module 20 allocates this logical slot to the external network ext-net-tenant-a-12345 and returns logical identifier 803 to the logical slot matching unit 13. The logical slot matching unit 13 adds the correspondence between ext-net-tenant-a-12345 and 803 to the mapping table, and passes the event information and logical identifier 803 to the reference count management module 20 for count update.

[0066] In this embodiment, after receiving the logical identifier 803, the location calculation unit of the reference count management module 20 calculates the physical slot index as 803 divided by 8 and taking the integer part, resulting in 100. It calculates the sub-slot index as 803 modulo 8, resulting in 3. The location calculation unit reads the 64-bit data of the physical slot with index 100, extracts the lower 3 bits to obtain the mode code 00, confirming it is in single-unit 8-bit mode. It calculates the bit offset as 3 multiplied by 8 bits, resulting in 24 bits. The effective count bit width is 5 bits. The location calculation unit extracts the reference count value from bits 24 to 28 of the physical slot data; the current value is 0. The atomic operation unit performs an atomic increment operation, updating the count value to 1. The system detects the count value changing from 0 to 1 and triggers a route advertisement operation. The route advertisement module 30 queries the routing information database, obtains the IPv6 subnet information of tenant A, generates a route advertisement message containing the prefix 2409:8a12:1234:: / 48, and sends it to the core switch via a BGP session. After receiving the routing advertisement message, the core switch adds the routing entry to the routing table, enabling tenant A's IPv6 subnet to connect to the Internet.

[0067] In this embodiment, as tenant A's business rapidly develops, the access volume of its core business increases dramatically. To cope with the high traffic, the cloud platform distributes the routing of this IPv6 subnet to multiple worker nodes for processing. Over the next month, the reference count value of this logical slot gradually rises to 28, always remaining within the single-entity 8-bit counting range. The reference count management module 20 completes the reading and updating of the count through a single memory access each time, resulting in very low operation latency and no impact on the business. The route advertising module 30 only sends a route advertisement message once when the count first changes from 0 to 1; subsequent intermediate changes in the count do not trigger any routing operations, greatly reducing the processing load on the core switch.

[0068] In this embodiment, when tenant A's business experiences a major annual promotion, the traffic volume reaches more than ten times the usual level. The cloud platform automatically expands a large number of worker nodes to handle the traffic, and the route of this IPv6 subnet is referenced by all thirty-two worker nodes simultaneously. When the reference count value grows to 31, the next atomic addition operation detects a bit width overflow. The mode switching unit 23 triggers an aggregation operation, checks the allocation flag of the fourth logical slot within the same physical slot, and finds it to be in an idle state. The mode switching unit 23 prepares the modified physical slot data, changes the mode code from 00 to 01, merges the original count value 31 and the newly added value 1 into 32 and writes it into the merged 13-bit count area, and sets the allocation flag of the fourth logical slot to 1. The mode switching of the physical slot is completed through an atomic comparison and exchange operation. After the aggregation operation is completed, the effective count bit width of the logical slot is expanded to 13 bits, which can support a maximum count value of 8191. All subsequent accesses to this logical slot are calculated in dual-body 16-bit mode. The upper-layer worker nodes and routing publishing module 30 are unaware of the change in the underlying storage mode, and the routing publishing process is not interrupted.

[0069] In this embodiment, after the promotional event ends, tenant A's business traffic gradually decreases, and the cloud platform gradually releases excess worker nodes. The reference count value of this logical slot gradually decreases to 24, which is below 80% of the upper limit of the single 8-bit mode. The mode switching unit triggers a split operation, prepares the modified physical slot data, changes the mode code from 01 to 00, writes the count value of 24 into the counting area of ​​the third logical slot, and sets the allocation flag of the fourth logical slot to 0. The mode switching of the physical slot is completed through an atomic comparison and exchange operation. After the split operation is completed, the released fourth logical slot can be allocated to other new external networks.

[0070] In this embodiment, the technical solution completely eliminates the dependence on external index tables by embedding metadata into physical slots using a self-verifying encoding design. Simultaneously, through a bit-width adjustment mechanism combining dynamic aggregation and recursive expansion, it perfectly adapts to the reference count distribution characteristics of cloud platform IPv6 routing deployment scenarios. Compared with existing technologies, the technical solution of this disclosure achieves significant improvements in memory utilization, access latency, concurrency performance, and data consistency, better supporting the deployment and operation of large-scale cloud-native IPv6 networks.

[0071] Those skilled in the art will understand that the above description is merely a preferred embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure. Further details are omitted here.

Claims

1. A method for dynamically publishing cloud-native IPv6 subnet routes, characterized in that, include: Obtain the routing change event of the IPv6 subnet, determine the external network identifier associated with the routing change event, and based on the external network identifier, determine the corresponding logical slot in the reference counting slot pool of shared memory. The reference counting slot pool consists of multiple 64-bit physical slots. The low bits of each physical slot contain a self-verifying mode code and an allocation flag. The mode code indicates the aggregation mode of the logical slots within the physical slot, and the allocation flag indicates whether the physical slot has any allocated logical slots. Based on the logical identifier of the logical slot, the low bit of the physical slot where it is located is read, the mode code is parsed to determine the current aggregation mode, and the bit offset and effective count bit width of the logical slot in the physical slot are calculated based on the current aggregation mode to obtain the current reference count of the logical slot. Perform atomic increment / decrement operations on the current reference count, and trigger the announcement or revocation of the route corresponding to the IPv6 subnet based on whether the count value changes from zero to a positive number or from a positive number to zero after the increment / decrement. The mode codes include: single-body 8-bit mode, double-body 16-bit mode, quad-body 32-bit mode, and full-width 64-bit mode. In the full-width 64-bit mode, when the high bit of a physical slot is set as a recursive node marker, the physical slot acts as a recursive node, and its counting area is used to store the offset pointing to the next level physical slot. The triggering of the announcement or revocation of the route corresponding to the IPv6 subnet further includes: If the count value changes from zero to a positive number after the increment or decrement, a BGP route advertisement message is sent to the core switch; If the count value changes from positive to zero after the increment or decrement, a BGP route cancellation message is sent to the core switch.

2. The method according to claim 1, characterized in that, In the single 8-bit mode, the physical slot is divided into 8 8-bit logical slots. The lower 2 bits of each 8-bit logical slot are the mode identifier, the 3rd bit from the lower bit is the allocation mark, and the 4th to 8th bits are 5 valid count bits.

3. The method according to claim 1, characterized in that, When the current aggregation mode is a full-width 64-bit mode and the high-order bits are identified as the recursive node marker, parsing the mode code to determine the current aggregation mode, and calculating the bit offset and effective count bit width of the logical slot within the physical slot based on the current aggregation mode, further includes: The offset of the next level physical slot is parsed from the counting area of ​​the physical slot; The low bit of the next-level physical slot is read based on the offset to determine the next-level aggregation mode; Repeat the above parsing and offset reading process until the non-recursive physical slot is reached to obtain the final effective count bit width and actual reference count.

4. The method according to claim 1, characterized in that, Also includes: When the count value of a logical slot in the current aggregation mode reaches the upper limit of the effective count bit width of the mode, check whether the logical slots adjacent to the logical slot in the same physical slot are free. If idle, the mode code of the physical slot is modified to the next-level aggregation mode through an atomic comparison and swap operation, and the logical slot is merged with the adjacent logical slot into a logical slot with a wider bit width. At the same time, the count value is merged and written into the merged count area.

5. The method according to claim 4, characterized in that, Also includes: When the count value of the merged logical slot decays to below the preset ratio of the upper limit of the effective count bit width of the next-level aggregation mode, the mode code of the physical slot is restored to the previous-level aggregation mode through an atomic comparison and exchange operation, and the logical slot is split into multiple logical slots that conform to the previous-level aggregation mode. The corresponding count value is written to each of the split logical slots.

6. The method according to claim 1, characterized in that, Also includes: When a logical slot is in full-width 64-bit mode and the count value exceeds a preset threshold, a new physical slot is allocated in the reference count slot pool. Write the current count value into the count area of ​​the new physical slot, and set the mode code of the new physical slot to full-width 64-bit mode with the high bits not containing the recursive node marker. The mode code of the original physical slot is kept in full-width 64-bit mode, while its high bits are set as recursive node markers, and the offset of the new physical slot relative to the original physical slot is written into the counting area of ​​the original physical slot.

7. The method according to claim 1, characterized in that, Also includes: During system initialization, all physical slots in the reference counting slot pool are set to single 8-bit mode, and the allocation flag of each physical slot is set to zero.

8. A cloud-native IPv6 subnet routing dynamic publishing system, characterized in that, include: The event acquisition module is used to acquire routing change events of IPv6 subnets, determine the external network identifier associated with the routing change event, and determine the corresponding logical slot in the reference counting slot pool of shared memory based on the external network identifier. The reference counting slot pool consists of multiple 64-bit physical slots. The low bits of each physical slot contain a self-verifying mode code and an allocation flag. The mode code indicates the aggregation mode of the logical slots in the physical slot, and the allocation flag indicates whether the physical slot has any allocated logical slots. The mode codes include: single-body 8-bit mode, double-body 16-bit mode, quad-body 32-bit mode, and full-width 64-bit mode. In the full-width 64-bit mode, when the high bit of a physical slot is set as a recursive node marker, the physical slot acts as a recursive node, and its counting area is used to store the offset pointing to the next level physical slot. The reference count management module is used to read the low bit of the physical slot where the logical slot is located according to the logical identifier of the logical slot, parse the mode code to determine the current aggregation mode, and calculate the bit offset and effective count bit width of the logical slot in the physical slot based on the current aggregation mode to obtain the current reference count of the logical slot. The route publishing module is used to perform atomic increment / decrement operations on the current reference count, and trigger the announcement or cancellation of the route corresponding to the IPv6 subnet based on whether the count value changes from zero to a positive number or from a positive number to zero after the increment / decrement. The triggering of the announcement or revocation of the route corresponding to the IPv6 subnet further includes: If the count value changes from zero to a positive number after the increment or decrement, a BGP route advertisement message is sent to the core switch; If the count value changes from positive to zero after the increment or decrement, a BGP route cancellation message is sent to the core switch.

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