2.5d substrate package structure and method of manufacturing a 2.5d substrate package structure

Abstract

This invention provides a 2.5D substrate packaging structure and a method for fabricating the 2.5D substrate packaging structure, relating to the field of chip packaging technology. The 2.5D substrate packaging structure includes a substrate wafer, a substitute chip, a substrate wiring layer, and a redistribution layer. Compared to existing technologies, this invention directly positions the first and second substrate chips using an integrally formed substrate layer, ensuring packaging positioning accuracy. Simultaneously, the substitute chip is mounted in the opposite direction to the first and second substrate chips. Dual-sided wiring is achieved through the substrate wiring layer and redistribution layer, reducing wiring layer density and mitigating short circuits and overheating caused by parasitic inductance leakage. Furthermore, the dual-sided wiring electrical connection is achieved by directly forming a first conductive pillar in the substrate layer, avoiding the warping and delamination problems of conventional molding processes and ensuring the structural reliability of the packaged chip.

Description

Technical Field

[0001] This invention relates to the field of chip packaging technology, and more specifically, to a 2.5D substrate packaging structure and a method for fabricating the 2.5D substrate packaging structure. Background Technology

[0002] Traditional reconfigurable wafer-level packaging technology typically involves cutting individual chips from a wafer, mounting them onto a carrier wafer for reconfiguration, and then performing wiring. Its main advantages include high-density integration, small package size, superior product performance, and high signal transmission frequency.

[0003] Conventional reconfigurable wafer packaging technology, due to the process requirements of reconfigurable wafers, integrates multiple chips together. Since the chips are oriented in the same direction, wiring can only be done on one side. This leads to an increase in wiring layer density, resulting in parasitic inductance, leakage current, short circuits between wiring layers, overheating, and other problems.

[0004] Furthermore, conventional reconfigurable wafer packaging technology typically requires the use of a molding compound to encapsulate the chip and to set conductive pillars in the molding compound to achieve multi-layer wiring and electrical connections. However, the thermal expansion coefficient of the molding compound is different from that of the silicon-based chip, which can easily concentrate thermal stress inside, causing delamination or warping of the molding compound and affecting the overall reliability of the packaging structure. Summary of the Invention

[0005] The purpose of this invention is to provide a 2.5D substrate packaging structure and a method for fabricating the 2.5D substrate packaging structure, which can reduce wiring density, mitigate leakage caused by parasitic inductance, and avoid plastic encapsulation warping and delamination problems, thereby ensuring the structural reliability of the packaged chip.

[0006] The technical problem of this invention is solved by the following solution: In a first aspect, the present invention provides a 2.5D substrate packaging structure, comprising: A substrate wafer includes a first substrate chip, a second substrate chip, and a substrate layer that are integrally formed. The substrate layer is located between the first substrate chip and the second substrate chip, and a receiving groove is provided on the back side of the substrate layer. A substitute chip is mounted in the receiving groove on its back side, and the front side of the substitute chip is flush with the back side of the substrate wafer. A substrate wiring layer is disposed on the back side of the substrate wafer and covers the receiving groove and the front side of the substitute chip, wherein the substitute chip is electrically connected to the substrate wiring layer; A redistribution layer is disposed on the front side of the substrate wafer and electrically connected to the first substrate chip and the second substrate chip; The substrate layer is further provided with a first conductive post, which penetrates the substrate layer and is spaced apart from the receiving groove. The substrate wiring layer is electrically connected to the redistribution layer through the first conductive post.

[0007] In an optional embodiment, the receiving groove extends to the sidewall of the first substrate chip or the second substrate chip, and the substitute chip is spaced apart from both the first substrate chip and the second substrate chip.

[0008] In an optional embodiment, the substrate packaging structure further includes a stacked chip and a molding compound, wherein the stacked chip is disposed on the redistribution layer and electrically connected to the redistribution layer, and the molding compound is disposed on the redistribution layer and covers the stacked chip.

[0009] In an optional embodiment, the substrate wiring layer includes a substrate dielectric layer, a substrate metal layer, a substrate protective layer, and substrate pads. The substrate dielectric layer is disposed on the back side of the substrate wafer and fills the receiving groove so that the substrate dielectric layer covers the sidewalls and front side of the substitute chip. The substrate metal layer is disposed in the substrate dielectric layer and is electrically connected to the substitute chip and the first conductive pillar. The substrate protective layer is disposed on the side of the substrate dielectric layer away from the redistribution layer. The substrate pads are disposed in the substrate protective layer and are provided with solder balls.

[0010] In an optional embodiment, the 2.5D substrate package structure further includes an integrated chip, the front side of which overlaps the front side of the substitute chip and is electrically connected to both the redistribution layer and the substitute chip, and the substrate wiring layer is disposed on the back side of the integrated chip.

[0011] In an optional embodiment, the front side of the substitute chip is further provided with conductive bumps, the conductive bumps are flush with the back side of the integrated chip, and the substrate wiring layer is electrically connected to the substitute chip through the conductive bumps. The back side of the substrate wafer is further provided with conductive extension pillars, the conductive extension pillars are connected to the first conductive pillars, and the first conductive pillars are electrically connected to the substrate wiring layer through the conductive extension pillars.

[0012] In an optional embodiment, the receiving groove is further filled with an integrated dielectric layer, which covers the substitute chip, the integrated chip, the conductive bumps and the conductive extension pillars, and covers the back side of the substrate wafer. The substrate wiring layer is disposed on the side of the integrated dielectric layer away from the redistribution layer.

[0013] In an optional embodiment, a second conductive pillar is further provided in the substrate wafer. The second conductive pillar is located in the receiving groove and penetrates the substrate wafer. The redistribution layer is electrically connected to the second conductive pillar. A guiding electrical pillar is further provided on the front side of the integrated chip. The guiding electrical pillar is spaced apart from the integrated chip and correspondingly connected to the second conductive pillar, so that the integrated chip is electrically connected to the redistribution layer.

[0014] Secondly, the present invention provides a method for fabricating a 2.5D substrate packaging structure, used to fabricate the 2.5D substrate packaging structure as described in the foregoing embodiments, the method comprising: A substrate wafer is provided, wherein the substrate wafer has a first substrate chip, a second substrate chip, and a substrate layer, the substrate layer being located between the first substrate chip and the second substrate chip; A groove is formed on the back side of the base layer to create a receiving recess; The back side of the substitute chip is attached to the receiving groove, wherein the front side of the substitute chip is flush with the back side of the substrate wafer; A first conductive post is formed in the substrate layer, wherein the first conductive post penetrates the substrate layer and is spaced apart from the receiving groove; A substrate wiring layer is formed on the back side of the substrate wafer, wherein the substrate wiring layer is electrically connected to the first conductive pillar; A redistribution layer is formed on the front side of the substrate wafer, wherein the redistribution layer is electrically connected to both the first substrate chip and the second substrate chip, and is electrically connected to the substrate wiring layer through the first conductive post.

[0015] In an optional embodiment, prior to the step of forming a substrate wiring layer on the back side of the substrate wafer, the method further includes: An integrated chip is mounted on the front side of the substitute chip, wherein the front side of the integrated chip overlaps with the front side of the substitute chip. An integrated dielectric layer is filled in the receiving groove, wherein the integrated dielectric layer covers the substitute chip and the integrated chip, and covers the back side of the substrate wafer.

[0016] In an optional embodiment, after the step of forming a redistribution layer on the front side of the substrate wafer, the method further includes: A stacked chip is mounted on the redistribution layer, wherein the stacked chip is electrically connected to the redistribution layer; A molding compound is formed on the redistribution layer, wherein the molding compound covers the stacked chips.

[0017] The beneficial effects of the embodiments of the present invention include: The 2.5D substrate packaging structure and its fabrication method provided in this invention integrate a first substrate chip, a second substrate chip, and a substrate layer to form a substrate wafer, with the substrate layer located between the first and second substrate chips. This direct wafer packaging avoids the conventional approach of first dicing the wafer into individual chips and then packaging them. Furthermore, a receiving groove is provided on the back side of the substrate layer, in which a substitute chip is mounted, with the mounting direction of the substitute chip exactly opposite to that of the first and second substrate chips. A redistribution layer and a substrate wiring layer are respectively provided on the front and back sides of the substrate wafer. A first conductive pillar is also provided in the substrate layer, enabling electrical connection between the redistribution layer and the substrate wiring layer.

[0018] Compared to existing technologies, the 2.5D substrate packaging structure and its fabrication method provided in this invention directly position the first and second substrate chips using an integrally formed substrate layer, ensuring packaging positioning accuracy. Simultaneously, the substitute chip is mounted in the opposite direction to the first and second substrate chips, with double-sided wiring achieved through a substrate wiring layer and a redistribution layer. This reduces the chip's wiring layer density and mitigates leakage caused by parasitic inductance, which can lead to short circuits and overheating between wiring layers. Furthermore, by directly forming the first conductive pillar in the substrate layer to achieve double-sided wiring electrical connection, the warping and delamination problems associated with conventional technologies are avoided, ensuring the structural reliability of the packaged chip. Attached Figure Description

[0019] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 A schematic diagram of the 2.5D substrate packaging structure provided in the first embodiment of the present invention; Figure 2 This is a schematic diagram of the structure corresponding to step S1 in the fabrication method of the 2.5D substrate packaging structure provided in the first embodiment of the present invention; Figure 3 This is a schematic diagram of the structure corresponding to step S2 in the fabrication method of the 2.5D substrate packaging structure provided in the first embodiment of the present invention; Figure 4 This is a schematic diagram of the structure corresponding to step S3 in the fabrication method of the 2.5D substrate packaging structure provided in the first embodiment of the present invention; Figure 5This is a schematic diagram of the structure corresponding to step S4 in the fabrication method of the 2.5D substrate packaging structure provided in the first embodiment of the present invention; Figure 6 This is a schematic diagram of the structure corresponding to step S5 in the fabrication method of the 2.5D substrate packaging structure provided in the first embodiment of the present invention; Figure 7 This is a schematic diagram of the structure corresponding to step S6 in the fabrication method of the 2.5D substrate packaging structure provided in the first embodiment of the present invention; Figure 8 This is a schematic diagram of the structure corresponding to step S7 in the fabrication method of the 2.5D substrate packaging structure provided in the first embodiment of the present invention; Figure 9 This is a schematic diagram of the structure corresponding to step S8 in the fabrication method of the 2.5D substrate packaging structure provided in the first embodiment of the present invention; Figure 10 A schematic diagram of a 2.5D substrate packaging structure provided in the second embodiment of the present invention; Figure 11 This is a schematic diagram of the structure corresponding to step S4 in the fabrication method of the 2.5D substrate packaging structure provided in the second embodiment of the present invention; Figure 12 This is a schematic diagram of the structure corresponding to step S5 in the fabrication method of the 2.5D substrate packaging structure provided in the second embodiment of the present invention; Figure 13 This is a schematic diagram of the structure corresponding to step S6 in the fabrication method of the 2.5D substrate packaging structure provided in the second embodiment of the present invention; Figure 14 This is a schematic diagram of the structure corresponding to step S7 in the fabrication method of the 2.5D substrate packaging structure provided in the second embodiment of the present invention; Figure 15 This is a schematic diagram of step S8 in the method for preparing the 2.5D substrate packaging structure provided in the second embodiment of the present invention.

[0021] Icons: 100 - 2.5D substrate package structure; 110 - Substrate wafer; 111 - First substrate chip; 112 - Second substrate chip; 113 - Substrate layer; 114 - Receiving groove; 115 - First conductive pillar; 116 - Second conductive pillar; 117 - Conductive extension pillar; 120 - Replacement chip; 121 - Conductive protrusion; 130 - Substrate wiring layer; 131 - Substrate dielectric layer; 132 - Substrate metal layer; 133 - Substrate protective layer; 134 - Substrate pad; 140 - Redistribution layer; 150 - Stacked chips; 160 - Molding layer; 170 - Integrated chip; 171 - Conductor electrical pillar; 180 - Integrated dielectric layer; 200 - Carrier. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0023] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0024] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0025] In the description of this invention, it should be noted that if terms such as "upper," "lower," "inner," or "outer" are used to indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the product of this invention is usually placed, they are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this invention.

[0026] Furthermore, the terms "first" and "second" are used only to distinguish descriptions and should not be interpreted as indicating or implying relative importance.

[0027] As disclosed in the background section, conventional reconfigurable wafer packaging technology, due to the requirements of reconfigurable wafers, integrates multiple chips together. Since the multiple chips are oriented in the same direction, wiring can only be performed on one side. This leads to an increase in wiring layer density, resulting in parasitic inductance, leakage current, short circuits between wiring layers, overheating, and other phenomena.

[0028] Furthermore, conventional reconfigurable wafer packaging technology typically involves cutting the chip from the wafer into individual chips and then positioning and mounting them onto a carrier, which can lead to inaccurate chip mounting and positioning.

[0029] Furthermore, conventional reconfigurable wafer packaging technology typically requires a molding compound to encapsulate the chips after multiple chips are mounted, and conductive pillars are placed within the molding compound to achieve electrical connections for multi-layer wiring. These conductive pillars are created using a laser grooving process, which generates significant heat. Since the thermal expansion coefficient of the molding compound differs from that of the silicon-based chip, thermal stress can easily concentrate internally, leading to delamination or warping of the molding compound and affecting the structural reliability of the packaged chip.

[0030] To address the aforementioned issues, embodiments of the present invention provide a novel 2.5D substrate packaging structure and a method for fabricating the 2.5D substrate packaging structure. It should be noted that, unless otherwise specified, the features in the embodiments of the present invention can be combined with each other.

[0031] First Embodiment See Figure 1 This invention provides a 2.5D substrate packaging structure 100, which can reduce wiring density, mitigate leakage caused by parasitic inductance, and avoid mold warping and delamination problems, thus ensuring the structural reliability of the packaged chip. It also improves packaging efficiency, provides better chip mounting and positioning, and enables multi-chip integration.

[0032] The 2.5D substrate packaging structure 100 provided in this embodiment of the invention includes a substrate wafer 110, a substitute chip 120, a substrate wiring layer 130, and a redistribution layer 140. The substrate wafer 110 includes a first substrate chip 111, a second substrate chip 112, and a substrate layer 113 integrally formed. The substrate layer 113 is located between the first substrate chip 111 and the second substrate chip 112, and a receiving groove 114 is provided on the back side of the substrate layer 113. The back side of the substitute chip 120 is attached to the receiving groove 114, and the front side of the substitute chip 120 is flush with the back side of the substrate wafer 110. The substrate wiring layer 130 is disposed on the back side of the substrate wafer 110 and covers the receiving groove 114 and the front side of the substitute chip 120. The substitute chip 120 is electrically connected to the substrate wiring layer 130. The redistribution layer 140 is disposed on the front side of the substrate wafer 110 and is electrically connected to the first substrate chip 111 and the second substrate chip 112. The substrate layer 113 is further provided with a first conductive post 115, which penetrates the substrate layer 113 and is spaced apart from the receiving groove 114. The substrate wiring layer 130 is electrically connected to the redistribution layer 140 through the first conductive post 115.

[0033] It should be noted that, in the embodiments of the present invention, the front side of the substitute chip 120 refers to the surface of the substitute chip 120 with solder pads (PADs), which enables electrical connection. The front side of the substrate wafer 110 mentioned in the embodiments of the present invention refers to the surface of the first substrate chip 111 and the second substrate chip 112 with solder pads (PADs), that is, the front sides of the first substrate chip 111, the second substrate chip 112, and the substrate layer 113 are located on the same surface. The back side mentioned in the embodiments of the present invention is opposite to the front side.

[0034] In this embodiment of the invention, the substrate wafer 110 can be a silicon substrate wafer or a silicon carbide substrate wafer. Transistors are designed on the substrate wafer 110, meaning the substrate layer can be silicon or silicon carbide, preferably silicon. Of course, the substrate layer can also be other III-V compounds, such as GaN, SiN, SiO2, etc., and is not specifically limited here.

[0035] It is worth noting that, in this embodiment of the invention, the first substrate chip 111, the second substrate chip 112, and the substrate layer 113 are configured as a single unit to form the substrate wafer 110. This means the wafer can be mounted without being diced into individual chips. Furthermore, the substrate layer 113 is located between the first substrate chip 111 and the second substrate chip 112, employing direct wafer packaging. This avoids the conventional approach of dicing into individual chips before packaging, significantly improving packaging efficiency. Moreover, the integrated substrate layer 113 directly positions the first substrate chip 111 and the second substrate chip 112, ensuring packaging positioning accuracy. Additionally, a receiving groove 114 is provided on the back side of the substrate layer 113, in which a replacement chip 120 is mounted, improving chip integration and achieving heterogeneous multi-chip integration. Furthermore, the mounting direction of the substitute chip 120 is exactly opposite to that of the first substrate chip 111 and the second substrate chip 112. Meanwhile, a redistribution layer 140 and a base wiring layer 130 are respectively provided on the front and back sides of the substrate wafer 110. A first conductive post 115 is also provided in the base layer 113. This first conductive post 115 enables electrical connection between the redistribution layer 140 and the base wiring layer 130, achieving double-sided wiring and reducing wiring density. Simultaneously, the substitute chip 120 is mounted in the opposite direction to the first substrate chip 111 and the second substrate chip 112, with double-sided wiring achieved by the base wiring layer 130 and the redistribution layer 140, reducing the wiring layer density of the chip and mitigating leakage caused by parasitic inductance, which can lead to short circuits and overheating between wiring layers. In addition, by directly forming the first conductive post 115 in the base layer 113 to achieve double-sided wiring electrical connection, the warping and delamination problems of conventional molding processes are avoided, ensuring the structural reliability of the packaged chip.

[0036] It should also be noted that the receiving groove 114 can be formed here through a half-cutting process. The receiving groove 114 does not penetrate the substrate layer 113, thus avoiding damage to the overall substrate wafer 110 and preventing any impact on the positioning accuracy of the first substrate chip 111 and the second substrate chip 112. The first substrate chip 111 and the second substrate chip 112 are chips of the same type or different types on the same wafer, and the substrate layer 113 is an ineffective region between adjacent chips (without chip transistors, such as a test area or a traditional dicing area). Alternatively, the substrate layer 113 can also include a single chip that fails inspection; it does not participate in subsequent electrical connections and wiring, but only serves a structural support function.

[0037] In this embodiment, the receiving groove 114 extends to the sidewall of the first substrate chip 111 or the second substrate chip 112, and the substitute chip 120 is spaced apart from both the first substrate chip and the second substrate chip 112. Specifically, the receiving groove 114 can use the first substrate chip 111 or the second substrate chip 112 as a cutting alignment mark, thereby ensuring that the slotting position of the receiving groove 114 avoids the first substrate chip 111 and the second substrate chip 112, and avoids affecting the normal performance of the first substrate chip 111 and the second substrate chip 112.

[0038] In this embodiment, the substrate packaging structure further includes stacked chips 150 and a molding compound 160. The stacked chips 150 are disposed on and electrically connected to the redistribution layer 140. The molding compound 160 is disposed on the redistribution layer 140 and covers the stacked chips 150. Specifically, there can be multiple stacked chips 150, and the multiple stacked chips 150 can correspond to the positions of the first substrate chip 111, the second substrate chip 112, and the substitute chip 120, respectively. The molding compound 160 covers the multiple stacked chips 150 and can provide protection. The stacked chips 150 can be flip chips. By setting up stacked chips 150, the chip integration of the packaging structure can be improved.

[0039] In this embodiment, the substrate wiring layer 130 includes a substrate dielectric layer 131, a substrate metal layer 132, a substrate protective layer 133, and substrate pads 134. The substrate dielectric layer 131 is disposed on the back side of the substrate wafer 110 and fills the receiving groove 114 so that the substrate dielectric layer 131 covers the sidewalls and front side of the substitute chip 120. The substrate metal layer 132 is disposed in the substrate dielectric layer 131 and is electrically connected to the substitute chip 120 and the first conductive pillar 115. The substrate protective layer 133 is disposed on the side of the substrate dielectric layer 131 away from the redistribution layer 140. The substrate pads 134 are disposed in the substrate protective layer 133 and are provided with solder balls. Specifically, the substrate dielectric layer 131 can fill the receiving groove 114 so that the substrate dielectric layer 131 can cover the substitute chip 120. The substrate metal layer 132 can be formed by electroplating metal after patterning the surface of the substrate dielectric layer 131, and the substrate metal layer 132 can be a copper layer, which is directly electrically connected to the substitute chip 120. The base protective layer 133 can cover the base metal layer 132, which can also be a dielectric material. Then, after slotting, a copper layer is electroplated to form an exposed base pad 134. Finally, solder balls are planted on the base pad 134 to form solder balls.

[0040] Furthermore, the redistribution layer 140 includes a stacked dielectric layer, a stacked metal layer, a stacked protective layer, and stacked pads. The stacked dielectric layer is disposed on the front side of the substrate wafer 110, and a stacked metal layer is formed by electroplating after patterning openings. The stacked metal layer is located in the stacked dielectric layer and is electrically connected to the first substrate chip 111 and the second substrate chip 112. The stacked protective layer is disposed on the stacked dielectric layer and covers the stacked metal layer. It can also be a dielectric material. Then, copper layers are electroplated after slotting to form exposed stacked pads. Finally, flip-chip stacked 150 can be soldered and fixed on the stacked pads.

[0041] This invention also provides a method for fabricating a 2.5D substrate packaging structure 100, which includes the following steps: S1: Provide a substrate wafer 110.

[0042] See also Figure 2 Specifically, the substrate wafer 110 can first be mounted on a carrier 200. For example, a bonding adhesive layer can be coated on the surface of the carrier 200 (this bonding adhesive layer can be debonded by irradiation with UV light). The substrate wafer 110 has a first substrate chip 111, a second substrate chip 112, and a base layer 113, with the base layer 113 located between the first substrate chip 111 and the second substrate chip 112. The carrier 200 can be made of materials such as glass, silicon oxide, or metal. By setting the carrier 200, it can support the substrate wafer 110 and prevent the wafer from cracking. Of course, when the wafer thickness is sufficient, the carrier 200 can be omitted, and step S2 can be performed directly.

[0043] S2: A groove 114 is formed on the back side of the base layer 113.

[0044] See also Figure 3 Specifically, the substrate layer 113 of the substrate wafer 110 can be partially cut along a predetermined dicing path using a diamond dicing process to form the receiving groove 114. The cutting can be performed along the side edge of the first substrate chip 111 to ensure cutting accuracy. Alternatively, in other preferred embodiments of the invention, the receiving groove 114 can also be formed using an etching process.

[0045] S3: The back side of the substitute chip 120 is attached to the receiving groove 114, wherein the front side of the substitute chip 120 is flush with the back side of the substrate wafer 110.

[0046] See also Figure 4 Specifically, the substitute chip 120 is mounted face down in the receiving groove 114 using a surface mount process, and the thickness of the substitute chip 120 is adapted to the depth of the receiving groove 114, so that the front of the substitute chip 120 is flush with the back of the substrate wafer 110.

[0047] S4: A first conductive post 115 is formed in the substrate layer 113, wherein the first conductive post 115 penetrates the substrate layer 113 and is spaced apart from the receiving groove 114.

[0048] See also Figure 5 Specifically, a conductive via can be formed by etching in an area of ​​the substrate 113 where no grooves are cut, and then the conductive via can penetrate the substrate 113. The first conductive pillar 115 can then be formed by electroplating.

[0049] It should be noted that the fabrication process of the first conductive pillar 115 can refer to existing TSV (Through-Silicon Via) technology. Furthermore, the etching process employed in this embodiment of the invention can further avoid the thermal stress problems caused by traditional laser-driven apertures, solve the warping and delamination problems between adjacent substrate chips, and simultaneously protect the conductive pillars and mitigate warping and delamination at the conductive pillar junctions.

[0050] S5: A substrate wiring layer 130 is formed on the back side of the substrate wafer 110, wherein the substrate wiring layer 130 is electrically connected to the first conductive pillar 115.

[0051] See also Figure 6Specifically, a layer of dielectric material can be spin-coated first, baked, and shaped to form a base dielectric layer 131. This base dielectric layer 131 covers the back side of the base wafer 110 and fills the receiving groove 114, enclosing the substitute chip 120. Then, a pattern is formed on the base dielectric layer 131 through an exposure and development process to form a patterned opening that exposes the solder pads and the first conductive pillar 115 of the substitute chip 120. Then, a metal layer (preferably a copper layer) is electroplated in the patterned opening to form a base metal layer 132, which is electrically connected to the substitute chip 120 and the first conductive pillar 115. Another layer of dielectric material is spin-coated, baked, and shaped to form a base protective layer 133. Finally, grooves are cut in the base protective layer 133 to expose the base metal layer 132, and metal is electroplated to form base pads 134, which are then formed into solder balls through a ball-mounting process.

[0052] S6: A redistribution layer 140 is formed on the front side of the substrate wafer 110, wherein the redistribution layer 140 is electrically connected to the first substrate chip 111 and the second substrate chip 112, and is electrically connected to the substrate wiring layer 130 through the first conductive post 115.

[0053] See also Figure 7 Specifically, a carrier 200 can first be attached to the substrate wiring layer 130 (also bonded using bonding adhesive), and then the carrier 200 on the front side of the substrate wafer 110 can be removed by irradiating with UV light to expose the bonding pads on the front side of the first substrate chip 111 and the second substrate chip 112. A redistribution layer 140 is then formed again through a wiring process.

[0054] Furthermore, when forming the redistribution layer 140, a dielectric material can first be spin-coated onto the front side of the substrate wafer 110 and cured to form a stacked dielectric layer. Then, a patterning process is used to pattern the stacked dielectric layer to form patterned openings that expose the pads on the front side of the first substrate chip 111 and the second substrate chip 112. A metal layer (preferably copper) is then electroplated into the patterned openings to form a stacked metal layer, which is electrically connected to both the first substrate chip 111 and the second substrate chip 112. After spin-coating another layer of dielectric material and baking, a stacked protective layer is formed. Finally, grooves are cut into the stacked protective layer to expose the stacked metal layer, and metal is electroplated to form stacked pads.

[0055] S7: Attach stacked chip 150 on redistribution layer 140, wherein stacked chip 150 is electrically connected to redistribution layer 140.

[0056] See also Figure 8Specifically, multiple stacked chips 150 are soldered and fixed on the stacked pads of the redistribution layer 140 using a flip-chip process, and the multiple stacked chips 150 correspond to the positions of the first base chip 111, the second base chip 112 and the substitute chip 120, respectively.

[0057] S8: A molding compound 160 is formed on the redistribution layer 140, wherein the molding compound 160 covers the stacked chip 150.

[0058] See Figure 9 Specifically, a molding compound 160 can be formed on the redistribution layer 140 using a molding process. This molding compound 160 can cover the stacked chips 150, providing protection. Finally, the carrier 200 can be debonded and removed, and the individual products can be cut to obtain individual products.

[0059] In summary, the 2.5D substrate packaging structure 100 and its fabrication method provided in this embodiment of the invention integrate a first substrate chip 111, a second substrate chip 112, and a substrate layer 113 to form a substrate wafer 110, with the substrate layer 113 located between the first substrate chip 111 and the second substrate chip 112. This direct wafer packaging avoids the conventional approach of first dicing the wafer into individual chips and then packaging them. Furthermore, a receiving groove 114 is provided on the back side of the substrate layer 113, in which a substitute chip 120 is mounted, with the mounting direction of the substitute chip 120 exactly opposite to that of the first substrate chip 111 and the second substrate chip 112. A redistribution layer 140 and a substrate wiring layer 130 are respectively provided on the front and back sides of the substrate wafer 110. A first conductive post 115 is also provided in the substrate layer 113, enabling electrical connection between the redistribution layer 140 and the substrate wiring layer 130. Compared to existing technologies, the 2.5D substrate packaging structure 100 and its fabrication method provided in this embodiment of the invention directly position the first substrate chip 111 and the second substrate chip 112 using an integrally formed substrate layer 113, ensuring packaging positioning accuracy. Simultaneously, the substitute chip 120 is mounted in the opposite direction to the first substrate chip 111 and the second substrate chip 112, with dual-sided wiring achieved by a substrate wiring layer 130 and a redistribution layer 140. This reduces the wiring layer density of the chip and mitigates leakage caused by parasitic inductance, which can lead to short circuits and overheating between wiring layers. Furthermore, by directly forming the first conductive pillar 115 in the substrate layer 113 to achieve dual-sided wiring electrical connection, the warping and delamination problems of conventional molding processes are avoided, ensuring the structural reliability of the packaged chip.

[0060] Second Embodiment See Figure 10This invention provides a 2.5D substrate packaging structure 100, whose basic structure, principle and technical effects are the same as those of the first embodiment. For the sake of brevity, any parts not mentioned in this embodiment can be referred to the corresponding content in the first embodiment.

[0061] In this embodiment of the invention, the 2.5D substrate package structure 100 further includes an integrated chip 170. The front side of the integrated chip 170 overlaps with the front side of the substitute chip 120 and is electrically connected to both the redistribution layer 140 and the substitute chip 120. The substrate wiring layer 130 is disposed on the back side of the integrated chip 170. Specifically, the size and thickness of the integrated chip 170 are smaller than those of the substitute chip 120, and one end of the integrated chip 170 overlaps with the front side of the substitute chip 120, while the other end extends toward the first substrate chip 111. By providing the integrated chip 170, the chip integration density can be improved.

[0062] In some embodiments, the front side of the substitute chip 120 is further provided with conductive protrusions 121, which are flush with the back side of the integrated chip 170. The substrate wiring layer 130 is electrically connected to the substitute chip 120 through the conductive protrusions 121. The back side of the substrate wafer 110 is further provided with conductive extension pillars 117, which are connected to the first conductive pillar 115. The first conductive pillar 115 is electrically connected to the substrate wiring layer 130 through the conductive extension pillars 117. Specifically, the conductive protrusions 121 are bonded to the substrate metal layer 132 of the substrate wiring layer 130, thereby realizing the electrical connection between the substitute chip 120 and the substrate wiring layer 130. The conductive extension pillars 117 can realize the electrical connection between the first conductive pillar 115 and the substrate wiring layer 130.

[0063] Furthermore, an integrated dielectric layer 180 is also filled in the receiving groove 114. The integrated dielectric layer 180 covers the substitute chip 120, the integrated chip 170, the conductive bumps 121, and the conductive extension pillars 117, and covers the back side of the substrate wafer 110. The substrate wiring layer 130 is disposed on the side of the integrated dielectric layer 180 away from the redistribution layer 140. Specifically, the integrated dielectric layer 180 is made of a dielectric material, capable of filling the receiving groove 114 and covering the back side of the substrate wafer 110. Moreover, the back side of the integrated chip 170 can be exposed in the integrated dielectric layer 180, and the surfaces of the integrated chip 170, the conductive bumps 121, the conductive extension pillars 117, and the integrated dielectric layer 180 can be kept flush, thereby ensuring planarization, which is beneficial for the fabrication of the substrate wiring layer 130.

[0064] In some embodiments, a second conductive post 116 is further provided in the substrate wafer 110. The second conductive post 116 is located in the receiving groove 114 and penetrates the substrate wafer 110. The redistribution layer 140 is electrically connected to the second conductive post 116. A guiding electrical post 171 is also provided on the front side of the integrated chip 170. The guiding electrical post 171 is spaced apart from the integrated chip 170 and correspondingly connected to the second conductive post 116, so that the integrated chip 170 and the redistribution layer 140 are electrically connected. Specifically, the second conductive post 116 is offset from the substitute chip 120. The guiding electrical post 171 on the front side of the integrated chip 170 can extend into the receiving groove 114 and connect to the second conductive post 116, so that the integrated chip 170 and the redistribution layer 140 are electrically connected through the guiding electrical post 171 and the second conductive post 116. By providing the second conductive post 116, the electrical connection path between the integrated chip 170 and the redistribution layer 140 can be shortened, which helps to improve transmission efficiency.

[0065] It should be noted that the integrated chip 170 here can be an inductor, voltage regulator, resistor, capacitor, transistor, or diode, which facilitates high-density interconnection and the formation of an integrated circuit (IC) package. The integrated chip 170 also serves as the IC chip within the IC package. The IC chip can be a system-on-a-chip (SoC). The IC chip is electrically coupled to the substrate wiring layer, thereby electrically coupled to other IC chips and / or other components within the IC package. The IC chip can also be electrically coupled to other circuits outside the IC package via electrical connections through the external metal interconnects of the IC package. For example, one or more embedded capacitors can provide decoupling capacitance for the power distribution network (PDN) within the IC package to reduce current resistance (IR) drop. Furthermore, the active wiring layer of the embedded capacitor is positioned between the IC chip and the substrate wiring layer to minimize the distance between the embedded capacitor and the IC chip. This reduces parasitic inductance in the wiring between the embedded capacitor and the IC chip, thereby reducing IR drop in the PDN and also helps reduce PDN noise.

[0066] This invention also provides a method for preparing a 2.5D substrate packaging structure 100. The basic steps, principles and technical effects of this method are the same as those in the first embodiment. For the sake of brevity, any parts not mentioned in this embodiment can be referred to the corresponding content in the first embodiment.

[0067] The method for fabricating the 2.5D substrate packaging structure 100 provided in this embodiment of the invention includes the following steps: S1: Provide a substrate wafer 110.

[0068] S2: A groove 114 is formed on the back side of the base layer 113.

[0069] S3: The back side of the substitute chip 120 is attached to the receiving groove 114, wherein the front side of the substitute chip 120 is flush with the back side of the substrate wafer 110.

[0070] S4: Form a first conductive pillar 115 and a second conductive pillar 116 in the substrate layer 113.

[0071] See Figure 11 The first conductive post 115 penetrates the substrate layer 113 and is spaced apart from the receiving groove 114, while the second conductive post 116 penetrates the substrate layer 113 and is located in the receiving groove 114. Specifically, conductive vias can be formed in and beside the receiving groove 114 by laser grooving, and then the first conductive post 115 and the second conductive post 116 can be formed by electroplating.

[0072] S5: An integrated chip 170 is mounted on the front side of the substitute chip 120, wherein the front side of the integrated chip 170 overlaps with the front side of the substitute chip 120.

[0073] See Figure 12 Specifically, the integrated chip 170 has a guiding electrical post 171 on its front side, which is connected to the second conductive post 116. At the same time, the micro bumps on the front side of the integrated chip 170 are soldered to the pads on the front side of the substitute chip 120 to achieve the docking between the integrated chip 170 and the substitute chip 120.

[0074] S6: An integrated dielectric layer 180 is filled in the receiving groove 114, wherein the integrated dielectric layer 180 covers the substitute chip 120 and the integrated chip 170, and covers the back side of the substrate wafer 110.

[0075] See Figure 13 Specifically, an integrated dielectric layer 180 can be formed by spin coating or deposition processes. This integrated dielectric layer 180 can fill the receiving groove 114 and completely cover the substitute chip 120 and the integrated chip 170. Then, a polishing process is used to expose the back side of the integrated chip 170, reducing the overall package height.

[0076] S7: A substrate wiring layer 130 is formed on the integrated dielectric layer 180, wherein the substrate wiring layer 130 is electrically connected to the first conductive post 115.

[0077] See Figure 14 Specifically, conductive protrusions 121 and conductive extension pillars 117 can first be electroplated in the integrated dielectric layer 180 to expose the electrical connection point between the first conductive pillar 115 and the substitute chip 120. Then, a substrate wiring layer 130 is formed through a wiring process.

[0078] S8: A redistribution layer 140 is formed on the front side of the substrate wafer 110.

[0079] See Figure 15 The redistribution layer 140 is electrically connected to both the first substrate chip 111 and the second substrate chip 112, and is electrically connected to the substrate wiring layer 130 via conductive extension post 117 and first conductive post 115. Simultaneously, the redistribution layer 140 can be electrically connected to the integrated chip 170 via the second conductive post 116 and conductive post 171.

[0080] S9: Attach stacked chip 150 on redistribution layer 140, wherein stacked chip 150 is electrically connected to redistribution layer 140.

[0081] S10: A molding compound 160 is formed on the redistribution layer 140, wherein the molding compound 160 covers the stacked chip 150.

[0082] In summary, the 2.5D substrate package structure 100 and its fabrication method provided in this embodiment of the invention improve chip integration by adding an integrated chip 170. Furthermore, the integrated chip 170 is electrically connected to the redistribution layer 140 via the second conductive post 116, shortening the signal transmission path and improving transmission efficiency. Compared to the prior art, the 2.5D substrate package structure 100 and its fabrication method provided in this embodiment of the invention directly position the first substrate chip 111 and the second substrate chip 112 using an integrally formed substrate layer 113, ensuring package positioning accuracy. Simultaneously, the substitute chip 120 is mounted in the opposite direction to the first substrate chip 111 and the second substrate chip 112, with double-sided wiring achieved by the substrate wiring layer 130 and the redistribution layer 140. This reduces the wiring layer density of the chip and mitigates leakage caused by parasitic inductance, which can lead to short circuits and overheating between wiring layers. Furthermore, by directly forming the first conductive pillar 115 in the substrate layer 113 to achieve bilateral wiring electrical connection, the warping and delamination problems of plastic encapsulation in conventional technologies are avoided, ensuring the structural reliability of the packaged chip. Moreover, it can further improve chip integration and reduce package height.

[0083] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A 2.5D substrate packaging structure, characterized in that, include: A substrate wafer includes a first substrate chip, a second substrate chip, and a substrate layer that are integrally formed. The substrate layer is located between the first substrate chip and the second substrate chip, and a receiving groove is provided on the back side of the substrate layer. A substitute chip is mounted in the receiving groove on its back side, and the front side of the substitute chip is flush with the back side of the substrate wafer. A substrate wiring layer is disposed on the back side of the substrate wafer and covers the receiving groove and the front side of the substitute chip, wherein the substitute chip is electrically connected to the substrate wiring layer; A redistribution layer is disposed on the front side of the substrate wafer and is electrically connected to the first substrate chip and the second substrate chip; The substrate layer is further provided with a first conductive post, which penetrates the substrate layer and is spaced apart from the receiving groove. The substrate wiring layer is electrically connected to the redistribution layer through the first conductive post.

2. The 2.5D substrate packaging structure according to claim 1, characterized in that, The receiving groove extends to the sidewall of the first substrate chip or the second substrate chip, and the substitute chip is spaced apart from both the first substrate chip and the second substrate chip.

3. The 2.5D substrate packaging structure according to claim 1, characterized in that, The substrate packaging structure further includes a stacked chip and a molding compound. The stacked chip is disposed on the redistribution layer and electrically connected to the redistribution layer. The molding compound is disposed on the redistribution layer and covers the stacked chip.

4. The 2.5D substrate packaging structure according to claim 1, characterized in that, The substrate wiring layer includes a substrate dielectric layer, a substrate metal layer, a substrate protective layer, and substrate pads. The substrate dielectric layer is disposed on the back side of the substrate wafer and fills the receiving groove so that the substrate dielectric layer covers the sidewalls and front side of the substitute chip. The substrate metal layer is disposed in the substrate dielectric layer and is electrically connected to the substitute chip and the first conductive pillar. The substrate protective layer is disposed on the side of the substrate dielectric layer away from the redistribution layer. The substrate pads are disposed in the substrate protective layer and are provided with solder balls.

5. The 2.5D substrate packaging structure according to claim 1, characterized in that, The 2.5D substrate packaging structure also includes an integrated chip, the front side of which overlaps with the front side of the substitute chip and is electrically connected to both the redistribution layer and the substitute chip. The substrate wiring layer is disposed on the back side of the integrated chip.

6. The 2.5D substrate packaging structure according to claim 5, characterized in that, The front side of the substitute chip is also provided with conductive protrusions, which are flush with the back side of the integrated chip. The substrate wiring layer is electrically connected to the substitute chip through the conductive protrusions. The back side of the substrate wafer is also provided with conductive extension pillars, which are connected to the first conductive pillars. The first conductive pillars are electrically connected to the substrate wiring layer through the conductive extension pillars.

7. The 2.5D substrate packaging structure according to claim 6, characterized in that, The receiving groove is further filled with an integrated dielectric layer, which covers the substitute chip, the integrated chip, the conductive protrusions and the conductive extension pillars, and covers the back side of the substrate wafer. The substrate wiring layer is disposed on the side of the integrated dielectric layer away from the redistribution layer.

8. The 2.5D substrate packaging structure according to claim 5, characterized in that, The substrate wafer is further provided with a second conductive pillar, which is located in the receiving groove and penetrates the substrate wafer. The redistribution layer is electrically connected to the second conductive pillar. The front side of the integrated chip is also provided with a guiding electrical pillar, which is spaced apart from the integrated chip and correspondingly connected to the second conductive pillar, so that the integrated chip is electrically connected to the redistribution layer.

9. A method for fabricating a 2.5D substrate packaging structure, used to fabricate the 2.5D substrate packaging structure as described in claim 1, characterized in that, The method includes: A substrate wafer is provided, wherein the substrate wafer has a first substrate chip, a second substrate chip, and a substrate layer, the substrate layer being located between the first substrate chip and the second substrate chip; A receiving groove is formed by slotting on the back side of the base layer; The back side of the substitute chip is attached to the receiving groove, wherein the front side of the substitute chip is flush with the back side of the substrate wafer; A first conductive post is formed in the substrate layer, wherein the first conductive post penetrates the substrate layer and is spaced apart from the receiving groove; A substrate wiring layer is formed on the back side of the substrate wafer, wherein the substrate wiring layer is electrically connected to the first conductive pillar; A redistribution layer is formed on the front side of the substrate wafer, wherein the redistribution layer is electrically connected to both the first substrate chip and the second substrate chip, and is electrically connected to the substrate wiring layer through the first conductive post.

10. The method for fabricating a 2.5D substrate packaging structure according to claim 9, characterized in that, Prior to the step of forming a substrate wiring layer on the back side of the substrate wafer, the method further includes: An integrated chip is mounted on the front side of the substitute chip, wherein the front side of the integrated chip overlaps the front side of the substitute chip. An integrated dielectric layer is filled in the receiving groove, wherein the integrated dielectric layer covers the substitute chip and the integrated chip, and covers the back side of the substrate wafer.

11. The method for fabricating a 2.5D substrate packaging structure according to claim 9, characterized in that, After the step of forming a redistribution layer on the front side of the substrate wafer, the method further includes: A stacked chip is mounted on the redistribution layer, wherein the stacked chip is electrically connected to the redistribution layer; A molding compound is formed on the redistribution layer, wherein the molding compound covers the stacked chips.

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