2.5d substrate package structure and method of manufacturing a 2.5d substrate package structure

Abstract

This invention provides a 2.5D substrate packaging structure and a method for fabricating the 2.5D substrate packaging structure, relating to the field of chip packaging technology. The structure includes a substrate wafer, a first molding compound layer, a substrate wiring layer, a redistribution layer, and a first mounted chip. A receiving groove is provided on the back side of the substrate layer of the substrate wafer, and a first metal layer is provided on the bottom wall of the receiving groove. The back side of the first mounted chip is at least partially attached to the first metal layer. The substrate wiring layer is disposed on the back side of the substrate wafer. The redistribution layer is disposed on the front side of the substrate wafer. A first conductive pillar is also provided in the substrate layer, and the substrate wiring layer is electrically connected to the redistribution layer through the first conductive pillar. Compared with the prior art, this invention ensures packaging positioning accuracy. Furthermore, by providing the first metal layer, heat dissipation capacity can be improved, resulting in uniform heat dissipation and controllable temperature, avoiding molding compound warpage and delamination problems, and ensuring the structural reliability of the packaged chip.

Description

Technical Field

[0001] This invention relates to the field of chip packaging technology, and more specifically, to a 2.5D substrate packaging structure and a method for fabricating the 2.5D substrate packaging structure. Background Technology

[0002] Traditional reconfigurable wafer-level packaging technology typically involves cutting individual chips from a wafer, mounting them onto a carrier wafer for reconfiguration, and then performing wiring. Its main advantages include high-density integration, small package size, superior product performance, and high signal transmission frequency.

[0003] Conventional reconfigurable wafer packaging technologies typically require a molding compound to encapsulate the chip, with conductive pillars within the compound to achieve multi-layer wiring and electrical connections. However, the thermal expansion coefficient of the molding compound differs from that of the silicon-based chip, easily leading to internal thermal stress concentration and causing delamination or warping, thus affecting the structural reliability of the packaged chip. Furthermore, with the increasing number of integrated chips in existing packaging structures, heat generation in the chip and wiring areas increases and becomes uneven, resulting in decreased temperature controllability. This further exacerbates problems such as warping, delamination, RDL cracking, and bump fatigue caused by thermal expansion and contraction. Summary of the Invention

[0004] The purpose of this invention is to provide a 2.5D substrate packaging structure and a method for preparing the 2.5D substrate packaging structure, which can improve heat dissipation capacity, make heat dissipation uniform and temperature controllable, avoid plastic encapsulation warping and delamination problems, and ensure the structural reliability of the packaged chip.

[0005] In a first aspect, the present invention provides a 2.5D substrate packaging structure, comprising: A substrate wafer includes a first substrate chip, a second substrate chip, and a substrate layer that are integrally formed. The substrate layer is located between the first substrate chip and the second substrate chip, and a receiving groove is provided on the back side of the substrate layer. A first metal layer is provided on the bottom wall of the receiving groove. At least one first mounting chip is disposed in the receiving groove, and the back side of the first mounting chip is at least partially attached to the first metal layer; A first molding compound is disposed in the receiving groove and covers the first mounted chip, and the first molding compound is flush with the back side of the substrate wafer; A substrate wiring layer is disposed on the back side of the substrate wafer and covers the first molding compound layer; A redistribution layer is disposed on the front side of the substrate wafer and is electrically connected to the first substrate chip and the second substrate chip; The first mounted chip is electrically connected to the substrate wiring layer or the redistribution layer. The substrate layer is further provided with a first conductive post, which penetrates the substrate layer and is spaced apart from the receiving groove. The substrate wiring layer is electrically connected to the redistribution layer through the first conductive post.

[0006] In an optional embodiment, the first mounting chip includes a plurality of first mounting chips, which are spaced apart in the receiving groove. The back side of each first mounting chip is attached to the first metal layer, and the front side of each first mounting chip is exposed to the first molding layer. The substrate wiring layer covers the front side of the first mounting chip and is electrically connected to the first mounting chip.

[0007] In an optional embodiment, the bottom wall of the receiving groove is further provided with a first metal groove, the first metal layer is embedded in the first metal groove, and the thickness of the first metal layer is the same as the depth of the first metal groove.

[0008] In an optional embodiment, a second metal trench is further provided on the front side of the substrate wafer, and a second metal layer is embedded in the second metal trench. The thickness of the second metal layer is the same as the depth of the second metal trench, and the redistribution layer covers the second metal layer.

[0009] In an optional embodiment, the first metal layer is further provided with a first heat dissipation protrusion on the side near the second metal layer, and the first heat dissipation protrusion is spaced apart from the second metal layer; the second metal layer is further provided with a second heat dissipation protrusion on the side near the first metal layer, and the second heat dissipation protrusion is spaced apart from the first metal layer.

[0010] In an optional embodiment, the 2.5D substrate packaging structure further includes a second mounting chip, which is disposed in the receiving groove and spaced apart from the first mounting chip. The back side of the second mounting chip is attached to the first metal layer, and a first connecting line is provided on the front side of the second mounting chip. A second conductive post electrically connected to the redistribution layer is also provided in the substrate layer. The second conductive post corresponds to the receiving groove and is spaced apart from the first metal layer. The first connecting line is connected to the second conductive post, and the second mounting chip is electrically connected to the redistribution layer through the second conductive post.

[0011] In an optional embodiment, the 2.5D substrate packaging structure further includes a third mounting chip, which is disposed in the receiving groove and stacked on the second mounting chip, with the back side of the third mounting chip attached to the front side of the second mounting chip, and the front side of the third mounting chip having a second connection line connected to the second mounting chip.

[0012] In an optional embodiment, the front side of the third mounted chip is further provided with a third connecting line, which extends between the second mounted chip and the first mounted chip and is connected to the first metal layer.

[0013] In an optional embodiment, a first connecting line is provided on the front side of the first mounted chip, and a second conductive post electrically connected to the redistribution layer is also provided in the substrate layer. The second conductive post corresponds to the receiving groove and is spaced apart from the first metal layer. The first connecting line is connected to the second conductive post, and the first mounted chip is electrically connected to the redistribution layer through the second conductive post.

[0014] In an optional embodiment, the 2.5D substrate packaging structure further includes a second mounting chip, the front side of which overlaps with the front side of the first mounting chip and is electrically connected to the first mounting chip, and the front side of the second mounting chip is also provided with an electrical protrusion, which is connected to the first metal layer.

[0015] In an optional embodiment, the back side of the second mounted chip is exposed outside the first molding compound, and a wiring metal layer is further disposed on the back side of the second mounted chip. The substrate wiring layer covers the back side of the second mounted chip and the wiring metal layer, and is electrically connected to the wiring metal layer.

[0016] In an optional embodiment, a stacked chip and a second molding compound are further disposed on the side of the redistribution layer away from the base wiring layer, the stacked chip being electrically connected to the redistribution layer, and the second molding compound covering the stacked chip.

[0017] Secondly, the present invention provides a method for fabricating a 2.5D substrate packaging structure, used to fabricate the 2.5D substrate packaging structure as described in the foregoing embodiments, the method comprising: A substrate wafer is provided, wherein the substrate wafer has a first substrate chip, a second substrate chip, and a substrate layer, the substrate layer being located between the first substrate chip and the second substrate chip; A receiving groove is formed by slotting on the back side of the base layer; A first metal layer is formed on the bottom wall of the receiving groove; The back side of the first mounted chip is attached to the receiving groove, wherein the back side of the first mounted chip is at least partially attached to the first metal layer; A first conductive post is formed in the substrate layer, wherein the first conductive post penetrates the substrate layer and is spaced apart from the receiving groove; A first molding compound is formed by filling the receiving groove, wherein the first molding compound covers the first mounted chip and is flush with the back side of the substrate wafer; A substrate wiring layer is formed on the back side of the substrate wafer, wherein the substrate wiring layer covers the first molding layer; A redistribution layer is formed on the front side of the substrate wafer, wherein the redistribution layer is electrically connected to the first substrate chip and the second substrate chip; The first mounted chip is electrically connected to the substrate wiring layer or the redistribution layer, and the substrate wiring layer is electrically connected to the redistribution layer through the first conductive post.

[0018] In an optional embodiment, the step of forming a first metal layer on the bottom wall of the receiving groove includes: A first metal groove is formed by slotting the bottom wall of the receiving groove; A first metal layer is formed by electroplating in the first metal tank, such that the first metal layer is embedded in the first metal tank, wherein the thickness of the first metal layer is the same as the depth of the first metal tank.

[0019] The beneficial effects of the embodiments of the present invention include: The 2.5D substrate packaging structure and its fabrication method provided in this invention integrate a first substrate chip, a second substrate chip, and a substrate layer to form a substrate wafer, with the substrate layer located between the first and second substrate chips. This direct wafer packaging avoids the conventional approach of first dicing the wafer into individual chips and then packaging them. Simultaneously, a receiving groove is provided on the back side of the substrate layer, in which the first mounting chip is attached. A redistribution layer and a substrate wiring layer are respectively provided on the front and back sides of the substrate wafer. A first conductive pillar is also provided in the substrate layer, enabling electrical connection between the redistribution layer and the substrate wiring layer.

[0020] Compared to existing technologies, the 2.5D substrate wafer packaging structure and its fabrication method provided in this invention directly position the first and second substrate chips through an integrally formed substrate layer, ensuring packaging positioning accuracy. Dual-sided wiring is achieved through a substrate wiring layer and a redistribution layer, reducing the chip's wiring layer density and mitigating leakage caused by parasitic inductance, which can lead to short circuits and overheating between wiring layers. Furthermore, forming a first conductive pillar directly in the substrate layer enables electrical connection of the dual-sided wiring, avoiding the warping and delamination problems associated with conventional technologies and ensuring the structural reliability of the packaged chip. The inclusion of a first metal layer enables heat dissipation of the intermediate chip (i.e., the first mounted chip), improving heat dissipation capacity, resulting in uniform heat dissipation and controllable temperature, thus preventing warping and delamination and ensuring the structural reliability of the packaged chip. Attached Figure Description

[0021] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1a A schematic diagram of the 2.5D substrate packaging structure provided in the first embodiment of the present invention; Figure 1b A schematic diagram of another 2.5D substrate packaging structure provided in the first embodiment of the present invention; Figure 2 This is a schematic diagram of the structure corresponding to step S1 in the fabrication method of the 2.5D substrate packaging structure provided in the first embodiment of the present invention; Figure 3 This is a schematic diagram of the structure corresponding to step S2 in the fabrication method of the 2.5D substrate packaging structure provided in the first embodiment of the present invention; Figure 4 This is a schematic diagram of the structure corresponding to step S3 in the fabrication method of the 2.5D substrate packaging structure provided in the first embodiment of the present invention; Figure 5 This is a schematic diagram of the structure corresponding to step S4 in the fabrication method of the 2.5D substrate packaging structure provided in the first embodiment of the present invention; Figure 6 This is a schematic diagram of the structure corresponding to step S5 in the fabrication method of the 2.5D substrate packaging structure provided in the first embodiment of the present invention; Figure 7 This is a schematic diagram of the structure corresponding to step S6 in the fabrication method of the 2.5D substrate packaging structure provided in the first embodiment of the present invention; Figure 8 This is a schematic diagram of the structure corresponding to step S7 in the fabrication method of the 2.5D substrate packaging structure provided in the first embodiment of the present invention; Figure 9 This is a schematic diagram of the structure corresponding to step S8 in the fabrication method of the 2.5D substrate packaging structure provided in the first embodiment of the present invention; Figure 10 This is a schematic diagram of the structure corresponding to step S9 in the fabrication method of the 2.5D substrate packaging structure provided in the first embodiment of the present invention; Figure 11 A schematic diagram of a 2.5D substrate packaging structure provided in the second embodiment of the present invention; Figure 12 This is a schematic diagram of the structure corresponding to step S3 in the fabrication method of the 2.5D substrate packaging structure provided in the second embodiment of the present invention; Figure 13 This is a schematic diagram of the structure corresponding to step S4 in the fabrication method of the 2.5D substrate packaging structure provided in the second embodiment of the present invention; Figure 14 A schematic diagram of a 2.5D substrate packaging structure provided in the third embodiment of the present invention; Figure 15 This is a schematic diagram of the structure corresponding to step S4 in the fabrication method of the 2.5D substrate packaging structure provided in the third embodiment of the present invention; Figure 16 This is a schematic diagram of step S7 in the method for preparing a 2.5D substrate packaging structure according to the third embodiment of the present invention.

[0023] Icons: 100 - 2.5D substrate package structure; 110 - Substrate wafer; 111 - First substrate chip; 112 - Second substrate chip; 113 - Substrate layer; 114 - Receiving groove; 115 - First metal layer; 1151 - First heat dissipation bump; 116 - First conductive pillar; 117 - Second metal layer; 1171 - Second heat dissipation bump; 118 - Second conductive pillar; 120 - First molding layer; 130 - Substrate wiring layer; 140 - Rewiring layer; 150 - First mounted chip; 160 - Stacked chips; 170 - Second molding layer; 180 - Second mounted chip; 181 - First interconnect; 182 - Wiring metal layer; 183 - Electrical bump; 190 - Third mounted chip; 191 - Second interconnect; 192 - Third interconnect; 200 - Carrier. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0025] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0026] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0027] In the description of this invention, it should be noted that if terms such as "upper," "lower," "inner," or "outer" are used to indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the product of this invention is usually placed, they are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this invention.

[0028] Furthermore, the terms "first" and "second" are used only to distinguish descriptions and should not be interpreted as indicating or implying relative importance.

[0029] As disclosed in the background section, existing reconfigurable wafer packaging technologies typically require cutting individual chips from the wafer and remounting them onto a carrier wafer. This process is prone to misalignment and inaccurate positioning, affecting packaging positioning accuracy. Furthermore, conventional technologies usually utilize a molding compound to encapsulate the chip. When using conductive pillars to achieve bilateral electrical conduction, laser-cut openings are needed in the molding compound to form apertures, followed by electroplating to create the conductive pillars. However, the thermal expansion coefficient of the molding compound differs from that of the silicon-based chip, easily leading to internal thermal stress concentration and causing delamination or warping of the molding compound, thus affecting the structural reliability of the packaged chip.

[0030] Furthermore, with the increase in the number of integrated chips, the existing packaging structure leads to increased and uneven heat distribution in the chip and wiring areas, resulting in decreased temperature controllability. This further leads to problems such as warping, delamination, RDL cracking, and bump fatigue caused by thermal expansion and contraction.

[0031] To address the aforementioned issues, embodiments of the present invention provide a 2.5D substrate packaging structure and a method for fabricating the 2.5D substrate packaging structure. It should be noted that, unless otherwise specified, the features in the embodiments of the present invention can be combined with each other.

[0032] First Embodiment See Figure 1a The present invention provides a 2.5D substrate packaging structure 100 and a method for preparing the 2.5D substrate packaging structure 100, which can improve heat dissipation capacity, make heat dissipation uniform and temperature controllable, avoid plastic encapsulation warping and delamination problems, and ensure the structural reliability of the packaged chip.

[0033] The 2.5D substrate packaging structure 100 provided in this embodiment of the invention includes a substrate wafer 110, a first molding compound 120, a substrate wiring layer 130, a redistribution layer 140, and at least one first mount chip 150. The substrate wafer 110 includes a first substrate chip 111, a second substrate chip 112, and a substrate layer 113 integrally configured. The substrate layer 113 is located between the first substrate chip 111 and the second substrate chip 112, and a receiving groove 114 is provided on the back side of the substrate layer 113. A first metal layer 115 is provided on the bottom wall of the receiving groove 114. At least one first mount chip 150 is disposed in the receiving groove 114, and the back side of the first mount chip 150 is at least partially attached to the first metal layer 115. The first molding compound 120 fills the receiving groove 114 and covers the first mount chip 150, and the first molding compound 120 is flush with the back side of the substrate wafer 110. A substrate wiring layer 130 is disposed on the back side of the substrate wafer 110 and covers the first molding compound layer 120. A redistribution layer 140 is disposed on the front side of the substrate wafer 110 and is electrically connected to the first substrate chip 111 and the second substrate chip 112. The first mount chip 150 is electrically connected to either the substrate wiring layer 130 or the redistribution layer 140. A first conductive post 116 is also disposed in the substrate layer 113, penetrating the substrate layer 113 and spaced apart from the receiving groove 114. The substrate wiring layer 130 is electrically connected to the redistribution layer 140 through the first conductive post 116.

[0034] It should be noted that, in the embodiments of the present invention, the front side of the chip refers to the surface of the chip with solder pads (PADs), which enables electrical connections. Similarly, in the embodiments of the present invention, the front side of the substrate wafer refers to the surface of the first substrate chip 111 and the second substrate chip 112 with solder pads (PADs), meaning the front sides of the first substrate chip 111, the second substrate chip 112, and the substrate layer 113 are located on the same surface. The back side mentioned in the embodiments of the present invention is opposite to the corresponding front side.

[0035] Specifically, the substrate wafer mentioned in the embodiments of the present invention can be a silicon substrate wafer or a silicon carbide substrate wafer. Transistors are designed on the substrate wafer, that is, the substrate layer 113 can be silicon or silicon carbide, preferably silicon. Of course, the substrate layer 113 can also be other III-V compounds, such as GaN, SiN, SiO2, etc., which are not specifically limited here.

[0036] It is worth noting that, in this embodiment of the invention, the first substrate chip 111, the second substrate chip 112, and the substrate layer 113 are integrated to form a substrate wafer 110. This means the wafer can be mounted without being diced into individual chips. Furthermore, the substrate layer 113 is located between the first substrate chip 111 and the second substrate chip 112, employing undicated wafer packaging. This simplifies the process steps and avoids the conventional approach of dicing into individual chips before packaging, significantly improving packaging efficiency. Simultaneously, since the substrate layer 113 is integrated with the first substrate chip 111 and the second substrate chip 112, the first substrate chip 111 and the second substrate chip 112 can be directly positioned using the substrate layer 113, ensuring accurate packaging positioning. Additionally, a receiving groove 114 is provided on the back of the substrate layer 113, allowing the first mounting chip 150 to be mounted within this groove, increasing chip integration and achieving multi-chip integration. A first conductive pillar 116 is also provided in the substrate layer 113. This first conductive pillar 116 enables dual-sided wiring of the substrate wiring layer 130 and the redistribution layer 140, greatly reducing the wiring layer density of the chip and mitigating leakage caused by parasitic inductance, which can lead to short circuits and overheating between wiring layers. Furthermore, forming the first conductive pillar 116 in the substrate layer 113 avoids the negative impact of forming conductive pillars in the molding layer in conventional technologies, avoiding the problems of molding warpage and delamination in conventional technologies, and ensuring the structural reliability of the packaged chip. Further, a first metal layer 115 is arranged in the receiving groove 114, which enables heat dissipation of the intermediate chip (i.e., the first mounted chip 150), improving heat dissipation capacity, making heat dissipation uniform and temperature controllable, further avoiding molding warpage and delamination problems, and ensuring the structural reliability of the packaged chip.

[0037] It should also be noted that the receiving groove 114 can be formed here through a half-cutting process. The receiving groove 114 does not penetrate the substrate layer 113, thus avoiding damage to the overall substrate wafer and preventing any impact on the positioning accuracy of the first substrate chip 111 and the second substrate chip 112. The first substrate chip 111 and the second substrate chip 112 are chips of the same type or different types on the same wafer, and the substrate layer 113 is an ineffective region between adjacent chips (without chip transistors, such as a test area or a traditional dicing area). Alternatively, the substrate layer 113 can also include a single chip that fails inspection; it does not participate in subsequent electrical connections and wiring, but only serves as structural support. The receiving groove 114 can extend to the sidewall of the first substrate chip 111 or the second substrate chip 112, thereby expanding the groove area of ​​the receiving groove 114. However, the receiving groove 114 does not extend to the entire substrate layer 113, thus reserving sufficient area for fabricating the first conductive pillar 116.

[0038] In this embodiment, multiple first-mount chips 150 are spaced apart and disposed in the receiving groove 114. The back side of each first-mount chip 150 is attached to a first metal layer 115, and the front side of each first-mount chip 150 is exposed to a first molding layer 120. A substrate wiring layer 130 covers the front side of the first-mount chip 150 and is electrically connected to it. It should be noted that the first metal layer 115 can be a metal material with good heat dissipation performance, such as a copper layer or an aluminum layer. The back sides of the multiple first-mount chips 150 are attached to the first metal layer 115, for example, by bonding them to the first metal layer 115 with thermally conductive adhesive. This achieves fixation while rapidly conducting the heat generated by the first-mount chips 150 to the first metal layer 115, and then dissipating it through the substrate layer 113. The first metal layer 115 can simultaneously contact the back sides of multiple first-mount chips 150, which also better balances heat and avoids localized heat concentration that could adversely affect the chips.

[0039] It should be noted that the first molding compound 120 can be a molding compound material, and the thickness of the first molding compound 120 is the same as the depth of the receiving groove 114. This allows the solder pads on the front side of the first mounted chip 150 to be exposed through a grinding process, facilitating the fabrication of the substrate wiring layer 130 and enabling electrical connection between the substrate wiring layer 130 and the first mounted chip 150. Of course, in other preferred embodiments of the present invention, the first molding compound 120 can also be replaced with a dielectric material. Furthermore, solder balls are provided on the side of the substrate wiring layer 130 away from the substrate wafer, enabling external electrical connection.

[0040] In this embodiment, the bottom wall of the receiving groove 114 is further provided with a first metal groove, and a first metal layer 115 is embedded in the first metal groove, with the thickness of the first metal layer 115 being the same as the depth of the first metal groove. Specifically, the first metal groove can be formed by further grooving the bottom wall of the receiving groove 114 through etching or laser grooving processes. The size of the first metal groove is smaller than the size of the receiving groove 114, and the first metal layer 115 can be precisely embedded in the first metal groove, ensuring the flatness of the bottom wall of the receiving groove 114 and facilitating the mounting of the first mounting chip 150. Furthermore, by providing the first metal groove, the volume of the metal layer can be effectively reduced, thus reducing the amount of metal used. Of course, in other preferred embodiments of the present invention, the first metal layer 115 can also be directly formed on the bottom wall of the receiving groove 114, and the first metal layer 115 can fill the entire bottom wall of the receiving groove 114.

[0041] Furthermore, a second metal trench is provided on the front side of the substrate wafer, and a second metal layer 117 is embedded in the second metal trench. The thickness of the second metal layer 117 is the same as the depth of the second metal trench, and the redistribution layer 140 covers the second metal layer 117. Specifically, the second metal layer 117 and the first metal layer 115 are respectively disposed on the two sides of the substrate wafer to achieve a double-sided design, separated by wafer material (substrate layer 113). Preferably, the second metal layer 117 is made of the same material as the first metal layer 115, has the same area and shape, and the same thickness. Preferably, the first metal layer 115 and the second metal layer 117 are symmetrically distributed on both sides of the substrate layer 113 to achieve stress balance and avoid cracking caused by the inconsistency of thermal expansion coefficients between the substrate layer 113 and the metal layer due to thermal expansion. In addition, the setting of the second metal trench here can ensure the planarization of the front side of the substrate wafer, which is beneficial for the subsequent fabrication of the redistribution layer 140.

[0042] In this embodiment, a stacked chip 160 and a second molding compound 170 are further disposed on the side of the redistribution layer 140 away from the base wiring layer 130. The stacked chip 160 is electrically connected to the redistribution layer 140, and the second molding compound 170 covers the stacked chip 160. Specifically, the stacked chip 160 is soldered and fixed to the pads on the redistribution layer 140 and protected by the second molding compound 170, thereby improving the chip integration density.

[0043] Further, see Figure 1b In other preferred embodiments of the present invention, a first heat dissipation protrusion 1151 is further provided on the side of the first metal layer 115 near the second metal layer 117, and the first heat dissipation protrusion 1151 is spaced apart from the second metal layer 117; a second heat dissipation protrusion 1171 is further provided on the side of the second metal layer 117 near the first metal layer 115, and the second heat dissipation protrusion 1171 is spaced apart from the first metal layer 115. Specifically, the first heat dissipation protrusion 1151 is integrally formed with the first metal layer 115, and the second heat dissipation protrusion 1171 is integrally formed with the second metal layer 117. The first heat dissipation protrusion 1151 and the second heat dissipation protrusion 1171 can correspond to each other respectively, or they can be staggered. By providing the first heat dissipation protrusion 1151 and the second heat dissipation protrusion 1171, the heat dissipation area of ​​the first metal layer 115 and the second metal layer 117 can be further increased, thereby significantly improving their heat dissipation capacity.

[0044] This invention also provides a method for fabricating a 2.5D substrate wafer packaging structure, used to fabricate the aforementioned 2.5D substrate wafer packaging structure. The method includes the following steps: S1: Provide a substrate wafer.

[0045] See Figure 2The substrate wafer comprises a first substrate chip 111, a second substrate chip 112, and a substrate layer 113, with the substrate layer 113 located between the first substrate chip 111 and the second substrate chip 112. Specifically, the substrate wafer can first be bonded to a carrier 200, for example, by coating the surface of the carrier 200 with a bonding adhesive layer (which can be debonded by irradiation with UV light) before bonding the substrate wafer. The carrier 200 can be made of materials such as glass, silicon oxide, or metal. By setting the carrier 200, it can support the substrate wafer and prevent the wafer from cracking. Of course, when the wafer thickness is sufficient, the carrier 200 can be omitted, and step S2100 can be performed directly.

[0046] S2: A groove 114 is formed on the back side of the base layer 113.

[0047] See Figure 3 Specifically, a half-cutting process can be used, employing a diamond dicing tool to cut the base layer 113 of the substrate wafer along a predetermined cutting path, thereby forming a receiving groove 114. During cutting, the cutting can be performed along the side edge of the first substrate chip 111 or the second substrate chip 112, thus ensuring cutting precision. Of course, in other preferred embodiments of the present invention, the receiving groove 114 can also be formed using an etching process.

[0048] S3: A first metal layer 115 is formed on the bottom wall of the receiving groove 114.

[0049] See Figure 4 Specifically, a first metal groove can be formed by first slotting the bottom wall of the receiving groove 114, and then a first metal layer 115 can be formed by electroplating in the first metal groove so that the first metal layer 115 is embedded in the first metal groove, wherein the thickness of the first metal layer 115 is the same as the depth of the first metal groove. It should be noted that the first metal layer 115 can preferably be a copper layer.

[0050] S4: The back side of the first mounted chip 150 is attached to the receiving groove 114.

[0051] See Figure 5 The back side of the first mounted chip 150 is at least partially attached to the first metal layer 115. Specifically, a surface mount technology can be used to mount the first mounted chip 150 with its back side facing down onto the first metal layer 115 in the receiving groove 114, and the thickness of the first mounted chip 150 is adapted to the depth of the receiving groove 114, so that the front side of the first mounted chip 150 is preferably flush with the back side of the substrate wafer. Multiple first mounted chips 150 can be mounted in the receiving groove 114, with the back side of each first mounted chip 150 attached to the first metal layer 115, using the first metal layer 115 for heat dissipation and structural support.

[0052] S5: Form a first conductive pillar 116 in the substrate layer 113.

[0053] See Figure 6 The first conductive post 116 penetrates the substrate layer 113 and is spaced apart from the receiving groove 114. Specifically, a conductive via can be formed by etching in an area of ​​the substrate layer 113 that is not grooved, thus forming a conductive via that penetrates the substrate layer 113. The first conductive post 116 is then formed by electroplating. It should be noted that the fabrication process of the first conductive post 116 can refer to existing TSV (Through-Silicon Via) technology. Furthermore, in this embodiment of the invention, the substrate layer 113 can protect the conductive post and mitigate warping and delamination at the conductive post junction.

[0054] S6: Fill the receiving groove 114 to form a first molding layer 120.

[0055] See Figure 7 The first molding compound 120 covers the first mounted chip 150 and is flush with the back side of the substrate wafer. Specifically, the first molding compound 120 can be formed on the back side of the substrate wafer using a molding process, and then the first molding compound 120 can be thinned by a grinding process until the first mounted chip 150 is exposed, so that the first molding compound 120 is flush with the back side of the substrate wafer.

[0056] S7: A substrate wiring layer 130 is formed on the back side of the substrate wafer.

[0057] See Figure 8 The substrate wiring layer 130 covers the first molding compound layer 120. Specifically, a layer of dielectric material can be spin-coated first, baked, and shaped to form a substrate dielectric layer. This substrate dielectric layer can cover the back side of the substrate wafer and the first molding compound layer 120, and encapsulate the first mounted chip 150 within it. Then, a pattern is formed on the substrate dielectric layer by an exposure and development process to form a pattern opening. This pattern opening can expose the solder pads and the first conductive pillars 116 of the first mounted chip 150. Then, a metal layer (preferably a copper layer) is electroplated in the pattern opening to form a substrate metal layer. This substrate metal layer is electrically connected to the first mounted chip 150 and the first conductive pillars 116. Another layer of dielectric material is spin-coated, baked, and shaped to form a substrate protective layer. Finally, grooves are cut in the substrate protective layer to expose the substrate metal layer, and metal is electroplated to form substrate pads. Then, solder balls are formed by a ball-mounting process.

[0058] S8: A redistribution layer 140 is formed on the front side of the substrate wafer.

[0059] See Figure 9The redistribution layer 140 is electrically connected to the first substrate chip 111 and the second substrate chip 112. Specifically, another carrier 200 can be first mounted on the substrate wiring layer 130 (also bonded using bonding adhesive), and then the carrier 200 on the front side of the substrate wafer can be removed by irradiating with UV light to expose the solder pads on the front side of the first substrate chip 111 and the second substrate chip 112. The redistribution layer 140 is then formed again through a wiring process.

[0060] It should be noted that before forming the redistribution layer 140, a second metal trench can be formed by slotting on the front side of the substrate wafer, and a second metal layer 117 can be formed by electroplating in the second metal trench. The second metal layer 117 is symmetrically arranged with the first metal layer 115.

[0061] Furthermore, when forming the redistribution layer 140, a dielectric material can first be spin-coated onto the front side of the substrate wafer and cured to form a stacked dielectric layer. Then, a patterning process is used to pattern the stacked dielectric layer to form patterned openings that expose the pads on the front sides of the first substrate chip 111 and the second substrate chip 112. A metal layer (preferably copper) is then electroplated into the patterned openings to form a stacked metal layer, which is electrically connected to both the first substrate chip 111 and the second substrate chip 112. After spin-coating another layer of dielectric material and baking, a stacked protective layer is formed. Finally, grooves are cut into the stacked protective layer to expose the stacked metal layer, and metal is electroplated to form stacked pads.

[0062] The first mounted chip 150 is electrically connected to the substrate wiring layer 130, and the substrate wiring layer 130 is electrically connected to the redistribution layer 140 through the first conductive post 116.

[0063] S9: Attach stacked chips 160 on redistribution layer 140.

[0064] See Figure 10 In this configuration, the stacked chips 160 are electrically connected to the redistribution layer 140. Specifically, multiple stacked chips 160 are soldered and fixed onto the stacked pads of the redistribution layer 140 using a flip-chip process.

[0065] S10: A second molding layer 170 is formed on the redistribution layer 140.

[0066] Please continue reading Figure 1a The second molding compound 170 encapsulates the stacked chip 160. Specifically, the second molding compound 170 can be formed on the redistribution layer 140 through a molding process. This second molding compound 170 can encapsulate the stacked chip 160 and provide protection. Finally, the carrier 200 can be debonded and removed, and the individual products can be cut.

[0067] In summary, the 2.5D substrate packaging structure 100 and its fabrication method provided in this embodiment of the invention integrate a first substrate chip 111, a second substrate chip 112, and a substrate layer 113 into a single substrate wafer, with the substrate layer 113 located between the first substrate chip 111 and the second substrate chip 112. This direct wafer packaging avoids the conventional approach of first cutting the wafer into individual chips and then packaging them. Furthermore, a receiving groove 114 is provided on the back side of the substrate layer 113, in which the first mounting chip 150 is mounted. A redistribution layer 140 and a substrate wiring layer 130 are respectively provided on the front and back sides of the substrate wafer. A first conductive post 116 is also provided in the substrate layer 113, enabling electrical connection between the redistribution layer 140 and the substrate wiring layer 130. Compared to existing technologies, the 2.5D substrate wafer packaging structure and its fabrication method provided in this invention directly position the first substrate chip 111 and the second substrate chip 112 through an integrally formed substrate layer 113, ensuring packaging positioning accuracy. Dual-sided wiring is achieved through a substrate wiring layer 130 and a redistribution layer 140, reducing the wiring layer density of the chip and mitigating leakage caused by parasitic inductance, which can lead to short circuits and overheating between wiring layers. Furthermore, by directly forming the first conductive pillar 116 in the substrate layer 113 to achieve electrical connection of the dual-sided wiring, the warping and delamination problems of conventional molding processes are avoided, ensuring the structural reliability of the packaged chip. The first metal layer 115 enables heat dissipation of the intermediate chip (i.e., the first mounted chip 150), improving heat dissipation capacity, resulting in uniform heat dissipation and controllable temperature, avoiding warping and delamination problems, and significantly reducing warping, delamination, RDL cracking, and bump fatigue caused by thermal expansion and contraction, thus ensuring the structural reliability of the packaged chip. Furthermore, a double-sided design is achieved through the first metal layer 115 and the second metal layer 117, separated by the substrate wafer, thereby reducing the volume of the metal layer and avoiding cracking caused by the inconsistency of the thermal expansion coefficients between the wafer substrate and the metal layer due to thermal expansion.

[0068] Second Embodiment See Figure 11 This invention provides a 2.5D substrate packaging structure 100, whose basic structure, principle and technical effects are the same as those of the first embodiment. For the sake of brevity, any parts not mentioned in this embodiment can be referred to the corresponding content in the first embodiment.

[0069] In this embodiment, the 2.5D substrate packaging structure 100 further includes a second mounting chip 180. The second mounting chip 180 is disposed in the receiving groove 114 and spaced apart from the first mounting chip 150. The back side of the second mounting chip 180 is attached to the first metal layer 115, and the front side of the second mounting chip 180 is provided with a first connecting line 181. A second conductive post 118 electrically connected to the redistribution layer 140 is also provided in the substrate layer 113. The second conductive post 118 corresponds to the receiving groove 114 and is spaced apart from the first metal layer 115. The first connecting line 181 is connected to the second conductive post 118, and the second mounting chip 180 is electrically connected to the redistribution layer 140 through the second conductive post 118. Specifically, the second conductive post 118 is spaced apart from the first conductive post 116 and also penetrates the substrate layer 113, enabling the electrical connection between the redistribution layer 140 and the second mounting chip 180.

[0070] It should be noted that, in the embodiment of the present invention, a first mounting chip 150 and a second mounting chip 180 can be simultaneously disposed in the receiving groove 114. The second mounting chip 180 and the first mounting chip 150 are spaced apart from each other, and their back sides are in contact with the first metal layer 115 to ensure heat dissipation.

[0071] Furthermore, the 2.5D substrate package structure 100 also includes a third mounting chip 190. The third mounting chip 190 is disposed in the receiving recess 114 and stacked on the second mounting chip 180, with the back side of the third mounting chip 190 attached to the front side of the second mounting chip 180. The front side of the third mounting chip 190 is provided with a second connection line 191 connecting to the second mounting chip 180. Specifically, the size of the third mounting chip 190 is smaller than that of the second mounting chip 180, and it can be stacked on the front side of the second mounting chip 180. The first mounting chip 150, the second mounting chip 180, and the third mounting chip 190 are all mounted using a front-mount process, with their back sides facing down.

[0072] In this embodiment, a third connecting line 192 is also provided on the front side of the third mounted chip 190. The third connecting line 192 extends between the second mounted chip 180 and the first mounted chip 150 and connects to the first metal layer 115. Specifically, the third mounted chip 190 is electrically connected to the electrical point on the front side of the second mounted chip 180 through the second connecting line 191, and the second mounted chip 180 is electrically connected to the redistribution layer 140 through the first connecting line 181 and the second conductive post 118. The third mounted chip 190 is connected to the first metal layer 115 through the third connecting line 192, so that the first metal layer 115 can act as a discharge pad, effectively mitigating lightning surge phenomena.

[0073] It should be noted that the lightning surge here is essentially a high-voltage pulse of several thousand volts in microseconds that is induced and conducted by lightning and intrudes into the chip transistor. This can easily lead to gate oxide breakdown, junction burnout, metal melting, leakage, and in severe cases, permanent chip failure. Here, the first metal layer 115 is used as a discharge pad. When a large instantaneous current flows through the arc to ground or back, the surge peak energy can be discharged through the first metal layer 115, thus protecting the chip. The first metal layer 115 is electrically connected to the third mounted chip 190 through the second connection line 191, thereby enabling surge discharge of the third mounted chip 190. Simultaneously, the third mounted chip 190 is stacked on top of the second mounted chip 180, so the first metal layer 115 can also release surges across the entire stacked chip, effectively protecting the stacked chip.

[0074] It is worth noting that both the second mounted chip 180 and the third mounted chip 190 are completely accommodated in the receiving groove 114, and the height of the third mounted chip 190 is lower than the height of the first mounted chip 150, thus leaving sufficient space for wire bonding to facilitate the formation of the first connecting line 181, the second connecting line 191, and the third connecting line 192. The first connecting line 181, the second connecting line 191, and the third connecting line 192 are all conductive copper wires, formed through a wire bonding process.

[0075] This invention also provides a method for fabricating a 2.5D substrate wafer packaging structure, used to prepare the aforementioned 2.5D substrate wafer packaging structure. The basic steps, principles, and technical effects of this method are the same as in the first embodiment. For the sake of brevity, any parts not mentioned in this embodiment can be referred to the corresponding content in the first embodiment. The method includes the following steps: S1: Provide a substrate wafer.

[0076] S2: A groove 114 is formed on the back side of the base layer 113.

[0077] S3: A first metal layer 115 and a second conductive post 118 are formed on the bottom wall of the receiving groove 114.

[0078] See also Figure 12 Specifically, a first metal groove and a conductive via can be formed first by slotting the bottom wall of the receiving groove 114. The conductive via is spaced apart from the first metal groove and penetrates the base layer 113. Then, a first metal layer 115 is formed by electroplating in the first metal groove, and a second conductive post 118 is formed by electroplating in the conductive via. Here, both the first metal layer 115 and the second conductive post 118 are preferably copper layers.

[0079] S4: The first mounted chip 150, the second mounted chip 180 and the third mounted chip 190 are mounted in the receiving groove 114.

[0080] See also Figure 13 Specifically, the bonding of the first mounted chip 150 can be completed first. Using a surface mount technology, the first mounted chip 150 is mounted face down on the first metal layer 115 in the receiving groove 114, and the thickness of the first mounted chip 150 is adapted to the depth of the receiving groove 114, so that the front side of the first mounted chip 150 is preferably flush with the back side of the substrate wafer. Then, the bonding of the second mounted chip 180 is completed. Using a surface mount technology, the second mounted chip 180 is mounted face down on the first metal layer 115 in the receiving groove 114, ensuring that the second mounted chip 180 is spaced apart from the first mounted chip 150, and also spaced apart from the second conductive post 118. Finally, the bonding of the third mounted chip 190 is completed. Using a surface mount technology, the third mounted chip 190 is mounted face down on the front side of the second mounted chip 180. Finally, wire bonding is completed, forming a first connection line 181 on the front side of the second mounted chip 180, which is connected to the second conductive post 118; and forming a second connection line 191 and a third connection line 192 on the front side of the third mounted chip 190, wherein the second connection line 191 is connected to the second mounted chip 180 and the third connection line 192 is connected to the first metal layer 115.

[0081] S5: Form a first conductive pillar 116 in the substrate layer 113.

[0082] S6: Fill the receiving groove 114 to form a first molding layer 120.

[0083] S7: A substrate wiring layer 130 is formed on the back side of the substrate wafer.

[0084] S8: A redistribution layer 140 is formed on the front side of the substrate wafer.

[0085] S9: Attach stacked chips 160 on redistribution layer 140.

[0086] S10: A second molding layer 170 is formed on the redistribution layer 140.

[0087] The 2.5D substrate packaging structure 100 and its fabrication method provided in this invention mount a first mounted chip 150, a second mounted chip 180, and a third mounted chip 190 in a receiving groove 114, which greatly increases the number of chips stacked and improves chip density. Simultaneously, the third connecting line 192 can connect the third mounted chip 190 to the first metal layer 115, allowing the first metal layer 115 to act as a discharge pad, effectively mitigating lightning surge phenomena.

[0088] Third Embodiment See Figure 14This invention provides a 2.5D substrate packaging structure 100, whose basic structure, principle and technical effects are the same as those of the first embodiment. For the sake of brevity, any parts not mentioned in this embodiment can be referred to the corresponding content in the first embodiment.

[0089] In this embodiment, a first connecting line 181 is provided on the front side of the first mounted chip 150. A second conductive post 118, electrically connected to the redistribution layer 140, is also provided in the substrate layer 113. The second conductive post 118 corresponds to the receiving groove 114 and is spaced apart from the first metal layer 115. The first connecting line 181 is connected to the second conductive post 118, and the first mounted chip 150 is electrically connected to the redistribution layer 140 through the second conductive post 118. Specifically, the thickness of the first mounted chip 150 is less than the depth of the receiving groove 114, facilitating wire bonding to form the first connecting line 181. Multiple first mounted chips 150 are present, and the back sides of all multiple first mounted chips 150 are in contact with the first metal layer 115. Multiple second conductive posts 118 are provided on the bottom edge of the receiving groove 114. The multiple first mounted chips 150 are respectively connected to the multiple second conductive posts 118 through multiple first connecting lines 181, thereby achieving electrical connection with the redistribution layer 140.

[0090] Furthermore, the 2.5D substrate package structure 100 also includes a second mounted chip 180. The front side of the second mounted chip 180 overlaps with and is electrically connected to the front side of the first mounted chip 150. The front side of the second mounted chip 180 also has electrical bumps 183 connected to the first metal layer 115. Specifically, the second mounted chip 180 is mounted with its back side facing upwards, and its front side has microbumps that are soldered to the pads on the front side of the first mounted chip 150, thus achieving an electrical connection between the second mounted chip 180 and the first mounted chip 150. The electrical bumps 183 connected to the first metal layer 115 allow the first metal layer 115 to act as discharge pads, effectively mitigating lightning surge phenomena.

[0091] In this embodiment, the back side of the second mounted chip 180 is exposed outside the first molding compound 120. A wiring metal layer 182 is also disposed on the back side of the second mounted chip 180. The substrate wiring layer 130 covers the back side of the second mounted chip 180 and the wiring metal layer 182, and is electrically connected to the wiring metal layer 182. Specifically, wiring pattern openings are formed on the back side of the second mounted chip 180 through etching, and a wiring metal layer 182 is formed by electroplating within these openings. This wiring metal layer 182 is electrically connected to the substrate wiring layer 130, thereby enabling the back side of the second mounted chip 180 to be used for routing, increasing wiring density and freeing up more wiring resources.

[0092] It should be noted that the wiring metal layer 182 is only distributed on the back of the second mounted chip 180, but there is no electrical connection between it and the second mounted chip 180, which can avoid the wiring structure from affecting the second mounted chip 180.

[0093] This invention also provides a method for fabricating a 2.5D substrate packaging structure 100, used to fabricate the 2.5D substrate packaging structure 100 as described above. The basic steps, principles, and technical effects of this method are the same as in the first embodiment. For the sake of brevity, any parts not mentioned in this embodiment can be referred to the corresponding content in the first embodiment. The method includes the following steps: S1: Provide a substrate wafer.

[0094] S2: A groove 114 is formed on the back side of the base layer 113.

[0095] S3: A first metal layer 115 and a second conductive post 118 are formed on the bottom wall of the receiving groove 114.

[0096] Specifically, a first metal groove can be formed by first slotting the bottom wall of the receiving groove 114, and a conductive through hole can be formed by slotting the edge of the bottom wall of the receiving groove 114. The conductive through hole is spaced apart from the first metal groove and penetrates the base layer 113. Then, a first metal layer 115 is formed by electroplating in the first metal groove, and a second conductive pillar 118 is formed by electroplating in the conductive through hole. Here, both the first metal layer 115 and the second conductive pillar 118 are preferably copper layers.

[0097] S4: The first mounted chip 150 and the second mounted chip 180 are mounted in the receiving groove 114.

[0098] See Figure 15 Specifically, the first mounted chip 150 can be mounted first using a surface mount process, with its back side facing down, onto the first metal layer 115 in the receiving groove 114. Then, a wire bonding process is used to form a first connecting line 181, which connects to a second conductive post 118. Next, a flip-chip bonding process is used to mount the second mounted chip 180, with the front side of the second mounted chip 180 mounted on the front side of the first mounted chip 150 and soldered to achieve electrical connection. Furthermore, an electrical bump 183 is pre-formed on the front side of the second mounted chip 180, which connects to the first metal layer 115 between adjacent first mounted chips 150, providing support and preventing the second mounted chip 180 from collapsing. Preferably, the back side of the second mounted chip 180 is flush with the back side of the substrate wafer.

[0099] S5: Form a first conductive pillar 116 in the substrate layer 113.

[0100] S6: Fill the receiving groove 114 to form a first molding layer 120.

[0101] Specifically, a first molding layer 120 can be formed by molding process, and the first molding layer 120 can be thinned by grinding until the back side of the second mounted chip 180 and the back side of the substrate wafer are exposed.

[0102] S7: A wiring metal layer 182 is formed on the back side of the second mounted chip 180.

[0103] See Figure 16 Specifically, a wiring pattern opening can first be formed by etching a groove on the back of the second mounted chip 180, and then a wiring metal layer 182 can be formed by electroplating in the wiring pattern opening.

[0104] S8: A substrate wiring layer 130 is formed on the back side of the substrate wafer.

[0105] S9: A redistribution layer 140 is formed on the front side of the substrate wafer.

[0106] S10: Attach stacked chips 160 on redistribution layer 140.

[0107] S11: A second molding layer 170 is formed on the redistribution layer 140.

[0108] The 2.5D substrate package structure 100 and its fabrication method provided in this embodiment of the invention form a wiring metal layer 182 on the back side of the second mounted chip 180, and electrically connect the redistribution layer 140 to the wiring metal layer 182. By utilizing the back side of the second mounted chip 180 for routing, the wiring density is increased, freeing up more wiring resources. Dense wiring enables high-density interconnection between multiple chips, supporting heterogeneous computing and large-scale data interaction of chip splicing. The first metal layer 115 is electrically connected to the second mounted chip 180 through electrical protrusions 183, thereby enabling the first metal layer 115 to act as a discharge pad. When a transient large current flows to ground or back through the arc, the surge peak energy is discharged through the first metal layer 115.

[0109] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A 2.5D substrate packaging structure, characterized in that, include: An uncut substrate wafer includes a first substrate chip, a second substrate chip, and a substrate layer that are integrally formed. The substrate layer is located between the first substrate chip and the second substrate chip, and a receiving groove is provided on the back side of the substrate layer. A first metal layer is provided on the bottom wall of the receiving groove. At least one first mounting chip is disposed in the receiving groove, and the back side of the first mounting chip is at least partially attached to the first metal layer; A first molding compound is disposed in the receiving groove and covers the first mounted chip, and the first molding compound is flush with the back side of the substrate wafer; A substrate wiring layer is disposed on the back side of the substrate wafer and covers the first molding compound layer; A redistribution layer is disposed on the front side of the substrate wafer and electrically connected to the first substrate chip and the second substrate chip; The first mounted chip is electrically connected to the substrate wiring layer or the redistribution layer. The substrate layer is further provided with a first conductive post, which penetrates the substrate layer and is spaced apart from the receiving groove. The substrate wiring layer is electrically connected to the redistribution layer through the first conductive post.

2. The 2.5D substrate packaging structure according to claim 1, characterized in that, The first mounting chip includes a plurality of chips, which are spaced apart in the receiving groove. The back side of each first mounting chip is attached to the first metal layer, and the front side of each first mounting chip is exposed to the first molding layer. The substrate wiring layer covers the front side of the first mounting chip and is electrically connected to the first mounting chip.

3. The 2.5D substrate packaging structure according to claim 1, characterized in that, The bottom wall of the receiving groove is also provided with a first metal groove, the first metal layer is embedded in the first metal groove, and the thickness of the first metal layer is the same as the depth of the first metal groove.

4. The 2.5D substrate packaging structure according to claim 3, characterized in that, A second metal trench is also provided on the front side of the substrate wafer, and a second metal layer is embedded in the second metal trench. The thickness of the second metal layer is the same as the depth of the second metal trench, and the redistribution layer covers the second metal layer.

5. The 2.5D substrate packaging structure according to claim 4, characterized in that, The first metal layer is provided with a first heat dissipation protrusion on the side near the second metal layer, and the first heat dissipation protrusion is spaced apart from the second metal layer; the second metal layer is provided with a second heat dissipation protrusion on the side near the first metal layer, and the second heat dissipation protrusion is spaced apart from the first metal layer.

6. The 2.5D substrate packaging structure according to claim 1, characterized in that, The 2.5D substrate packaging structure further includes a second mounting chip, which is disposed in the receiving groove and spaced apart from the first mounting chip. The back side of the second mounting chip is attached to the first metal layer, and a first connecting line is provided on the front side of the second mounting chip. A second conductive post electrically connected to the redistribution layer is also provided in the substrate layer. The second conductive post corresponds to the receiving groove and is spaced apart from the first metal layer. The first connecting line is connected to the second conductive post, and the second mounting chip is electrically connected to the redistribution layer through the second conductive post.

7. The 2.5D substrate packaging structure according to claim 6, characterized in that, The 2.5D substrate packaging structure further includes a third mounting chip, which is disposed in the receiving groove and stacked on the second mounting chip. The back side of the third mounting chip is attached to the front side of the second mounting chip, and the front side of the third mounting chip is provided with a second connection line connected to the second mounting chip.

8. The 2.5D substrate packaging structure according to claim 7, characterized in that, The front side of the third mounted chip is also provided with a third connecting line, which extends between the second mounted chip and the first mounted chip and is connected to the first metal layer.

9. The 2.5D substrate packaging structure according to claim 1, characterized in that, The first mounted chip has a first connecting line on its front side. The substrate layer also has a second conductive post that is electrically connected to the redistribution layer. The second conductive post corresponds to the receiving groove and is spaced apart from the first metal layer. The first connecting line is connected to the second conductive post. The first mounted chip is electrically connected to the redistribution layer through the second conductive post.

10. The 2.5D substrate packaging structure according to claim 9, characterized in that, The 2.5D substrate packaging structure further includes a second mounting chip, the front side of which overlaps with the front side of the first mounting chip and is electrically connected to the first mounting chip. The front side of the second mounting chip is also provided with an electrical protrusion, which is connected to the first metal layer.

11. The 2.5D substrate packaging structure according to claim 10, characterized in that, The back side of the second mounted chip is exposed outside the first molding compound. A wiring metal layer is also provided on the back side of the second mounted chip. The substrate wiring layer covers the back side of the second mounted chip and the wiring metal layer and is electrically connected to the wiring metal layer.

12. The 2.5D substrate packaging structure according to claim 1, characterized in that, The redistribution layer is further provided with a stacked chip and a second molding compound on the side away from the base wiring layer. The stacked chip is electrically connected to the redistribution layer, and the second molding compound covers the stacked chip.

13. A method for fabricating a 2.5D substrate packaging structure, used to fabricate the 2.5D substrate packaging structure as described in claim 1, characterized in that, The method includes: A substrate wafer is provided, wherein the substrate wafer has a first substrate chip, a second substrate chip, and a substrate layer, the substrate layer being located between the first substrate chip and the second substrate chip; A groove is formed on the back side of the base layer to create a receiving recess; A first metal layer is formed on the bottom wall of the receiving groove; The back side of the first mounted chip is attached to the receiving groove, wherein the back side of the first mounted chip is at least partially attached to the first metal layer; A first conductive post is formed in the substrate layer, wherein the first conductive post penetrates the substrate layer and is spaced apart from the receiving groove; A first molding compound is formed by filling the receiving groove, wherein the first molding compound covers the first mounted chip and is flush with the back side of the substrate wafer; A substrate wiring layer is formed on the back side of the substrate wafer, wherein the substrate wiring layer covers the first molding layer; A redistribution layer is formed on the front side of the substrate wafer, wherein the redistribution layer is electrically connected to the first substrate chip and the second substrate chip; The first mounted chip is electrically connected to the substrate wiring layer or the redistribution layer, and the substrate wiring layer is electrically connected to the redistribution layer through the first conductive post.

14. The method for fabricating a 2.5D substrate packaging structure according to claim 13, characterized in that, The step of forming a first metal layer on the bottom wall of the receiving groove includes: A first metal groove is formed by slotting the bottom wall of the receiving groove; A first metal layer is formed by electroplating in the first metal tank, such that the first metal layer is embedded in the first metal tank, wherein the thickness of the first metal layer is the same as the depth of the first metal tank.

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