Electronic pricing scale cheating password recognition method, device and storage medium

Abstract

The application relates to the technical field of electronic pricing scale cheating password recognition, in particular to an electronic pricing scale cheating password recognition method, equipment and a storage medium, the method comprises the following steps: acquiring multiple groups of binary chip data of an electronic pricing scale and corresponding bus communication signals of the electronic pricing scale, the bus communication signals comprising a serial clock line signal and a serial data line signal; evaluating data reliability based on voltage fluctuation, noise and timing cycle fluctuation of the bus communication signals, and calculating a disorder degree by using a sliding window binary array difference comparison; comprehensively considering the reliability and the disorder degree to determine the action weight of each group of chip data, and recognizing the cheating password of the electronic pricing scale through reverse analysis. The application solves the problem that the bypass probe reading data is prone to interference, leading to inaccurate analysis, and guides the reverse analysis to preferentially focus on high-reliability samples, thereby improving the accuracy and efficiency of the cheating password recognition.

Description

Technical Field

[0001] This application relates to the field of electronic price-computing scale cheating password identification technology, specifically to an electronic price-computing scale cheating password identification method, device and storage medium. Background Technology

[0002] As a key measuring instrument for trade settlement, the accuracy of electronic price-computing scales directly affects consumers' interests and the fair order of the market. In recent years, with the popularization of microcontrollers and embedded technology, some electronic price-computing scales have been implanted with hidden cheating programs. These programs can switch between "normal mode" and "cheating mode" through specific passwords or operation sequences. Such cheating behaviors are highly concealed, making it difficult for traditional regulatory methods to effectively detect and collect evidence.

[0003] Currently, cheating detection mainly relies on exhaustive attempts or chip disassembly for reverse engineering. However, to avoid damaging the device, reverse engineering often uses non-invasive bypass probes to read I²C data. Poor contact can easily introduce signal glitches, timing jitter, or momentary disconnections, leading to abnormal communication waveforms and data errors such as bit flips. Although existing hardware filtering measures can suppress some noise, they cannot completely eliminate residual data anomalies. Because reverse engineering is highly sensitive to the integrity and accuracy of input data, residual data errors still have a significant negative impact on the accuracy and efficiency of reverse engineering. Summary of the Invention

[0004] In a first aspect, embodiments of this application provide a method for identifying cheating passwords on electronic price-computing scales, the method comprising the following steps:

[0005] Acquire multiple sets of binary chip data and their corresponding bus communication signals of the electronic price-computing scale, wherein the bus communication signals include serial clock line signals and serial data line signals;

[0006] For each group of chip data, the level quality factor is determined based on the voltage deviation between the high-level and low-level regions in the bus communication signal; the fluctuation of the serial data line signal segment corresponding to the high-level region in the serial clock line signal is analyzed in terms of timing to quantify the noise level of the serial data line signal; the serial clock line signal is segmented, and the autocorrelation of all segments is analyzed to quantify the periodic fluctuation amplitude of the serial clock line signal. The reliability of each group of chip data is evaluated by combining the level quality factor and the noise level quantification results.

[0007] All chip data groups are segmented using the same sliding window. By comparing the differences between the binary arrays of each chip data group and the data of all other chip data groups within the same window, the disorder of each chip data group is calculated, which is used to characterize the overall deviation of each chip data group from the data of all other chip data groups.

[0008] By combining the credibility and the disorder, the influence weight of each group of chip data is determined, and the cheating password of the electronic price scale is identified through reverse analysis based on the influence weight.

[0009] Preferably, the process of determining the level quality factor includes:

[0010] For each group of chip data, calculate the average voltage of all high-level regions and the average voltage of all low-level regions in the serial clock line signal and serial data line signal respectively.

[0011] The differences between the average voltage of each high-level region and the average voltage of each low-level region relative to the power supply voltage are calculated and denoted as the first voltage deviation and the second voltage deviation, respectively.

[0012] The level quality factor is calculated based on the first voltage deviation and the second voltage deviation.

[0013] Preferably, the quantization result of the noise level of the serial data line signal is the average value of the fluctuation degree of the serial data line signal segment corresponding to all high-level regions in the serial clock line signal in terms of timing.

[0014] Preferably, the quantization process of the periodic fluctuation amplitude of the serial clock line signal is as follows:

[0015] Obtain the time displacement corresponding to the maximum value of all autocorrelation coefficients in each segment of the serial clock line signal after excluding zero displacement, and record the standard deviation of the time displacement corresponding to the maximum autocorrelation coefficient of all segments as the quantization result of the periodic fluctuation amplitude of the serial clock line signal.

[0016] Preferably, the reliability of each group of chip data is positively correlated with the level quality factor and negatively correlated with the quantization results of the serial data line signal noise level and the quantization results of the serial clock line signal period fluctuation amplitude.

[0017] Preferably, the calculation process for the disorder of the data in each group of chips is as follows:

[0018] Calculate the mean of the differences between the corresponding binary arrays of each group of chip data and all other groups of chip data within the same window, and record it as the data difference value of each group of chip data within the same window;

[0019] Mark the number of the binary value difference between each group of chip data and any other group of chip data within the same window, and calculate the degree of dispersion of each group of chip data and all other groups of chip data within the same window. This is recorded as the data mutation degree of each group of chip data within the same window.

[0020] Traverse all windows to obtain the data difference and data mutation rate of each group of chip data within any window;

[0021] Based on the data difference value and the data mutation degree, determine the difference coefficient of each group of chip data within any window;

[0022] The disorder of each group of chip data is the mean of the difference coefficients of each group of chip data across all windows.

[0023] Preferably, the weight of each group of chip data is positively correlated with the reliability of each group of chip data and negatively correlated with the degree of disorder.

[0024] Preferably, the step of identifying the cheating code of the electronic pricing scale through reverse analysis based on the effect weight includes:

[0025] The sorting results of all chip data groups according to their weight from largest to smallest are used as input to the reverse analysis algorithm. The candidate password dictionary is used to perform pattern matching verification on each chip data group, and the matching success status of each chip data group under each candidate password is output.

[0026] The cumulative weights of the chip data with successful matching status under each candidate password are calculated and used as the confidence score for each candidate inference mode;

[0027] The candidate password with the highest confidence score was selected as the cheating password for the electronic price-computing scale.

[0028] Secondly, embodiments of this application provide an electronic price-computing scale cheating password identification device, wherein the device stores a computer program, and when the computer program is executed by a processor, it implements the electronic price-computing scale cheating password identification method described in any of the above claims.

[0029] Thirdly, embodiments of this application also provide an electronic price-computing scale cheating password identification storage medium, including a memory, a processor, and a computer program stored in the memory and running on the processor. When the processor executes the computer program, it implements the steps of any of the above-described electronic price-computing scale cheating password identification methods.

[0030] As can be seen from the above embodiments, the electronic pricing scale cheating password identification method provided in this application has at least the following beneficial effects:

[0031] This application comprehensively evaluates data credibility by analyzing the physical characteristics of I2C bus communication signals. Specifically, it uses the level quality factor to quantify the level drift, the serial data line noise level to quantify glitches, and the clock line period fluctuation amplitude to characterize timing jitter. Finally, it combines the above indicators to construct credibility. This method can effectively identify signal distortion caused by unstable contact of bypass probes, accurately eliminate high-risk low-quality data introduced by level misjudgment, glitches, and period jitter, and ensure that the data participating in reverse analysis has high accuracy and reliability, thereby helping to improve the accuracy and efficiency of cheating password identification.

[0032] Furthermore, based on the physical layer analysis of the signal, this application introduces an error index and uses a sliding window technique to compare the binary differences of multiple sets of chip data. This allows for precise quantification of the degree of interference at the content level. This method is based on the strong overall regularity of non-cryptographic data and the local random disorder of interference data. By comprehensively evaluating the data dispersion through data difference values ​​and data mutation degree, it can effectively identify bit flips and local anomalies caused by contact instability, thereby achieving accurate removal of low-quality data. This provides highly consistent and reliable data support for subsequent reverse analysis and helps improve the accuracy of cheating password identification.

[0033] Finally, this application calculates the role weight of each group of chip data by comprehensively considering confidence and disorder, quantifying the contribution ability of samples of different quality in reverse analysis. This method uses role weight to prioritize the data and locks the optimal password based on the confidence score accumulated from high-weight data. This effectively suppresses the misleading influence of low-quality interference data on the analysis results, ensuring that the algorithm focuses on highly reliable communication samples, thereby improving the accuracy and efficiency of identifying cheating passwords for electronic price-computing scales. Attached Figure Description

[0034] To more clearly illustrate the technical solutions and advantages in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1 A flowchart illustrating the steps of a method for identifying cheating passwords on an electronic price-computing scale, as provided in one embodiment of this application;

[0036] Figure 2 This is a schematic diagram illustrating the process of extracting the role weight of chip data according to an embodiment of this application. Detailed Implementation

[0037] To further illustrate the technical means and effects adopted by this application to achieve its intended purpose, the following, in conjunction with the accompanying drawings and preferred embodiments, details the specific implementation, structure, features, and effects of an electronic price-computing scale cheating password identification method, device, and storage medium proposed in this application. In the following description, different "one embodiment" or "another embodiment" do not necessarily refer to the same embodiment. Furthermore, specific features, structures, or characteristics in one or more embodiments can be combined in any suitable form.

[0038] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains.

[0039] The following description, in conjunction with the accompanying drawings, details the specific scheme of the electronic pricing scale cheating password identification method, device, and storage medium provided in this application.

[0040] Please see Figure 1 The diagram illustrates a flowchart of a method for identifying cheating passwords on an electronic pricing scale according to an embodiment of this application. The method includes the following steps:

[0041] S1: Acquire multiple sets of binary chip data and their corresponding bus communication signals of the electronic price-computing scale. The bus communication signals include serial clock line signals and serial data line signals.

[0042] In this embodiment, the core storage chip of the electronic price-computing scale is an EEPROM that supports the I2C communication protocol. The microcontroller reads the binary chip data of the EEPROM through the I2C bus. Its operating voltage range is 1.7V~5.5V. In this embodiment, a total of 20 sets of chip data are collected. The implementer can also set the number of collections according to the specific situation. This embodiment does not impose any special restrictions. In order to obtain the bus communication signal corresponding to the chip data, the dual-channel probe of the oscilloscope is connected to the SCL pin and SDA pin of the EEPROM chip respectively. During the process of the microcontroller reading data, the oscilloscope is started to perform synchronous sampling, thereby obtaining waveform data including the serial clock line signal SCL and the serial data line signal SDA. In this embodiment, the sampling rate is set to 4MSa / s.

[0043] S2: The reliability of the data is evaluated based on the voltage fluctuation, noise, and timing cycle fluctuation of the bus communication signal. The error degree is calculated by comparing the differences of the sliding window binary array to comprehensively quantify the deviation of the data of each group of chips.

[0044] In the process of anti-cheating detection of electronic price-computing scales, accurately identifying the cheating password is crucial to proving cheating behavior. Existing brute-force methods are inefficient and have limited coverage. Therefore, there is a growing trend towards directly reading data from the scale's storage chip and performing reverse analysis to obtain the cheating password. However, this type of analysis typically relies on communication protocols such as I2C and uses non-invasive bypass probes to read data. Problems with the contact between the probe and the chip pins can easily lead to communication waveform jumps or bit sampling errors, resulting in localized, random bit differences in the decoded data, severely affecting data accuracy. Directly using a large amount of distorted data for reverse analysis will significantly reduce the accuracy and efficiency of the analysis. Therefore, it is urgent to select high-quality data for reverse analysis to improve the reliability of the results. The specific process is as follows:

[0045] S2.1: For each group of chip data, determine the level quality factor based on the voltage deviation between the high-level and low-level regions in the bus communication signal; analyze the fluctuation of the serial data line signal segment corresponding to the high-level region in the serial clock line signal in terms of timing to quantify the noise level of the serial data line signal; segment the serial clock line signal, analyze the autocorrelation of all segments to quantify the periodic fluctuation amplitude of the serial clock line signal, and combine the level quality factor and noise level quantification results to evaluate the reliability of each group of chip data.

[0046] In the reverse engineering process, the first step is to read the raw data from the electronic scale's storage chip. The specific steps are: disassemble the typical cheating scale circuit board and locate the core chip storing the password (usually a Flash memory or EEPROM), then use the microcontroller's matching chip's I2C communication protocol to read the data. Since data transmission must pass through the I2C bus, and the unstable contact of the bypass probes during the reading process can easily introduce interference, leading to data anomalies, it is essential to analyze any abnormalities in the I2C bus communication quality.

[0047] The I2C bus consists of two serial lines: the Serial Clock line (SCL) provides the communication timing reference, and the Serial Data line (SDA) transmits the actual data. In normal communication, SCL and SDA should be periodic square waves with steep edges and stable levels, strictly adhering to the protocol that "SDA remains stable when SCL is high and is allowed to transition when SCL is low." However, under interference, the bus signal may exhibit the following anomalies: first, level drift, i.e., a drop in high level or a rise in low level; second, signal glitches, i.e., unexpected spikes or dips in the waveform; and third, period jitter, i.e., interference disrupts the periodic stability of the SCL signal, leading to timing fluctuations.

[0048] Therefore, based on the above analysis, this embodiment determines the level quality factor based on the voltage deviation between the high-level and low-level regions in its bus communication signal; analyzes the fluctuation of the serial data line signal segment corresponding to the high-level region in the serial clock line signal in terms of timing to quantify the noise level of the serial data line signal; segments the serial clock line signal, analyzes the autocorrelation of all segments to quantify the periodic fluctuation amplitude of the serial clock line signal, and combines the level quality factor and noise level quantification results to evaluate the reliability of each group of chip data. The specific process is as follows:

[0049] First, for each group of chip data, based on the voltage deviation between the high-level and low-level regions in its bus communication signal, the level quality factor is determined. Specifically:

[0050] For each group of chip data, calculate the average voltage of all high-level regions and the average voltage of all low-level regions in the serial clock line signal and serial data line signal respectively.

[0051] It should be noted that the specific method for dividing the high-level and low-level regions is as follows: Taking the serial clock line signal as an example, calculate the absolute difference between each voltage value on the serial clock line signal and the power supply voltage and ground voltage, and retain the minimum of the two absolute differences as the minimum absolute difference of each voltage value; use the minimum absolute difference of all voltage values ​​on the serial clock line signal as the input of the threshold segmentation algorithm, output the segmentation threshold, and define the region consisting of voltage values ​​whose minimum absolute difference is less than the segmentation threshold and are continuous in time as the standard level region. Among them, the standard level region calculated by the voltage value and the power supply voltage is recorded as the high-level region, and the remaining standard level region is recorded as the low-level region. In addition, the threshold segmentation algorithm in this embodiment is obtained by the maximum inter-class variance algorithm. In actual applications, as other implementation methods, implementers may also use other threshold segmentation algorithms according to specific circumstances. This embodiment does not impose special restrictions on the selection of the threshold segmentation algorithm; the method for dividing the high and low level regions of the serial data line signal is the same as that of the serial clock line signal.

[0052] The process of obtaining the segmentation threshold using the Otsu's inter-class variance algorithm is a well-known technique and will not be elaborated further.

[0053] Furthermore, in this embodiment, the differences between the average voltage of each high-level region and the average voltage of each low-level region relative to the power supply voltage are calculated and denoted as the first voltage deviation and the second voltage deviation, respectively.

[0054] To facilitate understanding of the calculation process for the first and second voltage deviations, the specific calculation expressions for the first and second voltage deviations are given below:

[0055] The first voltage deviation of the nth high-level region in all high-level regions of the serial clock line signal and the serial data line signal The expression is: In the formula, This represents the average voltage in the nth high-level region across all high-level regions of the serial clock line signal and the serial data line signal. This indicates the power supply voltage.

[0056] The second voltage deviation of the m-th low-level region in all low-level regions of the serial clock line signal and serial data line signal The expression is: In the formula, This represents the average voltage in the m-th low-level region across all low-level regions of the serial clock line signal and serial data line signal. This indicates the power supply voltage.

[0057] Furthermore, in this embodiment, based on the first voltage deviation and the second voltage deviation, the expression for calculating the level quality factor is as follows:

[0058]

[0059] In the formula, This represents the level quality factor of the bus communication signal corresponding to the data in group t; This represents the first voltage deviation of the nth high-level region among all high-level regions of the serial clock line signal and serial data line signal corresponding to the t-th chip data; This represents the second voltage deviation of the m-th low-level region among all low-level regions of the serial clock line signal and serial data line signal corresponding to the t-th chip data; This represents the number of all high-level regions of the serial clock line signal and serial data line signal corresponding to the t-th group of chip data; This represents the number of all low-level regions corresponding to the serial clock line signal and serial data line signal of the t-th chip data; min[] represents the minimum value function.

[0060] Based on the level quality factor, it can be understood that the level quality factor is used to characterize how close the actual level state in the I2C bus communication signal is to the ideal logic level standard. Specifically, it reflects whether the high level reaches the expected power supply voltage level and whether the low level is effectively suppressed to a level close to zero potential, that is, the integrity and effectiveness of the signal logic amplitude. Its calculation is decisively influenced by two factors: the closeness of the average voltage of each high-level region to the power supply voltage, and the distance of the voltage value of each low-level region from the power supply voltage, that is, the magnitude of the low-level voltage value. and A higher level indicates that the high-level signal is closer to the power supply voltage, and the low-level signal is further away from the power supply voltage. In other words, a lower low-level signal indicates a higher level quality factor, reflecting clear communication signal logic, high noise tolerance, excellent communication quality, and a lower likelihood of data transmission errors. Conversely, a lower level indicates a lower level quality factor. and The smaller the value, the more severe the high-level drop or the abnormal rise of the low-level. The smaller the level quality factor, the more it reflects that the signal is interfered with, causing the logic level boundary to become blurred, and there is a great risk of level misjudgment.

[0061] Furthermore, this embodiment quantifies the noise level of the serial data line signal by analyzing the fluctuation of the high-level region in the serial clock line signal corresponding to the serial data line signal segment in terms of timing. Specifically:

[0062] In this embodiment, the average value of the fluctuation of the serial data line signal segments corresponding to all high-level regions in the serial clock line signal is used as the quantization result of the noise level of the serial data line signal.

[0063] It should be noted that in this embodiment, the standard deviation of all voltage values ​​of the serial data line signal segments corresponding to all high-level regions in the serial clock line signal is used as the fluctuation degree of the serial data line signal segments corresponding to the high-level regions in the serial clock line signal.

[0064] Based on the noise level quantization results of the serial data line signal, it can be understood that the noise level quantization result is used to characterize the dispersion of the serial data line signal voltage value during the high-level holding period of the serial clock line signal. Specifically, it reflects whether the serial data line signal is subject to transient interference, resulting in unexpected jumps or fluctuations that violate the protocol. Its calculation is mainly affected by the voltage standard deviation of the serial data line signal segment corresponding to the high-level region of the serial clock line signal in terms of timing. The larger this factor is, the larger the noise level quantization result of the serial data line signal, reflecting that the serial data line signal has experienced severe jitter or glitches during the period when the data should be stable. This can lead to the receiver sampling incorrect data bits, causing anomalies such as bit flips. Conversely, the smaller this factor is, the smaller the noise level quantization result of the serial data line signal, reflecting that the serial data line signal remains stable during the high-level period of the serial clock line signal, which meets the data stability requirements of the I2C protocol, and the transmitted data is accurate and reliable.

[0065] Furthermore, this embodiment segments the serial clock line signal and analyzes the autocorrelation of all segments to quantify the periodic fluctuation amplitude of the serial clock line signal. Combined with the quantization results of the level quality factor and noise level, the reliability of each group of chip data is evaluated. Specifically:

[0066] In this embodiment, the serial clock line signal is used as the input of the ACK mechanism, and the segmentation result of the serial clock line signal is output. The time displacement corresponding to the maximum value after excluding zero displacement among all autocorrelation coefficients of each segment is recorded as the standard deviation of the time displacement corresponding to the maximum autocorrelation coefficient of all segments as the quantization result of the periodic fluctuation amplitude of the serial clock line signal.

[0067] The process of segmenting the signal using the ACK mechanism, as well as the calculation of the autocorrelation coefficient and the acquisition of the time shift, are well-known techniques and will not be elaborated further.

[0068] Based on the quantization results of the periodic fluctuation amplitude of the serial clock line signal, it can be understood that the quantization results of the periodic fluctuation amplitude are used to characterize the stability of the clock signal period between different byte segments, specifically reflecting the consistency of the clock frequency, i.e., whether there is periodic jitter. Its calculation is affected by the standard deviation of the time displacement determined in the autocorrelation analysis of each segment. The larger this factor is, the larger the periodic fluctuation amplitude of the serial clock line signal, reflecting that the clock signal is disturbed, causing the timing reference to be unstable, resulting in jitter phenomena that are sometimes fast and sometimes slow, which destroys the synchronization mechanism of communication and is prone to byte misalignment or sampling point offset. Conversely, the smaller this factor is, the smaller the periodic fluctuation amplitude of the serial clock line signal, reflecting that the clock signal rhythm is constant, the periodicity is strong, the communication timing is accurate, and the synchronization and reliability of data transmission are guaranteed.

[0069] Furthermore, this embodiment uses the quantization results of the periodic fluctuation amplitude of the serial clock line signal, combined with the quantization results of the level quality factor and noise level, to evaluate the reliability of each group of chip data, specifically:

[0070] In this embodiment, the reliability of each group of chip data is positively correlated with the level quality factor, and negatively correlated with the quantization results of the serial data line signal noise level and the quantization results of the serial clock line signal period fluctuation amplitude.

[0071] It should be understood that a positive correlation means that the dependent variable increases as the independent variable increases, and the dependent variable decreases as the independent variable decreases. The specific relationship can be additive or multiplicative, etc., and is determined by the actual application. This application does not impose any special restrictions. A negative correlation means that the dependent variable decreases as the independent variable increases, and the dependent variable increases as the independent variable decreases. The relationship can be subtractive or divisive, etc., and is determined by the actual application.

[0072] Preferably, as one implementation method, the expression for the reliability of each group of chip data in this embodiment is: In the formula, This indicates the reliability of the data in the t-th chip group; This represents the level quality factor of the bus communication signal corresponding to the data in group t; This represents the normalized value of the noise level quantization result of the serial data line signal in the bus communication signal corresponding to the t-th group of chip data; represents the normalized value of the quantization result of the periodic fluctuation amplitude of the serial clock line signal in the bus communication signal corresponding to the t-th group of chip data; exp[ ] represents the exponential function with the natural constant as the base.

[0073] It should be noted that there are many commonly used normalization methods. In this embodiment, the noise level quantization result of the serial data line signal and the period fluctuation amplitude quantization result of the serial clock line signal are respectively mapped to the range of [0,1] using the maximum and minimum value normalization method. In practical applications, as other implementation methods, implementers may also use other normalization methods according to specific circumstances. This embodiment does not impose any special restrictions.

[0074] Based on the reliability of each group of chip data, it can be understood that reliability is used to comprehensively characterize the overall reliability and quality level of a single chip data reading process, reflecting the true and reliable degree of data acquired in the current communication environment. Its calculation is jointly affected by three factors: level quality factor, serial data line noise level quantization result, and serial clock line period fluctuation amplitude quantization result. Reliability is positively correlated with level quality factor and negatively correlated with the latter two. When the level quality factor is larger and the serial data line noise level quantization result and the serial clock line period fluctuation amplitude quantization result are smaller, the reliability is higher, reflecting that the communication level is standard, the noise is low, and the clock is stable, and the data is minimally affected by interference, making it safe for reverse analysis. Conversely, when the level quality factor is smaller, i.e., the level deviation is serious, and the serial data line noise level quantization result and the serial clock line period fluctuation amplitude quantization result are larger, the reliability is lower, reflecting that there is serious signal distortion, timing jitter, or glitches in the communication link, and the data has a very high risk of error.

[0075] Thus, this embodiment comprehensively evaluates data credibility by considering the physical characteristics of the I2C bus communication signal. Specifically, it uses the level quality factor to quantify the level drift, the serial data line noise level to quantify glitches, and the clock line period fluctuation amplitude to characterize timing jitter. Finally, it combines the above indicators to construct credibility. This method can effectively identify signal distortion caused by unstable contact of bypass probes, accurately eliminate high-risk, low-quality data introduced by level misjudgment, glitches, and period jitter, and ensure that the data participating in reverse analysis has high accuracy and reliability, thereby helping to improve the accuracy and efficiency of cheating password identification.

[0076] S2.2: All chip data are segmented using the same sliding window. By comparing the differences between the binary arrays of each chip data group and the data of all other chip data groups within the same window, the disorder of each chip data group is calculated to characterize the overall deviation of each chip data group from the data of all other chip data groups.

[0077] The aforementioned communication environment coefficients primarily analyze the changes in the I2C bus from a signal physical perspective. However, the specific impact of different levels of interference on transmitted data varies. Therefore, further in-depth analysis using data extracted from bus communication is needed to achieve a more accurate quantification of the degree of data interference.

[0078] Non-cheating password areas mainly contain information such as product names and unit prices. This type of data is not only scattered and disordered, but also exhibits an overall regularity despite variations across different samples. In contrast, cheating passwords, as a mode-switching instruction, are typically simple and highly static in design to balance ease of memorization and rapid input, thus remaining unchanged across multiple data extractions. Furthermore, when I2C communication is affected by unstable interference from bypass probes, leading to data anomalies, these anomalies mainly manifest as bit flips or level misjudgments, resulting in local byte corruption. This means that the interfered data only exhibits random fluctuations in localized areas, while the overall data structure remains relatively stable.

[0079] Therefore, based on the above analysis, this embodiment segments all chip data using the same sliding window. By comparing the differences between the binary arrays of each chip data group and all other chip data groups within the same window, the disorder of each chip data group is calculated to characterize the overall deviation of each chip data group from the other chip data groups. The specific process is as follows:

[0080] First, considering that cheating passwords need to be easy to remember, quick to input, and concealed, their length is usually limited to 2 to 6 characters. Therefore, a sliding window of length k can be used to scan the acquired chip data in segments. Since the specific location of the password is unknown, the sliding step size is set to 1 during scanning to traverse all possible starting points. At the same time, in order to take into account various password forms such as repeating patterns and continuous patterns, this embodiment preferably uses k=16 as the sliding window length to achieve more sensitive capture of cheating passwords.

[0081] Furthermore, this embodiment calculates the disorder of each group of chip data by comparing the differences between the binary arrays of each group of chip data and all other groups of chip data within the same window. This is used to characterize the overall deviation of each group of chip data from all other groups of chip data. The specific process is as follows:

[0082] Calculate the mean of the differences between the corresponding binary arrays of each group of chip data and all other groups of chip data within the same window, and record it as the data difference value of each group of chip data within the same window;

[0083] Furthermore, the number of the point in the whole group of chip data where the binary value of each group of chip data differs from that of any other group of chip data within the same window is marked, and the degree of dispersion of each group of chip data and all other groups of chip data within the same window is calculated, which is recorded as the data mutation degree of each group of chip data within the same window.

[0084] Furthermore, by traversing all windows, the data difference value and data mutation degree of each group of chip data within any window are obtained;

[0085] It should be noted that there are many methods to measure the differences between data groups. In this embodiment, the Hamming distance between binary arrays is used as the difference between binary groups. In practical applications, as other implementation methods, implementers may also adopt other difference measurement methods according to specific circumstances. This embodiment does not impose any special restrictions.

[0086] Furthermore, it should be noted that in this embodiment, the standard deviation of all numbers of each group of chip data and all other groups of chip data within the same window is used as the degree of dispersion of each group of chip data and all other groups of chip data within the same window.

[0087] Furthermore, this embodiment determines the difference coefficient of each group of chip data within any window based on the data difference value and the data mutation degree. Specifically, the difference coefficient of the t-th group of chip data within the v-th window is... The expression is: ,in, , Let represent the normalized values ​​of the data difference and the normalized values ​​of the data mutation rate in the v-th window of the t-th chip data, respectively, and min() represents the minimum value function;

[0088] The mean of the difference coefficients of each group of chip data across all windows is used as the disorder level of each group of chip data.

[0089] It should be noted that in this embodiment, the data difference value and the data mutation degree are mapped to the range of [0,1] using the maximum and minimum value normalization method. In actual application, the implementer may also use other normalization methods according to the specific situation. This embodiment does not impose any special restrictions on the selection of normalization methods.

[0090] Based on the error degree of each group of chip data, it can be understood that the error degree is used to characterize the degree of deviation of a single group of chip data from all other groups of chip data as a whole. Specifically, it reflects the density and distribution of random bit errors caused by interference in each group of chip data. Its calculation is directly affected by two factors: the mean of the difference between each group of chip data and other chip data within the same window (data difference value) and the dispersion of the difference position number (data abrupt change degree). If the data difference value and data abrupt change degree are larger, the error degree is larger, reflecting that the chip data has random bit flips that are inconsistent with other chip data in many places, and the error positions are distributed in a disorderly manner, indicating that it has been subjected to serious interference and the local data error is prominent. Conversely, if the data difference value and data abrupt change degree are smaller, the error degree is smaller, reflecting that the data in this group is highly consistent with other data or only has overall regular changes, without obvious random local errors, and the data quality is better.

[0091] Therefore, based on the physical layer analysis of the signal, this embodiment further introduces an error degree index and uses the sliding window technique to compare the binary differences of multiple sets of chip data. It accurately quantifies the degree of interference at the content level. This method is based on the characteristics of strong overall regularity of non-cryptographic data and local random disorder of interference data. By comprehensively evaluating the data dispersion through data difference value and data mutation degree, it can effectively identify bit flips and local anomalies caused by contact instability, thereby achieving accurate elimination of low-quality data. This provides highly consistent and reliable data support for subsequent reverse analysis and helps improve the accuracy of cheating password identification.

[0092] S3: Combining the credibility and the disorder, determine the weight of each group of chip data, and identify the cheating password of the electronic price scale through reverse analysis based on the weight of the weight.

[0093] In the process of identifying cheating codes on electronic price-computing scales, firstly, multiple sets of binary chip data are read from the storage core chip of the electronic price-computing scale according to step S1. Then, according to step S2, the reliability and disorder of each set of chip data are calculated. Furthermore, this embodiment determines the influence weight of each set of chip data by combining the reliability and disorder. Based on the influence weight, the cheating code of the electronic price-computing scale is identified through reverse analysis. The specific process is as follows:

[0094] First, based on the credibility and the disorder, the influence weight of each group of chip data is determined. Specifically, the influence weight of each group of chip data is positively correlated with the credibility of each group of chip data and negatively correlated with the disorder.

[0095] Preferably, as one implementation method, the expression for the weighting of each group of chip data in this embodiment is as follows: In the formula, This represents the weight of the t-th group of chip data; , These represent the reliability of the chip data in group t and group e, respectively. , represents the disorder degree of chip data in group t and group e, respectively; E represents the number of chip data in all groups. This represents a preset constant greater than 0, used to prevent the denominator from being 0. In this embodiment... The value of is 0.01. Provided that the denominator is not zero and does not excessively affect the calculation result, the implementer may also set it according to the specific situation. This embodiment does not impose any special restrictions.

[0096] Preferably, the schematic diagram of the chip data role weight extraction process provided in this embodiment is as follows: Figure 2 As shown.

[0097] Based on the role weight, it can be understood that the role weight is used to characterize the importance and priority of each group of chip data in the reverse analysis process. Specifically, it reflects the contribution ability and credibility level of a single group of data to the correct inference result in the overall dataset. Its calculation is affected by the credibility of each group of chip data. ) and degree of disorder ( The combined influence of these two factors, with their weights positively correlated with credibility and negatively correlated with error rate, indicates that a higher credibility and lower error rate result in a greater weight. This reflects high-quality chip data communication, minimal interference, and good internal logical consistency. Such data should be considered high-quality samples in reverse analysis, prioritized by the algorithm, and dominate the inference results. Conversely, a lower credibility and higher error rate result in a smaller weight, indicating severe signal distortion or random local errors in the chip data. This data is unreliable and is given lower priority or suppressed in reverse analysis to avoid misleading the final password deduction.

[0098] The sorting results of all chip data groups according to their weight from largest to smallest are used as input to the reverse analysis algorithm. The candidate password dictionary is used to perform pattern matching verification on each chip data group, and the matching success status of each chip data group under each candidate password is output.

[0099] It should be noted that the specific execution logic of the reverse analysis algorithm is as follows: extract candidate bytes from a specific offset address range of the chip data and compare them with a preset cheating password feature dictionary; if the comparison is consistent, the matching status of the chip data under the candidate password is determined to be successful, otherwise it is considered a failure.

[0100] Furthermore, the cumulative weights of the chip data with successful matching status under each candidate password are calculated as the confidence score for each candidate inference mode;

[0101] The candidate password with the highest confidence score will be used as the cheating password for the electronic price-computing scale.

[0102] The process of using reverse analysis algorithms to obtain the chip data decryption status and plaintext data under various candidate cryptographic methods is a well-known technology and will not be described in detail here.

[0103] Thus, this embodiment calculates the contribution weight of each group of chip data by comprehensively considering confidence and disorder, quantifying the contribution ability of samples of different quality in reverse analysis. This method uses the contribution weight to prioritize the data and locks the optimal password based on the confidence score accumulated from high-weight data. This effectively suppresses the misleading influence of low-quality interference data on the analysis results, ensuring that the algorithm focuses on highly reliable communication samples, thereby improving the accuracy and efficiency of identifying cheating passwords for electronic price-computing scales.

[0104] Based on the same inventive concept as the above method, this application also provides an electronic price-computing scale cheating password identification device, wherein the device stores a computer program, and when the computer program is executed by a processor, it implements the electronic price-computing scale cheating password identification method described above.

[0105] Based on the same inventive concept as the above methods, this application also provides an electronic price-computing scale cheating password identification storage medium, including a memory, a processor, and a computer program stored in the memory and running on the processor. When the processor executes the computer program, it implements the steps of any one of the above-described electronic price-computing scale cheating password identification methods.

[0106] It should be noted that the order of the embodiments described above is merely for descriptive purposes and does not represent the superiority or inferiority of the embodiments. Furthermore, specific embodiments of this specification have been described above. Additionally, the processes depicted in the accompanying drawings do not necessarily require a specific or sequential order to achieve the desired results. In some implementations, multitasking and parallel processing are possible or may be advantageous.

[0107] The various embodiments in this specification are described in a progressive manner. The same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on describing the differences from other embodiments.

[0108] The above description is only a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the principles of this application should be included within the protection scope of this application.

Claims

1. A method for identifying cheating passwords on electronic price-computing scales, characterized in that, The method includes the following steps: Acquire multiple sets of binary chip data and their corresponding bus communication signals of the electronic price-computing scale, wherein the bus communication signals include serial clock line signals and serial data line signals; For each group of chip data, the level quality factor is determined based on the voltage deviation between the high-level and low-level regions in the bus communication signal; the fluctuation of the serial data line signal segment corresponding to the high-level region in the serial clock line signal is analyzed in terms of timing to quantify the noise level of the serial data line signal; the serial clock line signal is segmented, and the autocorrelation of all segments is analyzed to quantify the periodic fluctuation amplitude of the serial clock line signal. The reliability of each group of chip data is evaluated by combining the level quality factor and the noise level quantification results. All chip data groups are segmented using the same sliding window. By comparing the differences between the binary arrays of each chip data group and the data of all other chip data groups within the same window, the disorder of each chip data group is calculated, which is used to characterize the overall deviation of each chip data group from the data of all other chip data groups. By combining the credibility and the disorder, the influence weight of each group of chip data is determined, and the cheating password of the electronic price scale is identified through reverse analysis based on the influence weight.

2. The method for identifying cheating passwords on electronic price-computing scales as described in claim 1, characterized in that, The process of determining the level quality factor includes: For each group of chip data, calculate the average voltage of all high-level regions and the average voltage of all low-level regions in the serial clock line signal and serial data line signal respectively. The differences between the average voltage of each high-level region and the average voltage of each low-level region relative to the power supply voltage are calculated and denoted as the first voltage deviation and the second voltage deviation, respectively. The level quality factor is calculated based on the first voltage deviation and the second voltage deviation.

3. The method for identifying cheating passwords on electronic price-computing scales as described in claim 1, characterized in that, The quantization result of the noise level of the serial data line signal is the average value of the fluctuation of the serial data line signal segment corresponding to all high-level regions in the serial clock line signal in terms of timing.

4. The method for identifying cheating passwords on electronic price-computing scales as described in claim 1, characterized in that, The quantization process of the periodic fluctuation amplitude of the serial clock line signal is as follows: Obtain the time displacement corresponding to the maximum value of all autocorrelation coefficients in each segment of the serial clock line signal after excluding zero displacement, and record the standard deviation of the time displacement corresponding to the maximum autocorrelation coefficient of all segments as the quantization result of the periodic fluctuation amplitude of the serial clock line signal.

5. The method for identifying cheating passwords on electronic price-computing scales as described in claim 1, characterized in that, The reliability of each group of chip data is positively correlated with the level quality factor, and negatively correlated with the quantization results of the serial data line signal noise level and the quantization results of the serial clock line signal period fluctuation amplitude.

6. The method for identifying cheating passwords on electronic price-computing scales as described in claim 1, characterized in that, The calculation process for the error degree of each group of chip data is as follows: Calculate the mean of the differences between the corresponding binary arrays of each group of chip data and all other groups of chip data within the same window, and record it as the data difference value of each group of chip data within the same window; Mark the number of the binary value difference between each group of chip data and any other group of chip data within the same window, and calculate the degree of dispersion of each group of chip data and all other groups of chip data within the same window. This is recorded as the data mutation degree of each group of chip data within the same window. Traverse all windows to obtain the data difference and data mutation rate of each group of chip data within any window; Based on the data difference value and the data mutation degree, determine the difference coefficient of each group of chip data within any window; The disorder of each group of chip data is the mean of the difference coefficients of each group of chip data across all windows.

7. The method for identifying cheating passwords on electronic price-computing scales as described in claim 1, characterized in that, The weight of each group of chip data is positively correlated with the reliability of each group of chip data and negatively correlated with the degree of disorder.

8. The method for identifying cheating passwords on electronic price-computing scales as described in claim 1, characterized in that, The method of identifying the cheating code of the electronic price-computing scale through reverse analysis based on the said action weight includes: The sorting results of all chip data groups according to their weight from largest to smallest are used as input to the reverse analysis algorithm. The candidate password dictionary is used to perform pattern matching verification on each chip data group, and the matching success status of each chip data group under each candidate password is output. The cumulative weights of the chip data with successful matching status under each candidate password are calculated and used as the confidence score for each candidate inference mode; The candidate password with the highest confidence score was selected as the cheating password for the electronic price-computing scale.

9. A cheating password identification device for electronic price-computing scales, wherein the device stores a computer program, characterized in that, When the computer program is executed by the processor, it implements a method for identifying cheating passwords on electronic price-computing scales as described in any one of claims 1-8.

10. A cheating password identification storage medium for an electronic price-computing scale, comprising a memory, a processor, and a computer program stored in the memory and running on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the electronic price-computing scale cheating password identification method as described in any one of claims 1-8.

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