Method, device, medium and equipment for online detection of power semiconductor switching loss

Abstract

This application belongs to the field of power electronics technology, specifically disclosing a method, apparatus, medium, and device for online detection of switching losses in power semiconductors. The method includes: constructing a detection link and injecting a dual-frequency carrier signal to acquire the high-frequency response voltage across a parasitic inductor in real time; decoupling the acquired high-frequency response voltage; locating the voltage and current change rates within the switching operation range of the power semiconductor based on the decoupled high-frequency response signal, and performing online calibration of the parasitic inductor under the current operating condition; calculating the switching losses of the power semiconductor based on the located voltage and current change rates within the switching operation range and the calibrated parasitic inductor; repeating the above steps, continuously iterating and updating the loss data to detect the health status of the power semiconductor. This application enables high-precision online detection of switching losses in power semiconductors.

Description

Technical Field

[0001] This application belongs to the field of power electronics technology, specifically relating to an online detection method, device, medium, and equipment for power semiconductor switching losses. Background Technology

[0002] In existing online detection technologies for power semiconductor switching losses, there are two main types of detection methods: one is the direct electrical measurement method, which directly acquires the transient voltage and current waveforms of the switch using a high-voltage differential probe and a Rogowski coil or coaxial shunt, and then integrates to calculate the loss. Although this method has high accuracy, it requires high-bandwidth, high-isolation sensing equipment, which is expensive. In addition, it poses safety hazards and serious electromagnetic interference problems in high-voltage, high-current scenarios, making it difficult to integrate into the driver for long-term online monitoring. The other is the indirect estimation method, which usually infers the switching loss based on the device's on-state voltage drop, case temperature, or thermal resistance network model. It does not require direct measurement of high-voltage transient signals, but the response lag is significant, and as the device ages, the mapping relationship between its on-state voltage drop, temperature, and loss will drift, leading to a gradual decrease in accuracy.

[0003] Given the shortcomings of existing detection methods, there is an urgent need for an online detection method that does not rely on direct measurement of the transient high voltage signal of the switch, can automatically compensate for changes in parasitic parameters, and can calculate the switching losses with high accuracy in each PWM cycle. Summary of the Invention

[0004] To address the shortcomings of existing technologies, the purpose of this application is to provide a method, apparatus, medium, and device for online detection of power semiconductor switching losses. This application enables high-precision online detection of power semiconductor switching losses without the need for direct measurement of high-voltage transient signals in the main circuit of the power semiconductor and without interrupting operation.

[0005] To achieve the above objectives, this application provides the following technical solution: A method for online detection of switching losses in power semiconductors includes: constructing a detection link; injecting a dual-frequency carrier signal into the detection link and acquiring the high-frequency response voltage across a parasitic inductor in real time; decoupling the acquired high-frequency response voltage; locating the voltage and current change rates within the switching operation range of the power semiconductor based on the decoupled high-frequency response signal, and calibrating the parasitic inductor under the current operating condition online; calculating the switching losses of the power semiconductor based on the located voltage and current change rates within the switching operation range and the calibrated parasitic inductor; and repeating the above steps to continuously iterate and update the loss data to detect the health status of the power semiconductor.

[0006] Optionally, the construction of the detection link includes: connecting a high-frequency signal injection transformer in series in the gate drive circuit of the power semiconductor; and pre-setting first and second low-noise differential detection terminals near the power terminals of the power semiconductor to capture the high-frequency response voltage across the parasitic inductance.

[0007] Optionally, the signal decoupling of the acquired high-frequency response voltage includes: separating the acquired high-frequency response voltage and extracting the single-frequency response signals corresponding to the injected carrier frequency; performing quadrature demodulation on each single-frequency response signal to extract the amplitude envelope of each single-frequency response signal; and obtaining the parasitic inductance dominant component based on the extracted amplitude envelope of the single-frequency response signal to complete the high-frequency response voltage decoupling.

[0008] Optionally, the step of performing quadrature demodulation on each single-frequency response signal to extract the amplitude envelope of each single-frequency response signal includes: multiplying each single-frequency response signal with a local cosine reference signal and a sine reference signal of the same frequency; performing low-pass filtering on the product result to extract the in-phase component and the quadrature component; and calculating the instantaneous amplitude envelope of each single-frequency response signal based on the in-phase component and the quadrature component.

[0009] Optionally, the step of locating the voltage and current change rates within the switching operation range of the power semiconductor based on the decoupled high-frequency response signal, and performing online calibration of the parasitic inductance under the current operating condition, includes: calibrating the instantaneous value of the parasitic inductance under the current operating condition online using the dual-frequency envelope ratio based on the decoupled amplitude envelope; detecting the start and end times of the switching transient based on the change in the decoupled amplitude envelope, and dividing the switching transient sub-interval based on the start and end times of the switching transient; and calculating the voltage and current change rates within the divided switching transient sub-intervals by combining the calibrated instantaneous value of the parasitic inductance.

[0010] Optionally, the calculation of power semiconductor switching losses based on the voltage and current change rates and calibrated parasitic inductance within the located switching operation interval includes: calculating the turn-on loss using a pre-calibrated loss model based on the current change rate, steady-state load current, and instantaneous parasitic inductance value within the located turn-on transient sub-interval; calculating the turn-off loss using a pre-calibrated loss model based on the voltage change rate, DC bus voltage, equivalent output capacitance of the device, and turn-off transient duration within the located turn-off transient sub-interval; and calculating the total switching loss based on the turn-on loss and turn-off loss.

[0011] Optionally, the step of continuously iteratively updating loss data to detect the health status of power semiconductors includes: setting a power semiconductor health baseline value; calculating the loss rise rate based on the switching loss of the current cycle and the health baseline value; and determining the health status of power semiconductors based on the rise rate.

[0012] This application also provides an online detection device for power semiconductor switching losses. The device includes: a construction module for constructing a detection link; an injection acquisition module for injecting a dual-frequency carrier signal into the detection link and acquiring the high-frequency response voltage across the parasitic inductor in real time; a decoupling module for decoupling the acquired high-frequency response voltage, locating the voltage and current change rates within the switching operation range of the power semiconductor based on the decoupled high-frequency response signal, and calibrating the parasitic inductor under the current operating condition online; a calculation module for calculating the power semiconductor switching losses based on the located voltage and current change rates within the switching operation range and the calibrated parasitic inductor; and a detection module for calling the above modules to continuously iterate and update the loss data to detect the health status of the power semiconductor.

[0013] This application also provides a storage medium including instructions that, when executed on a computer, cause the computer to perform the method as described in the preceding claim.

[0014] This application also provides an electronic device comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor, when executing the program, implements the method as described in any of the preceding claims.

[0015] Compared with the prior art, the beneficial effects of this application are as follows: This application achieves accurate online detection of power semiconductor switching losses by injecting dual-frequency carrier signals and decoupling high-frequency response voltage, without directly measuring the high-voltage transient signals in the main circuit of the power semiconductor or interrupting normal system operation. Simultaneously, this application utilizes online parasitic inductance calibration and envelope derivative transient positioning methods to adaptively compensate for parameter drift caused by changes in operating conditions and device aging. It acquires turn-on and turn-off losses in real time within each PWM cycle and performs a graded assessment of health status based on continuous iterative updates. Attached Figure Description

[0016] Figure 1 This is a schematic flowchart of an online detection method for power semiconductor switching losses provided in one embodiment of this application; Figure 2 This is an equivalent circuit diagram of the detection link provided in another embodiment of this application; Figure 3 This is a schematic diagram of the structure of an online power semiconductor switching loss detection device provided in another embodiment of this application. Detailed Implementation

[0017] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0018] Figure 1 This is a schematic flowchart of an online detection method for power semiconductor switching losses provided in one embodiment of this application, as shown below. Figure 1 As shown, the method includes the following steps: S1: Construct the detection chain; S2: Inject dual-frequency carrier signals into the detection link and collect the high-frequency response voltage across the parasitic inductor in real time; S3: Decouple the high-frequency response voltage collected, locate the voltage and current change rate within the switching action range of the power semiconductor based on the decoupled high-frequency response signal, and perform online calibration of the parasitic inductance under the current operating condition. S4: Calculate the power semiconductor switching losses based on the voltage and current change rates and the calibrated parasitic inductance within the located switching operation range; S5: Repeat the above steps to continuously update the loss data in order to detect the health status of the power semiconductor.

[0019] Based on the above steps, this application enables high-precision, high-response-speed online evaluation of power semiconductor switching losses in each PWM cycle without the need for high-voltage sensors or interruption of normal system operation, and effectively assesses the health status of power semiconductors.

[0020] In another exemplary embodiment, step S1, constructing the detection link, includes the following steps: S11: In the gate drive circuit of the power semiconductor, a high-frequency signal is injected into the transformer in series; In this step, the secondary winding of the injection transformer is connected in series between the gate of the power semiconductor device and the driving resistor, or between the driving resistor and the gate terminal of the device. The injection transformer is a broadband transmission line transformer with a turns ratio of 1:1. The core is made of nickel-zinc ferrite or nanocrystalline material with good high-frequency characteristics, and the operating frequency covers 1MHz to 30MHz. The isolation voltage between the primary and secondary sides must be higher than the peak operating voltage of the power semiconductor and meet the requirements for enhanced insulation (e.g., a 1700V device needs to withstand a voltage of 2500V or higher). Furthermore, the primary side of the injection transformer is connected to a broadband signal generator or a digital frequency synthesizer embedded in the driver board via a coaxial cable, and a DC blocking capacitor (e.g., 100nF / 100V) is connected in series to prevent the DC component from magnetizing the core. It should also be noted that the frequency of the injected signal should be much higher than the switching frequency of the power semiconductor (e.g., 10MHz injection, 10kHz switching frequency), and the amplitude should be controlled within ±1V to ensure that it does not falsely trigger or change the effective switching threshold of the gate voltage.

[0021] Figure 2 This is an equivalent circuit diagram of a detection link provided in one embodiment of this application, such as... Figure 2 As shown, the equivalent circuit includes a power semiconductor device Q1, a high-frequency signal injection transformer T1, gate drive circuit elements, a parasitic inductor, a first low-noise differential detection terminal, and a second low-noise differential detection terminal. The secondary winding of the high-frequency signal injection transformer T1 is connected in series to the gate drive circuit of the power semiconductor device Q1 (specifically located between the drive resistor Rg and the gate of Q1). Its primary side is used to receive externally injected dual-frequency carrier signals. On the power circuit side of Q1, the parasitic inductor is equivalent to the connection between the Kelvin emitter terminal of Q1 and the power circuit reference point (the negative terminal of the DC bus). The first low-noise differential detection terminal is connected to the Kelvin emitter terminal of Q1, and the second low-noise differential detection terminal is connected to the power circuit reference point. The two detection terminals are connected to a high-impedance differential probe after passing through a high-voltage DC blocking capacitor to capture the high-frequency response voltage across the parasitic inductor. The back end is then connected in sequence to a differential amplifier, a programmable gain amplifier, and an ADC, thus forming a complete carrier injection and response pickup link.

[0022] S12: First and second low-noise differential detection terminals are pre-set near the power terminals of the power semiconductor, denoted as... and It is used to capture the high-frequency response voltage across the parasitic inductor.

[0023] In this step, this embodiment sets a first low-noise differential detection terminal and a second low-noise differential detection terminal between the main current terminal of the power semiconductor (e.g., the emitter auxiliary terminal or Kelvin terminal of the IGBT) and the power circuit reference point (e.g., the negative terminal of the DC bus), and the first and second detection terminals are connected to the differential acquisition unit through a DC blocking coupling unit. During detection, a high-impedance differential probe (input impedance greater than 1MΩ, common-mode rejection ratio higher than 60dB @ 10MHz) is used to pick up the signal, and a short grounding spring pin is used to directly connect to the detection point, with the ground wire length controlled within 1cm to avoid forming a magnetic loop antenna. In addition, to block the DC bus voltage, this embodiment connects a high-voltage DC blocking capacitor (e.g., 1nF / 3kV) in series at the probe input terminal, so that the back-end circuit can only pass high-frequency response signals, thereby achieving isolation of the high-voltage DC component.

[0024] Subsequently, the differential signals detected by the first and second differential detection terminals are sent to a high-speed comparator or programmable gain amplifier for level shifting and amplification to match the input range (e.g., 0~3.3V) of the subsequent ADC or digital demodulator.

[0025] It should be noted that the high-impedance differential probe and the series-connected high-voltage DC blocking capacitor used here are functionally positioned as a "high-frequency response signal pickup front-end," rather than a "high-voltage sensor" in the traditional sense. Specifically, the high-voltage DC blocking capacitor is used to block the DC bus voltage (e.g., 600V or higher) of the power semiconductor main circuit, allowing the back-end circuit to process only the high-frequency carrier response signal with an amplitude in the millivolt to hundreds of millivolt range superimposed on the high voltage. Therefore, throughout the entire detection process, the back-end signal conditioning and demodulation unit always operates in a low-voltage, small-signal state, completely exempt from the high voltage of the main circuit, and does not need to directly measure the full amplitude voltage of the switching transient. Based on this, this application achieves the core technical objective of "not requiring direct measurement of the high-voltage transient signal of the main circuit."

[0026] In another exemplary embodiment, step S2, injecting a dual-frequency carrier signal into the detection link and acquiring the high-frequency response voltage across the parasitic inductor in real time, includes the following steps: S21: Generate a dual-frequency carrier signal; In this step, this embodiment first employs a dual-channel direct digital frequency synthesizer or a dual-frequency signal generator to generate a first high-frequency sinusoidal carrier signal and a second high-frequency sinusoidal carrier signal with different frequencies but similar amplitudes. The configuration of these two signals is as follows: carrier frequency... , The amplitude is V. Next, the first high-frequency sinusoidal carrier signal and the second high-frequency sinusoidal carrier signal are combined into a single composite dual-frequency signal using a broadband adder to ensure that the phase difference between the two frequency components is constant and there is no intermodulation distortion.

[0027] S22: The generated dual-frequency carrier signal is injected into the detection link, and the high-frequency response voltage across the parasitic inductor is obtained in real time through high-voltage isolation sampling; In this step, the synthesized dual-frequency carrier signal is first input to the primary side of the pre-constructed injection transformer. The secondary side of the injection transformer is connected in series in the gate drive circuit of the power semiconductor device, thereby realizing the injection of the dual-frequency carrier signal into the detection link. After injection, a identifiable but insufficient response voltage will be generated across the parasitic inductance, with the peak-to-peak value of the response voltage controlled between 10mV and 200mV. Simultaneously, this embodiment captures the response signal across the parasitic inductance through two pre-set low-noise differential detection points. Specifically, two high-bandwidth differential probes are connected to the detection points respectively. A high-voltage DC blocking capacitor (e.g., 1nF / 3kV) is connected in series at the front end of the differential probe to block the DC bus voltage (e.g., 600V or higher) of the power semiconductor main circuit, allowing the back-end circuit to pass only high-frequency components. This is the core implementation method of "high-voltage isolation sampling"—through the physical isolation of the DC blocking capacitor, it is ensured that the subsequent signal conditioning and demodulation circuits always operate in a low-voltage, small-signal state, without having to withstand the high voltage of the main circuit. Furthermore, a high-speed data acquisition card is used to simultaneously acquire two differential signals after high-voltage isolation. The acquisition time window is set to cover the entire switching transient process (e.g., from 1 μs before switching action to 5 μs after action). Finally, the acquired two differential signals are subjected to online differential calculation to obtain the actual response voltage across the parasitic inductor. The actual response voltage is stored after high-pass filtering for subsequent decoupling processing. It should be noted that the combination of the high-voltage DC blocking capacitor and the differential probe is positioned as a "high-voltage isolation sampling front-end," not a "high-voltage sensor" in the traditional sense. Traditional high-voltage sensors are used to directly measure the full-amplitude transient waveform of the switching voltage across power semiconductors (typically hundreds to thousands of volts), while the sampling front-end in this application is only used to safely extract high-frequency carrier response signals with extremely low amplitudes (millivolts to hundreds of millivolts) in a high-voltage environment; the back-end circuit never comes into contact with the high voltage. Therefore, this step achieves the technical goal of "real-time acquisition of high-frequency response voltage via high-voltage isolation sampling," while maintaining the innovation of "no need to directly measure the high-voltage transient signal of the main circuit." In another exemplary embodiment, step S3 involves decoupling the acquired high-frequency response voltage, including the following steps: S31: Separate the high-frequency response voltages collected and extract the single-frequency response signals corresponding to the injected carrier frequency respectively; In this step, the high-frequency response voltage collected in this embodiment will be... The injection carrier frequencies are respectively obtained through two center frequencies. , The digital bandpass filter is used to extract the corresponding single-frequency response signal. and .

[0028] S32: Perform quadrature demodulation on each single-frequency response signal to extract the amplitude envelope of each single-frequency response signal; In this step, this embodiment first employs quadrature demodulation for each single-frequency response signal, that is, respectively... and Multiplied by the local cosine reference signal and sinusoidal reference signal Next, the product result is low-pass filtered to extract the in-phase component. and orthogonal components Then, the instantaneous amplitude envelope of each single-frequency response signal is calculated based on the in-phase and quadrature components. To reflect the parasitic inductive reactance during switching transients. Follow The time-domain fluctuations caused by changes.

[0029] S33: Obtain the dominant component of parasitic inductance by decoupling the amplitude envelope of the extracted single-frequency response signal.

[0030] In this step, the amplitude envelopes of two single-frequency response signals are first utilized. and Construct the following ratio relationship: It should be noted that, assuming that other high-frequency parasitic parameters (such as distributed capacitance, series resistance, etc.) have approximately the same effect on the two frequency responses, the ratio... The change is mainly dominated by the frequency-dependent variation of the inductive impedance of the parasitic inductance. Next, the ratio... The instantaneous parasitic inductance value under the current operating condition is mapped as follows: :

[0031] in, and These are the system calibration coefficients, which can be obtained by pre-fitting the response of a standard load with a known inductance value at different frequencies.

[0032] It should be noted that when establishing the mapping relationship between the dual-frequency envelope ratio and the instantaneous value of parasitic inductance, this embodiment first uses a standard load or inductor sample with a known inductance value for pre-calibration in an offline state. To cover the changes in operating conditions during actual operation, the pre-calibration process performs multi-point sampling under multiple temperature, load current, and DC bus voltage conditions, collecting corresponding data between the dual-frequency envelope ratio and the reference inductance value under different operating conditions. Based on the collected sample data, a polynomial mapping relationship between the ratio and inductance is established using the least squares fitting method, or a piecewise linear interpolation lookup table is constructed to achieve rapid online mapping of the inductance value. Alternatively, a piecewise fitting model can be used to improve the calibration accuracy in the nonlinear region based on the device characteristics. The calibration coefficients obtained through the above methods are stored in the system and used to calculate the instantaneous value of parasitic inductance under the current operating condition online based on the envelope ratio obtained from real-time decoupling during actual operation.

[0033] The dominant parasitic inductance component extracted based on the above method Voltage change rate can be used in subsequent switching loss calculations. and rate of change of current The assessment.

[0034] In summary, the above decoupling method does not rely on high-voltage sensors or complex circuit compensation. It can highlight the dominant component of parasitic inductance simply by utilizing the dual-frequency ratio relationship. It has strong anti-interference ability and adaptability to changes in operating conditions. Thus, it can obtain the instantaneous value of parasitic inductance reflecting the rate of change of current / voltage in each PWM cycle in real time and stably. This provides a key characteristic quantity with high linearity and low delay for subsequent switching loss calculation and health status detection.

[0035] In another exemplary embodiment, step S3, which involves locating the voltage and current change rates within the switching operation range of the power semiconductor based on the decoupled high-frequency response signal, and performing online calibration of the parasitic inductance under the current operating condition, includes the following steps: S311: Based on the decoupled amplitude envelope, the instantaneous value of parasitic inductance under the current operating condition is calibrated online by the dual-frequency envelope ratio; In this step, this embodiment utilizes the amplitude envelopes of the two decoupled single-frequency response signals. and The instantaneous value of parasitic inductance under the current operating condition is calibrated online. Specifically, because the rate of voltage change across the parasitic inductance increases rapidly during switching transients, the inductive impedance changes, causing a steep rising or falling edge in the amplitude envelope of the injected high-frequency response signal. To detect this transient, this embodiment uses the amplitude envelope... (Using a higher frequency carrier as an example for explanation): First, calculate the amplitude envelope. The time derivative (first difference) is expressed as:

[0036] in, This represents the sampling time interval.

[0037] Then, an empirical threshold is set. When the condition is met at a certain moment When the time is determined to be the start time of the switching transient. As the switching transient gradually ends, the envelope signal gradually recovers to the steady-state fluctuation range. Several consecutive sampling points are less than And envelope value The difference from the steady-state average is less than the preset tolerance. When the time is reached, it is determined to be the end time of the switching transient. .

[0038] Using the above method, this embodiment can accurately extract the time window of the switching transient within each PWM cycle, thereby providing an accurate time reference for subsequent sub-interval division and rate of change calculation.

[0039] S312: Detect the start and end times of the switch transient based on the change in amplitude envelope after decoupling, and divide the switch transient sub-interval based on the start and end times of the switch transient; In this step, at the start time of obtaining the switching transient... and end time Subsequently, this embodiment further divides the transient interval into a turn-on transient sub-interval and a turn-off transient sub-interval, and identifies the current rate of change-dominated stage and the voltage rate of change-dominated stage respectively based on the physical process. The turn-on transient sub-interval is defined as the period from the start of the gate voltage rise to the end of the Miller plateau; this stage is mainly driven by the current rate of change. Dominant; the turn-off transient sub-interval is defined as the period from the start of the gate voltage decrease to the end of the current decrease, and this phase is characterized by the voltage change rate. Dominant; in addition, for precise positioning Maximum time and At the maximum moment, this embodiment utilizes the envelope The first derivative peak detection method is used for determination. Specifically, within the detected switching transient window, the envelope signal is calculated. first derivative The moment corresponding to the maximum absolute value of the derivative is the moment when the rate of change is most significant. Furthermore, this embodiment distinguishes between a turn-on transient and a turn-off transient by determining the sign of the first derivative, specifically as follows: when When the positive peak value is at its maximum, it corresponds to the turn-on transient. The largest moment is recorded as ; when When the negative peak value is at its minimum, it corresponds to the turn-off transient. The largest moment is recorded as .

[0040] In summary, this embodiment, through the first derivative peak detection method described above, can quickly and reliably locate key characteristic moments in the switching transient without relying on the gate drive signal, thereby providing a basis for subsequent rate of change calculation.

[0041] S313: Within the defined transient sub-intervals of the switch, calculate the rate of change of voltage and current by combining the calibrated instantaneous value of parasitic inductance.

[0042] In this step, after accurately locating the transient sub-interval of the switch, this embodiment utilizes the response voltage across the parasitic inductor. and the instantaneous value of parasitic inductance obtained by calibration of the two envelope ratios. Calculate the rate of change of current and the rate of change of voltage, respectively. The rate of change of current is calculated as follows:

[0043] in, To acquire and differentially obtain the response voltage, For the current PWM cycle, the ratio is determined by step S33. The parasitic inductance value obtained from online calibration.

[0044] For voltage change rate Considering the output capacitance of power semiconductor devices during switching transients... The voltage change is related to the current flowing through the device. In this embodiment, the voltage change rate is calculated using the following method:

[0045] in, This represents the current flowing through the power semiconductor at the current moment. This is the nonlinear output capacitance of the device, and its value varies with the collector-emitter voltage. change.

[0046] In summary, based on the above steps, this embodiment can obtain the amplitude envelope of the high-frequency response voltage across the parasitic inductor by injecting a dual-frequency carrier signal and decoupling, without relying on a high-voltage sensor or interrupting the normal operation of the system. and Using the ratio of the two Online calibration to obtain the instantaneous value of parasitic inductance under the current operating conditions At the same time, by analyzing the amplitude envelope... Peak detection is performed using the first derivative to accurately locate the start and end times of the switching transient within each PWM cycle. This allows for the division of turn-on and turn-off transient sub-intervals and the determination of the characteristic moments when the current and voltage change rates are at their maximum. This enables the location of the voltage and current change rates within the switching action range of the power semiconductor.

[0047] In another exemplary embodiment, step S4, calculating the power semiconductor switching loss based on the voltage and current change rate within the located switching operation range and the calibrated parasitic inductance, includes the following steps: S41: Based on the current change rate, steady-state load current, and instantaneous value of parasitic inductance within the located turn-on transient sub-interval, the turn-on loss is calculated using a pre-calibrated loss model. In this step, this embodiment utilizes the voltage across the parasitic inductor. The energy coupling relationship between voltage and current change rates during switching transients is considered, and the turn-on loss is calculated using the following pre-calibrated turn-on loss model. :

[0048] in, For activation losses; The pre-calibrated turn-on loss empirical coefficient (e.g., a value of 0.3~0.5) is specifically pre-calibrated based on the device characteristics; This is the steady-state load current; This is the instantaneous value of the parasitic inductance; This refers to the maximum rate of change of current during the turn-on transient.

[0049] S42: Based on the voltage change rate, DC bus voltage, equivalent output capacitance of the device, and duration of the turn-off transient within the located turn-off transient sub-interval, the turn-off loss is calculated using a pre-calibrated loss model. In this step, this embodiment calculates the turn-off loss based on the relationship between the voltage change rate and the bus voltage, and on the following pre-calibrated turn-off loss model. The specific calculations are as follows:

[0050] in, This is the equivalent output capacitance of the device; This is the DC bus voltage; This refers to the maximum rate of change of voltage during the identified turn-off transient. The duration of the shutdown transient for positioning; This is an empirical coefficient, for example, a value of 0.4 to 0.6.

[0051] S43: Based on turn-on loss and shutdown losses Calculate total switching losses .

[0052] In this step, after obtaining the turn-on loss and turn-off loss, this embodiment calculates the total switching loss in the current PWM cycle using the following summation method:

[0053] In another exemplary embodiment, step S5 involves continuously iteratively updating the loss data to detect the health status of the power semiconductor, including the following steps: S51: Set the power semiconductor health baseline value; In this step, after the system is powered on and the devices are in a known healthy state, this embodiment continuously measures the switching losses for 100 PWM cycles and takes the average value as the health baseline value. .

[0054] S52: Perform periodic updates and health assessments; In this step, the following operations are performed in each PWM cycle: 1. Calculate the switching loss for the current cycle according to step S4. ; 2. Based on health benchmarks and the switching losses of the current cycle Calculate the rate of increase in losses: rate of increase =

[0055] 3. The health status of power semiconductors is determined based on the rate of rise. In this embodiment, the determination rules are defined as follows: When the rate of increase The power semiconductors are in good condition; when rate of increase It is necessary to strengthen the status monitoring of power semiconductors; when rate of increase An abnormal warning needs to be issued; When the rate of increase The power semiconductor is in a severely faulty state.

[0056] In summary, this application, through its health status detection method that continuously iterates and updates loss data, enables real-time online assessment of the health status of power semiconductors without requiring external high-voltage sensors or interrupting normal system operation. This is achieved by utilizing the switching losses obtained through dual-frequency injection decoupling and their long-term trend changes. By establishing a health benchmark, periodically updating loss data, and comparing it with preset thresholds, this application can automatically identify multiple degradation levels from "healthy" to "dangerous," and issue timely warnings when losses abnormally increase. Simultaneously, an optional adaptive benchmark update mechanism effectively compensates for the slow drift caused by normal aging, avoiding false alarms. Compared to traditional methods relying on periodic offline detection or thermal resistance network back-calculation, this application offers advantages such as fast response, high accuracy, strong resistance to operating condition interference, and ease of integration into drivers for long-term online monitoring.

[0057] In another exemplary embodiment, this application also provides an online detection device for power semiconductor switching losses, such as... Figure 3 As shown, the device includes: a construction module 100 for constructing a detection link; an injection acquisition module 200 for injecting a dual-frequency carrier signal into the detection link and acquiring the high-frequency response voltage across the parasitic inductor in real time; a decoupling module 300 for decoupling the acquired high-frequency response voltage, locating the voltage and current change rates within the switching operation range of the power semiconductor based on the decoupled high-frequency response signal, and calibrating the parasitic inductor under the current operating condition online; a calculation module 400 for calculating the switching losses of the power semiconductor based on the located voltage and current change rates within the switching operation range and the calibrated parasitic inductor; and a detection module 500 for calling the above modules and continuously iteratively updating the loss data to detect the health status of the power semiconductor.

[0058] In another exemplary embodiment, this application also provides a storage medium including instructions that, when executed on a computer, cause the computer to perform the online power semiconductor switching loss detection method as described in the preceding embodiments.

[0059] In another exemplary embodiment, this application also provides an electronic device, the electronic device comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the online detection method for power semiconductor switching losses as described in the preceding embodiments.

[0060] The above are merely preferred embodiments of this application and do not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A method for online detection of power semiconductor switching losses, characterized in that, The method includes: Build a detection chain; A dual-frequency carrier signal is injected into the detection link, and the high-frequency response voltage across the parasitic inductor is acquired in real time. The high-frequency response voltage is decoupled from the signal. Based on the decoupled amplitude envelope, the instantaneous value of parasitic inductance under the current operating condition is calibrated online by the ratio of the dual-frequency envelope. The start and end times of the switching transient are detected based on the change of the decoupled amplitude envelope, and the switching transient sub-intervals are divided based on the start and end times of the switching transient. Within the divided switching transient sub-intervals, the voltage and current change rates are calculated by combining the calibrated instantaneous value of parasitic inductance. Based on the current change rate, steady-state load current, and instantaneous parasitic inductance value within the located turn-on transient sub-interval, the turn-on loss is calculated using a pre-calibrated loss model; based on the voltage change rate, DC bus voltage, equivalent output capacitance of the device, and turn-off transient duration within the located turn-off transient sub-interval, the turn-off loss is calculated using a pre-calibrated loss model; and the total switching loss is calculated based on the turn-on and turn-off losses. Repeat the above steps to continuously iterate and update the loss data in order to detect the health status of the power semiconductor.

2. The online detection method according to claim 1, characterized in that, The construction of the detection link includes: In the gate drive circuit of a power semiconductor, a high-frequency signal is injected into the transformer in series. First and second low-noise differential detection terminals are pre-positioned near the power terminals of the power semiconductor to capture the high-frequency response voltage across the parasitic inductance.

3. The online detection method according to claim 1, characterized in that, The signal decoupling of the acquired high-frequency response voltage includes: The high-frequency response voltages collected are separated, and the single-frequency response signals corresponding to the injected carrier frequency are extracted respectively; Quadrature demodulation is performed on each single-frequency response signal to extract the amplitude envelope of each single-frequency response signal; The parasitic inductance dominant component is obtained by decoupling the amplitude envelope of the extracted single-frequency response signal to complete the high-frequency response voltage decoupling.

4. The online detection method according to claim 3, characterized in that, The step of performing quadrature demodulation on each single-frequency response signal to extract the amplitude envelope of each single-frequency response signal includes: Multiply each single-frequency response signal by the local cosine reference signal and sine reference signal of the same frequency; The product result is low-pass filtered to extract the in-phase and quadrature components; The instantaneous amplitude envelope of each single-frequency response signal is calculated based on the in-phase and quadrature components.

5. The online detection method according to claim 1, characterized in that, The method of detecting the health status of power semiconductors by continuously iteratively updating loss data includes: Set a health baseline value for power semiconductors; The loss rise rate is calculated based on the switching losses and health baseline values ​​of the current cycle, and the health status of the power semiconductor is determined based on the rise rate.

6. An online detection device for power semiconductor switching losses, characterized in that, For implementing the method as described in any one of claims 1-5, the apparatus comprises: Modules for building the detection chain; The injection acquisition module is used to inject dual-frequency carrier signals into the detection link and acquire the high-frequency response voltage across the parasitic inductor in real time. The decoupling module is used to decouple the acquired high-frequency response voltage signal, locate the voltage and current change rate within the switching action range of the power semiconductor based on the decoupled high-frequency response signal, and perform online calibration of the parasitic inductance under the current operating condition. The calculation module is used to calculate the power semiconductor switching losses based on the voltage and current change rate and the calibrated parasitic inductance within the located switching operation range. The detection module is used to call the above modules and continuously iterate and update the loss data to detect the health status of the power semiconductor.

7. A storage medium, characterized in that, It includes instructions that, when executed on a computer, cause the computer to perform the method as described in any one of claims 1 to 5.

8. An electronic device, characterized in that, The electronic device includes: Memory, processor, and computer programs stored in memory and executable on the processor, wherein, When the processor executes the program, it implements the method as described in any one of claims 1 to 5.

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