Chip testing system and testing method based on pin multiplexing

Abstract

The application discloses a chip test system and method based on pin multiplexing, and relates to the technical field of chip testing. The system comprises a chip under test and a sequence sending device located outside the chip under test. The chip under test comprises at least a sequence detector and a pin multiplexing module. The sequence detector is connected to a sequence receiving pin of the chip under test. The sequence detector is used for identifying a test sequence signal sent by the sequence sending device and outputting a corresponding control signal to the pin multiplexing module according to an identification result. The pin multiplexing module switches and connects a test observation pin on the chip under test to an observation point corresponding to the control signal inside the chip under test according to the control signal, so that chip back piece hardware state testing is realized without running software of the chip under test. The application is used for solving the problem that a conventional pin multiplexing chip test method in the prior art cannot meet test requirements in a scenario where early software of a chip back piece is not started or cannot be run.

Description

Technical Field

[0001] This invention relates to the field of chip testing technology, and in particular to a chip testing system and method based on pin multiplexing. Background Technology

[0002] As chip functions and applications become increasingly complex, pin reuse has become a standard practice in chip design to reduce pin count and optimize chip layout. In the initial testing phase after chip fabrication, in addition to normal functional verification, it is also necessary to detect and locate faults in the chip's internal signals and critical node states. To avoid test signals occupying too many pins and affecting the chip's normal function, existing technologies typically employ two methods to implement pin reuse in test modes: First, a dedicated default test pin is reserved. After the test is completed, the test function is turned off and switched back to the normal function. Secondly, by pulling up or down the level of specific pins, the chip can be made to enter a preset test mode.

[0003] However, all of the above methods have significant limitations: dedicated test pins increase chip pin overhead, and pull-up / pull-down methods can only achieve a limited number of fixed mode switching, failing to meet complex and diverse testing needs. More importantly, in the early stages of chip return, design or process defects can easily cause the CPU to fail to boot and the software program to fail to run. Traditional pin multiplexing switching relies on the chip to boot normally and the software to configure registers. Once the software fails to run, it is impossible to switch pin functions, let alone observe the internal signals and status of the chip, making it impossible to locate chip faults and conduct tests.

[0004] Therefore, existing pin-reuse chip testing methods can no longer meet the chip testing needs in scenarios where the software is not started or cannot run in the early stages of chip return. There is an urgent need for a testing method that does not rely on CPU and software operation and can freely switch the pin reuse mode directly through external signals after the chip is powered on, so as to achieve rapid detection of the internal state of the chip and fault location. Summary of the Invention

[0005] The purpose of this invention is to provide a chip testing system and method based on pin multiplexing, which solves the problem that traditional pin multiplexing chip testing methods in the prior art cannot meet the testing requirements in scenarios where the software has not been started or cannot run in the early stages of chip return.

[0006] To achieve the above objectives, the present invention provides the following technical solution: In a first aspect, the present invention provides a chip testing system based on pin multiplexing, the system comprising: a chip under test and a sequence transmission device located outside the chip under test; The chip under test includes at least a sequence detector and a pin multiplexing module; the sequence detector is connected to the sequence receiving pin of the chip under test; the sequence detector is connected to the pin multiplexing module. The sequence detector is used to identify the test sequence signal sent by the sequence transmitting device, and outputs the corresponding control signal to the pin multiplexing module according to the identification result; The pin multiplexing module switches the test observation pins on the chip under test to the observation points inside the chip under test corresponding to the control signals according to the control signals, so as to realize the chip return hardware status test when the chip under test is not running software.

[0007] In one alternative implementation, the sequence transmitting device is any one of UART, SPI, GPIO, or JTAG sequence generator.

[0008] In one alternative implementation, the chip under test further includes a CPU; When the CPU is able to run the software normally, the sequence detector has a higher priority for controlling the pin multiplexing module than the priority configured by the CPU through software.

[0009] In one alternative implementation, the chip under test further includes a non-volatile memory unit for disabling sequence detection functionality.

[0010] In one alternative implementation, the non-volatile storage unit is an OTP or an eFuse.

[0011] In one optional implementation, the observation point includes at least one of the following: clock signal observation point, reset signal observation point, bus ready signal observation point, power status observation point, internal regulator output observation point, PLL lock signal observation point, bus clock observation point, reset state machine observation point, critical register default value observation point, and IO default level observation point.

[0012] In one alternative implementation, the sequence detector is connected to the input terminal of the sequence receiving pin of the chip under test.

[0013] In one alternative implementation, the pin multiplexing module includes a multiplexer and a control circuit; the control circuit is connected to the multiplexer. The multiplexer has multiple inputs connected to different observation points, and the multiplexer's output is connected to the test observation pin. The control circuit controls the multiplexer to select the corresponding observation point based on the control signal.

[0014] Compared with existing technologies, the chip testing system based on pin multiplexing provided by this invention, by independently setting up a sequence detector and a pin multiplexing module inside the chip under test, enables the testing process to be independent of CPU operation, software configuration, and the logic initialization of traditional pin multiplexing modules. This fundamentally solves the technical problem that traditional pin multiplexing chip testing methods cannot meet testing requirements in scenarios where software has not started or cannot run when the chip is returned to the die. Specifically, by directly connecting the sequence detector to the chip's sequence receiving pin, the system can immediately identify externally sent test sequence signals after the chip is powered on and directly output control signals to the pin multiplexing module. The pin multiplexing module directly switches the test observation pins to the corresponding observation points according to the control signals, enabling rapid observation of hardware status and fault location in the early stages of chip return without waiting for CPU startup or running any software programs. Therefore, this invention significantly improves the efficiency and reliability of chip return testing, and is particularly suitable for extreme testing scenarios such as chip malfunctions, CPU failure to start, and software malfunction, effectively overcoming the shortcomings of existing technologies.

[0015] Secondly, the present invention also provides a chip testing method based on pin multiplexing, implemented using any of the above-mentioned chip testing systems based on pin multiplexing, the method comprising: Using an external sequence transmitting device, a test sequence signal is sent to the chip under test through the sequence receiving pin on the chip under test; The sequence detector in the chip under test receives and identifies the test sequence signal, and outputs the corresponding control signal to the pin multiplexing module in the chip under test according to the identification result; The pin multiplexing module switches the test observation pins on the chip under test to different observation points according to the control signal, so as to realize the chip return hardware status test when the chip under test is not running software.

[0016] In one alternative implementation, the method further includes: After the test is completed, the sequence detection function is turned off by programming the non-volatile memory cells in the chip under test. Attached Figure Description

[0017] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings: Figure 1 A schematic diagram of a chip testing system based on pin multiplexing provided in an embodiment of the present invention; Figure 2 A schematic diagram of the internal structure of the sequence receiving pin and the connection position of the sequence detector is provided for one embodiment of the present invention; Figure 3A schematic diagram illustrating the structure and connection relationship of a pin multiplexing module provided in one embodiment of the present invention; Figure 4 This is a flowchart illustrating a chip testing method based on pin multiplexing, provided as an embodiment of the present invention.

[0018] 1-Chip under test; 10-Sequence detector; 11-Pin multiplexing module; 110-Multiple choice; 111-Control circuit; 12-CPU; 13-Non-volatile memory unit; 2-Sequence transmission device. Detailed Implementation

[0019] To facilitate a clear description of the technical solutions in the embodiments of the present invention, the terms "first" and "second" are used to distinguish identical or similar items with essentially the same function and effect. For example, the first threshold and the second threshold are merely used to distinguish different thresholds and do not limit their order. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or execution order, and that the terms "first" and "second" are not necessarily different.

[0020] It should be noted that in this invention, the terms "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in this invention should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0021] In this invention, "at least one" means one or more, and "more than one" means two or more. "And / or" describes the relationship between the associated objects, indicating that three relationships can exist.

[0022] like Figure 1 As shown, this embodiment of the invention provides a chip testing system based on pin multiplexing. The system includes: a chip under test 1 and a sequence transmission device 2 located outside the chip under test. The chip under test 1 includes at least a sequence detector 10 and a pin multiplexing module 11; the sequence detector is connected to the sequence receiving pin of the chip under test; the sequence detector 10 is connected to the pin multiplexing module 11; The sequence detector 10 is used to identify the test sequence signal sent by the sequence transmitting device 2, and outputs the corresponding control signal to the pin multiplexing module 11 according to the identification result; The pin multiplexing module 11 switches the test observation pins on the chip under test to the observation points inside the chip under test corresponding to the control signals according to the control signals, so as to realize the chip return hardware status test when the chip under test is not running software. The test sequence signal contains at least one test instruction, and the control signal contains control sub-signals that correspond one-to-one with the test instruction. Each control sub-signal corresponds to one observation point.

[0023] For example, Figure 1 There are n observation points and p external pins, where n and p are both positive integers greater than or equal to 1.

[0024] For example, external pin 0 can be used as the sequence receiving pin, and external pin p can be used as the test observation pin.

[0025] Understandably, see Figure 1 The chip under test 1 also includes a CPU (Central Processing Unit) 12.

[0026] An observation point is a signal node set up to realize the internal state detection of the chip. It is used to lead the internal hardware state signals of the chip to the pin multiplexing module so that the output and observation can be carried out externally through the test observation pin.

[0027] For example, the observation point may include at least one of the following: clock signal observation point, reset signal observation point, bus ready signal observation point, power status observation point, internal regulator output observation point, PLL (Phase Locked Loop) lock signal observation point, bus clock observation point, reset state machine observation point, key register default value observation point, and IO default level observation point.

[0028] The beneficial effects of this embodiment are as follows: By setting a sequence detector and a pin multiplexing module inside the chip under test (DUT), a sequence transmitting device located outside the DUT sends test sequence signals to the sequence receiving pins of the DUT. After recognizing the test sequence signal, the sequence detector directly outputs the corresponding control signal, thereby controlling the pin multiplexing module in hardware to switch the test observation pins on the DUT to the corresponding observation points. The entire testing process does not require CPU startup, software program execution, or register configuration. Even if the CPU fails to work or the software fails to run due to design or process defects in the DUT, the observation of the internal hardware status of the DUT and fault location can still be stably achieved.

[0029] Meanwhile, this invention achieves testing functions by reusing the existing external pins of the chip under test, without the need to add additional dedicated test pins, thus avoiding pin overhead. By applying different test sequence signals to the same test observation pin, multiple observation modes can be flexibly switched, which can meet diverse and complex chip testing needs and overcome the shortcomings of traditional level pull-up and pull-down methods that can only switch a few fixed test modes.

[0030] Therefore, this invention enables rapid detection of hardware status and fault location in the early stages of chip return without software or CPU, effectively compensating for the shortcomings of existing chip testing methods.

[0031] In an exemplary embodiment, the sequence transmitting device is any one of UART (Universal Asynchronous Receiver / Transmitter), SPI (Serial Peripheral Interface), GPIO (General-Purpose Input / Output), or JTAG (Joint Test Action Group) sequence generator.

[0032] In this embodiment, a general-purpose digital interface can be used to send test sequence signals without the need for dedicated test equipment. It is compatible with existing chip debugging environments, reduces test hardware costs, and improves the versatility and portability of the solution, making it suitable for chip testing scenarios with different interface types.

[0033] In an exemplary embodiment, when the CPU is able to run the software normally, the sequence detector has a higher control priority over the pin multiplexing module than the priority configured by the CPU through software.

[0034] The beneficial effects of this embodiment are: by setting the hardware test path to have a higher priority than the software configuration, it ensures that external test commands can be responded to first, avoids test function failure due to software configuration conflicts, crashes or anomalies, improves the stability and reliability of the test system, and enables the chip to complete internal observation normally even in a fault state.

[0035] In an exemplary embodiment, see Figure 1 The chip under test also includes a non-volatile memory unit 13, which is used to disable the sequence detection function. Specifically, after the test is completed, the working state of the sequence detector can be disabled by writing the corresponding control bits in the non-volatile memory unit, thus permanently disabling the sequence detection function.

[0036] For example, non-volatile memory cells are OTP (One-Time Programmable) or eFuse (Electrical Fuse).

[0037] The combined function of OTP and eFuse is to ensure that data is not lost when power is off, to permanently disable the sequence debugging function of this invention, to seal the test port during mass production, and to prevent leakage and tampering.

[0038] The beneficial effects of this embodiment are as follows: By setting a non-volatile memory unit within the chip, the sequence detection function can be permanently shut down after the test is completed, preventing the test circuit from interfering with the normal operation of the chip; at the same time, the use of a hardware-level one-time programmable unit eliminates the need for additional control circuits, resulting in a simple circuit structure, high reliability, and unrecoverable functionality after programming, which can completely shut down the test path at the physical level, ensuring that the chip will not accidentally enable the test function during multiple power-ups and shutdowns and long-term use, thus protecting the chip's functional safety, information security, and anti-tampering capabilities at the hardware level, and meeting the safety specifications for chip mass production and delivery.

[0039] In an exemplary embodiment, the sequence detector is connected to the input terminal of the sequence receiving pin of the chip under test.

[0040] In practical implementation, the chip's pins physically function as pads, or PADs, for signal connections between the chip and the external environment. Regardless of whether the receiver pin is a unidirectional input pin or a bidirectional input / output (I / O) pin, it internally contains independent input and output paths. See Figure 2 The sequence detector is directly connected to the output of the input buffer (pin input), located before the pin multiplexing module and other internal modules. It can directly acquire the raw test sequence signal without any internal circuit processing. The external test sequence signal first reaches the physical pin pad (PAD), passes through the pin's input buffer, and enters the chip under test (DUT). The output of this input buffer is the pin input, representing the entry point for the external signal into the DUT's internal hardware circuitry. The test sequence signal continues from the pin input into the DUT's internal hardware circuitry, including the pin multiplexing module, function control circuitry, and output driver circuitry. For bidirectional pins, the input and output paths are independent; the input path is activated upon power-up, requiring neither CPU configuration nor software operation.

[0041] The sequence detector of this invention is directly connected to the pin input of the sequence receiving pin, that is, connected to the output of the input buffer, and located before all the internal hardware circuits of the chip under test. The purpose of this connection method is to enable the sequence detector to acquire the most original, authentic external test sequence signal without any internal circuit processing, and to avoid the pin multiplexing module, output driver circuit or other internal hardware circuits from obstructing, rewriting or interfering with the test sequence signal.

[0042] If the sequence detector is connected after the pin multiplexing module or other internal hardware circuits of the chip under test, the test sequence signal will first pass through these circuits for processing and switching. This may result in signal shielding, tampering, or failure to transmit normally, causing the sequence detector to fail to correctly identify externally input test sequence signals. Especially in the early stages of chip return, when the CPU is not powered on, or when the software is not running, the pin multiplexing module is usually in a default unconfigured state, which cannot guarantee normal signal transmission. Therefore, connecting the sequence detector directly to the pin input terminal allows the testing function to operate independently of internal circuit configuration, CPU startup, and software operation. The chip can respond to external test sequence signals in real time after power-on, ensuring the reliability and availability of hardware state testing in the early stages of chip return.

[0043] In an exemplary embodiment, see Figure 3 The pin multiplexing module 11 includes a multiplexer 110 and a control circuit 111; the control circuit 111 is connected to the multiplexer 110. The multiple inputs of the multiplexer 110 are connected to different observation points, and the output of the multiplexer 110 is connected to the test observation pin. The control circuit 111 controls the multiplexer 110 to select the corresponding observation point according to the corresponding control signal output by the sequence detector.

[0044] Specifically, see Figure 3 Observation point 1 is connected to the first input terminal I0 of multiplexer 110, observation point 2 is connected to the second input terminal I1 of multiplexer 110, and so on, with observation point n connected to the nth input terminal In-1 of multiplexer 110. Multiplexer 110 is a multi-input single-output selection circuit, and its one output terminal Out outputs only the signal of the currently selected observation point, that is, the selected observation signal shown by the arrow in the figure.

[0045] Control circuit 111 is connected to multiple selection terminals of multiplexer 110. The number of selection terminals is determined by the total number of observation points n, and is not less than [a certain value]. The smallest integer is used to ensure that enough encoded signals can be generated to uniquely select each observation point. The control signal output by the sequence detector 10 is decoded by the control circuit 111 to generate a multiplexing signal, which is then input to the selection terminal of the multiplexer 110 to achieve switching and selection of different observation points.

[0046] The chip testing method based on pin multiplexing provided by the present invention is described below. The chip testing method based on pin multiplexing described below can be referred to in correspondence with the chip testing system based on pin multiplexing described above.

[0047] like Figure 4 As shown, embodiments of the present invention also provide a chip testing method based on pin multiplexing, implemented using the chip testing system based on pin multiplexing in any of the above embodiments. This chip testing method based on pin multiplexing may include: Step S1: Using the external sequence transmitting device of the chip under test, send the test sequence signal to the chip under test through the sequence receiving pin on the chip under test; Step S2: The sequence detector in the chip under test receives and identifies the test sequence signal, and outputs the corresponding control signal to the pin multiplexing module in the chip under test according to the identification result; Step S3: The pin multiplexing module switches the test observation pins on the chip under test to different observation points according to the control signal, so as to realize the chip return hardware status test when the chip under test is not running software.

[0048] In an exemplary embodiment, after the test is completed, the non-volatile memory cell in the chip under test is programmed to disable the sequence detection function, thereby restoring the chip to normal working mode without affecting subsequent mass production and use.

[0049] In one specific embodiment, the complete test process of this embodiment is illustrated below in the scenario where the CPU is not started and the software is not running in the early stage of chip return (in the following process, the chip under test will be simply referred to as the chip): In this embodiment, the sequence sending device on the PC (Personal Computer) uses a UART serial port to send test sequence signals to the chip through the chip's sequence receiving pin (pin 0).

[0050] The test sequence signal is a series of consecutive high and low level combinations, which is equivalent to the hardware test instructions of the chip. The sequence detector is used to identify the test sequence signal and output a control signal according to the identification result, which controls the multiplexer in the pin multiplexing module to complete the switching of observation points.

[0051] After the chip is returned to the die, pin 0 is directly connected to the TX terminal of the UART serial port, and no changes to the test environment are required throughout the process. If the chip is working properly and the CPU can run software, you can send commands to the CPU via the UART serial port for routine debugging. If the chip malfunctions, the CPU fails to start, or the software fails to run, a series of test sequence signals will be sent directly through the UART serial port via the PC-side serial port debugging assistant. The internal hardware circuit of the chip will automatically select multiple observation points in sequence according to the preset timing, realizing automatic testing without software.

[0052] The chip has multiple observation points pre-set inside, including but not limited to clock signal observation points, reset signal observation points, bus ready signal observation points, power status observation points, PLL lock signal observation points, etc.

[0053] Testers can include any number of test instructions in a single test sequence signal according to their testing needs, and the chip hardware will automatically execute them in sequence without needing to send them multiple times.

[0054] In this embodiment, for ease of explanation, the tester includes the following three consecutive test instructions in a test sequence signal: clock signal observation, reset signal observation, and bus ready signal observation.

[0055] The pin multiplexing module includes a multiplexer and a control circuit; the multiple input terminals of the multiplexer are connected to different observation points inside the chip, and the output terminal is connected to the test observation pin; the number of selection terminals is determined by the maximum number of observation points supported by the chip, ensuring that any observation point can be uniquely selected.

[0056] This embodiment also includes testing equipment, which is an oscilloscope or logic analyzer, and is an important part of the chip testing system. It is used to obtain and observe the actual state of the signals inside the chip from the test observation pins.

[0057] In the early stages of chip return, when the CPU is not started and the software is not running, testers only need to send a complete test sequence signal without changing the wiring, and the chip can automatically complete multiple tests in sequence.

[0058] In this test, the PC-side serial port debugging assistant sent a complete test sequence signal to pin 0 via the UART serial port: The test sequence signal = clock observation instruction + reset observation instruction + bus ready observation instruction, i.e.: sequence 0001_0010_0011, where: 0001: Indicates a test command to switch to clock observation; 0010: Indicates a test command to switch to reset observation; 0011: Indicates a test command to switch to bus-ready observation.

[0059] After receiving the test sequence signal, the chip hardware automatically switches and executes the commands according to the built-in instruction sequence of the test sequence signal, without waiting for external observation feedback, as follows: Step (1): Automatically perform clock observation Test command: 0001; The sequence detector recognized the instruction and obtained the recognition result: it is currently necessary to switch to the clock signal observation point; Based on the recognition result, the sequence detector outputs the corresponding control sub-signal: 000; The control circuit receives the control sub-signal 000 and drives the multiplexer to select the clock signal observation point. The testing equipment can be used to observe the following at the test observation pins: whether the chip clock starts oscillating, whether the signal is stable, and whether the frequency meets expectations.

[0060] After clock observation is completed, the internal hardware circuitry of the chip automatically switches to the next test instruction according to the preset timing sequence.

[0061] Step (2): Automatically execute reset observation Test command: 0010; The sequence detector recognized the instruction and obtained the recognition result: It is currently necessary to switch to the reset signal observation point; Based on the recognition result, the sequence detector outputs the corresponding control sub-signal: 001; The control circuit receives control sub-signal 001 and drives the multiplexer to select the reset signal observation point. The testing equipment can observe the following at the test observation pins: whether the chip reset is released normally, whether the reset is successfully completed, and whether the reset level meets the design requirements.

[0062] After the reset observation is completed, the internal hardware circuit of the chip automatically switches to the last test instruction according to the preset timing.

[0063] Step (3): Automatically perform bus-ready observation Test command: 0011; The sequence detector recognized the instruction and obtained the recognition result: It is currently necessary to switch to the bus ready signal observation point; Based on the recognition result, the sequence detector outputs the corresponding control sub-signal: 100; The control circuit receives the control sub-signal 100 and drives the multiplexer to select the bus ready signal observation point. The testing equipment can observe the following at the test observation pin: Check if the bus ready signal is abnormally pulled low / locked, and whether the internal bus status is normal.

[0064] Step (4): Test complete → Disable test function (lock it in mass production) After all tests are completed, the sequence detector's test function is permanently disabled by programming the corresponding control bits of the non-volatile memory cells (OTP or eFuse) inside the chip.

[0065] After being shut down, the test path becomes ineffective, the chip returns to normal operating mode, and the test port is physically sealed to prevent leakage and tampering, without affecting subsequent mass production and use.

[0066] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings, the disclosure, and the appended claims in carrying out the claimed invention. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality.

[0067] Although the invention has been described in conjunction with specific features and embodiments, it is obvious that various modifications and combinations can be made therein without departing from the spirit and scope of the invention. Accordingly, this specification and drawings are merely exemplary descriptions of the invention as defined by the appended claims, and are considered to cover any and all modifications, variations, combinations, or equivalents within the scope of the invention. Clearly, those skilled in the art can make various alterations and modifications to the invention without departing from its spirit and scope. Thus, if such modifications and modifications of the invention fall within the scope of the claims and their equivalents, the invention is also intended to include such modifications and modifications.

Claims

1. A chip testing system based on pin multiplexing, characterized in that, The system includes: a chip under test and a sequence transmission device located outside the chip under test; The chip under test includes at least a sequence detector and a pin multiplexing module; the sequence detector is connected to the input terminal of the sequence receiving pin of the chip under test, connected to the output terminal of the input buffer, and located before the pin multiplexing module and other internal modules, directly acquiring the raw test sequence signal without any internal circuit processing; the sequence detector is connected to the pin multiplexing module; the sequence transmitting device is any one of UART, SPI, GPIO, and JTAG sequence generator; The sequence detector is used to identify the test sequence signal sent by the sequence sending device, and outputs a corresponding control signal to the pin multiplexing module according to the identification result; the test sequence signal contains at least one test instruction; the control signal contains control sub-signals that correspond one-to-one with the test instruction, and each control sub-signal corresponds to an observation point; the observation point includes at least one of the following: clock signal observation point, reset signal observation point, bus ready signal observation point, power status observation point, internal regulator output observation point, PLL lock signal observation point, bus clock observation point, reset state machine observation point, key register default value observation point, and IO default level observation point; The pin multiplexing module switches the test observation pins on the chip under test to the observation points inside the chip under test corresponding to the control signal according to the control signal, so as to realize the chip return hardware status test when the chip under test is not running software. The chip under test also includes a CPU; When the CPU is able to run the software normally, the sequence detector has a higher control priority for the pin multiplexing module than the priority configured by the CPU through software. The chip under test also includes a non-volatile memory unit, which is used to disable the sequence detection function; The pin multiplexing module includes a multiplexer and a control circuit; the control circuit is connected to the multiplexer. The multiple inputs of the multiplexer are connected to different observation points, and the output of the multiplexer is connected to the test observation pin. The control circuit controls the multiplexer to select the corresponding observation point according to the control signal.

2. The chip testing system based on pin multiplexing according to claim 1, characterized in that, The non-volatile storage unit is either OTP or eFuse.

3. A chip testing method based on pin reuse, characterized in that, The chip testing system based on pin multiplexing as described in any one of claims 1-2 is used, and the method includes: Using an external sequence transmitting device, a test sequence signal is sent to the chip under test through the sequence receiving pin on the chip under test; The sequence detector in the chip under test receives and identifies the test sequence signal, and outputs a corresponding control signal to the pin multiplexing module in the chip under test according to the identification result; The pin multiplexing module switches the test observation pins on the chip under test to different observation points according to the control signal, so as to realize the chip return hardware status test when the chip under test is not running software. The method further includes: After the test is completed, the sequence detection function is turned off by programming the non-volatile memory cells in the chip under test.

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