Calibration methods for internal chip calibration values, computer devices, and readable storage media

Abstract

This invention provides a calibration method, computer device, and readable storage medium for internal calibration values ​​of a chip. The method includes a test board sending a sampling trigger signal to the chip via a clock line and a data line. The chip receives the sampling trigger signal. The chip's analog-to-digital converter performs a single voltage sampling on the chip's analog module and serially outputs the sampled voltage data to the test board via the data line. This sampling step is repeated until the test board obtains a predetermined number of voltage data points. The test board calculates a calibration value based on the predetermined number of voltage data points and serially outputs the calibration value to the chip via the data line. This invention employs a calibration process where the test board triggers sampling, the chip immediately outputs data after a single voltage sampling, the test board collects a predetermined number of sampled data points to calculate the calibration value, and the calibration value is written back to the chip. This allows for high-precision calibration even on resource-constrained chips.

Description

Technical Field

[0001] This invention relates to the field of chip calibration technology, and in particular to a calibration method, computer device, and readable storage medium for internal chip calibration values. Background Technology

[0002] After the chip is packaged, it usually needs to undergo final testing and FT calibration of its internal analog modules, such as the bandgap reference voltage source (VBG) and negative temperature coefficient thermistor (NTC) module, to ensure that the actual output voltage or temperature detection value of each chip reaches the preset accuracy. Due to the influence of process fluctuations, packaging stress and temperature characteristic dispersion, the actual value of VBG of different chips may deviate significantly from the design value, and the voltage-temperature curve of NTC will also drift. If not calibrated, it will directly affect the application performance of the chip.

[0003] One of the commonly used calibration methods is to directly output the voltage of VBG or NTC through the chip pins, and have it acquired by the ADC of an external test board such as an STM32-based test system. Then, the calibration data is calculated based on the deviation between the acquired value and the target value and written back to the chip.

[0004] However, the above method has certain drawbacks. First, VBG and NTC are usually high-impedance, weak-drive signal outputs. Directly leading them out makes them susceptible to being pulled off-center by external loads, affecting measurement accuracy.

[0005] Secondly, there is a millivolt-level voltage difference between the test board and the chip's GND. For high-precision calibration, the error of the ground wire cannot be ignored.

[0006] Furthermore, the above method completely fails to consider the offset and gain errors of the chip's internal ADC during actual operation, resulting in calibration results that are out of sync with actual usage scenarios.

[0007] To address the aforementioned issues, existing technologies have begun to use the chip's internal ADC to acquire VBG and NTC data, and then send the acquired data to the test board via a communication interface. The test board calculates the calibration value and writes it back to the chip. This closed-loop calibration method ensures that the calibration path is consistent with the actual usage path, includes the error of the internal ADC, does not require strong driving capability, and also eliminates the influence of ground voltage difference.

[0008] However, for one-time programmable OTP chips, especially those with a RISC architecture and extremely limited resources, the above method presents new problems. With sufficient SRAM, the program can run within the chip, allowing the ADC to sample, buffer, and filter multiple times before sending the final result to the test board.

[0009] However, for some chips with only a small SRAM capacity, such as only 128 bytes of SRAM, there is no space to implement multiple sampling buffers and filtering algorithms. In addition, the number of I / O pins of this type of chip is also limited, often with only 2 usable communication pins. Therefore, there are also significant limitations in state switching and data transmission. Summary of the Invention

[0010] The primary objective of this invention is to provide a calibration method for internal calibration values ​​of a chip.

[0011] A second object of the present invention is to provide a computer device for performing the above-described calibration method.

[0012] A third objective of the present invention is to provide a readable storage medium storing the above-described calibration method.

[0013] To achieve the first objective of this invention, a calibration method for internal calibration values ​​of a chip is provided, applied to a chip and a test board. The chip is a one-time programmable chip with an SRAM capacity of less than or equal to 128 bytes. The chip has only two I / O pins, which are connected to the test board via a clock line and a data line, respectively. The calibration method includes: a triggering step, in which the test board sends a sampling trigger signal to the chip via the clock line and the data line; a sampling step, in which the chip receives the sampling trigger signal, the chip's analog-to-digital converter performs a single voltage sampling on the chip's analog module, and serially outputs the sampled voltage data to the test board via the data line; repeating the above sampling step until the test board obtains a predetermined number of voltage data; and a writing step, in which the test board calculates a calibration value based on the predetermined number of voltage data, and serially outputs the calibration value to the chip via the data line.

[0014] As can be seen from the above scheme, the chip used in this case is a one-time programmable chip with an SRAM capacity of no more than 128 bytes and only two I / O pins (clock line CLK and data line DAT). Since the chip does not need to cache multiple sampled data or perform calculations such as filtering and averaging, it only needs to store the current single sample result. This allows high-precision calibration to be completed even under the limited conditions of 128 bytes of SRAM. Moreover, the functions of sampling trigger, conversion wait, serial data output, and calibration value writing can be realized simultaneously using only two I / O pins (CLK and DAT). No additional chip select signal (CS) or dedicated control line is required, which allows a calibration communication link to be established on a chip with scarce I / O. This case adopts a calibration process in which the test board triggers sampling, the chip outputs data immediately after a single voltage sampling, the test board collects a predetermined number of sampled data and calculates the calibration value, and the calibration value is written back to the chip. This allows the case to complete accurate calibration on a chip with limited resources, breaking through the dependence on large SRAM and multiple I / O interfaces in the existing technology.

[0015] A further approach is to include an idle step between the two sampling steps in the calibration method, during which the test board and chip are in an idle state for a preset idle time.

[0016] As can be seen from the above, by setting an idle step and a preset idle time as a delay between the two sampling steps, the voltage fluctuation instability caused by the previous CLK / DAT communication can be avoided. The analog-to-digital converter (ADC) can be delayed to stabilize before sampling, making the sampling state more stable.

[0017] A further proposed solution is to set both the clock and data lines to high levels when the system is idle.

[0018] As can be seen above, defining both the clock and data lines as high level in the idle state simplifies the detection logic of the bus idle state and also facilitates the subsequent transition of the trigger state.

[0019] A further approach is to have the clock line and data line both at a high level when the analog-to-digital converter performs a single voltage sampling, and the test board and chip are in a data acquisition waiting state.

[0020] As can be seen from the above, during the single voltage sampling of the analog-to-digital converter (ADC), keeping the clock and data lines at high levels keeps the test board and chip in a data acquisition waiting state, providing sufficient acquisition time for the ADC.

[0021] A further approach involves, after a single voltage sampling by the analog-to-digital converter and before the voltage data output, the sampling step further includes: the chip setting the data line to a low level, and the test board receiving the voltage data sent by the chip.

[0022] As can be seen above, after ADC sampling and before data output, the chip actively sets the data line to a low level as a handshake signal indicating that the conversion is complete and ready for output. This allows the test board to accurately determine the start time of data output and prevents data misalignment.

[0023] A further approach is to include an idle step in the calibration method before the triggering step. During the idle step, the test board and chip are in an idle state, and the clock line and data line are both at a high level.

[0024] As can be seen from the above, an idle step is set before each trigger step to ensure that each sampling trigger starts from the same known state, thereby improving the consistency of sampling.

[0025] A further approach is to include a bandgap reference voltage source and / or a negative temperature coefficient thermistor module in the analog module.

[0026] As can be seen from the above, the calibration targets are bandgap reference voltage sources and / or negative temperature coefficient thermistor modules, which enables the method in this case to be directly applied to the most common and most calibrated analog units in the chip.

[0027] A further approach is to first remove the maximum and minimum values ​​when the test board calculates a predetermined number of voltage data points, then filter and average the remaining voltage data to obtain a calibration value.

[0028] As can be seen from the above, the test board first removes the maximum and minimum values ​​from a predetermined number of voltage data, and then filters and averages them, which effectively suppresses random noise and occasional interference, significantly improves the calculation accuracy of the calibration value, and makes up for the defect that the chip cannot perform multiple sampling and filtering.

[0029] To achieve the second objective of the present invention, the present invention provides a computer device including a processor, which executes a computer program stored in a memory to implement the steps of the calibration method as described above.

[0030] To achieve the third objective of this invention, this invention provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the calibration method as described above.

[0031] As can be seen from the above scheme, the above calibration method is implemented by the processor executing the program in the memory, or by the readable storage medium storing the above program, so that this invention can be configured into an automated FT test equipment to improve test efficiency and repeatability. Attached Figure Description

[0032] Figure 1 This is a system block diagram of an embodiment of the calibration method for the internal calibration values ​​of the chip according to the present invention.

[0033] Figure 2 This is a flowchart of an embodiment of the calibration method for the internal calibration values ​​of the chip according to the present invention.

[0034] Figure 3 This is a communication timing diagram of an embodiment of the calibration method for the internal calibration values ​​of the chip of the present invention.

[0035] The present invention will be further described below with reference to the accompanying drawings and embodiments. Detailed Implementation

[0036] Example of a calibration method for internal chip calibration values: Reference Figure 1 , Figure 1This is a system block diagram showing the connection between the chip and the test board. It includes the FT test board and the chip to be internally calibrated. The chip contains SRAM, an analog-to-digital converter (ADC acquisition module), a bandgap reference voltage source VBG, and a negative temperature coefficient thermistor NTC. In addition to the power supply terminal VDD and the ground terminal GND, the chip only has two I / O pins. The chip is connected to the test board through the two I / O pins, which are the clock line CLK and the data line DAT. The chip is a one-time programmable chip, and the SRAM capacity of the chip is less than or equal to 128 bytes.

[0037] Reference Figure 2 and Figure 3 The calibration method for the internal calibration values ​​of the chip in this case is applied to both the chip and the test board. The calibration method includes the following steps.

[0038] The initialization process begins with step S11, where the test board downloads the VBG / NTC chip calibration acquisition driver into the chip's SRAM. Step S12 is then executed, where the chip receives the program and stores it in the SRAM. Next, the test board executes step S13, where the chip sets DAT to pull-up (high level) and CLK to high level. Finally, the chip executes step S14, where the SRAM starts running the driver and sets the DAT port on the chip as an input. During this process, the test board will also handle other tasks.

[0039] Then, the triggering step is executed. When the test board is ready to receive data from the chip, the test board sets CLK and DAT to pull-down (low level). Then, the test board sends a sampling trigger signal to the chip through the clock line and data line. Then, through the synchronization state, the chip receives the sampling trigger signal. Then, step S22 is executed. The chip sets the DAT level to high, indicating that the chip is ready. The test board learns of this state through the synchronization state.

[0040] Following the sampling step, after the chip receives the sampling trigger signal, step S24 is executed. The chip's analog-to-digital converter performs a single voltage sampling on the chip's analog module. The analog module includes a bandgap reference voltage source and / or a negative temperature coefficient thermistor module. Sampling of the bandgap reference voltage source and the negative temperature coefficient thermistor module needs to be done separately. For example, the bandgap reference voltage source can be sampled first. After the entire calibration method is completed, the above calibration method is re-executed, and then the temperature coefficient thermistor module is sampled again. When the analog-to-digital converter performs a single voltage sampling, the clock line is high, the data line is high, the test board and chip are in a data acquisition waiting state, and there is a delay for a period of time until the chip's ADC completes the acquisition.

[0041] The chip then sets the data line to low level, and the test board receives the voltage data sent by the chip. Subsequently, steps S25 and S26 are executed. The test board provides the clock signal, and DAT is driven by the chip. Each bit of data changes on the edge of CLK. Then, the chip serially outputs the sampled voltage data to the test board through the data line. Then, step S27 is executed to perform an idle step. The test board sets both the clock line and the data line to high level, and the test board and the chip are in an idle state. This idle state is maintained for a preset idle time, which allows the analog-to-digital converter to delay for a while and then collect data after it stabilizes, making the acquisition state more stable.

[0042] Subsequently, both the test board and the chip determine whether the transmitted or received voltage data has reached the predetermined quantity. If not, they return to step S21 and its synchronization state, and repeat the above sampling steps until the test board obtains the predetermined quantity of voltage data.

[0043] Then, the writing step is executed. First, step S28 is executed. The test board calculates the calibration value based on a predetermined number of voltage data. The maximum and minimum values ​​are removed first. Then, the remaining voltage data is filtered and averaged, and the calibration value is calculated. Then, the test board serially outputs the calibration value to the chip through the data line and stores it in the chip's calibration register.

[0044] Computer device embodiment: The computer device includes a processor that executes a computer program stored in memory to implement the steps of the calibration method described above.

[0045] Examples of computer-readable storage media: A computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the calibration method described above.

[0046] Of course, the above embodiments are merely preferred implementations of the present invention. Beyond these embodiments, the definitions of high and low voltage levels for clock and data lines, edge triggering methods, data line driving directions, and idle voltage levels can all be adjusted equivalently according to actual application scenarios and the internal circuit structure of the chip. Furthermore, the number of samplings of the analog module by the analog-to-digital converter and the filtering algorithm of the test board can also be adjusted according to actual application scenarios.

[0047] As can be seen from the above, this case adopts a calibration process of test board triggering sampling, chip outputting data immediately after single voltage sampling, test board collecting a predetermined number of sampling data to calculate calibration value, and writing calibration value back to chip, which enables this case to complete high-precision calibration on chip with limited resources.

Claims

1. A calibration method for the internal calibration values ​​of the chip, applied to the chip and the test board; Its features are: The chip is a one-time programmable chip with an SRAM capacity of less than or equal to 128 bytes. The chip has only two I / O pins, which are connected to the test board. The two I / O pins are the clock line and the data line, respectively. The calibration method includes: In the triggering step, the test board sends a sampling trigger signal to the chip through the clock line and the data line; In the sampling step, the chip receives the sampling trigger signal, the analog-to-digital converter of the chip performs a single voltage sampling on the analog module of the chip, and outputs the voltage data obtained in the current sampling to the test board serially through the data line. The analog module includes a bandgap reference voltage source and / or a negative temperature coefficient thermistor module. Repeat the sampling steps described above until the test board obtains a predetermined number of voltage data. In the writing step, the test board calculates a calibration value based on the predetermined number of voltage data, and the test board serially outputs the calibration value to the chip through the data line.

2. The calibration method according to claim 1, characterized in that: Between the two sampling steps, the calibration method further includes an idle step, during which the test board and the chip are in an idle state for a preset idle time.

3. The calibration method according to claim 2, characterized in that: When in the idle state, the clock line is at a high level and the data line is at a high level.

4. The calibration method according to claim 1, characterized in that: When the analog-to-digital converter performs a single voltage sampling, the clock line is at a high level, the data line is at a high level, and the test board and the chip are in a data acquisition waiting state.

5. The calibration method according to claim 4, characterized in that: After the analog-to-digital converter performs a single voltage sampling and before the voltage data is output, the sampling step further includes: the chip setting the data line to a low level, and the test board receiving the voltage data sent by the chip.

6. The calibration method according to claim 1, characterized in that: Prior to the triggering step, the calibration method further includes an idle step. During the idle step, the test board and the chip are in an idle state. In the idle state, the clock line is at a high level and the data line is at a high level.

7. The calibration method according to any one of claims 1 to 6, characterized in that: When the test board calculates the predetermined number of voltage data, it first removes the maximum and minimum values, then performs filtering and averaging on the remaining voltage data, and obtains the calibration value.

8. A computer device, characterized in that, The computer device includes a processor that executes a computer program stored in a memory to implement the steps of the calibration method as described in any one of claims 1 to 7.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, it implements the steps of the calibration method as described in any one of claims 1 to 7.

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