Auxiliary detection device and performance detection method of three-dimensional space circuit

CN122330660BActive Publication Date: 2026-08-11SOUTHWEST CHINA RES INST OF ELECTRONICS EQUIP
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2026-06-04
Publication Date
2026-08-11

AI Technical Summary

Technical Problem

但该方案存在无法克服的固有缺陷:立体空间电路中立碑结构的交叉遮挡,会在磁控溅射、电镀、激光活化等制备过程中,形成显著的电场畸变、粒子沉积阴影、激光角度遮挡等效应,直接影响立碑表面尤其是遮挡面的成膜质量与图形精度,而平面随炉件完全无法模拟上述立体空间的特殊制备工况,导致检测得到的工艺参数与产品实际工况参数存在严重偏差,无法真实反映立体空间电路立碑结构的制备质量,极易造成量产批次的工艺失控与产品不良

Benefits of technology

本发明有效的实现了通过辅助件将设置将一体化立体空间电路结构中存在遮挡的立碑结构拆分为独立的立碑结构,且每组立碑结构中的碑体不出现遮挡,随后在辅助件通过底座组件进行组装,在辅助件表面进行电路制备;制备完成后对每组立碑结构的电路性能进行检测,实现在不切割破坏存在遮挡的立碑结构的情况下实现检测;

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Abstract

This invention relates to the field of three-dimensional spatial circuit manufacturing technology, specifically disclosing an auxiliary testing device and performance testing method for three-dimensional spatial circuits. The device includes auxiliary components designed and manufactured based on the substrate prefabrication structure in an integrated three-dimensional spatial circuit product, and a base assembly for fixing and supporting the auxiliary components. The auxiliary components include a tombstone assembly, and two blocks located on either side of the tombstone assembly and connected to it. The tombstone assembly includes multiple sets of tombstone structures connected in sequence; each set of tombstone structures is equipped with a tombstone body. This invention enables the testing of the circuit performance on the surface of the three-dimensional spatial circuit without cutting or damaging the tombstone bodies that may obstruct the circuit, obtaining the required circuit fabrication process parameters, reducing testing costs, and improving the accuracy of circuit fabrication.
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Description

Technical Field

[0001] This invention relates to the field of three-dimensional spatial circuit technology, and more specifically, to an auxiliary testing device and performance testing method for three-dimensional spatial circuits. Background Technology

[0002] As the performance requirements of electronic products increase, the product's radiation structure and power supply structure are developing towards integration. The circuit is no longer a single planar circuit, but a three-dimensional spatial circuit with multiple directions.

[0003] The core structural feature of 3D spatial circuits lies in the inclusion of multiple vertically arranged tombstoning structures. The tombstoning surfaces support critical feed lines and matching circuits. These tombstoning structures are arranged in a crisscrossing pattern in three-dimensional space, inevitably causing mutual occlusion. During circuit fabrication, the occlusion effect of the tombstoning structures directly leads to problems such as uneven metallization thickness, thinning at corners, and insufficient interfacial adhesion. It also causes defects such as laser activation pattern misalignment and out-of-tolerance circuit precision, directly affecting the circuit's RF performance and long-term reliability. Therefore, the plating thickness, interfacial adhesion, pattern size, and positional accuracy of the surface circuitry on the tombstoning structure are core quality control indicators for 3D spatial circuit fabrication, and precise testing is essential for process verification and parameter optimization.

[0004] Currently, conventional testing techniques for circuit fabrication quality all have clear limitations: For plating thickness, the mainstream methods used are optical microscopy, white light interferometry, and other optical testing methods, or physical testing methods such as eddy current thickness measurement and X-ray fluorescence thickness measurement. These methods can only accurately detect exposed circuit surfaces without visual obstruction and cannot cover the obstructed surfaces of tombstone structures. For plating adhesion, industry-standard testing methods such as cross-cut adhesion, tape peeling, and tensile peeling all require direct contact with the circuit surface and cannot effectively detect the adhesion of plating in obstructed areas. For the size and positional accuracy of circuit patterns, conventional methods use two-dimensional optical measurement and three-coordinate contact measurement, which are limited by visual obstruction and accessibility and cannot complete the accuracy testing of circuits in tombstone-obstructed areas.

[0005] To address the challenge of detecting obstructed tombstoning structures, two main approaches have emerged in the industry: The first is the indirect verification approach using planar in-furnace components. This involves preparing planar in-furnace components of the same material as the product according to relevant standards. These components are then manufactured alongside the 3D spatial circuit product under the same batch and operating conditions. By testing the plating thickness, adhesion, and circuit accuracy of the planar components, the fabrication quality of the 3D spatial circuit can be inferred. However, this approach has inherent drawbacks: the cross-obstruction of tombstoning structures in 3D spatial circuits creates significant effects such as electric field distortion, particle deposition shadows, and laser angle obstruction during magnetron sputtering, electroplating, and laser activation processes. These effects directly impact the film quality and pattern accuracy on the tombstoning surface, especially the obstructed surface. Planar in-furnace components cannot simulate the unique fabrication conditions of 3D spatial circuits, leading to severe discrepancies between the measured process parameters and the actual product parameters. This results in a failure to accurately reflect the fabrication quality of the tombstoning structure in 3D spatial circuits, potentially causing process control issues and product defects in mass production batches.

[0006] The second type is the destructive sectioning inspection scheme for finished products. This involves mechanically cutting or precisely sectioning the completed three-dimensional spatial circuit product to destroy and remove the shielding structure, fully exposing the tombstone's shielding surface, and then using conventional testing methods to complete the manufacturing quality inspection. The core drawbacks of this scheme are significant: First, the cutting process causes mechanical stress damage to the circuit plating, resulting in problems such as plating edge chipping, interface peeling, and circuit breakage. This leads to severe distortion of parameters such as adhesion and thickness obtained during testing, failing to reflect the true manufacturing state of the circuit. Second, the inspection process directly causes permanent damage to the finished sample, making it unusable and significantly increasing the cost of process trial and error during the R&D phase. Furthermore, it cannot be applied to full-scale testing in the mass production phase, only allowing for limited process monitoring through small-batch sampling, resulting in a high risk of missed detections. Third, the cutting process can only achieve single-point cross-sectional inspection, failing to complete the performance distribution testing of the entire tombstone shielding surface, making it difficult to obtain complete process parameter distribution patterns and support refined process optimization for complex three-dimensional structures.

[0007] Existing technologies cannot achieve accurate, low-cost, and non-destructive testing of the entire surface preparation quality of the obscured monument without disrupting the product's integrated structure, altering its original design, or affecting its performance. They also cannot provide highly compatible real process parameters for mass production process optimization, which severely restricts the large-scale application and performance improvement of integrated three-dimensional spatial circuits. Summary of the Invention

[0008] The technical problem to be solved by the present invention is to provide an auxiliary testing device and performance testing method for three-dimensional spatial circuits, which can test the circuit performance on the surface of the three-dimensional spatial circuit without cutting or destroying the obstructing monuments, obtain the required circuit fabrication process parameters, and reduce the testing cost; The solution adopted by this invention to solve the technical problem is: An auxiliary testing device for a three-dimensional spatial circuit includes an auxiliary component designed and manufactured based on the substrate preform in the structure of an integrated three-dimensional spatial circuit product, and a base assembly for fixing and supporting the auxiliary component. The auxiliary components include a monument erection assembly, a first stop block and a second stop block located on both sides of the monument erection assembly and connected to the monument erection assembly; The monument erection assembly includes multiple sets of monument erection structures connected in sequence; each set of monument erection structures is equipped with a monument body.

[0009] In some possible implementations, the base assembly includes a U-shaped support base and a baffle connected to the support base and closing the opening of the U-shaped structure to form a mounting cavity; the auxiliary component is installed inside the mounting cavity.

[0010] In some possible implementations, positioning marks are provided on the first and second stops.

[0011] In some possible implementations, the connection between two adjacent sets of monument structures, and between the monument structure and the adjacent stop block one or stop block two, is achieved by the cooperation of pins and pin holes.

[0012] In some possible implementations, each set of the monument structures is provided with a concave curved surface, and the monument body is disposed within the concave curved surface.

[0013] In some possible implementations, each group of the monument structures is arranged in parallel, and each group of the monument structures has the same thickness.

[0014] In some possible implementations, the support base includes two sets of parallel support plates and a connecting plate disposed between the two sets of support plates and connected to the two sets of support plates; the baffle is arranged parallel to the connecting plate and is connected to the two sets of support plates respectively.

[0015] In some possible implementations, the support plate is L-shaped and includes a base plate and a horizontal plate mounted on the base plate; the two sets of base plates cooperate to form a support surface for supporting the bottom of the auxiliary component.

[0016] A performance testing method for a three-dimensional spatial circuit, based on the aforementioned auxiliary testing device for a three-dimensional spatial circuit; specifically, it refers to: assembling auxiliary components and a base assembly into an integral structure; fabricating a circuit on this integral structure; disassembling the integral structure and testing the circuit on the auxiliary components to obtain process parameters for circuit fabrication that conform to the actual integrated three-dimensional spatial circuit structure.

[0017] In some possible implementations, the specific steps include: Step S1: Assemble the auxiliary parts and base assembly; Step S2: Sputtering to form a sputtered layer; Step S3: Disassemble the auxiliary components and base assembly, and test and determine the performance indicators of the sputtered layer in each group of tombstone structures; If the performance indicators meet the requirements, record the sputtering process parameters and use these sputtering process parameters as the sputtering process parameters for the integrated three-dimensional spatial circuit product structure. If the performance indicators do not meet the requirements, clean the sputtered layer and repeat step S2 until the performance indicators meet the requirements. Step S4: After the performance indicators of the sputtered layer of the auxiliary component meet the requirements, assemble the auxiliary component with the base assembly; perform laser etching of circuit patterns on the surface of the tombstone structure; Step S5: Disassemble the auxiliary parts from the base assembly, and inspect and determine the size and positional accuracy of the surface circuit pattern of the monument structure; If the size and positional accuracy of the circuit pattern meet the requirements, record the laser etching process parameters and use these laser etching process parameters as the laser etching process parameters for the integrated three-dimensional spatial circuit product structure. If the size and positional accuracy of the circuit pattern do not meet the requirements, repeat step S4 until the size and positional accuracy of the circuit pattern meet the requirements.

[0018] Compared with the prior art, the beneficial effects of the present invention are as follows: This invention effectively separates the obstructed monumental structure in the integrated three-dimensional spatial circuit structure into independent monumental structures using auxiliary components, ensuring that the monuments in each group of monumental structures are not obstructed. Subsequently, the auxiliary components are assembled using a base assembly, and circuitry is fabricated on the surface of the auxiliary components. After fabrication, the circuit performance of each group of monumental structures is tested, achieving testing without cutting or damaging the obstructed monumental structures. This invention can completely simulate the manufacturing process of circuits in an integrated three-dimensional spatial circuit structure, ensuring that the performance obtained from testing can fully reflect the performance of the actual integrated three-dimensional spatial circuit structure. If the circuit performance is found to be unsatisfactory during the testing process using this invention, the circuit can be remade, effectively enabling the reuse of the auxiliary testing device and reducing testing costs. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of the structure of the present invention; Figure 2 This is a schematic diagram of the auxiliary component in this invention; Figure 3 This is a schematic diagram of the base assembly in this invention; Figure 4 This is a schematic diagram of the supporting plate in this invention; Figure 5 This is a schematic diagram of the structure of the second stop in this invention; Figure 6 This is a schematic diagram of the tombstone structure in this invention; in: 1. Auxiliary components; 11. Tombstone erection components; 111. Structure of the monument; 1111. Monument body; 11111. Metalized through holes; 1112. Concave surface; 1113. Pin; 12. Stop block one; 13. Stop block two; 131. Positioning mark; 132. Cavity; 2. Base assembly; 21. Support base; 211. Support plate; 2111. Base plate; 2112. Horizontal plate; 212. Connecting plate; 22. Baffle; 3. Installation cavity. Detailed Implementation

[0020] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. The terms "first," "second," and similar terms used in this application do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, "a" or "one," etc., do not indicate a quantity limitation, but rather indicate the existence of at least one. In the implementation of this application, "and / or" describes the association relationship of related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. In the description of the embodiments of this application, unless otherwise stated, "multiple" means two or more. For example, multiple positioning posts refer to two or more positioning posts. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0021] The present invention will now be described in detail.

[0022] In this invention, the substrate prefabrication in the integrated three-dimensional spatial circuit product structure is a prefabricated carrier substrate with a preset three-dimensional topology structure before sputtering, etching and other processes are completed; like Figures 1-6 As shown, the present invention provides an auxiliary testing device for a three-dimensional spatial circuit, including an auxiliary component 1 designed and manufactured according to the base preform in the structure of an integrated three-dimensional spatial circuit product, and a base assembly 2 for fixing and supporting the auxiliary component 1. like Figure 2 As shown, the auxiliary component 1 includes a monument erection assembly 11, a first stop block 12 and a second stop block 13 located on both sides of the monument erection assembly 11 and detachably connected to the monument erection assembly 11; The monument component 11 includes multiple sets of monument structures 111 that are detachably connected in sequence; each set of monument structures 111 is provided with a monument body 1111; the monument body 1111 on each set of monument structures 111 is not obstructed; the structure formed by the connection of multiple sets of monument bodies 1111 and multiple sets of monument structures 111 is the same as the monument structure in the integrated three-dimensional spatial circuit product structure. The present invention firstly uses an auxiliary component 1 designed and manufactured according to the substrate prefabrication in the integrated three-dimensional spatial circuit product structure, and then disassembles the auxiliary component 1 into multiple independent monument structures 111, block one 12 and block two 13, so that the monument body 1111 on each independent monument structure 111 is not obstructed. Multiple independent tombstone structures 111, block one 12 and block two 13 are formed into auxiliary components 1 that are completely consistent with the structure and size of the precast base body, and are supported and fixed by base assembly 2. Then, circuitry is fabricated on the surface of auxiliary component 1, which has a structure and dimensions that are completely identical to the substrate preform. Finally, the auxiliary component 1 is removed from the base assembly 2 and disassembled. The circuit on the surface of the disassembled tombstone structure 111 is then subjected to performance testing. After testing, the required process parameters for circuit fabrication in the integrated three-dimensional spatial circuit product structure are obtained. These process parameters are then used for circuit fabrication in the actual integrated three-dimensional spatial circuit product structure. This invention allows for the testing of the surface circuit performance of the tombstone 1111 without cutting or damaging the obstructing tombstone 1111. If the test data does not meet the requirements, the circuit fabrication can be repeated until the required process parameters are obtained, greatly reducing the cost of three-dimensional spatial circuit performance testing. Since the monument 1111 in this invention is consistent with the monument of the actual integrated three-dimensional spatial circuit product, this invention can completely simulate the manufacturing process of the three-dimensional spatial circuit and ensure that the performance obtained through testing can fully reflect the performance of the actual product.

[0023] In some possible implementations, the base assembly 2 includes a U-shaped support base 21 and a baffle 22 connected to the support base 21 and closing the opening of the U-shaped structure to form a mounting cavity 3; the auxiliary component 1 is installed in the mounting cavity 3. To ensure that the structure formed after assembly of auxiliary component 1 fully conforms to the prefabricated base body in the integrated three-dimensional spatial circuit product structure, auxiliary component 1 is installed in the mounting cavity 3 during assembly. The baffle 22 contacts and abuts against the first baffle 12, while another set of second baffles 13 contacts and abuts against the bottom of the U-shaped structure in the support base 21. This prevents auxiliary component 1 from moving within the mounting cavity 3, effectively supporting and fixing auxiliary component 1 and ensuring that it does not deform during subsequent circuit fabrication.

[0024] In some possible implementations, such as Figure 2 As shown, positioning marks 131 are provided on the first block 12 and the second block 13; the setting of positioning marks 131 will facilitate the later fabrication of the circuit.

[0025] In some possible implementations, in order to effectively connect the components in the auxiliary component 1, the connection between two adjacent sets of monument structures 111 and between the monument structure 111 and the adjacent stop block 12 or stop block 2 13 is achieved by the cooperation of pins 1113 and pin holes. That is, if one of the two adjacent sets of monument structures 111 is equipped with a pin 1113, then a pin hole that mates with the pin hole is provided on the other set of monument structures 111; the connection between the monument structure 111 and the adjacent stop (stop 12 or stop 2 13) is also the same, which will not be described in detail here.

[0026] In some possible implementations, such as Figure 6 As shown, each group of the monument structure 111 is provided with a concave curved surface 1112, and the monument body 1111 is disposed in the concave curved surface 1112; Furthermore, each group of monuments 1111 is provided with a metallized through hole 11111, which enables the interconnection of the monuments 1111 and ultimately connects the circuit on the monument 1111 with the circuit on the outer surface of the auxiliary component 1. Multiple sets of concave curved surfaces 1112 on the monument structure 111 form inner grooves; such as Figure 5 As shown, the first stop 12 and the second stop 13 are respectively provided with concave cavities 132 that communicate with the inner groove. The inner groove and the two sets of concave cavities 132 are interconnected to form an inner concave cavity.

[0027] In some possible implementations, each group of monument structures 111 is arranged in parallel without obstruction, and each group of monument structures 111 has the same thickness. This arrangement allows the monument assembly 11 to be divided into multiple groups of structures with equal thickness, which facilitates arraying.

[0028] Of course, there are also cases where the monument structures 111 are not arranged in parallel, that is, when adjacent monuments 1111 are perpendicular to each other or form a certain angle, the thickness of each group of monument structures 111 may not be equal.

[0029] In some possible implementations, such as Figure 3 , Figure 4 As shown, when the outer contour of the auxiliary component 1 is a square structure, the support base 21 includes two sets of parallel support plates 211 and a connecting plate 212 disposed between the two sets of support plates 211 and connected to the two sets of support plates 211; the baffle 22 is parallel to the connecting plate 212 and is respectively connected to the two sets of support plates 211; the support plate 211 is L-shaped and includes a base plate 2111 and a horizontal plate 2112 mounted on the base plate 2111; the two sets of base plates 2111 cooperate with each other to form a support surface for supporting the bottom of the auxiliary component 1; With the above configuration, the bottom of the auxiliary component 1 is supported by the base plate 2111, and the baffle 22 is detachably connected to the horizontal plate 2112 to form a whole, thereby effectively supporting and fixing the auxiliary component 1 in the mounting cavity 3. Preferably, the horizontal plate 2112 and the baffle 22 are connected by bolts, and the horizontal plate 2112 is provided with a number of through holes for the bolts to pass through; the through holes are arranged at equal intervals along the length of the horizontal plate 2112; when the thickness of the monument structure 111 is equal, the distance between adjacent through holes is equal to the thickness of the monument structure 111.

[0030] In the design of auxiliary component 1, based on the characteristics of the substrate prefabricated body in the integrated three-dimensional spatial circuit structure, auxiliary component 1 is divided into multiple sets of monumental structures 111 and auxiliary structures. The auxiliary structures include block one 12 and block two 13 and do not contain the monument body 1111. At the same time, it is necessary to ensure that each monument body 1111 is completely in an independent monumental structure 111.

[0031] When processing auxiliary part 1, auxiliary part 1 and the base preform are made of the same material; that is, non-metallic materials can be used, such as polyetheretherketone, polyimide, cyanate matrix materials, etc., and can be made by means of, but not limited to, machining, 3D printing, prepreg curing, etc.

[0032] The supporting base 21 and baffle 22 in the base assembly 2 are made of steel or other materials that meet the requirements for strength, rigidity, temperature resistance, etc., and can be manufactured by means of, but not limited to, machining, 3D printing, etc.

[0033] on the other hand, This invention provides a performance testing method for three-dimensional spatial circuits, based on the aforementioned auxiliary testing device for three-dimensional spatial circuits; specifically, it involves: assembling an auxiliary component 1 and a base assembly 2 into an integral structure; fabricating a circuit on this integral structure; disassembling the integral structure and testing the circuit on the auxiliary component 1 to obtain the required circuit fabrication process parameters; Specifically, the following steps are included: Step S1: The auxiliary component 1 is assembled with the base assembly 2. The base assembly 2 supports and fixes the auxiliary component 1 to prevent deformation of the auxiliary component 1 during the later circuit fabrication. Furthermore, during the first assembly, the dimensions of each component can be adjusted and modified appropriately. The baffle 22 is used to assist the component 1 to ensure good contact between the components inside the component 1. Finally, the baffle 22 is fixed to the base assembly 2. Step S2: Perform magnetron sputtering on auxiliary component 1 to form a sputtered layer; Step S3: Disassemble the auxiliary component 1 from the base assembly 2, and test and determine the performance indicators of the sputtered layer in each group of tombstone structures 111; The performance indicators of the sputtered layer include thickness, adhesion, and hardness. Specifically, optical methods can be used to detect the thickness of the sputtered layer, while peeling methods can be used to detect the adhesion of the sputtered layer. If the performance indicators meet the requirements, record the sputtering process parameters and use these sputtering process parameters as the sputtering process parameters when fabricating the integrated three-dimensional spatial circuit product structure. If the performance indicators do not meet the requirements, clean the sputtered layer and repeat step S2 until the performance indicators meet the requirements. Step S4: After the performance indicators of the sputtered layer of the auxiliary component 1 meet the requirements, assemble the auxiliary component 1 with the base assembly 2; perform laser etching of circuit patterns on the surface of the tombstone structure 111, and align the laser-etched circuit patterns using the positioning marks 131 on the first stop block 12 and the second stop block 13. Step S5: Separate the auxiliary component 1 from the base assembly 2, and use optical equipment or a coordinate measuring machine to detect and determine the size and positional accuracy of the surface circuit pattern of the monument structure 111; If the size and positional accuracy of the circuit pattern meet the requirements, record the laser etching process parameters and use these laser etching process parameters as the laser etching process parameters for the integrated three-dimensional spatial circuit product structure. If the size and positional accuracy of the circuit pattern do not meet the requirements, repeat step S4 until the size and positional accuracy of the circuit pattern meet the requirements.

[0034] If the size and positional accuracy of the circuit pattern do not meet the requirements after repeating step S4 multiple times, and there is no area on the surface of all tombstone structures 111 that can be used for circuit pattern verification, then remove the sputtering layer on the surface of all tombstone structures 111 and repeat step S1.

[0035] It should be noted that the outer surface of the integrated three-dimensional spatial circuit product is curved, with the same curvature as the concave cavity. The overall curved surface is a thin-walled structure of uniform thickness. Since the outer surface is unobstructed, the testing difficulty is reduced. Therefore, in the design of the auxiliary component, all outer surfaces are designed as planes, only making the tombstone structure 111 in the auxiliary component the same as the tombstone structure in the integrated three-dimensional spatial circuit product, and the concave cavity in the auxiliary component the same as the concave cavity in the integrated three-dimensional spatial circuit product. Thus, the outer contour of the entire auxiliary component is a square structure, which facilitates clamping and fixing.

[0036] This invention is not limited to the specific embodiments described above. The invention extends to any new feature or combination disclosed in this specification, as well as any new method or process step or combination disclosed herein.

Claims

1. An auxiliary detection device for a three-dimensional space circuit, characterized in that This includes auxiliary components designed and manufactured based on the substrate preform in the integrated three-dimensional spatial circuit product structure, as well as base assemblies used to fix and support the auxiliary components; the substrate preform is a pre-fabricated carrier substrate with a preset three-dimensional topology structure, which is manufactured before the sputtering and etching processes are completed; The auxiliary components include a monument erection assembly, a first stop block and a second stop block located on both sides of the monument erection assembly and connected to the monument erection assembly; The monument erection assembly includes multiple sets of monument erection structures connected in sequence; each set of monument erection structures is respectively provided with a monument body; The two adjacent sets of monument structures, as well as the monument structure and the adjacent block one or block two, are detachably connected.

2. An auxiliary detection device for a three-dimensional space circuit according to claim 1, characterized in that The base assembly includes a U-shaped support base and a baffle connected to the support base and closing the opening of the U-shaped structure to form an installation cavity; the auxiliary component is installed inside the installation cavity.

3. The auxiliary detection device for a three-dimensional space circuit according to claim 1, characterized by Positioning marks are provided on the first and second stops.

4. The apparatus of claim 1, wherein, The two adjacent sets of monument structures are connected by the use of pins and pin holes, as well as between the monument structure and the adjacent stop block one or stop block two.

5. The apparatus of claim 1 wherein, Each group of the monument structures has a concave curved surface, and the monument body is set inside the concave curved surface.

6. The apparatus of claim 1 wherein, Each group of the monument structures is arranged in parallel, and the thickness of each group of the monument structures is equal.

7. An auxiliary detection device for a three-dimensional space circuit according to claim 2, characterized in that, The support base includes two sets of parallel support plates and a connecting plate disposed between the two sets of support plates and connected to the two sets of support plates; the baffle is arranged parallel to the connecting plate and is connected to the two sets of support plates respectively.

8. An auxiliary detection device for a three-dimensional space circuit according to claim 7, characterized in that The support plate is L-shaped and includes a base plate and a horizontal plate mounted on the base plate; the two sets of base plates cooperate to form a support surface for supporting the bottom of the auxiliary component.

9. A method of performance detection of a three-dimensional space circuit, characterized by It is implemented based on the auxiliary testing device for a three-dimensional spatial circuit as described in any one of claims 1-8; the performance testing method specifically refers to: assembling the auxiliary components and the base assembly into an integral structure; fabricating the circuit on the integral structure; disassembling the integral structure and testing the circuit on the auxiliary components to obtain the process parameters for circuit fabrication in the integrated three-dimensional spatial circuit structure.

10. The method of claim 9, wherein the method further comprises: Specifically, the following steps are included: Step S1: Assemble the auxiliary parts and base assembly; Step S2: Sputtering to form a sputtered layer; Step S3: Disassemble the auxiliary components and base assembly, and test and determine the performance indicators of the sputtered layer in each group of tombstone structures; If the performance indicators meet the requirements, record the sputtering process parameters and use these sputtering process parameters as the sputtering process parameters for the integrated three-dimensional spatial circuit product structure. If the performance indicators do not meet the requirements, clean the sputtered layer on all tombstone structures and repeat steps S1-S2 until the performance indicators meet the requirements. Step S4: After the performance indicators of the sputtered layer of the auxiliary component meet the requirements, assemble the auxiliary component with the base assembly; perform laser etching of circuit patterns on the surface of the tombstone structure; Step S5: Disassemble the auxiliary parts from the base assembly, and inspect and determine the size and positional accuracy of the surface circuit pattern of the monument structure; If the size and positional accuracy of the circuit pattern meet the requirements, record the laser etching process parameters and use these laser etching process parameters as the laser etching process parameters for the integrated three-dimensional spatial circuit product structure. If the size and position accuracy of the circuit pattern does not meet the requirement, repeat step S4 until the size and position accuracy of the circuit pattern meets the requirement.

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