A high-efficiency controllable adaptive adjustment LDO circuit

Abstract

The application relates to a high-efficiency controllable self-adaptive adjustment LDO circuit. PT , comprising a band-gap reference module, a controlled LDO main circuit module providing a bias current I BG to generate a stable bias voltage V unit ; an adaptive control signal generation module, comprising a first proportional adaptive unit, a comparator COMP and a digital adaptive control logic module; the first proportional adaptive unit dynamically adjusts the size of its output current I ST and adjustable resistance R Z to dynamically output a voltage V BG ; a controlled LDO main circuit module generates a plurality of voltage grades of power supply voltage V FB according to the input control signals A-E and the bias voltage V LDO and feedback voltage V . The application can increase the output voltage of the LDO output voltage, has the advantages of high efficiency, self-adaptive adjustment, low noise and the like.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology, and specifically relates to a highly efficient, controllable, adaptive adjustment LDO circuit. Background Technology

[0002] The rapid development of digital technology in recent years has led to increasingly higher requirements for low-dropout linear regulator (LDO) circuits in multi-power-domain systems. LDO circuits, due to their simple structure, low output noise, and fast response speed, are widely used in system-on-a-chip (SoC), portable devices, RF modules, and other fields requiring high-quality, stable power supplies. As semiconductor process nodes continue to evolve and supply voltages continue to decrease, the dynamic range of load circuits increases and transients become more severe, thus placing even more stringent demands on the performance of LDOs.

[0003] At the same time, the rapid development of high-performance computing and multi-power-domain chips has also put forward new requirements for the dynamic power management of electronic systems. At this time, LDOs need to be able to quickly switch between different preset voltage levels, and the switching process needs to be smooth to avoid system logic errors and data loss. Traditional LDOs cannot meet the requirements.

[0004] Therefore, there is an urgent need for this invention to propose an efficient and controllable adaptive adjustment LDO circuit to solve the above-mentioned technical problems. Summary of the Invention

[0005] The purpose of this invention is to provide a highly efficient and controllable adaptive adjustment LDO circuit. This invention can increase the output voltage range of the LDO and has the advantages of high efficiency, adaptive adjustment, and low noise.

[0006] To solve the above technical problems, the present invention provides a high-efficiency, controllable, adaptive adjustment LDO circuit, comprising: The bandgap reference module receives a bias current I from the controlled LDO main circuit module. PT To generate a stable bias voltage V BG ; The adaptive control signal generation module includes a first proportional adaptive unit, a comparator COMP, and a digital adaptive control logic module; the first proportional adaptive unit dynamically adjusts its output current I based on the control signals A~E fed back from the digital adaptive control logic module. unit and adjustable resistor R ST The magnitude of the voltage, thus dynamically outputting voltage V. Z The comparator COMP is enabled by the enable signal ENP fed back from the digital adaptive control logic module, and responds to the input voltage V. Z and voltage divider V Q The comparison outputs a high or low level control signal V. COMPThe digital adaptive control logic module controls the input clock CLK and control signal V. COMP After logical processing, the control signals A~E are output as digital adaptive signals; The controlled LDO main circuit module, based on the input control signals A~E and the bias voltage V... BG and feedback voltage V FB To generate power supply voltages V at multiple voltage levels. LDO .

[0007] Preferably, the first proportional adaptive unit includes: PMOS transistors MP7~MP13; wherein the source terminals of PMOS transistors MP7~MP11 and PMOS transistor MP13 are connected to power supply AVDD; the gate terminals of PMOS transistors MP7~MP11 are sequentially connected to control signals A~E, and the gate terminal of PMOS transistor MP13 is connected to voltage V. cons The drains of PMOS transistors MP7~MP10 and MP12~MP13 are connected to generate a current I. unit And connect the adjustable resistor R to ground GND. ST With output voltage V Z Furthermore, the drain terminal of PMOS transistor MP11 is connected to the source terminal of PMOS transistor MP12, and the gate terminals of the two are interconnected.

[0008] Preferably, the aspect ratio of PMOS transistors MP7 to MP12 is 8:4:2:1:1:1, respectively.

[0009] Preferably, the comparator COMP includes: PMOS transistors MP1~MP6, NMOS transistors MN1~MN7, and an inverter INV1; the source terminals of PMOS transistors MP1~MP6 are connected to the power supply AVDD; the gate terminal of PMOS transistor MP1 is connected to the drain-gate terminal of PMOS transistor MP2 and the drain terminal of NMOS transistor MN2; the drain terminal of PMOS transistor MP1 is connected to the drain terminal of NMOS transistor MN1 and the gate terminals of NMOS transistors MN5~MN6; the gate terminal of NMOS transistor MN1 is connected to the gate terminal of NMOS transistor MN7; the source terminals of NMOS transistors MN1 and NMOS transistors MN5~MN7 are grounded to GND; and the gate terminal of NMOS transistor MN2 is connected to the voltage V. Z The source terminal of NMOS transistor MN2 is connected to the drain terminal of NMOS transistor MN3 and the source terminal of NMOS transistor MN4; the gate terminal of NMOS transistor MN3 is connected to the enable signal ENP, and the source terminal of NMOS transistor MN3 is grounded to GND; the gate terminal of NMOS transistor MN4 is connected to voltage V. QThe drain of NMOS transistor MN4 is connected to the drain-gate of PMOS transistor MP3 and the gate of PMOS transistor MP4; the drain of PMOS transistor MP4 is connected to the drain of NMOS transistor MN5; the drain of NMOS transistor MN6 is connected to the drain-gate of PMOS transistor MP5 and the gate of PMOS transistor MP6; the drain of PMOS transistor MP6 is connected to the drain of NMOS transistor MN7 and the input of inverter INV1; the output of inverter INV1 outputs a control signal V. COMP The enable terminal of the inverter INV1 is connected to the enable signal ENP.

[0010] Preferably, the digital adaptive control logic module includes: a logic gate module, a multi-level counting trigger module, and buffers BUF1~BUF5; the logic gate module is used to input clock CLK and control signal V. COMP The multi-level counting trigger module is connected to the logic gate module to form a loop feedback structure, and the output terminal of each level of the multi-level counting trigger module is connected to the input terminal of buffer BUF1~BUF5 in sequence. The output terminals of buffer BUF1~BUF5 output control signals A~E in sequence. At the same time, the output terminal of the loop feedback structure outputs the enable signal ENP.

[0011] Preferably, the logic gate module includes: an OR gate OR1, inverters INV2~INV3, and AND gates AND1~AND2; two inputs of the OR gate OR1 are respectively input to the clock CLK and the control signal V. COMP The third input terminal serves as a feedback terminal and is connected to the output terminal of AND gate AND2; the output terminal of AND gate AND2 is also connected to the input terminal of inverter INV3, and the output terminal of inverter INV3 outputs an enable signal ENP; the output terminal of OR gate OR1 is connected to the input terminal of inverter INV2, and the output terminal of inverter INV2 is connected to the first stage clock terminal of the multi-stage counting trigger module; the three input terminals of AND gate AND1 and the two input terminals of AND gate AND2 are sequentially connected to the output terminals of each stage of the multi-stage counting trigger module, and the output terminal of AND gate AND1 is connected to the third input terminal of AND gate AND2.

[0012] Preferably, the multi-level counting trigger module includes: D flip-flops D1 to D5; the reset terminals of the D flip-flops D1 to D5 are connected to an external reset signal CDN; the input terminals and output NOT terminals of each of the D flip-flops D1 to D5 are interconnected; the clock terminal of the D flip-flop D1 is connected to the input terminal of the D flip-flop D2; the clock terminal of the D flip-flop D2 is connected to the input terminal of the D flip-flop D3; the clock terminal of the D flip-flop D3 is connected to the input terminal of the D flip-flop D4; the clock terminal of the D flip-flop D4 is connected to the input terminal of the D flip-flop D5; the clock terminal of the D flip-flop D5 is connected to the output terminal of the inverter INV2; and the output terminals of the D flip-flops D1 to D5 are sequentially connected to the input terminals of the buffers BUF1 to BUF5.

[0013] Preferably, the controlled LDO main circuit module includes: an error amplifier A E PMOS transistor MP14, feedback resistor R FB1 ~R FB2 Second proportional adaptive unit, resistor R, filter resistor R ESR and filter capacitor C; the error amplifier A E The positive input terminal is connected to the bias voltage V. BG The negative input terminal is connected to the feedback voltage V. FB The output terminal is connected to the gate terminal of the PMOS transistor MP14; the source terminal of the PMOS transistor MP14 is connected to the ground GND resistor R and the filter resistor R. ESR One end of the second proportional adaptive unit outputs the power supply voltage V. LDO The control signals A~E are input to the input terminal of the second proportional adaptive unit; the filter resistor R ESR The other end is connected to a filter capacitor C grounded to GND; the drain of the PMOS transistor MP14 is connected to a feedback resistor R connected in series with grounded to GND. FB1 ~R FB2 And the feedback resistor R FB1 ~R FB2 The series connection point generates the feedback voltage V. FB .

[0014] Preferably, the error amplifier A E Includes: PMOS transistors MP15~MP18, NMOS transistors MN8~MN9, and bias current source I. PT The source terminals of PMOS transistors MP15-MP16 are connected to the power supply AVDD, and the drain-gate terminal of PMOS transistor MP15 is connected to the gate terminal of PMOS transistor MP16 and the bias current source I connected to ground GND. PTThe drain of PMOS transistor MP16 is connected to the drain of PMOS transistors MP17-MP18, and the gate of PMOS transistor MP17 is connected as the negative input terminal to the feedback voltage V. FB The source terminal of the PMOS transistor MP17 is connected to the drain-gate terminal of NMOS transistor MN8 and the gate terminal of NMOS transistor MN9. The source terminals of NMOS transistors MN8-MN9 are grounded to GND. The drain terminal of NMOS transistor MN9 is connected to the source terminal of PMOS transistor MP18 and serves as its output terminal. The gate terminal of PMOS transistor MP18 serves as its positive input terminal and is connected to the bias voltage V. BG .

[0015] Preferably, when the loop gain of the controlled LDO main circuit module is sufficiently large, the PMOS transistor MP14 and the feedback resistor R... FB1 ~R FB2 The constructed feedback branch will reduce the bias voltage V. BG and feedback voltage V FB The difference between them, and finally the feedback voltage V FB The bias voltage V is mirrored. BG The feedback voltage V is transmitted through the second proportional adaptive unit and the resistor R. FB For the bias voltage V BG The forced mirror transfer to the power supply voltage V output by the controlled LDO main circuit module LDO middle.

[0016] Compared with the prior art, the present invention has the following beneficial effects: The present invention provides a high-efficiency and controllable adaptive LDO circuit. By adding a proportional adaptive unit current source control circuit, the adjustable resistance value can be adjusted by encoding according to the feedback signal of the digital core circuit, thereby increasing the output range of the LDO output voltage. It has the advantages of high efficiency, adaptive adjustment, and low noise. Attached Figure Description

[0017] Figure 1 The present invention provides a circuit block diagram of a highly efficient and controllable adaptive LDO circuit.

[0018] Figure 2 The circuit diagram of the adaptive control signal generation module provided by the present invention.

[0019] Figure 3 The circuit diagram of the first proportional adaptive unit provided by the present invention.

[0020] Figure 4 The circuit diagram of the comparator COMP provided for this invention.

[0021] Figure 5The circuit diagram of the digital adaptive control logic module provided by the present invention.

[0022] Figure 6 The circuit diagram of the controlled LDO main circuit module provided by the present invention. Detailed Implementation

[0023] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0024] like Figures 1 to 6 As shown, this embodiment of the invention specifically provides a high-efficiency, controllable, adaptive adjustment LDO circuit, including: The bandgap reference module receives a bias current I from the controlled LDO main circuit module. PT To generate a stable bias voltage V BG ; The adaptive control signal generation module includes a first proportional adaptive unit, a comparator COMP, and a digital adaptive control logic module; the first proportional adaptive unit dynamically adjusts its output current I based on the control signals A~E fed back from the digital adaptive control logic module. unit and adjustable resistor R ST The magnitude of the voltage, thus dynamically outputting voltage V. Z The comparator COMP is enabled by the enable signal ENP fed back from the digital adaptive control logic module, and responds to the input voltage V. Z and voltage divider V Q The comparison outputs a high or low level control signal V. COMP ; where the voltage divider V Q The voltage is generated by a series resistor R1~R2 connected at the series junction, with one end connected to the power supply AVDD and the other end grounded GND. The digital adaptive control logic module generates the voltage based on the input clock CLK and control signal V. COMP After logical processing, the control signals A~E are output as digital adaptive signals; The controlled LDO main circuit module, based on the input control signals A~E and the bias voltage V... BG and feedback voltage V FB To generate power supply voltages V at multiple voltage levels. LDO .

[0025] like Figure 3As shown, the first proportional adaptive unit includes: PMOS transistors MP7~MP13; wherein the source terminals of PMOS transistors MP7~MP11 and PMOS transistor MP13 are connected to power supply AVDD; the gate terminals of PMOS transistors MP7~MP11 are sequentially connected to control signals A~E, and the gate terminal of PMOS transistor MP13 is connected to voltage V. cons The drains of PMOS transistors MP7~MP10 and MP12~MP13 are connected to generate a current I. unit And connect the adjustable resistor R to ground GND. ST With output voltage V Z Furthermore, the drain terminal of PMOS transistor MP11 is connected to the source terminal of PMOS transistor MP12, and the gate terminals of the two are interconnected.

[0026] The resistors R1 and R2 mentioned above generate a voltage divider V. Q At this time, the voltage V Q for:

[0027] The adaptive control signal generation module will, according to V comp The control signals A, B, C, D, and E of the first proportional adaptive unit and the control enable signal ENP of the output comparator COMP are adaptively adjusted. The control signals A, B, C, D, and E dynamically adjust the output current I of the preceding first proportional adaptive unit. unit At this time, the input voltage V of comparator COMP is... Z for:

[0028] When the feedback loop consisting of the first proportional adaptive unit, comparator COMP, and digital adaptive control logic module is stable, the control signals A, B, C, D, and E will also be a stable output.

[0029] As a further description of the present invention, the aspect ratio (W / L) of the above-mentioned PMOS transistors MP7 to MP12 is 8:4:2:1:1:1, respectively; the substrate end and source end of the PMOS transistors MP7 to MP13 are interconnected.

[0030] Assume the current in the series branch of MP11 and MP12 is 0.5I, and the current in the MP13 branch is I. cons Then the current in branch MP10 is I, the current in branch MP9 is 2I, the current in branch MP8 is 4I, the current in branch MP7 is 8I, and the output current I of the first proportional adaptive unit controlled by adaptive control signals A, B, C, D, E is... unit The minimum is I cons (That is, at this time, control signals A, B, C, D, and E are all 0), output current I unitThe maximum is 15.5I+I cons .

[0031] like Figure 4 As shown, the comparator COMP includes: PMOS transistors MP1~MP6, NMOS transistors MN1~MN7, and an inverter INV1; the source terminals of PMOS transistors MP1~MP6 are connected to the power supply AVDD; the gate terminal of PMOS transistor MP1 is connected to the drain-gate terminal of PMOS transistor MP2 and the drain terminal of NMOS transistor MN2; the drain terminal of PMOS transistor MP1 is connected to the drain terminal of NMOS transistor MN1 and the gate terminals of NMOS transistors MN5~MN6; the gate terminal of NMOS transistor MN1 is connected to the gate terminal of NMOS transistor MN7; the source terminals of NMOS transistors MN1 and NMOS transistors MN5~MN7 are grounded to GND; the gate terminal of NMOS transistor MN2 is connected to the voltage V. Z The source terminal of NMOS transistor MN2 is connected to the drain terminal of NMOS transistor MN3 and the source terminal of NMOS transistor MN4; the gate terminal of NMOS transistor MN3 is connected to the enable signal ENP, and the source terminal of NMOS transistor MN3 is grounded to GND; the gate terminal of NMOS transistor MN4 is connected to voltage V. Q The drain of NMOS transistor MN4 is connected to the drain-gate of PMOS transistor MP3 and the gate of PMOS transistor MP4; the drain of PMOS transistor MP4 is connected to the drain of NMOS transistor MN5; the drain of NMOS transistor MN6 is connected to the drain-gate of PMOS transistor MP5 and the gate of PMOS transistor MP6; the drain of PMOS transistor MP6 is connected to the drain of NMOS transistor MN7 and the input of inverter INV1; the output of inverter INV1 outputs a control signal V. COMP The enable terminal of the inverter INV1 is connected to the enable signal ENP. The substrate and source terminals of the PMOS transistors MP1~MP6 and NMOS transistors MN1~MN7 are interconnected.

[0032] When V Z >V Q At that time, the comparator COMP outputs signal V comp When V is low; Z <V Q At that time, the comparator COMP outputs signal V comp It is a high level.

[0033] like Figure 5 As shown, the digital adaptive control logic module includes: a logic gate module, a multi-level counting trigger module, and buffers BUF1~BUF5; the logic gate module is used to input the clock CLK and the control signal V. COMPThe multi-level counting trigger module is connected to the logic gate module to form a loop feedback structure, and the output terminal of each level of the multi-level counting trigger module is connected to the input terminal of buffer BUF1~BUF5 in sequence. The output terminals of buffer BUF1~BUF5 output control signals A~E in sequence. At the same time, the output terminal of the loop feedback structure outputs the enable signal ENP.

[0034] Digital adaptive control logic module such as Figure 5 As shown, the circuit includes output buffers BUF1, BUF2, BUF3, BUF4, and BUF5; a 5-bit counter composed of five D flip-flops D1, D2, D3, D4, and D5; three-input AND gates AND1 and AND2; a three-input OR gate OR1; inverters INV2 and INV3; signal CDN is the external reset signal for the D flip-flops; signal ENP provides the enable signal for the pre-amplifier COMP; and signal V... comp This is the output signal of the preamplifier, and signal CLK is the clock input for the counter. Signals A, B, C, D, and E are the output digital adaptive air control signals.

[0035] Continue reading Figure 5 The logic gate module includes: an OR gate OR1, inverters INV2~INV3, and AND gates AND1~AND2; two inputs of the OR gate OR1 are respectively input to the clock CLK and the control signal V. COMP The third input terminal serves as a feedback terminal and is connected to the output terminal of AND gate AND2; the output terminal of AND gate AND2 is also connected to the input terminal of inverter INV3, and the output terminal of inverter INV3 outputs an enable signal ENP; the output terminal of OR gate OR1 is connected to the input terminal of inverter INV2, and the output terminal of inverter INV2 is connected to the first stage clock terminal of the multi-stage counting trigger module; the three input terminals of AND gate AND1 and the two input terminals of AND gate AND2 are sequentially connected to the output terminals of each stage of the multi-stage counting trigger module, and the output terminal of AND gate AND1 is connected to the third input terminal of AND gate AND2.

[0036] Continue reading Figure 5The multi-level counting trigger module includes: D flip-flops D1 to D5; the reset terminals of D flip-flops D1 to D5 are connected to an external reset signal CDN; the input terminals and output NOT terminals of each D flip-flop D1 to D5 are interconnected; the clock terminal of D flip-flop D1 is connected to the input terminal of D flip-flop D2; the clock terminal of D flip-flop D2 is connected to the input terminal of D flip-flop D3; the clock terminal of D flip-flop D3 is connected to the input terminal of D flip-flop D4; the clock terminal of D flip-flop D4 is connected to the input terminal of D flip-flop D5; the clock terminal of D flip-flop D5 is connected to the output terminal of the inverter INV2; the output terminals of D flip-flops D1 to D5 are sequentially connected to the input terminals of buffers BUF1 to BUF5.

[0037] like Figure 6 As shown, the controlled LDO main circuit module includes: error amplifier A E PMOS transistor MP14, feedback resistor R FB1 ~R FB2 Second proportional adaptive unit, resistor R, filter resistor R ESR and filter capacitor C; the error amplifier A E The positive input terminal is connected to the bias voltage V. BG The negative input terminal is connected to the feedback voltage V. FB The output terminal is connected to the gate terminal of the PMOS transistor MP14; the source terminal of the PMOS transistor MP14 is connected to the ground GND resistor R and the filter resistor R. ESR One end of the second proportional adaptive unit outputs the power supply voltage V. LDO The control signals A~E are input to the input terminal of the second proportional adaptive unit; the filter resistor R ESR The other end is connected to a filter capacitor C grounded to GND; the drain of the PMOS transistor MP14 is connected to a feedback resistor R connected in series with grounded to GND. FB1 ~R FB2 And the feedback resistor R FB1 ~R FB2 The series connection point generates the feedback voltage V. FB The structure of the second proportional adaptive unit is the same as that of the first proportional adaptive unit, so it will not be described in detail again.

[0038] Continue reading Figure 6 The error amplifier A E Includes: PMOS transistors MP15~MP18, NMOS transistors MN8~MN9, and bias current source I. PT The source terminals of PMOS transistors MP15-MP16 are connected to the power supply AVDD, and the drain-gate terminal of PMOS transistor MP15 is connected to the gate terminal of PMOS transistor MP16 and the bias current source I connected to ground GND.PT The drain of PMOS transistor MP16 is connected to the drain of PMOS transistors MP17-MP18, and the gate of PMOS transistor MP17 is connected as the negative input terminal to the feedback voltage V. FB The source terminal of the PMOS transistor MP17 is connected to the drain-gate terminal of NMOS transistor MN8 and the gate terminal of NMOS transistor MN9. The source terminals of NMOS transistors MN8-MN9 are grounded to GND. The drain terminal of NMOS transistor MN9 is connected to the source terminal of PMOS transistor MP18 and serves as its output terminal. The gate terminal of PMOS transistor MP18 serves as its positive input terminal and is connected to the bias voltage V. BG The substrate and source ends of the aforementioned PMOS transistors MP14~MP18 and NMOS transistors MN8~MN8 are interconnected.

[0039] The above PMOS transistor MP14 and resistor R FB1 R FB2 This forms a feedback branch, with the feedback voltage V of this branch being the input to the negative input terminal of the error amplifier. FB The positive input terminal of the error amplifier receives the bias voltage V from the bandgap reference module. BG When the loop gain is large enough, the feedback branch will reduce V. BG and V FB The difference between them, ultimately V FB Mirror V BG The second proportional adaptive unit and resistor R will V FB For V BG The forced mirror transfer to the output voltage signal V of the controlled LDO main circuit LDO In the middle, the resistance R ESR Together with the filter capacitor C, they form an output filter to ensure stable output voltage and reduce noise interference.

[0040] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A high-efficiency, controllable, adaptive adjustment LDO circuit, characterized in that, include: The bandgap reference module receives a bias current I from the controlled LDO main circuit module. PT To generate a stable bias voltage V BG ; The adaptive control signal generation module includes a first proportional adaptive unit, a comparator COMP, and a digital adaptive control logic module; the first proportional adaptive unit dynamically adjusts its output current I based on the control signals A~E fed back from the digital adaptive control logic module. unit and adjustable resistor R ST The magnitude of the voltage, thus dynamically outputting voltage V. Z The comparator COMP is enabled by the enable signal ENP fed back from the digital adaptive control logic module, and responds to the input voltage V. Z and voltage divider V Q The comparison outputs a high or low level control signal V. COMP The digital adaptive control logic module controls the input clock CLK and control signal V. COMP After logical processing, the control signals A~E are output as digital adaptive signals; The controlled LDO main circuit module, based on the input control signals A~E and the bias voltage V... BG and feedback voltage V FB To generate power supply voltages V at multiple voltage levels. LDO ; The controlled LDO main circuit module includes: error amplifier A E PMOS transistor MP14, feedback resistor R FB1 ~R FB2 Second proportional adaptive unit, resistor R, filter resistor R ESR and filter capacitor C; the error amplifier A E The positive input terminal is connected to the bias voltage V. BG The negative input terminal is connected to the feedback voltage V. FB The output terminal is connected to the gate terminal of the PMOS transistor MP14; the source terminal of the PMOS transistor MP14 is connected to the ground GND resistor R and the filter resistor R. ESR One end of the second proportional adaptive unit outputs the power supply voltage V. LDO The control signals A~E are input to the input terminal of the second proportional adaptive unit; the filter resistor R ESR The other end is connected to a filter capacitor C that is grounded to GND; the drain of the PMOS transistor MP14 is connected to a feedback resistor R connected in series with grounded to GND. FB1 ~R FB2 And the feedback resistor R FB1 ~R FB2 The series connection point generates the feedback voltage V. FB .

2. The high-efficiency, controllable, adaptive adjustment LDO circuit as described in claim 1, characterized in that, The first proportional adaptive unit includes: PMOS transistors MP7~MP13; wherein the source terminals of PMOS transistors MP7~MP11 and PMOS transistor MP13 are connected to power supply AVDD; the gate terminals of PMOS transistors MP7~MP11 are sequentially connected to control signals A~E, and the gate terminal of PMOS transistor MP13 is connected to voltage V. cons The drains of PMOS transistors MP7~MP10 and MP12~MP13 are connected to generate a current I. unit And connect the adjustable resistor R to ground GND. ST With output voltage V Z Furthermore, the drain terminal of PMOS transistor MP11 is connected to the source terminal of PMOS transistor MP12, and the gate terminals of the two are interconnected.

3. The high-efficiency, controllable, adaptive adjustment LDO circuit as described in claim 2, characterized in that, The aspect ratios of PMOS transistors MP7 to MP12 are 8:4:2:1:1:1, respectively.

4. The high-efficiency, controllable, adaptive adjustment LDO circuit as described in claim 1, characterized in that, The comparator COMP includes: PMOS transistors MP1~MP6, NMOS transistors MN1~MN7, and an inverter INV1; the source terminals of PMOS transistors MP1~MP6 are connected to the power supply AVDD; the gate terminal of PMOS transistor MP1 is connected to the drain-gate terminal of PMOS transistor MP2 and the drain terminal of NMOS transistor MN2; the drain terminal of PMOS transistor MP1 is connected to the drain terminal of NMOS transistor MN1 and the gate terminals of NMOS transistors MN5~MN6; the gate terminal of NMOS transistor MN1 is connected to the gate terminal of NMOS transistor MN7; the source terminals of NMOS transistors MN1 and MN5~MN7 are grounded to GND; the gate terminal of NMOS transistor MN2 is connected to the voltage V. Z The source terminal of NMOS transistor MN2 is connected to the drain terminal of NMOS transistor MN3 and the source terminal of NMOS transistor MN4; the gate terminal of NMOS transistor MN3 is connected to the enable signal ENP, and the source terminal of NMOS transistor MN3 is grounded to GND; the gate terminal of NMOS transistor MN4 is connected to voltage V. Q The drain of NMOS transistor MN4 is connected to the drain-gate of PMOS transistor MP3 and the gate of PMOS transistor MP4; the drain of PMOS transistor MP4 is connected to the drain of NMOS transistor MN5; the drain of NMOS transistor MN6 is connected to the drain-gate of PMOS transistor MP5 and the gate of PMOS transistor MP6; the drain of PMOS transistor MP6 is connected to the drain of NMOS transistor MN7 and the input of inverter INV1; the output of inverter INV1 outputs a control signal V. COMP The enable terminal of the inverter INV1 is connected to the enable signal ENP.

5. The high-efficiency, controllable, adaptive adjustment LDO circuit as described in claim 1, characterized in that, The digital adaptive control logic module includes: a logic gate module, a multi-level counter trigger module, and buffers BUF1~BUF5; the logic gate module is used to input clock CLK and control signal V. COMP The multi-level counting trigger module is connected to the logic gate module to form a loop feedback structure, and the output terminal of each level of the multi-level counting trigger module is connected to the input terminal of buffer BUF1~BUF5 in sequence. The output terminals of buffer BUF1~BUF5 output control signals A~E in sequence. At the same time, the output terminal of the loop feedback structure outputs the enable signal ENP.

6. The high-efficiency, controllable, adaptive adjustment LDO circuit as described in claim 5, characterized in that, The logic gate module includes: an OR gate OR1, inverters INV2~INV3, and AND gates AND1~AND2; two inputs of the OR gate OR1 are respectively input to the clock CLK and the control signal V. COMP The third input terminal serves as a feedback terminal and is connected to the output terminal of AND gate AND2; the output terminal of AND gate AND2 is also connected to the input terminal of inverter INV3, and the output terminal of inverter INV3 outputs an enable signal ENP; the output terminal of OR gate OR1 is connected to the input terminal of inverter INV2, and the output terminal of inverter INV2 is connected to the first stage clock terminal of the multi-stage counting trigger module; the three input terminals of AND gate AND1 and the two input terminals of AND gate AND2 are sequentially connected to the output terminals of each stage of the multi-stage counting trigger module, and the output terminal of AND gate AND1 is connected to the third input terminal of AND gate AND2.

7. The high-efficiency, controllable, adaptive adjustment LDO circuit as described in claim 6, characterized in that, The multi-level counting trigger module includes: D flip-flops D1 to D5; the reset terminals of D flip-flops D1 to D5 are connected to an external reset signal CDN; the input terminals and output NOT terminals of each D flip-flop D1 to D5 are interconnected; the clock terminal of D flip-flop D1 is connected to the input terminal of D flip-flop D2; the clock terminal of D flip-flop D2 is connected to the input terminal of D flip-flop D3; the clock terminal of D flip-flop D3 is connected to the input terminal of D flip-flop D4; the clock terminal of D flip-flop D4 is connected to the input terminal of D flip-flop D5; the clock terminal of D flip-flop D5 is connected to the output terminal of the inverter INV2; the output terminals of D flip-flops D1 to D5 are sequentially connected to the input terminals of buffers BUF1 to BUF5.

8. The high-efficiency, controllable, adaptive adjustment LDO circuit as described in claim 1, characterized in that, The error amplifier A E Includes: PMOS transistors MP15~MP18, NMOS transistors MN8~MN9, and bias current source I. PT The source terminals of PMOS transistors MP15-MP16 are connected to the power supply AVDD, and the drain-gate terminal of PMOS transistor MP15 is connected to the gate terminal of PMOS transistor MP16 and the bias current source I connected to ground GND. PT The drain of PMOS transistor MP16 is connected to the drain of PMOS transistors MP17-MP18, and the gate of PMOS transistor MP17 is connected as the negative input terminal to the feedback voltage V. FB The source terminal of the PMOS transistor MP17 is connected to the drain-gate terminal of NMOS transistor MN8 and the gate terminal of NMOS transistor MN9. The source terminals of NMOS transistors MN8-MN9 are grounded to GND. The drain terminal of NMOS transistor MN9 is connected to the source terminal of PMOS transistor MP18 and serves as its output terminal. The gate terminal of PMOS transistor MP18 serves as its positive input terminal and is connected to the bias voltage V. BG .

9. The high-efficiency, controllable, adaptive adjustment LDO circuit as described in claim 8, characterized in that, When the loop gain of the controlled LDO main circuit module is sufficiently large, the PMOS transistor MP14 and the feedback resistor R... FB1 ~R FB2 The constructed feedback branch will reduce the bias voltage V. BG and feedback voltage V FB The difference between them, and finally the feedback voltage V FB The bias voltage V is mirrored. BG The feedback voltage V is transmitted through the second proportional adaptive unit and the resistor R. FB For the bias voltage V BG The forced mirror transfer to the power supply voltage V output by the controlled LDO main circuit module LDO middle.

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