Network-on-chip based processing unit reset system, method, and semiconductor device

Abstract

The disclosure provides a network-on-chip-based processing unit reset system and method and a semiconductor device, relates to the technical field of semiconductors, in particular to the fields of system-on-chip design, reset management of system-on-chip, and the implementation scheme is as follows: the processing unit has a master device mode and a slave device mode, and communicates with external devices through a network-on-chip; the network-on-chip includes a first interface unit and a second interface unit; a reset protection unit is arranged in the internal top packaging of the processing unit and is located on a data path between the network-on-chip and the processing unit; in a first reset mode, the reset protection unit waits for the processing unit to return to an idle state, if the processing unit returns within a preset time, a reset operation is performed, if the waiting time is exceeded, the two interface units are controlled to complete data transmission and then the reset operation is performed; in a second reset mode, the two interface units are directly controlled to complete data transmission and then the reset operation is performed; in a third reset mode, the reset operation is directly performed on the processing unit.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to the fields of system-on-chip design and system-on-chip reset management, and especially to a processing unit reset system, method and semiconductor device based on a network-on-chip. Background Technology

[0002] In a system-on-a-chip (SoC), processing units typically interact with other devices via an on-chip network. When a processing unit encounters an error or needs to reload a task during operation, a reset is required. However, bus interactions between the processing unit and external devices are often in progress. If a reset is performed directly on the processing unit before data transmission is complete, the processing unit will discard the currently incomplete transmission transaction. The external devices interacting with it will not be aware that the processing unit has been reset and will continue to wait for the processing unit to complete subsequent data transmission or return a response, potentially affecting the normal operation of the entire SoC. Therefore, how to protect the processing units in the on-chip network from reset has become an important technical direction. Summary of the Invention

[0003] This disclosure provides a processing unit reset system, method, and semiconductor device based on an on-chip network.

[0004] According to one aspect of this disclosure, a processing unit reset system based on an on-chip network is provided, comprising: a processing unit, including a master device mode and a slave device mode; an on-chip network, through which the processing unit communicates with external devices, the on-chip network including a first interface unit and a second interface unit, wherein the first interface unit corresponds to the network interface through which the processing unit initiates a request in master device mode, and the second interface unit corresponds to the network interface through which the processing unit receives a request in slave device mode; and a reset protection unit, disposed inside the top-level package of the processing unit and located on the data path between the on-chip network and the processing unit, the reset protection unit being configured to operate in a first reset mode, a second reset mode, and a third reset mode. The system operates as follows: In a first reset mode, the reset protection unit is configured to wait for the processing unit to return to an idle state; in response to the processing unit returning to an idle state within a preset time, the reset protection unit performs a reset operation on the processing unit; and in response to the reset protection unit waiting for a time exceeding a preset time, the reset protection unit controls the first interface unit and the second interface unit to perform data transmission, and performs a reset operation on the processing unit after the data transmission is completed; in a second reset mode, the reset protection unit is configured to control the data transmission of the first interface unit and the second interface unit, and performs a reset operation on the processing unit after the data transmission is completed; and in a third reset mode, the reset protection unit is configured to perform a reset operation on the processing unit.

[0005] In some embodiments, the reset protection unit controls the first interface unit and the second interface unit to perform data transmission, including: in response to the processing unit being in master device mode, the reset protection unit completes the current burst transmission via the first interface unit; and in response to the processing unit being in slave device mode, the reset protection unit waits for the second interface unit to generate a timeout signal.

[0006] In some embodiments, the request initiated by the processing unit includes a write request and a read request. The reset protection unit completes the current burst transmission via the first interface unit, including: in response to the request initiated by the processing unit being a write request, based on the burst length information in the write request, the reset protection unit pads the write data corresponding to the write request with preset padding data and sends it to the external device via the first interface unit, wherein the burst length information is used to indicate the amount of data contained in the current burst transmission; and in response to the request initiated by the processing unit being a read request, the reset protection unit receives the read data returned by the external device and discards it.

[0007] In some embodiments, performing a reset operation on the processing unit includes: a reset protection unit performing data isolation on the processing unit; and the reset protection unit sending a reset indication signal to a reset sequence to cause the reset sequence to perform a reset on the processing unit.

[0008] In some embodiments, the on-chip network-based processing unit reset system further includes a top-level controller configured to issue reset requests for the processing unit. The reset requests include a normal reset request for when the processing unit is operating normally, a forced takeover reset request for when the processing unit malfunctions, and a forced reset request for when a forced reset is required.

[0009] In some embodiments, the reset protection unit is further configured to send a reset completion signal to the top-level controller after performing a reset operation.

[0010] In some embodiments, the top-level controller is further configured to, upon receiving a reset completion signal, turn off the clocks of the first interface unit and the second interface unit, and issue an interface reset request for the first interface unit and the second interface unit.

[0011] In some embodiments, the reset protection unit has an operating clock independent of the processing unit.

[0012] According to one aspect of this disclosure, a method for resetting a processing unit based on an on-chip network is provided, comprising: receiving a reset request for the processing unit, wherein the reset request includes a normal reset request issued when the processing unit is operating normally, a forced takeover reset request issued when the processing unit malfunctions, and a forced reset request issued during forced reset; in response to receiving a normal reset request for the processing unit, controlling a reset protection unit to perform a reset operation on the processing unit in a first reset mode; in response to receiving a forced takeover reset request for the processing unit, controlling the reset protection unit to perform a reset operation on the processing unit in a second reset mode; and in response to receiving a forced reset request for the processing unit, controlling the reset protection unit to perform a reset operation on the processing unit in a third reset mode.

[0013] According to another aspect of this disclosure, a semiconductor device is provided, the semiconductor device including the on-chip network-based processing unit reset system as provided above in this disclosure.

[0014] According to one or more embodiments of this disclosure, a safe dynamic reset of the processing unit can be achieved.

[0015] These and other aspects of this disclosure will be apparent from the embodiments described below, and will be elucidated with reference to the embodiments described below. Attached Figure Description

[0016] The accompanying drawings exemplify embodiments and form part of the specification, serving together with the textual description to explain exemplary implementations of the embodiments. The illustrated embodiments are for illustrative purposes only and do not limit the scope of this disclosure. Throughout the drawings, the same reference numerals refer to similar but not necessarily identical elements.

[0017] Figure 1 This is a schematic diagram illustrating a network-on-chip-based processing unit reset system according to an exemplary embodiment.

[0018] Figure 2 This is a schematic diagram illustrating a network-on-chip-based processing unit reset system according to another exemplary embodiment.

[0019] Figure 3 This is a flowchart illustrating a network-on-chip-based processing unit reset method according to an exemplary embodiment.

[0020] Figure 4 This is a schematic diagram illustrating a semiconductor device according to an exemplary embodiment. Detailed Implementation

[0021] The exemplary embodiments of this disclosure are described below with reference to the accompanying drawings, including various details of the embodiments to aid understanding, and should be considered merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope of this disclosure. Similarly, for clarity and brevity, descriptions of well-known functions and structures are omitted in the following description.

[0022] In this disclosure, unless otherwise stated, the use of terms such as "first," "second," etc., to describe various elements is not intended to limit the positional, temporal, or importance relationships of these elements; such terms are merely used to distinguish one element from another. In some examples, the first element and the second element may refer to the same instance of that element, while in other cases, based on the context, they may refer to different instances.

[0023] The terminology used in the description of the various examples described in this disclosure is for the purpose of describing particular examples only and is not intended to be limiting. Unless the context explicitly indicates otherwise, an element may be one or more unless the number of elements is specifically limited. As used herein, the term "multiple" means two or more, and the term "based on" should be interpreted as "at least partially based on". Furthermore, the terms "and / or" and "at least one of..." cover any one of the listed items and all possible combinations thereof.

[0024] In related technologies, a direct reset is typically used when resetting the processing unit. While the direct reset method is simple, it can interrupt ongoing bus transactions on the on-chip network, causing external devices interacting with the processing unit to enter a continuous waiting state because they cannot receive the expected data or response, thus affecting the normal operation of the entire on-chip system.

[0025] First, existing solutions typically lack the ability to differentiate between different reset scenarios. The reasons why a processing unit needs to be reset are varied, ranging from scenarios where the unit is running normally but requires task reloading to scenarios where the unit malfunctions and cannot respond normally. The requirements for the reset process differ in different scenarios, but existing solutions often employ a uniform reset strategy, failing to provide optimal handling for different scenarios.

[0026] Secondly, the protection module in the existing solution is usually deployed between the device and the bus, existing as an independent external module. It cannot directly obtain the internal operating status of the processing unit, and can only rely on the timeout mechanism on the bus interface to passively determine whether the processing unit is abnormal, which has the problem of response lag, and also increases the additional hardware resource overhead.

[0027] To address this, embodiments of this disclosure propose a processing unit reset system and method based on on-chip network. By setting a reset protection unit with multiple reset modes, a reset strategy can be selected according to different reset scenarios. This ensures that unfinished bus transactions in the on-chip network are safely processed while completing the reset operation, thereby avoiding the impact of the reset process on external devices and the on-chip network, and improving the reset reliability and overall operational stability of the on-chip system.

[0028] Exemplary embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0029] Figure 1 This is a schematic diagram illustrating a network-on-chip-based processing unit reset system according to an exemplary embodiment.

[0030] In some embodiments, the on-chip network-based processing unit reset system includes a processing unit, which includes a master device mode and a slave device mode.

[0031] In the example, such as Figure 1 As shown, the on-chip network-based processing unit reset system includes a processing unit. Within the on-chip network, the processing unit needs to actively initiate data access requests to external devices, such as writing or reading data from external memory (in which case the processing unit is in master mode). Simultaneously, the processing unit also needs to receive and respond to access requests from external devices, such as receiving configuration operations from an external master controller on its internal registers (in which case the processing unit is in slave mode). Because the processing unit operates in both modes, resetting it requires considering any unfinished tasks in both directions.

[0032] In some embodiments, the on-chip network-based processing unit reset system further includes an on-chip network, through which the processing unit communicates with external devices. The on-chip network includes a first interface unit and a second interface unit, wherein the first interface unit corresponds to the network interface through which the processing unit initiates a request in master device mode, and the second interface unit corresponds to the network interface through which the processing unit receives a request in slave device mode.

[0033] In the example, such as Figure 1As shown, the on-chip network includes a first interface unit and a second interface unit. The processing unit can communicate with external devices through the on-chip network. The first interface unit corresponds to the network interface through which the processing unit initiates a request in master device mode. That is, when the processing unit needs to actively access an external device, its read / write request enters the on-chip network through the first interface unit and is then forwarded to the target device by the routing unit in the on-chip network. The second interface unit corresponds to the network interface through which the processing unit receives a request in slave device mode. That is, when an external device needs to access the processing unit, the request initiated by the external device is routed through the on-chip network and reaches the processing unit through the second interface unit. The first and second interface units respectively carry the data transmission paths of the processing unit in the two operating modes. Therefore, when the processing unit needs to be reset, there may be access requests initiated by the processing unit but not yet completed in the direction of the first interface unit, and there may be requests initiated by external devices but not yet responded to by the processing unit in the direction of the second interface unit. The unfinished transactions in the two directions need to be processed separately.

[0034] In some embodiments, the on-chip network-based processing unit reset system further includes a reset protection unit disposed inside the top-level package of the processing unit and located on the data path between the on-chip network and the processing unit. The reset protection unit is configured to operate in a first reset mode, a second reset mode, and a third reset mode. In the first reset mode, the reset protection unit is configured to wait for the processing unit to return to an idle state, and in response to the processing unit returning to an idle state within a preset time, perform a reset operation on the processing unit; and in response to the reset protection unit waiting for a time exceeding a preset time, the reset protection unit controls the first interface unit and the second interface unit to perform data transmission, and performs a reset operation on the processing unit after the data transmission is completed. In the second reset mode, the reset protection unit is configured to control the data transmission of the first interface unit and the second interface unit, and performs a reset operation on the processing unit after the data transmission is completed. In the third reset mode, the reset protection unit is configured to perform a reset operation on the processing unit.

[0035] In the example, such as Figure 1As shown, the reset protection unit is located inside the top-level package 101 of the processing unit and on the data path between the on-chip network and the processing unit, transmitting data via the data bus. This deployment allows the reset protection unit to directly monitor the data interaction between the processing unit and the on-chip network. Under normal operating conditions, the reset protection unit does not interfere with data transmission, and data between the on-chip network and the processing unit is transmitted normally via the data bus. When a reset of the processing unit is required, the reset protection unit can take over the data path and complete any unfinished transactions between the processing unit and the on-chip network. The reset protection unit's location inside the top-level package 101 of the processing unit allows it to directly obtain the internal operating status signals of the processing unit, such as whether the processing unit is in an idle state.

[0036] In the example, the reset protection unit is configured to operate in three modes: a first reset mode, a second reset mode, and a third reset mode, each corresponding to a different reset scenario. The first reset mode is suitable for scenarios where the processing unit is running normally but needs to be reset, such as when the processing unit has completed its current computational task and needs to reload a new task. In this scenario, the processing unit itself has not malfunctioned and is capable of autonomously completing its current transaction and returning to an idle state. Therefore, in the first reset mode, the reset protection unit can first wait for the processing unit to return to an idle state. If the processing unit returns to an idle state within a preset time, it indicates that the processing unit has autonomously completed all ongoing transactions, and the reset protection unit can safely perform a reset operation on the processing unit. However, if the processing unit fails to return to an idle state within the preset time, it may mean that although the processing unit was running normally before receiving the reset request, a problem occurred during the waiting process, preventing it from autonomously completing its current transaction. In this case, the reset protection unit switches to a takeover process, controlling the data transmission of the first interface unit and the second interface unit respectively, completing the unfinished transactions in both directions on behalf of the processing unit, and then performing a reset operation on the processing unit after all data transmission is completed. This hierarchical takeover strategy avoids unnecessary takeover operations when the processing unit can respond normally, and ensures safe execution of the reset when the processing unit cannot recover on its own.

[0037] In the example, the second reset mode is applicable to scenarios where the processing unit has encountered an abnormality, such as a fault in the internal logic of the processing unit causing it to malfunction and triggering an abnormal interrupt. In this scenario, the processing unit can no longer return to the idle state on its own, and the reset protection unit directly enters the takeover process, controlling the data transmission between the first interface unit and the second interface unit, completing the unfinished transactions in both directions on behalf of the processing unit, and performing a reset operation on the processing unit after all data transmission is completed.

[0038] In the example, the third reset mode is suitable for scenarios where the entire on-chip system requires a unified reset, such as a chip power-on reset or a system-level reset. In this scenario, not only the processing unit needs to be reset, but also the external devices interacting with it and the on-chip network itself will be reset simultaneously. Based on this, in the third reset mode, the reset protection unit does not perform a takeover operation but directly performs a reset operation on the processing unit. This design avoids performing unnecessary operations in scenarios where the entire system needs to be reset, simplifying the reset process. The design of three reset modes allows the reset protection unit to adopt the most appropriate reset strategy according to different reset scenarios, ensuring reset safety.

[0039] Therefore, the reset protection unit is located inside the top-level package of the processing unit and on the data path between the on-chip network and the processing unit. It can directly obtain the operating status of the processing unit and take over the data path when a reset is required, ensuring that unfinished transactions in the on-chip network are correctly processed during the reset process. This prevents external devices from entering an abnormal state while waiting for a response or data from the processing unit. Simultaneously, the reset protection unit provides three reset modes to adapt to different reset scenarios, enabling the system to safely reset the processing unit in various situations, thus improving the reset reliability and overall operational stability of the on-chip system.

[0040] In some embodiments, the reset protection unit controls the first interface unit and the second interface unit to perform data transmission, including: in response to the processing unit being in master device mode, the reset protection unit completes the current burst transmission via the first interface unit; and in response to the processing unit being in slave device mode, the reset protection unit waits for the second interface unit to generate a timeout signal.

[0041] In the example, after the reset protection unit enters the takeover process, it needs to handle the incomplete transactions of the processing unit in both operating modes. For the processing unit acting as the master device, it may have previously initiated access requests to external devices through the first interface unit. For example, it may have initiated a write address request but not yet sent all write data, or initiated a read request but not yet received all the data returned by the external device. If these incomplete transmissions are not processed before resetting the processing unit, the external device will be stuck in a continuous wait because it cannot receive the expected subsequent data or cannot send the prepared return data. Therefore, after taking over, the reset protection unit completes the currently ongoing burst transmission through the first interface unit, enabling the external device to complete the transaction normally and release the relevant bus resources.

[0042] In the example, for the processing unit acting as a slave device, the external device may have previously initiated an access request to the processing unit through the second interface unit. Since the transaction in this direction was initiated by the external device, the second interface unit of the on-chip network itself has a timeout mechanism. When the processing unit cannot respond normally, the second interface unit will automatically return a timeout signal to the external device after the timeout, causing the external device to exit the waiting state. Therefore, the reset protection unit only needs to wait for the second interface unit to generate a timeout signal in the slave device direction to confirm that the transaction in this direction has been processed by the on-chip network itself.

[0043] Therefore, by actively taking over and completing the incomplete burst transmission in the direction of the master device through the reset protection unit, it is ensured that the external device can receive the expected data normally and thus complete the transaction; in the direction of the slave device, the timeout mechanism of the second interface unit of the on-chip network is used to handle the incomplete transaction, reducing the hardware resource overhead of the reset protection unit.

[0044] In some embodiments, the request initiated by the processing unit includes a write request and a read request. The reset protection unit completes the current burst transmission via the first interface unit, including: in response to the request initiated by the processing unit being a write request, based on the burst length information in the write request, the reset protection unit pads the write data corresponding to the write request with preset padding data and sends it to the external device via the first interface unit, wherein the burst length information is used to indicate the amount of data contained in the current burst transmission; and in response to the request initiated by the processing unit being a read request, the reset protection unit receives the read data returned by the external device and discards it.

[0045] In the example, when the reset protection unit takes over an incomplete burst transmission in the master device direction, it can adopt different processing methods according to the request type initiated by the processing unit. When the request initiated by the processing unit is a write request, the write address channel of the write request carries burst length information, which indicates the number of write data entries included in this burst transmission. Based on the burst length information and the number of write data entries actually sent by the processing unit before the anomaly, the reset protection unit can calculate the number of remaining data entries that have not yet been sent, and then fill in these remaining write data entries with preset padding data, and send them to the external device via the first interface unit. It should be noted here that the preset padding data does not need to guarantee the correctness of the data; its purpose is to complete the transmission process of the bus protocol so that the external device can receive the number of data entries consistent with the burst length information, thereby normally ending this write transaction and releasing bus resources.

[0046] In the example, when the processing unit initiates a read request, it has already sent a read address request to the external device through the first interface unit before the exception. Upon receiving the read address request, the external device prepares the corresponding read data and returns it. Since the processing unit has now encountered an exception and cannot normally receive and process this read data, but if this data is not received, the external device's return channel will be blocked. Therefore, the reset protection unit receives the read data returned by the external device on behalf of the processing unit and discards the received data directly, allowing the external device to normally terminate this read transaction.

[0047] Therefore, in master device mode, by processing write requests and read requests separately, it is ensured that all kinds of incomplete transactions of the processing unit can be processed correctly, so that external devices and bus resources can be released in a timely manner.

[0048] In some embodiments, performing a reset operation on the processing unit includes: a reset protection unit performing data isolation on the processing unit; and the reset protection unit sending a reset indication signal to a reset sequence to cause the reset sequence to perform a reset on the processing unit.

[0049] In the example, performing a reset operation on the processing unit involves two steps. First, the reset protection unit performs data isolation on the processing unit, that is, it cuts off the data path between the processing unit and the on-chip network, preventing the processing unit from initiating or receiving new access requests to the on-chip network while it is about to be reset, thereby preventing the generation of new unfinished transactions during the reset process. After the data isolation is completed, the reset protection unit sends a reset indication signal to the reset sequence, which then performs the actual reset operation on the processing unit. The reset sequence can manage the reset order and timing relationship of each module within the processing unit, ensuring that each module within the processing unit completes the reset in the correct sequence.

[0050] Therefore, by isolating before resetting, it can be ensured that the processing unit is isolated from the external bus before the reset signal reaches the processing unit, thus avoiding interference from the on-chip network caused by the uncertain state of the processing unit at the moment of reset, thereby ensuring the orderliness and reliability of the reset process.

[0051] In some embodiments, the system further includes a top-level controller configured to issue reset requests for the processing unit. The reset requests include a normal reset request for when the processing unit is operating normally, a forced takeover reset request for when the processing unit malfunctions, and a forced reset request for when a forced reset is required.

[0052] In the example, the system also includes a top-level controller, which plays the role of reset decision-making in the entire on-chip system. The top-level controller is responsible for issuing corresponding reset requests to the reset protection unit based on the current status of the processing unit. Specifically, there are three types of reset requests. The first is a normal reset request, applicable to scenarios where the processing unit is running normally but needs to be reset. For example, the processing unit's current computation task has been completed and a new task configuration needs to be reloaded. In this case, the processing unit itself has not failed, and the top-level controller notifies the reset protection unit to reset the processing unit by issuing a normal reset request. The second is a forced takeover reset request, applicable to scenarios where the processing unit has experienced an anomaly. For example, a fault in the processing unit's internal logic causes it to malfunction, and the processing unit reports the fault status to the top-level controller via an abnormal interrupt signal. Upon receiving this abnormal interrupt, the top-level controller determines that the processing unit cannot recover autonomously and immediately issues a forced takeover reset request, notifying the reset protection unit to intervene and take over immediately. The third is a forced reset request, applicable to scenarios where the entire on-chip system needs to be reset uniformly, such as chip power-on initialization or system-level fault recovery. In this case, all modules, including the processing unit, will be reset, and the top-level controller issues a forced reset request to complete the reset in the simplest way. The distinction between the three reset requests allows the top-level controller to select the most appropriate reset strategy based on the actual situation, and the reset protection unit executes the corresponding reset procedure.

[0053] Therefore, the top-level controller issues different types of reset requests based on the different conditions of the processing unit, enabling the reset protection unit to execute the most appropriate reset process for different scenarios.

[0054] In some embodiments, the reset protection unit is further configured to send a reset completion signal to the top-level controller after performing a reset operation.

[0055] In the example, since the time for the reset protection unit to perform the reset operation is not fixed—the time from receiving the reset request to completing the reset varies under different reset modes and different transaction completion scenarios—the top-level controller cannot determine in advance when the reset operation will be completed. Therefore, after completing the reset operation on the processing unit, the reset protection unit can send a reset completion signal to the top-level controller. This signal informs the top-level controller that the processing unit has completed the reset, allowing the top-level controller to execute subsequent operation steps accordingly.

[0056] Therefore, by receiving the reset completion signal, the top-level controller can execute subsequent steps, thereby ensuring the determinism and reliability of the timing of the entire reset process.

[0057] In some embodiments, the top-level controller is further configured to, upon receiving a reset completion signal, turn off the clocks of the first interface unit and the second interface unit, and issue an interface reset request for the first interface unit and the second interface unit.

[0058] In the example, since the first and second interface units may have cached transaction state information related to the processing unit during previous data transmission, if they are not reset, this residual state information may cause the behavior of the interface units to be inconsistent with the actual state of the processing unit after the processing unit resumes operation. Therefore, after the processing unit completes its reset, the first and second interface units also need to be reset. Specifically, after receiving the reset completion signal sent by the reset protection unit, the top-level controller can first turn off the clocks of the first and second interface units, and then issue interface reset requests for these two interface units. Turning off the clocks before performing the interface reset can avoid signal races or state chaos that may be caused by performing the reset while the clock is still running. The interface units are part of the on-chip network, and their reset operations need to be coordinated with the overall state of the on-chip network. Therefore, the reset of the first and second interface units can be independently controlled by the top-level controller through configuration registers.

[0059] Therefore, by performing clock shutdown and reset operations on the first and second interface units after the processing unit is reset by the top-level controller, the transaction state information related to the processing unit that may remain in the interface units is cleared, ensuring that the processing unit can communicate normally with external devices through the on-chip network after the reset.

[0060] Figure 2 This is a schematic diagram illustrating a network-on-chip-based processing unit reset system according to another exemplary embodiment.

[0061] like Figure 2 As shown, the on-chip network-based processing unit reset system includes a top-level controller, an on-chip network, a reset protection unit, and a processing unit. The on-chip network internally includes a first interface unit and a second interface unit. The reset protection unit and the processing unit are located within the same package. The reset protection unit is located on the data path between the on-chip network and the processing unit, connected to both the on-chip network and the processing unit via a data bus. The reset protection unit also has a reset control connection to the processing unit. The top-level controller sends a reset request to the reset protection unit. After completing the reset operation, the reset protection unit sends a reset completion signal to the top-level controller. Upon receiving the reset completion signal, the top-level controller sends interface reset requests for the first and second interface units to the on-chip network. Furthermore, when an abnormality occurs in the processing unit, the processing unit reports an abnormal signal to the top-level controller, and the top-level controller sends a reset request.

[0062] In some embodiments, the reset protection unit has an operating clock independent of the processing unit.

[0063] In the example, the reset protection unit has an independent operating clock, which is a free-running clock unaffected by the clock control logic of the processing unit. During the reset process, the processing unit's clock may be shut down; for example, the top-level controller may turn off the processing unit's clock to put it into a quiescent state during a reset operation. If the reset protection unit shares the same clock as the processing unit, it will also cease operation when the processing unit's clock is shut down, unable to maintain control of the data path or interact with the top-level controller to complete the subsequent reset release process. Using an independent operating clock allows the reset protection unit to continue operating normally throughout the period when the processing unit's clock is shut down, maintaining continuous control of the data path and synchronizing between different clock domains after the processing unit's clock is restored, ensuring that control of the data path can be safely returned to the processing unit.

[0064] Therefore, by using an independent operating clock for the reset protection unit, it is ensured that the reset protection unit can still work normally when the clock of the processing unit is turned off, thereby ensuring the continuity and integrity of the entire reset process.

[0065] Figure 3 This is a flowchart illustrating a network-on-chip-based processing unit reset method according to an exemplary embodiment.

[0066] like Figure 3 As shown, the on-chip network-based processing unit reset method includes steps S301 to S304.

[0067] In step S301, a reset request for the processing unit is received. The reset request includes a normal reset request issued when the processing unit is operating normally, a forced takeover reset request issued when the processing unit malfunctions, and a forced reset request issued during a forced reset.

[0068] In the example, a reset request for the processing unit is first received. This reset request is determined and issued by the top-level controller based on the current operating status of the processing unit. There are three types of reset requests: when the processing unit is operating normally but needs to be reset (e.g., the current computation task has been completed and a new task needs to be reloaded), the top-level controller issues a normal reset request; when an internal abnormality occurs in the processing unit, causing it to malfunction (e.g., an internal logic fault is reported to the top-level controller via an abnormal interrupt signal), the top-level controller issues a forced takeover reset request; and when the entire on-chip system needs a unified reset (e.g., during chip power-on initialization or system-level fault recovery), the top-level controller issues a forced reset request. Upon receiving the reset request, the reset protection unit enters the corresponding reset procedure based on the request type. The different types of reset requests determine how the reset protection unit subsequently performs the reset operation on the processing unit.

[0069] In step S302, in response to receiving a normal reset request for the processing unit, the reset protection unit is controlled to perform a reset operation on the processing unit in the first reset mode.

[0070] In the example, a normal reset request is typically initiated when the processing unit is running normally, for example, when the current task of the processing unit has been completed and a new task configuration needs to be reloaded. In this scenario, the processing unit itself has not failed and has the ability to autonomously complete the current transaction and return to an idle state, so the first reset mode is suitable. In the first reset mode, the reset protection unit first waits for the processing unit to complete the current transaction and return to an idle state on its own, and only transfers the takeover control flow if the wait times out.

[0071] In step S303, in response to receiving a forced takeover reset request for the processing unit, the reset protection unit is controlled to perform a reset operation on the processing unit in the second reset mode.

[0072] In the example, a forced takeover reset request is typically initiated when a processing unit has already encountered an exception, such as a fault in the internal logic of the processing unit reported via an exception interrupt signal. In this scenario, the processing unit is no longer functioning properly and lacks the ability to autonomously complete the current transaction and return to an idle state. In the second reset mode, the reset protection unit skips the waiting for the idle state step and directly enters the takeover process, completing the unfinished transaction in place of the processing unit before performing the reset.

[0073] In step S304, in response to receiving a forced reset request for the processing unit, the reset protection unit is controlled to perform a reset operation on the processing unit in the third reset mode.

[0074] In the example, a forced reset request is typically initiated in scenarios where the entire on-chip system requires a unified reset, such as chip power-on initialization or system-level fault recovery. In such scenarios, not only the processing unit needs to be reset, but also the external devices interacting with it and the on-chip network itself will be reset simultaneously. In the third reset mode, the reset protection unit does not execute the takeover procedure but directly performs the reset operation on the processing unit.

[0075] Therefore, by controlling the reset protection unit to perform the reset operation in the corresponding reset mode according to the different types of reset requests received by the system, the processing unit can be reset in the most appropriate way under different reset scenarios, taking into account both the safety and efficiency of the reset.

[0076] According to another aspect of this disclosure, a semiconductor device is provided that includes the on-chip network-based processing unit reset system provided above.

[0077] Figure 4 This is a schematic diagram illustrating a semiconductor device according to an exemplary embodiment.

[0078] In embodiments of this disclosure, the semiconductor device may include, for example, a semiconductor chip. Figure 4 As shown, a semiconductor device may include a processing unit reset system based on an on-chip network. This semiconductor device may be an integrated circuit chip containing multi-core processing units and an on-chip network, such as a system-on-a-chip (SoC), graphics processor, or network processor. These chip products typically contain multiple processing units, which are interconnected via an on-chip network and interact with external devices. During actual operation, a single processing unit may require a reset due to task switching, software debugging, or internal malfunctions, while other processing units and external devices on the same chip must continue to operate normally. By integrating the processing unit reset system provided in this disclosure into the semiconductor device, the semiconductor device gains the ability to safely and dynamically reset a single processing unit. When resetting a target processing unit, it ensures that unfinished transactions on the on-chip network are correctly processed, preventing the reset operation from affecting the normal operation of other devices on the same chip, thereby improving the overall operational reliability and maintainability of the semiconductor device.

[0079] Although the present disclosure has been described and illustrated in detail in the accompanying drawings and the foregoing description, such description and illustration should be considered illustrative and schematic, not restrictive, and the present disclosure is not limited to the disclosed embodiments.

Claims

1. A processing unit reset system based on an on-chip network, characterized in that, The system includes: The processing unit includes master device mode and slave device mode; The on-chip network allows the processing unit to communicate with external devices. The on-chip network includes a first interface unit and a second interface unit. The first interface unit corresponds to the network interface that the processing unit uses when initiating a request in master device mode, and the second interface unit corresponds to the network interface that the processing unit uses when receiving a request in slave device mode. A reset protection unit is disposed inside the top-level package of the processing unit and located on the data path between the on-chip network and the processing unit. The reset protection unit is configured to operate in a first reset mode, a second reset mode, and a third reset mode. In the first reset mode, the reset protection unit is configured to wait for the processing unit to return to the idle state, and in response to the processing unit returning to the idle state within a preset time, to perform a reset operation on the processing unit. In response to the reset protection unit waiting time exceeding the preset time, the reset protection unit controls the first interface unit and the second interface unit to perform data transmission respectively, and performs a reset operation on the processing unit after the data transmission is completed; In the second reset mode, the reset protection unit is configured to control the data transmission between the first interface unit and the second interface unit, and to perform a reset operation on the processing unit after the data transmission is completed; and In the third reset mode, the reset protection unit is configured to perform a reset operation on the processing unit.

2. The system according to claim 1, characterized in that, The reset protection unit controls the first interface unit and the second interface unit to perform data transmission, including: In response to the processing unit being in the master device mode, the reset protection unit completes the current burst transmission via the first interface unit; and In response to the processing unit being in the slave device mode, the reset protection unit waits for the second interface unit to generate a timeout signal.

3. The system according to claim 2, characterized in that, The requests initiated by the processing unit include write requests and read requests. The reset protection unit completes the current burst transmission via the first interface unit, including: In response to a write request initiated by the processing unit, based on the burst length information in the write request, the reset protection unit pads the write data corresponding to the write request with preset padding data and sends it to the external device via the first interface unit. The burst length information indicates the amount of data contained in the current burst transmission. In response to a read request initiated by the processing unit, the reset protection unit receives the read data returned by the external device and discards it.

4. The system according to any one of claims 1 to 3, characterized in that, The reset operation on the processing unit includes: The reset protection unit performs data isolation on the processing unit; and The reset protection unit sends a reset indication signal to the reset sequence so that the reset sequence performs a reset on the processing unit.

5. The system according to any one of claims 1 to 3, characterized in that, The system also includes a top-level controller configured to issue reset requests for the processing unit. The reset requests include a normal reset request issued when the processing unit is operating normally, a forced takeover reset request issued when the processing unit malfunctions, and a forced reset request issued during a forced reset.

6. The system according to claim 5, characterized in that, The reset protection unit is also configured to send a reset completion signal to the top-level controller after performing the reset operation.

7. The system according to claim 6, characterized in that, The top-level controller is also configured to, upon receiving the reset completion signal, turn off the clocks of the first interface unit and the second interface unit, and issue an interface reset request for the first interface unit and the second interface unit.

8. The system according to claim 1, characterized in that, The reset protection unit has an operating clock independent of the processing unit.

9. A method for resetting a processing unit based on an on-chip network, applied to the system according to any one of claims 1-8, characterized in that, The method includes: Receive a reset request for the processing unit, wherein the reset request includes a normal reset request issued when the processing unit is operating normally, a forced takeover reset request issued when the processing unit malfunctions, and a forced reset request issued during a forced reset. In response to receiving a normal reset request for the processing unit, the reset protection unit is controlled to perform a reset operation on the processing unit in the first reset mode; In response to receiving a forced takeover reset request for the processing unit, the reset protection unit is controlled to perform a reset operation on the processing unit in the second reset mode; and In response to receiving a forced reset request for the processing unit, the reset protection unit is controlled to perform a reset operation on the processing unit in the third reset mode.

10. A semiconductor device, characterized in that, The semiconductor device includes a processing unit reset system based on a network-on-chip according to any one of claims 1 to 8.

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