A set type data stream analysis hardware acceleration method based on FPGA

CN122331968APending Publication Date: 2026-07-03NANJING UNIV

Patent Information

Authority / Receiving Office: CN · China
Patent Type: Applications(China)
Current Assignee / Owner: NANJING UNIV
Filing Date: 2026-04-13
Publication Date: 2026-07-03

AI Technical Summary

Technical Problem

In existing technologies, traditional software algorithms cannot be directly mapped to FPGA on-chip resources, resulting in spatial scalability and timing efficiency issues, making it difficult to effectively accelerate data flow analysis of large-scale programs.

Method used

Through hardware-software collaborative spatial reconstruction and hardware microarchitecture optimization, including data flow fact segmentation, equivalent reconstruction of control flow graphs, custom circuit microarchitecture, and register bitmap queue management, FPGA memory capacity is optimized and computational efficiency is improved.

Benefits of technology

It significantly improves the processing efficiency and energy efficiency of data flow analysis, and accelerates larger programs on the FPGA platform, achieving an execution speedup of 14.84 times and 12.00 times compared to traditional software analysis frameworks.

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Abstract

The application discloses a set type data stream analysis hardware acceleration method based on FPGA, wherein a program code to be analyzed is processed at a host end, a control flow graph for static data stream analysis and initial data stream facts are generated, data of an adaptive hardware storage structure suitable for the capacity limitation of an on-chip memory of FPGA is constructed, the data of the adaptive hardware storage structure is transmitted to an on-board memory of an accelerator card, and is dispatched to an on-chip memory BRAM of a FPGA acceleration kernel by a processing system on the accelerator card, and work list iteration calculation is performed through a circuit micro-architecture; after convergence of each iteration calculation, an analysis result is written back to the on-board memory of the accelerator card, and is dispatched back to the host end by the processing system on the accelerator card, and the host end splices and reconstructs to generate a final static data stream analysis result. The application effectively alleviates the on-chip memory limitation faced by a traditional algorithm when directly mapped to hardware, and improves the processing efficiency and energy efficiency performance of a program on set type data stream analysis under limited FPGA resources.

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