Method and apparatus for determining memory access latency, system

Abstract

The disclosure provides a memory access delay determination method, device and system, wherein the determination method comprises: determining the starting time of a plurality of memory access commands based on the same timer; for any one of the plurality of memory access commands, in response to detecting that the memory access command is executed, determining the latest value of the timer overflow identifier corresponding to the memory access command, wherein the latest value of the timer overflow identifier corresponding to the memory access command is used to indicate the number of times the timer reaches the maximum timing value from the starting time of the memory access command to the execution completion; and determining the access delay duration corresponding to the memory access command based on the latest value of the timer overflow identifier corresponding to the memory access command. The method can accurately calculate the access delay duration corresponding to the memory access command under the premise of reducing the occupation of hardware resources, thereby efficiently and accurately realizing memory access delay monitoring.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit technology, and specifically to a method for determining memory access latency, a device for determining memory access latency, a system for determining memory access latency, an electronic device, a computer-readable storage medium, and a computer program product. Background Technology

[0002] In graphics card chip systems, memory access latency is a key factor affecting performance. Accurate monitoring of memory access latency plays a crucial role in optimizing system performance and improving user experience. Currently, some solutions for memory access latency monitoring configure an independent timer for each memory access command to record the latency of the command, thus measuring the latency of a single memory access. While this method can obtain the latency corresponding to each memory access command relatively accurately, as the number of memory access commands increases, the number of timers required also increases accordingly, thus consuming significant hardware resources. This not only increases hardware costs but also increases the complexity and layout difficulty of hardware design. Summary of the Invention

[0003] This disclosure provides a method for determining memory access latency, a device for determining memory access latency, a system for determining memory access latency, an electronic device, a computer-readable storage medium, and a computer program product.

[0004] In a first aspect, embodiments of this disclosure propose a method for determining memory access latency, comprising: determining the start time of multiple memory access commands based on the same timer; for any one of the multiple memory access commands, in response to detecting that the memory access command has been executed, determining the latest value of a timer overflow flag corresponding to the memory access command, wherein the latest value of the timer overflow flag corresponding to the memory access command is used to indicate the number of times the timer reaches its maximum time value from the start time of the memory access command to the completion of execution; and determining the access latency duration corresponding to the memory access command based on the latest value of the timer overflow flag corresponding to the memory access command.

[0005] Secondly, embodiments of this disclosure provide a memory access latency determination apparatus, comprising: a first determination module, a second determination module, and a processing module. The first determination module is configured to determine the start time of multiple memory access commands based on a single timer; the second determination module is configured to, for any one of the multiple memory access commands, determine the latest value of a timer overflow flag corresponding to the memory access command in response to detecting the completion of the memory access command, wherein the latest value of the timer overflow flag corresponding to the memory access command is used to indicate the number of times the timer reaches its maximum time value from the start time of the memory access command until its completion; the processing module is configured to determine the access latency duration corresponding to the memory access command based on the latest value of the timer overflow flag corresponding to the memory access command.

[0006] Thirdly, embodiments of this disclosure provide a system for determining memory access latency, including: a memory controller and a latency measurement module. The memory controller is configured to schedule multiple memory access commands; the latency measurement module, including a timer, is configured to: determine the start time of the multiple memory access commands using the timer; for any one of the multiple memory access commands, in response to receiving an instruction from the memory controller indicating that the memory access command has been completed, determine the latest value of a timer overflow flag corresponding to the memory access command; and determine the access latency duration corresponding to the memory access command based on the latest value of the timer overflow flag corresponding to the memory access command; wherein the latest value of the timer overflow flag corresponding to the memory access command is used to indicate the number of times the timer reaches its maximum time value from the start time of the memory access command until its completion.

[0007] Fourthly, embodiments of this disclosure provide an electronic device, including: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform a memory access latency determination method as described in any implementation of the first aspect.

[0008] Fifthly, embodiments of this disclosure provide a non-transitory computer-readable storage medium storing computer instructions that, when executed by a processor, enable a method for determining memory access latency as described in any implementation of the first aspect.

[0009] In a sixth aspect, embodiments of this disclosure provide a computer program product including a computer program that, when executed by a processor, can implement the method for determining memory access latency described in any implementation of the first aspect.

[0010] According to the technical solution provided in this disclosure, the start time of each memory access command can be determined based on a timer shared by multiple memory access commands. Then, for any one of the multiple memory access commands, i.e., each memory access command, in response to detecting that each memory access command has been executed, the latest value of the timer overflow flag corresponding to each memory access command is determined to indicate the number of times the timer reaches its maximum time value from the start time of the memory access command to the completion of execution. Furthermore, the access delay duration corresponding to each memory access command can be determined based on the latest value of the timer overflow flag corresponding to each memory access command.

[0011] By setting multiple memory access commands to share the same timer and using a timer overflow flag to record the number of times the timer reaches its maximum value from the start to the completion of each memory access command, the access latency of each memory access command can be accurately determined based on the latest value of the timer overflow flag corresponding to each memory access command, using only a small amount of hardware resources. This effectively avoids the hardware overhead of configuring a separate timer for each command, reducing hardware resource consumption and thus lowering the complexity and layout difficulty of hardware design. This helps reduce hardware design costs, chip area, and improve hardware integration, while also supporting accurate measurement of the access latency of memory access commands whose execution time exceeds the timer's single range or timing cycle.

[0012] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0013] Other features, objects, and advantages of this disclosure will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings: Figure 1 A flowchart illustrating a method for determining memory access latency provided in an embodiment of this disclosure; Figure 2 A flowchart illustrating another method for determining memory access latency provided in an embodiment of this disclosure; Figure 3 A schematic diagram illustrating the distribution statistics of access latency provided in an embodiment of this disclosure; Figure 4 This embodiment of the present disclosure provides a schematic diagram for calculating the access latency of a single memory access command. Figure 1 ; Figure 5 This embodiment of the present disclosure provides a schematic diagram for calculating the access latency of a single memory access command. Figure 2 ; Figure 6 A structural block diagram of a memory access latency determination device provided in an embodiment of this disclosure; Figure 7 A structural block diagram of a system for determining memory access latency provided in an embodiment of this disclosure; Figure 8 A schematic diagram of the structure of a system for determining memory access latency provided in an embodiment of this disclosure; Figure 9 This is a schematic diagram of the structure of an electronic device suitable for performing a method for determining memory access latency, provided in an embodiment of this disclosure. Detailed Implementation

[0014] The exemplary embodiments of this disclosure are described below with reference to the accompanying drawings, including various details of the embodiments to aid understanding; these should be considered merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of this disclosure. Similarly, for clarity and brevity, descriptions of well-known functions and structures are omitted in the following description. It should be noted that, unless otherwise specified, the embodiments and features described in this disclosure can be combined with each other.

[0015] This disclosure relates to the field of integrated circuit technology, specifically to a method, apparatus, system, electronic device, computer storage medium, and program product for determining memory access latency, applicable to scenarios such as memory performance monitoring, bottleneck analysis, and system debugging in systems such as graphics card chips and video processing chips.

[0016] In graphics card chip systems, memory access latency is one of the key factors affecting its performance. Accurately monitoring memory access latency is of great significance for optimizing system performance, locating performance bottlenecks, and improving user experience.

[0017] Currently, some solutions for monitoring memory access latency configure a separate timer for each memory access command to record its latency, thus measuring the latency of a single memory access. While this method can accurately obtain the latency corresponding to each memory access command, the number of timers required increases with the number of memory access commands, consuming significant hardware resources. This not only increases hardware costs but also adds complexity and layout difficulty to the hardware design.

[0018] Other monitoring schemes employ a simple method of calculating the average memory access latency, which involves averaging all memory access latencies over a period of time without considering the distribution of latency data. This approach fails to provide a comprehensive understanding of the actual state of memory access latency and cannot accurately reflect its true characteristics. For example, it cannot determine the distribution ratio of latency across different latency intervals, making it difficult to identify potential performance bottlenecks in the system.

[0019] Some schemes for calculating the average memory access latency require storing the latency data corresponding to all memory access commands before calculating the average. This not only requires a large amount of storage resources to store this data, but also results in high computational complexity and hardware implementation difficulties when handling large amounts of data. This limits the clock frequency that the system can operate at, thus affecting the overall monitoring efficiency and real-time performance of the system.

[0020] Moreover, existing memory access latency monitoring solutions also have shortcomings in statistical accuracy, resulting in large errors in the statistical results of memory access latency, such as those obtained by simple averaging operations. These results cannot accurately reflect the true characteristics of memory access latency, thus leading to poor performance optimization measures based on statistical results.

[0021] Therefore, existing memory access latency monitoring solutions have significant shortcomings in terms of hardware resource consumption, statistical accuracy, computational complexity, and hardware implementation difficulty, and cannot meet the needs of graphics card systems for efficient and accurate monitoring of memory access latency.

[0022] The following description of several optional embodiments illustrates the technical solutions of this disclosure and the technical effects produced by these solutions. It should be noted that the following embodiments can be referenced, learned from, or combined with each other. Identical terms, similar features, and similar implementation steps in different embodiments will not be repeated.

[0023] Please refer to Figure 1 , Figure 1 A flowchart of a method for determining memory access latency provided in this disclosure embodiment, wherein process 100 includes the following steps: Step 101: Determine the start time of multiple memory access commands based on the same timer.

[0024] In this embodiment, the start time of multiple memory access commands can be determined based on a shared timer. Optionally, this timer can be a cyclic timer that increments from zero, automatically resets to zero and restarts after reaching a maximum count value, and possesses high-precision timing capabilities, providing a unified time base for all memory access commands. When any memory access command is initiated, the hardware logic does not allocate a separate timer for that memory access command. Instead, it directly reads the current count value or timing value of the shared timer and uses this current count value as the start timestamp, i.e., the start time, of the memory access command.

[0025] In some optional implementations of the embodiments of this disclosure, the start time of each of the above memory access commands can be stored and recorded for retrieval when needed, for example, by storing and recording through registers, accumulators, caches, etc., without specific limitations.

[0026] It should be noted that, in order to locate the corresponding start time when a memory access command completes execution, the start time can be associated with and stored along with the command's identifier, storage location, storage port number, or channel number, etc. Various storage methods can be used, such as register arrays or simple caches, to store the start time of each incomplete memory access command; no specific limitation is made here. In this way, regardless of the order in which subsequent commands return, their corresponding start times can be found using the memory access command's attribute information.

[0027] Step 102: For any one of the multiple memory access commands, in response to detecting that the memory access command has been executed, determine the latest value of the timer overflow flag corresponding to the memory access command.

[0028] In this embodiment of the disclosure, the latest value of the timing overflow flag corresponding to each of the plurality of memory access commands can be used to indicate the number of times the timer shared by the plurality of memory access commands reaches its maximum timing value from the start time of each memory access command to the completion of execution. The maximum timing value of the timer can be understood as the timer's single-shot range or timing cycle, the start time of each memory access command can be understood as the moment when the request to access data stored in memory is initiated through the command, and the completion of the corresponding memory access command can be understood as the successful acquisition of the required data from memory.

[0029] In this embodiment, in order to accurately measure the delay of commands that exceed the single range or timing cycle of the timer, a timing overflow flag can be set for each memory access command that has not yet been executed among multiple memory access commands. This flag is used to record the number of times the timer reaches its maximum timing value during the period from the start time of the command (i.e., the timer value recorded when the command is initiated) to the completion of the command execution. This optimizes the hardware overhead of the timer shared by the multiple memory access commands.

[0030] For example, when a memory access command is initiated, its corresponding timer overflow flag can be initialized to 0. Subsequently, whenever the timer reaches its maximum count, the value of the timer overflow flag corresponding to all incomplete memory access commands at that moment is automatically incremented by 1. When the memory access command completes, the current value of its corresponding timer overflow flag is read, representing the latest value of the timer overflow flag. This value is the total number of times the timer has reached its maximum count from the start to the completion of the memory access command, providing a key parameter for determining the access latency of each memory access command.

[0031] Step 103: Determine the access delay duration corresponding to the memory access command based on the latest value of the timer overflow flag corresponding to the memory access command.

[0032] In this embodiment of the disclosure, the access latency corresponding to the memory access command can be simply referred to as memory latency, which can refer to the delay phenomenon that occurs when waiting for the memory access data to be completed from the start of the request to access the data stored in memory, and the access latency duration corresponding to the memory access command can refer to the duration of the process of waiting for the memory access data to be completed from the start of the request to access the data stored in memory.

[0033] In this embodiment, since the value of the timing overflow flag corresponding to each memory access command is related to the entire execution process of the memory access command and to the single range or timing period of the timer, when the latest value of the timing overflow flag corresponding to each memory access command among multiple memory access commands sharing the same timer is known, the access delay duration corresponding to each memory access command can be accurately determined based on the latest value of the timing overflow flag.

[0034] According to the memory access latency determination method provided in this disclosure, by setting multiple memory access commands to share the same timer and using a timer overflow flag to record the number of times the timer reaches its maximum time value from the start to the completion of each memory access command, the access latency of each memory access command can be accurately determined based on the latest value of the timer overflow flag corresponding to each memory access command, using only a small amount of hardware resources. This effectively avoids the hardware overhead of configuring a separate timer for each command, reducing hardware resource usage and thus reducing hardware resource consumption. This reduces the complexity and layout difficulty of hardware design, thereby helping to reduce hardware design costs, chip area, and improve hardware integration. Simultaneously, it supports accurate measurement of the access latency of memory access commands whose execution time exceeds the single range or timing cycle of the timer.

[0035] Please refer to Figure 2 , Figure 2 A flowchart of another method for determining memory access latency provided in an embodiment of this disclosure, wherein process 200 includes the following steps: Step 201: Determine the start time of multiple memory access commands based on the same timer.

[0036] Step 202: For any one of the multiple memory access commands, in response to detecting that the memory access command has been executed, determine the latest value of the timer overflow flag corresponding to the memory access command.

[0037] Optionally, the latest value of the timing overflow flag corresponding to each memory access command among the multiple memory access commands that share a timer is used to indicate the number of times the timer reaches the maximum timing value from the start time of the memory access command until the execution is completed.

[0038] Step 203: Determine the access delay duration corresponding to the memory access command based on the latest value of the timer overflow flag corresponding to the memory access command.

[0039] Steps 201-203 above are the same as those mentioned above. Figure 1 The steps 101-103 shown are the same. For the same parts, please refer to the corresponding parts of the previous embodiment. They will not be repeated here.

[0040] Step 204: Based on the relationship between the access latency of each memory access command and the preset latency threshold, determine the preset latency interval to which the access latency of each memory access command belongs.

[0041] In this step, the delay range is divided into a plurality of consecutive different preset delay intervals by setting at least one preset delay threshold, which can improve the statistical accuracy for access delay duration. For example, three delay thresholds may be preset: Tlow, Tmid-low and Tmid-high, wherein Tlow is less than Tmid-low and Tmid-low is less than Tmid-high, so that four preset delay intervals are divided: a low delay interval (access delay duration < Tlow), a medium-low delay interval (Tlow ≤ access delay duration < Tmid-low), a medium-high delay interval (Tmid-low ≤ access delay duration < Tmid-high) and a high delay interval (access delay duration ≥ Tmid-high). The specific values of the preset delay thresholds can be configured according to actual application scenarios, which are not specifically limited in the embodiments of the present disclosure.

[0042] For each completed memory access command, after the access delay duration thereof is calculated, the access delay duration can be compared with the corresponding preset delay threshold, and the preset delay interval corresponding to or where the memory access command is located is determined according to the comparison result.

[0043] It should be noted that the specific values of the at least one preset delay threshold may be determined according to specific conditions, and are not specifically limited herein.

[0044] Step 205: counting the total number of memory access commands associated with each preset delay interval, and outputting a statistical value.

[0045] In this step, the number of memory access commands falling into the corresponding preset delay interval can be counted. For example, the total number of memory access commands associated with each preset delay interval may be initialized first. When it is determined that the access delay duration of a memory access command belongs to a certain preset delay interval, the count value of memory access commands corresponding to the preset delay interval is increased by 1. With the continuous execution of memory access commands, the count values corresponding to each preset delay interval are updated in real time, so as to determine the total number of memory access commands associated with the preset delay interval.

[0046] In this embodiment, the total number of memory access commands associated with each preset latency interval can be output as a statistical value for further statistical analysis. This can be achieved through one or more forms, such as data statistics tables, line graphs, and histograms. This allows for a visual representation of the distribution of memory access commands associated with different preset latency intervals, as well as the differences in the total number of memory access commands associated with each preset latency interval. For example, if the total number of memory access commands associated with the high latency interval is significantly high, it indicates a potential performance bottleneck in the system, requiring further optimization of the memory access strategy or investigation of hardware anomalies, thereby helping to improve the overall system performance.

[0047] According to the memory access latency determination method provided in this disclosure, by setting multiple memory access commands to share the same timer and using a timer overflow flag to record the number of times the timer reaches its maximum time value from the start to the completion of each memory access command, the access latency duration corresponding to each memory access command can be accurately determined based on the latest value of the timer overflow flag corresponding to each memory access command, using only a small amount of hardware resources. This supports precise measurement of the access latency duration of memory access commands whose execution time exceeds the single range or timing cycle of the timer. Simultaneously, latency distribution statistics are achieved by setting one or more preset latency thresholds to divide different intervals. Thus, while effectively avoiding the hardware overhead of configuring a separate timer for each command and optimizing hardware resource usage, the distribution of memory access latency in different latency intervals—that is, the statistical distribution of the number of memory access commands associated with each different latency interval—can be accurately presented, providing a more comprehensive characterization of memory access latency characteristics.

[0048] For a deeper understanding, please refer to Figure 3 This is a schematic diagram illustrating the distribution statistics of access latency provided in an embodiment of this disclosure, such as... Figure 3 As shown: In this embodiment, the preset delay interval to which the access delay duration corresponding to the memory access command belongs is determined according to the magnitude relationship between the access delay duration (which may be represented as D, for example) and a preset delay threshold. For example, 3 preset delay thresholds are set in advance, which are Tlow=11, Tmid-low=21 and Tmid-high=31 respectively, and the unit may be ms or the like by way of example. The delay range is divided into 4 preset delay intervals: if the access delay duration corresponding to a memory access command satisfies D<Tlow, it can be considered that the memory access command is associated with a low delay interval, that is, 0<D<11 (which may be represented as wr_latency_low, for example), and at this time, the total number of memory access commands associated with the low delay interval can be increased by 1; if the access delay duration corresponding to a memory access command satisfies Tlow≤D<Tmid-low, it can be considered that the memory access command is associated with a medium-low delay interval, that is, 11≤D<21 (which may be represented as wr_latency_mid_low, for example), and at this time, the total number of memory access commands associated with the medium-low delay interval can be increased by 1; if the access delay duration corresponding to a memory access command satisfies Tmid-low≤D<Tmid-high, it can be considered that the memory access command is associated with a medium-high delay interval, that is, 21≤D<31 (which may be represented as wr_latency_mid_high, for example), and at this time, the total number of memory access commands associated with the medium-high delay interval can be increased by 1; if the access delay duration corresponding to a memory access command satisfies D≥Tmid-high, it can be considered that the memory access command is associated with a high delay interval, that is, D≥31 (which may be represented as wr_latency_high, for example), and at this time, the total number of memory access commands associated with the high delay interval can be increased by 1.

[0049] In the embodiment of the present disclosure, for the access delay duration corresponding to each memory access command, the access delay duration is compared with the corresponding preset delay threshold. When the preset delay interval to which the access delay duration corresponding to each memory access command belongs is determined, it can be represented by a high-level signal, and then the statistics of the total number of memory access commands associated with each preset delay interval can be realized by counting the number of high-level signals. For example, as Figure 3As shown, the access latency durations belonging to the low latency range include 5, 8, 10, 10, and 6, meaning there are 5 high-level signals, and the total number of memory access commands associated with this low latency range is 5; the access latency durations belonging to the low-to-medium latency range include 20, 15, 11, and 15, meaning there are 4 high-level signals, and the total number of memory access commands associated with this low-to-medium latency range is 4; the access latency durations belonging to the high latency range include 24, 23, and 27, meaning there are 3 high-level signals, and the total number of memory access commands associated with this high latency range is 3; the access latency durations belonging to the high latency range include 55, 45, and 32, meaning there are 3 high-level signals, and the total number of memory access commands associated with this high latency range is 3.

[0050] In this embodiment, whenever the level signal corresponding to a preset delay interval is pulled high, the total number of memory access commands associated with that preset delay interval is updated; that is, the count value associated with the preset delay interval is automatically incremented by 1. After the statistics are completed, the total number of memory access commands associated with each preset delay interval is output. Thus, by statistically analyzing the data associated with different delay intervals, it is helpful to clearly understand the distribution ratio of the access latency duration corresponding to memory access commands within different delay ranges, thereby facilitating performance optimization.

[0051] In some optional implementations of the embodiments of this disclosure, in the above... Figure 1 and Figure 2 Based on the corresponding embodiments, step 103 or step 203 above can be executed as follows: in response to determining that the latest value of the timing overflow flag corresponding to the memory access command is greater than a preset value, the preset memory access delay duration is determined as the access delay duration corresponding to the memory access command.

[0052] In this embodiment, the timing overflow flag can be represented using a finite number of bits to record the number of times the timer reaches its maximum timing value from the start time of the memory access command to the end time. For example, when the timing overflow flag uses 2 bits, its value ranges from 0 to 3, meaning there are four scenarios: 0, 1, 2, and 3. For instance, if a memory access command arrives and the timer's current value is 50, then the start time for the memory access command is 50. At this point, the timer has not overflowed, and the value of the timing overflow flag corresponding to the memory access command is recorded as 0. The timer then continues counting. If the timer increments from 0 to the maximum timing value, at the moment the maximum timing value is reached, the value of the timing overflow flag is incremented by 1, i.e., updated to 1. The timer then starts a new round of counting from 0 until the memory access command returns data, indicating completion.

[0053] When the latest value of the timer overflow flag exceeds a preset value, it indicates that the system may have experienced a serious anomaly, such as deadlock, memory controller hang-up, or bus congestion. This causes the latency of memory access commands to exceed the normal range, resulting in multiple timer overflows. To avoid increasing the complexity and power consumption of the hardware logic, and to ensure the statistical efficiency of memory access latency, the access latency of the memory access command can no longer be precisely calculated. Instead, a preset memory access latency can be directly determined as the access latency corresponding to the memory access command. For example, the preset memory access latency can be a large value, such as greater than or equal to the product of the preset value and the maximum timing value of the timer, to accurately reflect or characterize the long latency.

[0054] In some optional implementations of the embodiments of this disclosure, the specific value of the above-mentioned preset value can be determined according to the specific situation, and is not specifically limited here. As an optional example, the preset value can be set to 1. When the latest value of the timer overflow flag corresponding to the memory access command is 2 or 3 after the memory access command is executed, that is, when it is greater than the preset value 1, the delay of the memory access command is determined to be abnormal. At this time, a preset memory access delay duration can be directly used as the access delay duration corresponding to the memory access command.

[0055] The above method simplifies the complexity of hardware operations. For abnormal memory access commands, there is no need to perform time-consuming calculations. The preset memory access latency is directly output, ensuring the real-time performance of the monitoring process and facilitating subsequent performance analysis.

[0056] In some optional implementations of the embodiments of this disclosure, in the above... Figure 1 and Figure 2 Based on the corresponding embodiments, step 103 or step 203 above can also be performed as follows: in response to determining that the latest value of the timer overflow flag is less than or equal to a preset value, the end time of the memory access command is determined based on the timer; based on the latest value of the timer overflow flag corresponding to the memory access command, the end time of the memory access command, and the start time of the memory access command, the access delay duration corresponding to the memory access command is determined.

[0057] In this embodiment, when a memory access command completes execution, such as returning the required data, the current count value of a timer shared by multiple memory access commands can be read and recorded as the end time of the memory access command. That is, the shared timer can accurately track the end time of each memory access command. Furthermore, if the latest value of the timer overflow flag is less than or equal to a preset value, indicating that the delay duration of the memory access command is within a normal and acceptable range and no abnormal delay has occurred, the access delay duration corresponding to each memory access command can be accurately determined based on the latest value of the timer overflow flag corresponding to the memory access command, the end time of the memory access command, and the start time of the memory access command. For a detailed explanation of the preset value, please refer to the preceding description; it will not be repeated here.

[0058] For example, the access latency corresponding to each memory access command can be represented as Latency, the start time can be represented as Ts, the end time can be represented as Te, and the timeout flag can be represented as Flag. Then, it can be calculated using the following formula (1):

[0059] It should be noted that when the latest value of the timer overflow flag is 0, it means that the timer has not overflowed during the period from the start to the completion of the memory access command, and a new round of timing has started after reaching the maximum time value. The difference between the end time and the start time of the memory access command can be directly used as the access delay time, that is, formula (1) can be simplified to .

[0060] For a deeper understanding, please refer to Figure 4 , Figure 4 This embodiment of the present disclosure provides a schematic diagram for calculating the access latency of a single memory access command. Figure 1 ,like Figure 4 As shown: In this embodiment, when the memory access command is a memory (Mem) (or storage) type access command, the characteristic of Mem type access commands is that the commands are initiated and returned out of order. That is, the execution order of the commands can be shuffled; commands that complete first return first, and commands initiated later may finish first. The initiated commands and returned results can be matched using command identifiers (IDs). For example, a read address ID (arid) can be generated when the command is initiated to uniquely identify each initiated memory access command. When the command completes and returns the corresponding result, it carries a read data ID (readID, rid). Here, arid and rid correspond one-to-one and are used to match the same memory access command.

[0061] For example, the preset value used for comparison with the latest value of the timer overflow flag can be set to 1. Since the timer does not reach its maximum count during the execution of all memory access commands, the latest value of the timer overflow flag for each command is 0, which is less than the preset value, meaning the timer has not overflowed. Therefore, the calculation process for the access delay duration of Mem class access commands is as follows: When a memory access command is initiated, the hardware logic synchronously obtains the current count value of the timer as the start time of the command. For example, a memory access command with AID of 0 is initiated when the timer count value is 4, and its start time is 4; a memory access command with AID of 2 is initiated when the timer count value is 12, and its start time is 12; a memory access command with AID of 3 is initiated when the timer count value is 13, and its start time is 13; a memory access command with AID of 4 is initiated when the timer count value is 5, and its start time is 5.

[0062] When a memory access command is detected to have completed execution, the hardware logic synchronously obtains the current count value of the timer as the end time of the command. For example, a memory access command with a timer count of 0 completes execution when the timer count is 21, and its end time is 21; a memory access command with a timer count of 2 completes execution when the timer count is 23, and its end time is 23; a memory access command with a timer count of 3 completes execution when the timer count is 18, and its end time is 18; a memory access command with a timer count of 4 completes execution when the timer count is 25, and its end time is 25.

[0063] The access latency of each memory access command is calculated using formula (1). Since the timer does not overflow during the execution of all commands, the latest value of the timer overflow flag corresponding to each command is 0. Therefore, the access latency of the memory access command with arid and rid of 0 is 21-4=17; the access latency of the memory access command with arid and rid of 2 is 23-12=11; the access latency of the memory access command with arid and rid of 3 is 18-13=5; and the access latency of the memory access command with arid and rid of 4 is 25-5=20. In this example, after the access latency of each Mem-type access command is calculated, the access latency of each memory access command can be indicated by pulling up the level signal corresponding to the access latency, such as... Figure 4 The effective delay durations shown, i.e., access delay durations 5, 17, 11, and 20, correspond to high-level signals.

[0064] For a deeper understanding, please refer to Figure 5 , Figure 5This embodiment of the present disclosure provides a schematic diagram for calculating the access latency of a single memory access command. Figure 2 ,like Figure 5 As shown: In this embodiment, when the memory access command is a First-In-First-Out (FIFO) type access command, the characteristic of FIFO type access commands is that commands are initiated and returned sequentially. That is, data written to the FIFO type access command first is read out first, and data written later is read out later. There is no situation of out-of-order execution or out-of-order return, and the initiated commands and returned results can be matched by read and write counts. For example, when initiating a FIFO type access command, a write count identifier (e.g., represented as put_cnt) is generated, which increments according to the writing order of the commands, such as... Figure 5 As shown, numbers 0 to 3 are used to uniquely identify each initiated FIFO-type access command; a read data identifier (e.g., get_cnt) is generated when data is read after command execution, incrementing in the order the commands are read, such as... Figure 5 As shown, from 0 to 3, get_cnt and put_cn correspond one-to-one and are used to match the same FIFO type access command.

[0065] In this example, the preset value used for comparison with the latest value of the timer overflow flag can be set to 1. Since the timer does not reach its maximum count during the execution of all memory access commands, the latest value of the timer overflow flag for each command is 0, which is less than the preset value, meaning the timer has not overflowed. Therefore, the calculation process for the access latency of FIFO-type access commands is as follows: When a memory access command is initiated, the hardware logic synchronously obtains the current count value of the timer as the start time of the command. For example, a memory access command with command identifier 0 is initiated when the timer count value is 4, and its start time is 4; a memory access command with command identifier 1 is initiated when the timer count value is 5, and its start time is 5; a memory access command with command identifier 2 is initiated when the timer count value is 12, and its start time is 12; a memory access command with command identifier 3 is initiated when the timer count value is 13, and its start time is 13.

[0066] When a memory access command with a specific command identifier is detected to have completed execution, the hardware logic synchronously obtains the current count value of the timer as the end time of the command. For example, a memory access command with a command identifier of 0 completes execution when the timer count value is 18, and its end time is 18; a memory access command with a command identifier of 1 completes execution when the timer count value is 19, and its end time is 19; a memory access command with a command identifier of 2 completes execution when the timer count value is 20, and its end time is 20; a memory access command with a command identifier of 3 completes execution when the timer count value is 21, and its end time is 21.

[0067] The access latency of the memory access command is calculated using formula (1). Since the timer does not overflow during the execution of all commands, the latest value of the timer overflow flag corresponding to each command is 0. Therefore, the access latency of the memory access command with command flag 0 is 18-4=14; the access latency of the memory access command with command flag 1 is 19-5=14; the access latency of the memory access command with command flag 2 is 20-12=8; and the access latency of the memory access command with command flag 3 is 21-13=8. In this example, after the access latency of each FIFO access command is calculated, the access latency of each memory access command can be indicated by pulling up the level signal corresponding to the access latency, such as... Figure 5 The effective delay durations shown, i.e., access delay durations 14, 14, 8 and 8, correspond to high-level signals.

[0068] By using the above method, a timer shared by multiple memory access commands can be used to accurately measure the latency of each memory access command, based on the start time, end time, and the latest value of the timer overflow flag when each memory access command is completed. This significantly reduces hardware resource consumption while also accurately measuring the latency of each memory access command.

[0069] In some optional implementations of the embodiments of this disclosure, the method for determining the memory access latency may further include the following: for any statistical period, in response to detecting the end of the statistical period, the number of all memory access commands executed within the statistical period is counted to obtain the total number of commands corresponding to the statistical period, and the access latency durations corresponding to all memory access commands executed within the statistical period are cumulatively summed to obtain the total latency duration corresponding to the statistical period.

[0070] In this embodiment, a statistical period can be pre-configured to segment the monitoring process of memory access latency commands over time, forming multiple intervals. This statistical period can be a fixed time window, such as 1 millisecond, 10 milliseconds, 100 milliseconds, or other durations set according to the application scenario. This allows for the periodic statistics of the number of memory access commands completed within each statistical period and their corresponding access latency, obtaining the total number of commands and total latency for each statistical period. This provides timely and reliable data support for optimizing and adjusting memory access strategies and facilitates comparative analysis of latency performance across different time periods. Whenever the timer for monitoring memory access latency commands reaches the preset duration of the statistical period, a periodic statistics end event is triggered, automatically initiating a new round of periodic statistics.

[0071] Optionally, step 102 or step 202 above can be performed as follows: In response to detecting that a memory access command has been executed within a preset statistical period, the latest value of the timing overflow flag corresponding to the memory access command is determined. Within each statistical period, when a memory access command is detected to have been executed, the latest value of the timing overflow flag corresponding to each completed memory access command can be determined, which can then be used to accurately determine the access latency duration corresponding to the memory access command. For the same part, please refer to the corresponding part of the above embodiment, which will not be repeated here.

[0072] It should be noted that the latency of each memory access command can be calculated and temporarily stored or cached in real time within the corresponding statistical period, or it can be output in a timely manner once the latency of each memory access command is determined, or the latency of all memory access commands executed within the statistical period can be processed or output uniformly. For example, at the end of each statistical period, the latency of each memory access command calculated within this period can be output in batches to ensure the real-time nature of monitoring and facilitate time-segmented management of access latency.

[0073] In some optional implementations of the embodiments of this disclosure, the method for determining memory latency may further include: for the latest ended target statistical period, determining the average latency based on the total number of commands corresponding to the target statistical period, the total latency duration corresponding to the target statistical period, the historical total number of commands, and the historical total latency duration.

[0074] In this embodiment of the disclosure, the total number of historical commands is the total number of all memory access commands executed within the historical statistical periods preceding the target statistical period, and the total historical latency is the sum of the access latency corresponding to all memory access commands executed within the historical statistical period. Optionally, the historical statistical periods preceding the target statistical period may refer to all completed statistical periods preceding the latest completed target statistical period, or may refer to a portion of completed statistical periods preceding the latest completed target statistical period selected or specified according to specific needs.

[0075] In this embodiment, the number of all memory access commands executed within each interval, i.e., each statistical period, and their corresponding access latency can be statistically analyzed in a timely manner. This can be understood as follows: for each recently ended target statistical period, such as the nth interval or statistical period (where n is an integer greater than or equal to 1), when the timer for that target statistical period ends, the total number of all memory access commands executed within that latest ended target statistical period is counted to obtain the total number of commands corresponding to that target statistical period, which can be denoted as N. n Then, the access latency of all memory access commands executed within the target statistical period is accumulated and summed to obtain the total latency for the target statistical period, which can be denoted as S. n .

[0076] Furthermore, the average latency can be accurately determined by combining the total number of commands and total latency corresponding to the target statistical period with historical total command counts and historical total latency, i.e., by combining historical statistical data corresponding to historical statistical periods prior to the latest ended target statistical period (e.g., from the 1st interval to the (n-1th interval). In this way, by obtaining memory access latency data corresponding to the latest statistical period and historical memory access latency data corresponding to historical statistical periods through step-by-step calculation, the calculation logic is simplified, enabling the hardware to operate at higher clock frequencies.

[0077] For example, taking the aforementioned historical statistical period as all statistical periods prior to the latest target statistical period, the aforementioned total historical command count is the total number of all memory access commands executed within that historical statistical period, which can be denoted as... ,in, Let represent the total number of commands corresponding to the i-th interval or statistical period, and let represent the total historical latency, which is the sum of the latency of each memory access command executed within the historical statistical period. This can be denoted as . ,in, This represents the total delay time corresponding to the i-th interval or statistical period.

[0078] Optionally, the aforementioned memory access commands may include all memory access commands executed within the latest completed target statistical period and historical statistical periods.

[0079] In some optional implementations of the embodiments of this disclosure, the process of determining the average delay time based on the total number of commands corresponding to the target statistical period, the total delay time corresponding to the target statistical period, the historical total number of commands, and the historical total delay time can be executed as follows: the total number of commands corresponding to the target statistical period and the total delay time corresponding to the target statistical period are weighted respectively to obtain the weighted number of commands and the weighted delay time; the average delay time is determined based on the sum of the weighted delay time and the historical total delay time, and the sum of the weighted number of commands and the historical total command time.

[0080] In this embodiment, during the process of obtaining the average latency, to highlight the impact of the number of memory access commands and their corresponding total latency within the most recently concluded statistical period (i.e., the target statistical period) on the average latency, a configurable weight, such as W, can be assigned to the latency data corresponding to the latest interval (i.e., the target statistical period). Optionally, this weight can be adapted to different application scenarios and needs. For example, when a faster reflection of current system performance changes is required, W can be set to a larger value; when a smoother historical average result is needed, W can be set to a smaller value. Specifically, the total number of commands and their corresponding total latency corresponding to the target statistical period are weighted to obtain a weighted number of commands, such as W×N. n And the weighted delay duration, which can be denoted as W×S n .

[0081] Furthermore, the average latency can be calculated based on the sum of the weighted latency and the historical total latency, and the sum of the weighted command count and the historical total command count. For example, it can be calculated using the following formula (2):

[0082] The above calculation method can quickly and accurately calculate the weighted average, which can effectively improve monitoring efficiency and real-time performance, and provide more timely and reliable data support for the dynamic adjustment of memory access strategies.

[0083] In this embodiment, the latency data of the latest interval is assigned configurable weights by weighted average calculation, and the required average latency is obtained by step-by-step calculation. This saves hardware resources, reduces the difficulty of hardware implementation, avoids the storage of large amounts of data, and only requires the storage of key statistical values. At the same time, step-by-step calculation simplifies the operation logic, enabling the hardware to operate at a higher clock frequency, improving monitoring efficiency, providing accurate average latency data faster, and enhancing the real-time performance of the system. This provides more timely and reliable data support for the system to dynamically adjust memory access strategies.

[0084] In some optional implementations of the embodiments of this disclosure, the method for determining the memory access latency may further include: storing the sum of the total number of commands corresponding to the target statistical period and the historical total number of commands as a new historical total number of commands; and storing the sum of the total latency duration corresponding to the target statistical period and the historical total latency duration as a new historical total latency duration.

[0085] In this embodiment, given the total number of commands and total latency corresponding to the latest completed statistical period (i.e., the target statistical period), to facilitate subsequent calculation of the average latency based on accurate historical data—that is, to ensure the accuracy of the average latency obtained through step-by-step calculation—it is necessary to periodically update the historical statistical data, namely the historical total number of commands and historical total latency, according to the aforementioned statistical period, and store the updated historical total number of commands and the new historical total latency. Thus, it is unnecessary to store the latency data corresponding to each historical command individually; only the historical total latency and historical total number of commands need to be stored. This avoids storing large amounts of data; only key statistical values ​​need to be stored, which reduces hardware implementation difficulty and saves storage resources. Specifically, the sum of the total number of commands corresponding to the latest completed target statistical period and the historical total number of commands can be stored as the new historical total number of commands, overwriting the original historical total number of commands. Similarly, the sum of the total latency corresponding to the latest completed target statistical period and the historical total latency can be stored as the new historical total latency, overwriting the original historical total latency.

[0086] It should be noted that, regardless of whether the data corresponding to the current statistical period has been weighted, the current total number of commands and the current total delay time are used when updating historical statistical data to ensure that the historical statistical data can accurately reflect the total number of all completed commands and the corresponding total delay, providing an accurate base for subsequent weighted calculations.

[0087] In some optional implementations of the embodiments of this disclosure, the method for determining the memory access latency may further include: storing the command identifier of the memory access command, the start time of the memory access command, and the value of the timing overflow identifier corresponding to the memory access command in a hardware lookup table.

[0088] In this embodiment, a hardware lookup table (LUT) can be set up to maintain information about all memory access commands that have not yet been completed. This information includes at least: the command identifier of the memory access command, such as the command identifier when the memory access command arrives, such as arid; the command identifier when the memory access command returns, such as rid; the delay start point corresponding to the memory access command, i.e., the start time; and the value of the timing overflow flag, etc.

[0089] When a new memory access command is initiated, its command identifier is obtained and the current count value of the timer is read as the start time of the memory access command. At the same time, the timer overflow flag corresponding to the memory access command is initialized to 0. Using the command identifier of the memory access command as an index, the start time and the current or latest value of the timer overflow flag are associated and written into the hardware lookup table.

[0090] For example, during the operation of the timer, whenever the timer reaches its maximum count value, all incomplete memory access commands in the hardware lookup table can be automatically traversed, and the value of the timer overflow flag in all incomplete memory access commands can be incremented by 1. This is to ensure that the lookup table stores the latest value of the timer overflow flag, reflecting the exact number of times the timer has reached its maximum count value from the start time of the memory access command to the current time.

[0091] In some optional implementations of the embodiments of this disclosure, in the above... Figure 1 and Figure 2 Based on the corresponding embodiments, the process of determining the latest value of the timing overflow flag corresponding to the memory access command in step 102 or step 202 above in response to detecting that the memory access command has been executed can be performed as follows: In response to detecting that the memory access command has been executed, a lookup table is performed based on the command flag of the memory access command to obtain the latest value of the timing overflow flag corresponding to the memory access command.

[0092] In this embodiment, for any one of multiple memory access commands, when the memory access command completes execution and returns data, a lookup table can be performed based on the command identifier of the memory access command to accurately and efficiently obtain the latest value of the timing overflow identifier corresponding to the memory access command. Then, based on the latest value of the timing overflow identifier, the access latency duration corresponding to each memory access command can be accurately determined. Specific methods can be found in the relevant descriptions in the above embodiments, and will not be repeated here. Optionally, the information corresponding to the memory access commands that have been executed and whose access latency durations have been determined can be released from the lookup table to free up storage space for subsequent new commands.

[0093] In large-scale memory access scenarios, by associating and storing the command identifier, start time, and timer overflow flag in a hardware lookup table, out-of-order return of memory access commands can be supported. Regardless of the order in which commands are completed, their corresponding start time and timer overflow flag can be quickly located through the command identifier. This also avoids configuring a separate hardware timer for each command, saving hardware resource consumption, helping to reduce hardware design costs, reduce chip area, improve hardware integration, and make the system more compact and efficient.

[0094] Further reference Figure 6 As an implementation of the methods shown in the above figures, this disclosure provides an embodiment of a memory access latency determination apparatus, which is similar to... Figure 1 The method for determining memory access latency shown corresponds to the embodiment illustrated.

[0095] like Figure 6 As shown, the memory access latency determination device 600 of this embodiment may include: a first determination module 601, a second determination module 602, and a processing module 603.

[0096] The first determining module 601 is configured to determine the start time of multiple memory access commands based on the same timer; the second determining module 602 is configured to, for any one of the multiple memory access commands, determine the latest value of the timer overflow flag corresponding to the memory access command in response to detecting that the memory access command has been executed, wherein the latest value of the timer overflow flag corresponding to the memory access command is used to indicate the number of times the timer has reached its maximum time value from the start time of the memory access command to the completion of execution; the processing module 603 is configured to determine the access delay duration corresponding to the memory access command based on the latest value of the timer overflow flag corresponding to the memory access command.

[0097] In some optional implementations of the embodiments of this disclosure, the specific processing of the first determining module 601, the second determining module 602, and the processing module 603, and the resulting technical effects, can be referred to respectively. Figure 1 The relevant descriptions of steps 101-103 in the corresponding embodiments will not be repeated here.

[0098] In some optional implementations of the embodiments of this disclosure, the processing module 603 is further configured to: in response to determining that the latest value of the timing overflow flag corresponding to the memory access command is greater than a preset value, determine the preset memory access delay duration as the access delay duration corresponding to the memory access command.

[0099] In some optional implementations of the embodiments of this disclosure, the first determining module 601 may be further configured to: determine the end time of the memory access command based on the timer in response to determining that the latest value of the timer overflow flag is less than or equal to a preset value; and the processing module 603 may be further configured to: determine the access delay duration corresponding to the memory access command based on the latest value of the timer overflow flag corresponding to the memory access command, the end time of the memory access command, and the start time of the memory access command.

[0100] In some optional implementations of the embodiments of this disclosure, the memory access latency determination device 600 may further include a storage module (not shown in the figure), which is configured to associate and store the command identifier of the memory access command, the start time of the memory access command, and the value of the timing overflow identifier corresponding to the memory access command in a hardware lookup table.

[0101] In some optional implementations of the embodiments of this disclosure, the second determining module 602 is further configured to: in response to detecting that a memory access command has been executed, search the hardware lookup table based on the command identifier of the memory access command to obtain the latest value of the timing overflow identifier corresponding to the memory access command.

[0102] In some optional implementations of the embodiments of this disclosure, the processing module 603 may further be configured to: determine the preset delay interval to which the access delay duration of each memory access command belongs based on the relationship between the access delay duration of each memory access command and the preset delay threshold; count the total number of memory access commands associated with each preset delay interval and output the statistical value.

[0103] In some optional implementations of the embodiments of this disclosure, the processing module 603 may be further configured to: for any statistical period, in response to detecting the end of the statistical period timer, count the number of all memory access commands executed within the statistical period to obtain the total number of commands corresponding to the statistical period, and sum the access latency times corresponding to all memory access commands executed within the statistical period to obtain the total latency time corresponding to the statistical period.

[0104] In some optional implementations of the embodiments of this disclosure, the processing module 603 may further be configured to: for the latest ended target statistical period, determine the average latency based on the total number of commands corresponding to the target statistical period, the total latency corresponding to the target statistical period, the historical total number of commands, and the historical total latency; wherein, the historical total number of commands is the total number of all memory access commands executed in the historical statistical periods before the target statistical period, and the historical total latency is the sum of the access latency corresponding to all memory access commands executed in the historical statistical periods.

[0105] In some optional implementations of the embodiments of this disclosure, the processing module 603 is further configured to: perform weighted processing on the total number of commands corresponding to the target statistical period and the total delay time corresponding to the target statistical period to obtain the weighted number of commands and the weighted delay time; and determine the average delay time based on the sum of the weighted delay time and the historical total delay time, and the sum of the weighted number of commands and the historical total number of commands.

[0106] In some optional implementations of the embodiments of this disclosure, the memory access latency determination device 600 may further include an update module (not shown in the figure), which is further configured to: store the sum of the total number of commands corresponding to the target statistical period and the historical total number of commands as the new historical total number of commands; and store the sum of the total latency duration corresponding to the target statistical period and the historical total latency duration as the new historical total latency duration.

[0107] This embodiment exists as a device 600 embodiment corresponding to the above method embodiment. The key steps or equivalent technical means that can be implemented by each component of the memory access latency determination device 600 embodiment provided in this embodiment, as well as the technical effects brought about by this device embodiment, can be referred to the relevant descriptions in the above method embodiments, and will not be repeated here.

[0108] Further reference Figure 7 and Figure 8 As an implementation of the methods shown in the above figures, this disclosure provides an embodiment of a system for determining memory access latency, which is similar to... Figure 1 The method embodiments shown correspond to those described.

[0109] like Figure 7 and Figure 8 As shown, the memory access latency determination system 700 of this embodiment may include a memory controller 701 and a latency measurement module 702.

[0110] The memory controller 701 is configured to schedule multiple memory access commands. The delay measurement module 702 includes a timer 7021 and is configured to: determine the start time of the multiple memory access commands using the timer 7021; for any one of the multiple memory access commands, in response to receiving an instruction from the memory controller 701 indicating that the memory access command has been executed, determine the latest value of the timing overflow flag corresponding to the memory access command; and determine the access delay duration corresponding to the memory access command based on the latest value of the timing overflow flag corresponding to the memory access command. The latest value of the timing overflow flag corresponding to the memory access command is used to indicate the number of times the timer 7021 reaches its maximum timing value from the start time of the memory access command until the execution is completed.

[0111] In the memory access latency determination system 700 of this disclosure embodiment: the specific processing of the memory controller 701 and the latency measurement module 702 and the resulting technical effects can be referred to respectively. Figure 1 The relevant descriptions of steps 101-103 in the corresponding embodiments will not be repeated here.

[0112] In some optional implementations of the embodiments of this disclosure, the delay measurement module 702 is further configured to: in response to determining that the latest value of the timing overflow flag corresponding to the memory access command is greater than a preset value, determine the preset memory access delay duration as the access delay duration corresponding to the memory access command.

[0113] In some optional implementations of the embodiments of this disclosure, the delay measurement module 702 further includes a delay arithmetic unit 7022, and the delay measurement module 702 is further configured to: in response to determining that the latest value of the timing overflow flag is less than or equal to a preset value, and receiving an instruction that the memory access command has been executed, determine the end time of the memory access command based on the timer 7021, and determine the access delay duration corresponding to the memory access command through the delay arithmetic unit 7022 based on the latest value of the timing overflow flag corresponding to the memory access command, the end time of the memory access command, and the start time of the memory access command.

[0114] Optionally, the aforementioned delay arithmetic unit 7022 may include a subtractor.

[0115] In some optional implementations of the embodiments of this disclosure, the delay measurement module 702 further includes a hardware lookup table 7023, and the delay measurement module 702 is further configured to: associate and store the command identifier of the memory access command, the start time of the memory access command, and the value of the timing overflow identifier corresponding to the memory access command in the hardware lookup table 7023.

[0116] In some optional implementations of the embodiments of this disclosure, the delay measurement module 702 is further configured to: in response to receiving an instruction that a memory access command has been executed, search in a hardware lookup table based on the command identifier of the memory access command to obtain the latest value of the timing overflow identifier corresponding to the memory access command.

[0117] For example, the scheduling of multiple memory access commands by the memory controller 701 can be understood as follows: when a memory access command is initiated, a start signal is sent to the delay measurement module 702 to trigger the reading of the current value of the timer 7021 as the start time of the command (e.g., ...). Figure 8 The Ts shown can also indicate the command identifier corresponding to the memory access command (e.g., Figure 8 The command identifier, such as id_i (0≤i≤n, where n is an integer greater than or equal to 1), address information, etc., can be written into the hardware lookup table 7023 via hardware logic, and the start time of the command is recorded simultaneously. When the memory access command is completed, an end signal is sent to the delay measurement module 702 to trigger the current value of the read timer 7021 as the end time of the command and the read timer overflow flag (e.g., ...). Figure 8 The latest value of the Flag shown. The latest values ​​of the command identifier, start time, and timer overflow flag for each memory access command are associated and stored in hardware lookup table 7023, such as... Figure 8 As shown.

[0118] In this embodiment, to obtain the specific delay of each command, a shared timer is used, abandoning the approach of configuring a dedicated timer for each command. A hardware lookup table is used to determine the delay start point or start timestamp corresponding to each memory access command. This significantly reduces hardware resource usage and consumption. With this embodiment, only a small amount of hardware resources are needed for timer timing and lookup logic to meet the monitoring requirements of numerous command delays, greatly reducing hardware resource consumption. This not only helps reduce hardware design costs but also reduces chip area, improves hardware integration, and makes the system more compact and efficient.

[0119] In some optional implementations of the embodiments of this disclosure, such as Figure 8As shown, the memory access latency determination system 700 further includes: a plurality of first counters 703 corresponding to a plurality of preset latency intervals; a comparator 704 corresponding to a preset latency threshold, wherein the comparator 704 is configured to: determine the preset latency interval to which the access latency of each memory access command belongs from the plurality of preset latency intervals based on the relationship between the access latency duration of each memory access command and the preset latency threshold; and the first counters 703 are configured to: count the total number of memory access commands associated with the preset latency interval corresponding to the first counter 703 and output the statistical value.

[0120] For example, the access delay duration corresponding to each memory access command output by the delay measurement module 702 is input to the comparator 704, which corresponds one-to-one with the preset delay threshold. When there are multiple preset delay thresholds, multiple comparators 704 are correspondingly set. The comparator 704 compares the real-time received access delay duration with its corresponding preset delay threshold. Upon determining the preset delay interval required for the access delay duration, it updates the total number of memory access commands associated with the preset delay interval through a first counter 703 associated with that preset delay interval. Thus, the output of each comparator 704 can be connected to a first counter 703 to count the number of commands falling into the corresponding delay interval. As commands are continuously executed, the values ​​of each counter are continuously updated, thereby reflecting the distribution of delays in different intervals in real time and improving statistical accuracy.

[0121] Optionally, the aforementioned preset delay intervals correspond one-to-one with the multiple first counters 703.

[0122] In this embodiment, a comparator is used to compare latency with a preset latency threshold to divide corresponding intervals, thereby achieving statistical analysis of the normal distribution of latency. This allows for a comprehensive understanding of memory access latency by monitoring data distribution. For example, when analyzing system performance bottlenecks, latency distribution statistics can accurately identify which intervals high-latency commands are concentrated in, enabling targeted optimization of memory access strategies. This approach effectively improves statistical accuracy while minimizing resource consumption. Furthermore, by statistically analyzing data within different latency intervals, the distribution ratio of latency across various ranges can be clearly understood, helping to identify potential performance bottlenecks and ultimately improving overall system performance.

[0123] In some optional implementations of the embodiments of this disclosure, such as Figure 8 As shown, the memory access latency determination system 700 may further include: a second counter 705 and an accumulator (not shown in the figure).

[0124] The second counter 705 is configured to: for any statistical period, in response to detecting the end of the statistical period, count the number of all memory access commands executed within the statistical period to obtain the total number of commands corresponding to the statistical period; the accumulator is configured to: in response to detecting the end of the statistical period, sum the access latency times corresponding to all memory access commands executed within the statistical period to obtain the total latency time corresponding to the statistical period.

[0125] In some optional implementations of the embodiments of this disclosure, such as Figure 8 As shown, the memory access latency determination system 700 may further include a register 706 configured to store the total number of historical commands and the total historical latency, wherein the total number of historical commands is the total number of all memory access commands executed within the historical statistical period prior to the latest target statistical period, and the total historical latency is the sum of the access latency corresponding to all memory access commands executed within the historical statistical period; wherein the sum of the weighted latency obtained by weighting the total latency corresponding to the target statistical period and the total historical latency, and the sum of the weighted command number obtained by weighting the total number of commands corresponding to the target statistical period and the total historical command number, are used to determine the average latency.

[0126] In some optional implementations of the embodiments of this disclosure, the register 706 is further configured to: store the sum of the total number of commands corresponding to the target statistical period and the historical total number of commands as the new historical total number of commands; and store the sum of the total delay duration corresponding to the target statistical period and the historical total delay duration as the new historical total delay duration.

[0127] For example, the access delay duration corresponding to each memory access command output by the delay measurement module 702 can also be input into the register 706 to calculate the current total delay duration corresponding to the latest statistical period, and to update and store the historical total delay duration.

[0128] For example, for each completed memory access command, the second counter 705 can be used to count the current total number of commands corresponding to the latest statistical period, and update the historical total number of commands.

[0129] In this embodiment, the weighted average is calculated by assigning configurable weights to the latency data of the latest interval to obtain the average latency over the entire time range. Furthermore, the hardware implementation complexity can be reduced through step-by-step calculation. Specifically, the total latency and total command count for the first n-1 intervals are calculated separately and stored in specific registers. When the data for the nth interval (the latest interval) arrives, the data for that nth interval is weighted, and the historical total latency and total command count are read from the registers. The average command latency is then calculated by software. This avoids storing large amounts of data, specifically the latency data of all commands, requiring only the storage of key statistical values, thus saving hardware resources. Simultaneously, the step-by-step calculation method simplifies hardware implementation, enabling the hardware to operate at higher clock frequencies. This not only improves monitoring efficiency and provides accurate average latency data more quickly, but also enhances system real-time performance, providing more timely and reliable data support for dynamically adjusting memory access strategies.

[0130] This embodiment exists as a system 700 embodiment corresponding to the above method embodiment. The key steps or equivalent technical means that can be implemented by each component in the memory access latency determination system 700 embodiment provided in this embodiment, as well as the technical effects brought about by the device embodiment, can be referred to the relevant descriptions in the above method embodiment, and will not be repeated here.

[0131] According to embodiments of the present disclosure, the present disclosure also provides an electronic device comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform a method for determining memory access latency as described in any implementation of the first aspect.

[0132] According to embodiments of this disclosure, this disclosure also provides a non-transitory computer-readable storage medium having computer instructions stored thereon, which, when executed by a processor, can implement the memory access latency determination method described in any of the above embodiments.

[0133] For example, the computer instructions corresponding to a method for determining memory access latency in this disclosure embodiment can be stored on storage media such as optical discs, hard disks, and USB flash drives. When the computer instructions corresponding to the method for determining memory access latency in the storage media are read or executed by a computer, the method for determining memory access latency as described in any of the above embodiments can be implemented.

[0134] According to embodiments of this disclosure, this disclosure also provides a computer program product including a computer program that, when executed by a processor, can implement the method for determining memory access latency described in any of the above embodiments.

[0135] Figure 9 A schematic block diagram of an example electronic device 900 that can be used to implement embodiments of the present disclosure is shown. The electronic device 900 according to embodiments of the present disclosure includes a processor 901 and a memory 902 storing an executable computer program. The processor 901, when executing the executable computer program stored in the memory 902, implements the memory access latency determination method provided in embodiments of the present disclosure.

[0136] In some optional implementations of the embodiments of this disclosure, the electronic device 900 may further include a communication interface 903 and a bus 904 for connecting the processor 901, the memory 902 and the communication interface 903.

[0137] In some optional implementations of the embodiments of this disclosure, bus 904 is used to connect communication interface 903, processor 901 and memory 902 to realize mutual communication between these devices.

[0138] In some optional implementations of the embodiments of this disclosure, the processor 901 may be at least one of the following: Application Specific Integrated Circuit (ASIC), Digital Signal Processor (DSP), Digital Signal Processing Device (DSPD), Programmable Logic Device (PLD), Field Programmable Gate Array (FPGA), Central Processing Unit (CPU), Controller, Microcontroller, and Microprocessor. It is understood that, for different devices, the electronic device used to implement the function of the processor 901 may also be other types, and the embodiments of this disclosure do not specifically limit it.

[0139] The aforementioned memory 902 is used to store executable computer programs and data. The executable computer program includes computer operation instructions. Memory 902 may include high-speed RAM and may also include non-volatile memory, such as at least two disk drives. In practical applications, the aforementioned memory 902 can be volatile memory, such as Random-Access Memory (RAM); or non-volatile memory, such as Read-Only Memory (ROM), flash memory, Hard Disk Drive (HDD), or Solid-State Drive (SSD); or a combination of the above types of memory, and provides executable computer programs and data to the processor.

[0140] Furthermore, the functional modules in this embodiment can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional module.

[0141] If the integrated units described above are implemented as software functional modules and not sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this disclosure embodiment, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute all or part of the steps of the method of this disclosure embodiment. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0142] According to the technical solution of this disclosure, by setting multiple memory access commands to share the same timer and using a timer overflow flag to record the number of times the timer reaches its maximum time value from the start to the completion of each memory access command, the access latency of each memory access command can be accurately determined based on the latest value of the timer overflow flag corresponding to each memory access command, using only a small amount of hardware resources. This effectively avoids the hardware overhead of configuring a separate timer for each command, reducing hardware resource consumption and thus reducing hardware design complexity and layout difficulty, which helps to reduce hardware design costs, chip area, and improve hardware integration. Simultaneously, it supports accurate measurement of the access latency of memory access commands whose execution time exceeds the single range or timing cycle of the timer.

[0143] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this disclosure can be achieved, and this is not limited herein.

[0144] It should also be understood that expressions such as "comprising," "including," "having," "containing," and / or "comprising" are open-ended rather than closed-ended expressions in this disclosure, indicating the presence of the stated features, elements, and / or components, but not excluding the presence of one or more other features, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features, not just individual elements in the list. Additionally, when describing embodiments of this disclosure, the word "may" is used to mean "one or more embodiments of this disclosure." And the term "exemplary" is intended to refer to an example or illustration.

[0145] Unless otherwise specified, all terms used herein (including engineering and technical terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It should also be understood that, unless expressly stated in this disclosure, terms as defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or overly formalized meaning.

[0146] The specific embodiments described above do not constitute a limitation on the scope of protection of this disclosure. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A method for determining memory access latency, characterized in that, The determination method includes: The start time of multiple memory access commands is determined based on the same timer; the timer is a timer shared by multiple memory access commands. For any one of the plurality of memory access commands, in response to detecting that the memory access command has been executed, the latest value of the timer overflow flag corresponding to the memory access command is determined, wherein the latest value of the timer overflow flag corresponding to the memory access command is used to indicate the number of times the timer has reached its maximum time value from the start time of the memory access command to the completion of execution; Based on the latest value of the timer overflow flag corresponding to the memory access command, the access delay duration corresponding to the memory access command is determined.

2. The determination method according to claim 1, wherein, The step of determining the access latency duration corresponding to the memory access command based on the latest value of the timing overflow flag corresponding to the memory access command includes: In response to determining that the latest value of the timing overflow flag corresponding to the memory access command is greater than a preset value, the preset memory access delay duration is determined as the access delay duration corresponding to the memory access command.

3. The determination method according to claim 1, wherein, The step of determining the access latency duration corresponding to the memory access command based on the latest value of the timing overflow flag corresponding to the memory access command includes: In response to determining that the latest value of the timer overflow flag is less than or equal to a preset value, the end time of the memory access command is determined based on the timer; Based on the latest value of the timer overflow flag corresponding to the memory access command, the end time of the memory access command, and the start time of the memory access command, the access delay duration corresponding to the memory access command is determined.

4. The determination method according to claim 1, wherein, The determination method further includes: The command identifier of the memory access command, the start time of the memory access command, and the value of the timer overflow identifier corresponding to the memory access command are associated and stored in the hardware lookup table.

5. The determination method according to claim 4, wherein, The step of determining the latest value of the timer overflow flag corresponding to the memory access command in response to detecting that the memory access command has been executed includes: In response to detecting that the memory access command has been executed, a lookup is performed in the hardware lookup table based on the command identifier of the memory access command to obtain the latest value of the timer overflow identifier corresponding to the memory access command.

6. The determining method according to claim 1, wherein, The determination method further includes: Based on the relationship between the access latency duration of each memory access command and the preset latency threshold, the preset latency interval to which the access latency duration of each memory access command belongs is determined. The total number of memory access commands associated with each preset delay interval is counted, and the statistical value is output.

7. The determining method according to any one of claims 1 to 6, wherein, The determination method further includes: For any given statistical period, in response to detecting the end of the statistical period, the total number of commands corresponding to the statistical period is obtained by counting the number of all memory access commands executed within the statistical period, and the total latency of the access commands corresponding to all memory access commands executed within the statistical period is accumulated and summed to obtain the total latency of the statistical period.

8. The determination method according to claim 7, wherein, The determination method further includes: For the latest completed target statistical period, the average latency is determined based on the total number of commands corresponding to the target statistical period, the total latency corresponding to the target statistical period, the historical total number of commands, and the historical total latency. Wherein, the total number of historical commands is the total number of all memory access commands executed within the historical statistical period prior to the target statistical period, and the total historical latency is the sum of the access latency corresponding to all memory access commands executed within the historical statistical period.

9. The determining method according to claim 8, wherein, The step of determining the average latency based on the total number of commands corresponding to the target statistical period, the total latency corresponding to the target statistical period, and the historical total number of commands and historical total latency includes: The total number of commands and the total delay time corresponding to the target statistical period are weighted to obtain the weighted number of commands and the weighted delay time. The average latency is determined based on the sum of the weighted latency and the total historical latency, and the sum of the weighted command count and the total historical command count.

10. The determining method according to claim 8, wherein, The determination method further includes: The sum of the total number of commands corresponding to the target statistical period and the total number of historical commands is stored as the new total number of historical commands; and The sum of the total delay time corresponding to the target statistical period and the historical total delay time is stored as the new historical total delay time.

11. A device for determining memory access latency, characterized in that, include: The first determining module is configured to determine the start time of multiple memory access commands based on the same timer; The timer is a timer shared by multiple memory access commands; The second determining module is configured to, in response to detecting that the memory access command has been executed, determine the latest value of the timer overflow flag corresponding to the memory access command for any one of the plurality of memory access commands, wherein the latest value of the timer overflow flag corresponding to the memory access command is used to indicate the number of times the timer has reached its maximum time value from the start time of the memory access command to the completion of the execution. The processing module is configured to determine the access delay duration corresponding to the memory access command based on the latest value of the timer overflow flag corresponding to the memory access command.

12. A system for determining memory access latency, characterized in that, include: The memory controller is configured to schedule multiple memory access commands. The delay measurement module includes a timer and is configured to determine the start time of the plurality of memory access commands by means of the timer; For any one of the plurality of memory access commands, in response to receiving an instruction from the memory controller that the memory access command has been executed, the latest value of the timer overflow flag corresponding to the memory access command is determined; And based on the latest value of the timer overflow flag corresponding to the memory access command, determine the access delay duration corresponding to the memory access command; the timer is a timer shared by multiple memory access commands; The latest value of the timing overflow flag corresponding to the memory access command is used to indicate the number of times the timer reaches its maximum timing value from the start time of the memory access command until the execution is completed.

13. The determining system according to claim 12, wherein, The delay measurement module is also configured to: In response to determining that the latest value of the timing overflow flag corresponding to the memory access command is greater than a preset value, the preset memory access delay duration is determined as the access delay duration corresponding to the memory access command.

14. The determining system according to claim 12, wherein, The delay measurement module further includes a delay calculator, and the delay measurement module is also configured to: In response to determining that the latest value of the timer overflow flag is less than or equal to a preset value and receiving an instruction to complete the execution of the memory access command, the end time of the memory access command is determined based on the timer, and the access delay duration corresponding to the memory access command is determined by the delay arithmetic unit based on the latest value of the timer overflow flag corresponding to the memory access command, the end time of the memory access command, and the start time of the memory access command.

15. The determining system according to claim 12, wherein, The delay measurement module further includes a hardware lookup table, and the delay measurement module is also configured to: The command identifier of the memory access command, the start time of the memory access command, and the value of the timer overflow identifier corresponding to the memory access command are associated and stored in the hardware lookup table.

16. The determining system according to claim 15, wherein, The delay measurement module is also configured to: In response to receiving an instruction that the memory access command has been executed, the system searches the hardware lookup table based on the command identifier of the memory access command to obtain the latest value of the timer overflow identifier corresponding to the memory access command.

17. The determining system according to claim 12, wherein, The determining system further includes: Multiple first counters corresponding to multiple preset delay intervals; A comparator corresponding to a preset delay threshold, wherein the comparator is configured to: determine, based on the relationship between the access delay duration of each memory access command and the preset delay threshold, the preset delay interval to which the access delay duration of each memory access command belongs from the plurality of preset delay intervals; and The first counter is configured to: count the total number of memory access commands associated with the preset delay interval corresponding to the first counter, and output the statistical value.

18. The determining system according to any one of claims 12 to 17, wherein, The determining system further includes: The second counter is configured to: for any statistical period, in response to detecting the end of the statistical period, count the number of all memory access commands executed within the statistical period to obtain the total number of commands corresponding to the statistical period; The accumulator is configured to: in response to detecting the end of the statistical period timing, sum the access latency durations corresponding to all memory access commands executed within the statistical period to obtain the total latency duration corresponding to the statistical period.

19. The determining system according to claim 18, wherein, The determining system further includes: The register is configured to store the total number of historical commands and the total historical latency, wherein the total number of historical commands is the total number of all memory access commands executed within the historical statistical period before the latest target statistical period ends, and the total historical latency is the sum of the access latency corresponding to all memory access commands executed within the historical statistical period. The sum of the weighted delay time obtained by weighting the total delay time corresponding to the target statistical period and the historical total delay time, and the sum of the weighted number of commands obtained by weighting the total number of commands corresponding to the target statistical period and the historical total number of commands, are used to determine the average delay time.

20. The determining system according to claim 19, wherein, The register is also configured as follows: The sum of the total number of commands corresponding to the target statistical period and the total number of historical commands is stored as the new total number of historical commands; and The sum of the total delay time corresponding to the target statistical period and the historical total delay time is stored as the new historical total delay time.

21. An electronic device, characterized in that, include: At least one processor; as well as A memory communicatively connected to the at least one processor; wherein, The memory stores instructions executable by the at least one processor, which, when executed by the at least one processor, enables the at least one processor to perform the method for determining memory access latency as described in any one of claims 1-10.

22. A non-transitory computer-readable storage medium storing computer instructions, characterized in that, The computer instructions are used to cause the processor to execute the method for determining memory access latency as described in any one of claims 1-10.

23. A computer program product, characterized in that, Includes a computer program, which, when executed by a processor, implements the method for determining memory access latency according to any one of claims 1-10.

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