Data repair method and device, computer device, readable storage medium and program product

Abstract

The application relates to a data repair method and device, computer equipment, a readable storage medium and a program product. The method comprises the following steps: reading target data from a storage chip in response to a read request of a current transaction of a processor by a controller; recording a first address corresponding to the target data in the storage chip by the controller in the case that the target data has a correctable error; checking and repairing the target data corresponding to the first address by the controller to obtain corrected data, and returning the corrected data to the processor; and writing the corrected data into the storage chip by triggering a read-overwrite operation according to the first address corresponding to the target data in the storage chip by the controller. The method can improve the accuracy of data in the storage chip.

Description

Technical Field

[0001] This application relates to the field of computer storage technology, and in particular to a data repair method, apparatus, computer equipment, computer-readable storage medium, and computer program product. Background Technology

[0002] With the development of computer storage technology and the increasing demands for data reliability and real-time performance, error handling technology in memory systems has become a crucial element in ensuring stable system operation. Among these technologies, Error Correction Code (ECC) is widely used to detect and correct correctable ECC errors (CE) in memory chips such as Dynamic Random Access Memory (DRAM). However, traditional ECC mechanisms only perform corrections on the data read path and output the corrected data to the requesting party.

[0003] In traditional technology, accumulated soft errors are scanned and repaired by periodically performing read, modify, and write operations on the entire memory chip.

[0004] However, current methods have the problem that CE errors may accumulate into uncorrectable ECC errors (UCE), causing inaccurate data in the memory chip. Summary of the Invention

[0005] Therefore, it is necessary to provide a data repair method, apparatus, computer equipment, computer-readable storage medium, and computer program product that can improve data accuracy in response to the above-mentioned technical problems.

[0006] Firstly, this application provides a data repair method, the method comprising:

[0007] The controller responds to the processor's current transaction read request to read the target data from the memory chip;

[0008] If it is determined that a correctable error has occurred in the target data, the controller records the first address corresponding to the target data in the memory chip.

[0009] The controller verifies and repairs the target data corresponding to the first address to obtain corrected data, and then returns the corrected data to the processor.

[0010] The controller triggers a read-modify-write operation based on the first address corresponding to the target data in the storage chip, and writes the corrected data into the storage chip.

[0011] In one embodiment, triggering a read-to-write operation based on the first address corresponding to the target data in the memory chip, and writing the corrected data into the memory chip, includes:

[0012] Read the target data from the storage chip according to the first address;

[0013] The target data corresponding to the first address is verified and repaired again through the controller to obtain the corrected data.

[0014] The corrected data is written into the storage chip.

[0015] In one embodiment, after the controller records the first address corresponding to the target data in the memory chip when a correctable error is determined to have occurred in the target data, the method further includes:

[0016] The controller updates the count of correctable errors recorded in the register.

[0017] The count value in the register corresponding to each controller is obtained through the interface module;

[0018] If the sum of all the count values ​​exceeds the global threshold, a global error count interrupt signal is generated through the interface module, and a first error log is recorded.

[0019] In one embodiment, the method further includes:

[0020] The interface module obtains the cumulative value of correctable errors occurring at the same first address; when the cumulative value exceeds a local threshold, the interface module generates a single address interrupt signal and records a second error log.

[0021] In one embodiment, before the controller triggers a read-to-write operation based on the first address corresponding to the target data in the memory chip and writes the corrected data into the memory chip, the method further includes:

[0022] If a read request for a subsequent transaction is obtained through the controller before the corrected data is returned to the processor, then after the corrected data is returned to the processor, the read request for the subsequent transaction continues to be executed until completion, wherein the subsequent transaction is the transaction following the current transaction.

[0023] In one embodiment, after writing the corrected data to the memory chip, the method further includes:

[0024] If, during the verification of the subsequent data, a correctable error is determined, the controller triggers a read-over-write operation based on the second address corresponding to the subsequent data in the storage chip; wherein, the subsequent data is read from the storage chip based on a read request of the subsequent transaction.

[0025] Secondly, this application also provides a data repair apparatus, the apparatus comprising:

[0026] The controller is configured to respond to a read request from the processor's current transaction, read target data from the memory chip; if a correctable error is determined to have occurred in the target data, record the first address corresponding to the target data in the memory chip; verify and repair the target data corresponding to the first address to obtain corrected data, and return the corrected data to the processor; trigger a read-over-write operation based on the first address corresponding to the target data in the memory chip, and write the corrected data into the memory chip.

[0027] Thirdly, this application also provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of the above-described method.

[0028] Fourthly, this application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the above-described method.

[0029] Fifthly, this application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the above-described method.

[0030] The aforementioned data repair method, apparatus, computer equipment, computer-readable storage medium, and computer program product first read the target data from the storage chip by responding to the processor's read request for the current transaction. If a correctable error is determined in the target data, the controller records the first address corresponding to the target data in the storage chip. Next, the controller verifies and repairs the target data corresponding to the first address, obtaining the corrected data, and returns the corrected data to the processor, thus completing the execution of the current transaction. Finally, the controller triggers a read-over-write operation based on the first address corresponding to the target data in the storage chip, writing the corrected data into the storage chip. This timely triggering repair mechanism, performing a read-over-write operation immediately after the current transaction is completed for repair, and storing the corrected data in the storage chip, effectively avoids the possibility of CE errors accumulating into UCE errors, thus improving the accuracy of the data stored in the storage chip. Attached Figure Description

[0031] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0032] Figure 1 This is a flowchart illustrating a data repair method in one embodiment;

[0033] Figure 2 This is a schematic diagram of a process in one embodiment where a read-modify-write operation is triggered based on the first address corresponding to the target data in the memory chip, and the corrected data is written into the memory chip.

[0034] Figure 3 This is a flowchart illustrating the global interrupt reporting process in one embodiment;

[0035] Figure 4 This is a schematic diagram illustrating the execution order of transactions in a multi-transaction pipeline scenario in one embodiment;

[0036] Figure 5 This is a block diagram of the logic chip in one embodiment;

[0037] Figure 6 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation

[0038] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0039] In one embodiment, such as Figure 1 As shown, a data repair method is provided. This embodiment illustrates the application of this method to a logic chip. It should be understood that the data repair method proposed in this application is applicable to any control chip or controller chip that includes error verification logic, has the ability to independently initiate storage access operations, and is located between the host and the storage medium, such as a memory controller chip or an SSD controller chip. In this embodiment, the logic chip includes a controller; the method includes the following steps S102 to S108. Wherein:

[0040] Step S102: The controller responds to the processor's current transaction read request and reads the target data from the storage chip.

[0041] The logic chip, also known as the buffer die, is the core of memory control. The storage chip is the chip that actually stores the data, such as DRAM. The controller can be a DRAM controller. A transaction consists of three phases: the first phase is sending a read or write command; the second phase is reading the target data from the storage chip and verifying it; the third phase is returning the target data or corrected data to the requester, such as a processor.

[0042] Optionally, a processor, such as a GPU or CPU, initiates a read request for the current transaction, with the read request carrying a first address; the logic chip responds to the processor's read request for the current transaction through the DRAM controller and reads the target data from the DRAM.

[0043] Step S104: If it is determined that a correctable error has occurred in the target data, the controller records the first address corresponding to the target data in the memory chip.

[0044] Optionally, the logic chip buffer die determines whether a correctable ECC error has occurred in the target data being read through the DRAM controller. This can be achieved by quickly determining the error type using a preset error status register. This error status register is a 2-bit register, storing values ​​such as: 00: no ECC error (data correct); 01: a correctable ECC error (CE); 10: an uncorrectable ECC error (UCE). The logic chip buffer die reads the value from the 2-bit error status register through the DRAM controller. If the value is 00, no error has occurred. If the register value is 01, a correctable error (CE) has occurred. If the register value is 10, an uncorrectable error (UCE) has occurred.

[0045] If a correctable error is detected in the target data, the controller records the first address of the target data in the DRAM memory chip.

[0046] If it is determined that no correctable errors have occurred in the target data, the target data is returned to the processor via the controller DRAM, and the read and write performance is unaffected.

[0047] Step S106: The controller verifies and repairs the target data corresponding to the first address to obtain the corrected data, and then returns the corrected data to the processor.

[0048] Optionally, the logic chip buffer die uses an error correction code mechanism via the DRAM controller to verify and repair the target data corresponding to the first address where a correctable error occurred, obtaining the corrected data. This corrected data is then returned to the requester, i.e., the processor, indicating that the current transaction is complete. It's important to note that the logic chip buffer die does not store the corrected data at this point, nor does it write the corrected data back to the source storage location in the memory chip, i.e., the location corresponding to the first address.

[0049] In step S108, the controller triggers a read-modify-write operation based on the first address corresponding to the target data in the storage chip, and writes the corrected data into the storage chip.

[0050] Optionally, after the current transaction is completed, the logic chip buffer die immediately triggers a read modify write operation through the DRAM controller according to the first address corresponding to the target data in the memory chip, thereby erasing the error bit in the DRAM and writing the corrected data to the first address corresponding to the memory chip.

[0051] In the aforementioned data repair method, firstly, the controller responds to the processor's read request for the current transaction and reads the target data from the memory chip. If a correctable error is determined in the target data, the controller records the first address corresponding to the target data in the memory chip. Secondly, the controller verifies and repairs the target data corresponding to the first address, obtaining the corrected data, and returns the corrected data to the processor, thus completing the execution of the current transaction. Finally, the controller triggers a read-over-write operation based on the first address corresponding to the target data in the memory chip, writing the corrected data into the memory chip. This timely triggering repair mechanism, performing a read-over-write operation immediately after the current transaction is completed for repair, and storing the corrected data in the memory chip, effectively avoids the possibility of CE errors accumulating into UCE errors, thus improving the accuracy of the data stored in the memory chip.

[0052] In one exemplary embodiment, such as Figure 2 As shown, a read-modify-write operation is triggered based on the first address corresponding to the target data in the memory chip, and the corrected data is written into the memory chip, including the following steps S202 to S206. Wherein:

[0053] Step S202: Read the target data in the memory chip according to the first address.

[0054] Optionally, the logic chip buffer die reads the target data in the DRAM according to the first address through the DRAM controller.

[0055] Step S204: The target data corresponding to the first address is verified and repaired again through the controller to obtain the corrected data.

[0056] Optionally, the logic chip buffer die again uses the ErrorCorrection Code mechanism of the DRAM controller to verify and repair the target data corresponding to the first address where the correctable error occurred, obtaining the corrected data. Since the corrected data obtained during step S106 is not stored in the logic chip buffer die, the verification and repair operation needs to be performed again. This is because the bit width of directly storing the corrected data is much larger than the address bit width, and storing the address saves more area than storing the corrected data.

[0057] Step S206: Write the corrected data into the storage chip.

[0058] Optionally, the logic chip buffer die writes the corrected data into the first address in DRAM through the DRAM controller, replacing the target data where the correctable error occurred.

[0059] In this embodiment, a smaller logic chip area is achieved by performing the verification action again.

[0060] In one exemplary embodiment, a global interrupt is reported, such as Figure 3 As shown, after determining that a correctable error has occurred in the target data and recording the first address corresponding to the target data in the memory chip via the controller, the method further includes steps S302 to S306. Wherein:

[0061] Step S302: Update the count of correctable errors recorded in the register through the controller.

[0062] The logic chip also includes an interface module; the interface module connects to at least two controllers. The interface module receives commands and distributes them to the respective DRAM controllers; the interface module can be an AXI interface. The DRAM controller translates the commands from the interface module into DRAM interface timing and verifies the data written and read. Registers are used to record the number of correctable errors.

[0063] Optionally, if it is determined that a correctable error has occurred in the target data, that is, the target data is faulty, the logic chip records the first address corresponding to the target data in the memory chip through the controller, and then updates the count value of the correctable error recorded in the register through the controller.

[0064] Optionally, if a correctable error is determined to have occurred in the target data, the controller records the first address corresponding to the target data in the memory chip and simultaneously updates the count value of the correctable error recorded in the register.

[0065] It should be noted that the count value is monotonically increasing and counted in an arithmetic sequence. For example, if no correctable error occurs, the initial count value is 0; if a correctable error occurs for the first time, the count value is increased by 1 based on the initial count value, and the count value is 1; if a correctable error occurs for the second time, the count value is increased by 1 based on the count value, and the count value is 2.

[0066] Step S304: Obtain the count value in the register corresponding to each controller through the interface module.

[0067] Optionally, the logic chip obtains the count value from the register corresponding to each controller through the interface module. For example, if the interface module connects to N controllers, the logic chip obtains the count values ​​from the registers corresponding to each of the N controllers through the interface module, that is, the interface module obtains N count values. Here, N is a positive integer greater than 2.

[0068] In step S306, if the sum of all count values ​​is greater than the global threshold, a global error count interrupt signal is generated through the interface module, and the first error log is recorded.

[0069] The global error count interrupt signal is used to indicate that the error rate of the entire logic chip is too high, which may be caused by environmental factors (temperature, voltage, electromagnetic interference) or the overall aging of DRAM chips.

[0070] Optionally, the logic chip uses the interface module to sum the count values, representing the accumulated error (CE) value returned by all DRAM controllers under the interface module. This accumulated CE value is compared with a global threshold. If the accumulated CE value is greater than the global threshold, the logic chip generates a global error counting interrupt signal through the interface module and records a first error log. The first error log records all addresses where correctable errors occurred and the corresponding number of times each address occurred. If the accumulated CE value is less than or equal to the global threshold, it indicates a normal operation.

[0071] In this embodiment, the overall error rate of the entire logic chip can be determined by comparing the cumulative error value of CE with the global threshold.

[0072] In an exemplary embodiment, the method further includes: obtaining the cumulative value of correctable errors occurring at the same first address through an interface module; and generating a single address interrupt signal through the interface module and recording a second error log when the cumulative value exceeds a local threshold.

[0073] The global threshold is much larger than the local threshold.

[0074] Optionally, the logic chip obtains the cumulative value of correctable errors occurring at the same first address through the interface module; for example, it is set that the number of correctable errors occurring at the same address cannot exceed 3. When the actual cumulative value exceeds a preset local threshold of 3, a single address interrupt signal is generated through the interface module, and a second error log is recorded. The second error log records the cumulative number of correctable errors occurring at the first address. The specific faulty cell in the DRAM can be directly located based on the first address.

[0075] In this embodiment, by comparing the actual cumulative value with a preset local threshold, the specific faulty unit in the DRAM can be located.

[0076] In an exemplary embodiment, before triggering a read-modify-write operation based on the first address corresponding to the target data in the storage chip by the controller and writing the corrected data into the storage chip, the method further includes: if the read request of the subsequent transaction is obtained by the controller before the corrected data is returned to the processor, then after the corrected data is returned to the processor, the read request of the subsequent transaction continues to be executed until completion.

[0077] In this context, a subsequent transaction is a transaction that follows the current transaction.

[0078] Optionally, if the logic chip obtains a read request for a subsequent transaction through the controller before the corrected data is returned to the processor—that is, before the current transaction is completed—then the logic chip continues to execute the read request for the subsequent transaction until it is completed, after the logic chip returns the corrected data to the processor through the controller, i.e., after the current transaction is completed. Figure 4 As shown, Transaction 1, Transaction 2, and Transaction 3 are three independent memory access requests, processed by BufferDie in chronological order. While the current transaction (Transaction 1) is still executing, and before Transaction 1 is completed, BufferDie obtains the command and address information of the next transaction (Transaction 2) in advance, so that Transaction 2 can be started immediately after Transaction 1 is completed, reducing idle time. Until the read request of Transaction 2 is completed, the logic chip executes an immediate scrub of the current transaction (Transaction 1) through the controller. That is, the logic chip triggers a read-write operation based on the first address corresponding to the target data in the memory chip, writing the corrected data corresponding to the current transaction into the memory chip.

[0079] In this embodiment, multiple transactions can be executed in a pipeline, and the Immediate Scrub operation is also inserted between normal transactions in the form of a transaction, reducing the waiting time for later transactions to be executed.

[0080] In an exemplary embodiment, after writing the corrected data into the storage chip, the method further includes: if a verification is performed on the subsequent data and it is determined that a correctable error has occurred in the subsequent data, a read-modify-write operation is triggered by the controller based on the second address corresponding to the subsequent data in the storage chip.

[0081] In this context, subsequent data is read from the storage chip based on read requests from subsequent transactions.

[0082] Optionally, after the corrected data is written to the storage chip, that is, after the immediate scrub of the current transaction is completed, if a subsequent transaction, such as transaction two, also has a verification error, that is, it is determined that a correctable error has occurred in the subsequent data, the repair action for the read-modify-write operation of the subsequent transaction (transaction two) is performed after the current transaction (transaction one) has been repaired.

[0083] Furthermore, the repair process for the subsequent transaction (Transaction Two) is as follows: The logic chip buffer die reads the subsequent data from the DRAM according to the second address through the DRAM controller. The logic chip buffer die again uses the error correction code mechanism through the DRAM controller to verify and repair the subsequent data corresponding to the second address where a correctable error occurred, obtaining the corrected data corresponding to the subsequent data. The corrected data corresponding to the subsequent data is written into the second address in the DRAM, replacing the subsequent data where a correctable error occurred. After both the current transaction (Transaction One) and the subsequent transaction (Transaction Two) have completed their repair actions, the logic chip buffer die continues to execute Transaction Three through the DRAM controller. If Transaction Three also has a verification error, then Transaction Three also needs to be repaired immediately.

[0084] In this embodiment, by performing immediate repair on correctable errors detected in subsequent transactions after the current transaction is repaired, accurate and orderly processing of continuous errors can be achieved in multi-transaction pipeline scenarios, avoiding error accumulation, while not affecting the prefetching and concurrent execution of normal transactions, thus balancing data reliability and system performance.

[0085] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0086] Based on the same inventive concept, this application also provides a data repair apparatus for implementing the data repair method described above. The solution provided by this data repair apparatus is similar to the implementation scheme described in the above method; therefore, the specific limitations in one or more data repair apparatus embodiments provided below can be found in the limitations of the data repair method described above, and will not be repeated here.

[0087] In one exemplary embodiment, such as Figure 5 As shown, a data repair device is provided, including: a controller 501, an interface module 502, and a register 503, wherein:

[0088] The controller 501 is used to respond to the read request of the current transaction of the processor, read the target data from the memory chip; if it is determined that the target data has a correctable error, record the first address corresponding to the target data in the memory chip; verify and repair the target data corresponding to the first address, obtain the corrected data, and return the corrected data to the processor; trigger a read-over-write operation according to the first address corresponding to the target data in the memory chip, and write the corrected data into the memory chip.

[0089] In an exemplary embodiment, the controller 501 is further configured to read target data in the storage chip according to the first address; verify and repair the target data corresponding to the first address again through the controller to obtain corrected data; and write the corrected data into the storage chip.

[0090] In one exemplary embodiment, the interface module 502 is connected to at least two controllers 501; the controllers 501 are also configured to update the count values ​​of correctable errors recorded in the registers.

[0091] Interface module 502 is used to obtain the count value in the register corresponding to each controller; if the sum of the count values ​​is greater than the global threshold, interface module 502 is also used to generate a global error count interrupt signal and record the first error log.

[0092] In an exemplary embodiment, the interface module 502 is configured to obtain the cumulative value of correctable errors occurring at the same first address; when the cumulative value is greater than a local threshold, the interface module 502 is further configured to generate a single address interrupt signal and record a second error log.

[0093] In an exemplary embodiment, if the controller obtains a read request for a subsequent transaction before the corrected data is returned to the processor, the controller 501 is further configured to continue executing the read request for the subsequent transaction until completion after the corrected data is returned to the processor, wherein the subsequent transaction is the transaction following the current transaction.

[0094] In an exemplary embodiment, the controller 501 is further configured to, if the subsequent data is verified and a correctable error is determined to have occurred in the subsequent data, trigger a read-over-write operation based on the second address corresponding to the subsequent data in the storage chip; wherein the subsequent data is read from the storage chip based on a read request of a subsequent transaction.

[0095] Each module in the aforementioned data repair device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in the processor of a computer device in hardware form or independent of it, or stored in the memory of the computer device in software form, so that the processor can call and execute the operations corresponding to each module.

[0096] In one exemplary embodiment, a computer device is provided, which may be a server, and its internal structure diagram may be as follows: Figure 6As shown, this computer device includes a processor, memory, input / output (I / O) interfaces, and a communication interface. The processor, memory, and I / O interfaces are connected via a system bus, and the communication interface is also connected to the system bus via the I / O interfaces. The processor provides computational and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system, computer programs, and a database. The internal memory provides the environment for the operating system and computer programs stored in the non-volatile storage media. The database stores target data and data to be repaired. The I / O interfaces are used for exchanging information between the processor and external devices. The communication interface is used for communicating with external terminals via a network connection. When the computer program is executed by the processor, it implements a data repair method.

[0097] Those skilled in the art will understand that Figure 6 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0098] In one embodiment, a computer device is also provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps in the above method embodiments.

[0099] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon that, when executed by a processor, implements the steps in the above method embodiments.

[0100] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps in the above method embodiments.

[0101] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, artificial intelligence (AI) processors, etc., and are not limited to these.

[0102] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0103] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A data repair method, characterized in that, The method includes: The controller responds to the processor's current transaction read request to read the target data from the memory chip; If it is determined that a correctable error has occurred in the target data, the controller records the first address corresponding to the target data in the memory chip. The controller verifies and repairs the target data corresponding to the first address to obtain corrected data, and then returns the corrected data to the processor. If a read request for a subsequent transaction is obtained through the controller before the corrected data is returned to the processor, then after the corrected data is returned to the processor, the read request for the subsequent transaction continues to be executed until completion, wherein the subsequent transaction is the transaction following the current transaction; The controller reads the target data in the storage chip according to the first address; the controller then immediately verifies and repairs the target data corresponding to the first address to obtain corrected data; and the corrected data is written into the storage chip.

2. The method according to claim 1, characterized in that, After the controller records the first address corresponding to the target data in the memory chip when a correctable error is determined to have occurred in the target data, the method further includes: The controller updates the count of correctable errors recorded in the register. The count value in the register corresponding to each controller is obtained through the interface module; If the sum of all the count values ​​exceeds the global threshold, a global error count interrupt signal is generated through the interface module, and a first error log is recorded.

3. The method according to claim 2, characterized in that, The method further includes: The interface module obtains the cumulative value of correctable errors occurring at the same first address; when the cumulative value exceeds a local threshold, the interface module generates a single address interrupt signal and records a second error log.

4. The method according to claim 1, characterized in that, After writing the corrected data into the memory chip, the method further includes: If a correctable error is determined during the verification of subsequent data, the controller triggers a read-over-write operation based on the second address corresponding to the subsequent data in the storage chip; wherein the subsequent data is read from the storage chip based on a read request of the subsequent transaction.

5. A data repair device, characterized in that, The device includes: A controller is configured to respond to a read request from the processor's current transaction, read target data from the memory chip; if a correctable error is determined in the target data, record a first address corresponding to the target data in the memory chip; verify and repair the target data corresponding to the first address to obtain corrected data, and return the corrected data to the processor; if a read request for a subsequent transaction is obtained through the controller before the corrected data is returned to the processor, then after returning the corrected data to the processor, the read request for the subsequent transaction continues to be executed until completion, wherein the subsequent transaction is the transaction following the current transaction; read the target data in the memory chip according to the first address; verify and repair the target data corresponding to the first address again through the controller to obtain corrected data; and write the corrected data into the memory chip.

6. The apparatus according to claim 5, characterized in that, The device further includes an interface module and a controller, which are also used to update the count values ​​of correctable errors recorded in the register; the interface module is used to obtain the count values ​​in the register corresponding to each controller; and when the sum of the count values ​​is greater than a global threshold, a global error count interrupt signal is generated and a first error log is recorded.

7. The apparatus according to claim 6, characterized in that, The interface module is also used to obtain the cumulative value of correctable errors occurring at the same first address; when the cumulative value is greater than a local threshold, a single address interrupt signal is generated and a second error log is recorded.

8. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 4.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 4.

10. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 4.

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