A verification system supporting response conversion function

Abstract

The present application relates to chip verification technical field, especially in supporting response conversion function's verification system, its behavior predictor captures false write response through the initiator protocol layer driver, and sends false write response to the score board, simultaneously, false write response is converted into write response request and is sent into interface layer through the receiver protocol layer driver;Interface layer converts write response request into actual write response, and sends to the score board;The score board compares the actual write response and the false write response, and the two are consistent, then the verification passes.It is clever to generate write response request by taking false write response as a prototype, which solves the problem that the traditional verification platform cannot simulate the generation of write response request by the receiver.Compared with the conventional verification, the write response request needs to be converted into response again before being compared and verified with the actual write response, the present application only needs to compare the false write response with the actual write response to realize functional verification, reducing the comparison channel of the verification platform.

Description

Technical Field

[0001] This invention relates to the field of chip verification technology, and in particular to a verification system that supports response conversion function. Background Technology

[0002] In the era of big data, the demand for computing power is exploding, and GPU chips can provide powerful computing capabilities. GPU chip interconnect technology enables data exchange and cross-chip computation between GPUs, thereby distributing heavy training and computing tasks across multiple GPUs. Simultaneously, multiple GPU chips can collaborate on training, achieving the synergy of computing power and storage. Therefore, GPU chip interconnect technology is a key technology for breaking through computing power boundaries and optimizing resource utilization. Currently, most GPU chip interconnects are board-level interconnects, which have longer transmission distances and longer transmission times compared to on-chip interconnects. Therefore, to improve the performance of board-level interconnect-based interconnect systems, write requests mostly use Posted write requests, meaning that the bus is released step-by-step as the request passes through the interconnect system without returning a response. However, for write requests that require a response, such as atomic operations, Posted write requests are generally not supported.

[0003] To achieve write request responses based on board-level interconnects, most traditional high-speed interfaces employ non-posted requests, meaning the bus continues to wait for a response until it returns to the initiating end. PCIe (Peripheral Component Interconnect Express) serves as an example. A similar function in PCIe is atomic operation, which involves initiating a special request. Upon reaching the peer device, the device processes the data and returns a response to the initiating end. During the request transmission, the bus cannot be used by other requests.

[0004] The above method has two main problems: First, using Non-Posted requests means the bus will continue to be used until the request is completed, significantly reducing bus utilization and performance. Second, it cannot support more specialized requests. Currently, PCIe only supports FetchADD, Swap, and CAS atomic operations; other requests are not supported, greatly reducing scalability. Therefore, a write response method that can improve bus utilization and offer good scalability is urgently needed. Summary of the Invention

[0005] To address the aforementioned technical problems, the present invention adopts the following technical solution: a verification system supporting write response request return, the system comprising: an initiating protocol layer driver, connected to the interface layer, for generating and randomly returning fake write responses to the interface layer when multiple write requests are received consecutively, wherein each fake write response carries a unique identifier of its write request; an initiating protocol layer monitor, connected to the data path between the initiating protocol layer driver and the interface layer, for monitoring the fake write responses and forwarding them; a behavior predictor, connected to the initiating protocol layer monitor, for receiving and forwarding the fake write responses; and simultaneously converting the fake write responses into write response requests and sending them; a sequence generator, connected to the behavior predictor, for receiving and forwarding the write response requests; and a receiving protocol layer driver, connected to both the sequence generator and the interface layer, for receiving and forwarding the write response requests to the interface layer to trigger the interface layer to generate and return actual write responses out of order based on the write response requests, wherein the actual write responses carry a unique identifier of the write request in their respective write response requests. An initiator monitor, connected to the data path between the initiator driver and the interface layer, and also connected to the behavior predictor, is used to monitor the actual write response and forward it to the behavior predictor. A scoring board, connected to the behavior predictor, is used to receive the actual write response and the fake write response forwarded by the behavior predictor, and compares the actual write response and the fake write response with the same unique identifier. If they match, the verification is successful.

[0006] The present invention has at least the following beneficial effects: The verification system provided in this invention enables the interface layer to predict and compare the conversion behavior of write responses. It cleverly solves the problem that traditional verification platforms cannot simulate the receiving end's ability to generate write response requests by using a fake write response as a prototype to generate the actual write response request. The write response request is then sent to the interface layer for processing to generate the actual write response. Verification is performed by comparing the actual write response and the fake write response, which share the same unique identifier, using a scoring board. Compared to conventional verification, which requires converting the write response request back into a response before comparing it with the actual write response, this invention only needs to compare the fake and actual write responses to achieve functional verification. Therefore, it can directly reuse the comparison channels from conventional transmission, reducing the number of comparison channels required by the verification platform. Attached Figure Description

[0007] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0008] Figure 1 This is a schematic diagram of the GPU interconnect system structure provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of a verification system supporting response conversion function provided in an embodiment of the present invention; Figure 3 A flowchart of the initiator interface layer behavior verification system provided in this embodiment of the invention; Figure 4 A flowchart of a receiver interface layer behavior verification system provided in an embodiment of the present invention. Detailed Implementation

[0009] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0010] Unless otherwise defined, all technical and scientific terms used in the embodiments of this invention have the same meaning as commonly understood by those skilled in the art.

[0011] Please see Figure 1 In a GPU interconnect system, when one chip initiates a request to another, the requesting chip acts as the data initiator, and the peer acts as the receiver. The interface layer of the interconnect system is a dedicated I / O subsystem within the GPU chip for high-speed board-level interconnection. It converts internal transactions into high-speed serial signals conforming to a preset GPU interconnect protocol and communicates with the remote GPU via PCB channels. The interface layer of the interconnect system supports bidirectional communication, including both initiator and receiver paths. For the local side, the initiator path sequentially includes: local interface layer - local protocol and physical layers - peer protocol and physical layers - peer interface layer. The receiver path sequentially includes: peer interface layer - peer protocol and physical layers - local protocol and physical layers - local interface layer. For the interface layer verification system, if the verification system can simulate the output behavior of the protocol layer, it is possible to verify the correctness of both the initiator and receiver logic using only one interface layer.

[0012] Please see Figure 2 The present invention illustrates a verification system that supports response conversion functionality, the system comprising: a behavior predictor, a sequence generator, a scoreboard, an initiator monitor, an initiator driver, an initiator protocol layer driver, an initiator protocol layer monitor, a receiver monitor, a receiver driver, a receiver protocol layer driver, and a receiver protocol layer monitor.

[0013] It should be noted that, Figure 2 The complete verification system is shown in the figure. Figure 2 The interface layer in the system is the target to be verified. The initiating and receiving ends share the same interface layer, or rather, the interface layer can serve as both the initiating and receiving interfaces. Therefore, when verifying the interface layer functionality, both the initiating and receiving ends use the same interface layer as the target to be verified. The driver and monitor are bound verification components. The monitor monitors the data path between the driver and the interface layer and packages the corresponding responses into data packets, which are then sent to the behavior predictor. The verification system provided by this invention can verify both the initiating and receiving ends simultaneously; therefore, it includes verification components for both the initiating and receiving ends. The verification component for the initiating end includes two sets of drivers and monitors, located on opposite sides of the interface layer: one set for the initiating end facing the on-chip interconnect network, and the other set for the initiating end protocol layer driver and monitor facing the protocol layer. Similarly, the verification component for the initiating end also includes two sets of drivers and monitors, located on opposite sides of the interface layer: one set for the receiving end facing the on-chip interconnect network, and the other set for the receiving end protocol layer driver and monitor facing the protocol layer.

[0014] It should be noted that since the verification components consist of four groups, to better distinguish between the initiator and receiver, they are named with "initiator" and "receiver" as prefixes. Furthermore, to differentiate between those oriented towards the protocol layer and those towards the on-chip interconnect network, the verification components oriented towards the protocol layer are prefixed. Therefore, the four components are: a group of initiator-oriented components facing the on-chip interconnect network {initiator driver, initiator monitor}; a group of initiator-oriented components facing the protocol layer {initiator protocol layer driver, initiator protocol layer monitor}; a group of receiver-oriented components facing the on-chip interconnect network {receiver driver, receiver monitor}; and a group of receiver-oriented components facing the protocol layer {receiver protocol layer driver, receiver protocol layer monitor}.

[0015] First, for the functional verification of the initiating interface layer, the main focus is on verifying whether the actual write response generated by the interface layer based on the write response request is correct. Please refer to [link / reference]. Figure 2 and Figure 3 During the verification process, the following components are required in the verification system: the initiator protocol layer driver, the initiator protocol layer monitor, the behavior predictor, the sequence generator, the receiver protocol layer driver, the initiator monitor, and the scoring board.

[0016] Furthermore, the initiating protocol layer driver is connected to the interface layer to continuously receive multiple write requests, generate and randomly return the fake write response to the interface layer, wherein each fake write response carries a unique identifier of its write request.

[0017] The interface layer is the target to be verified, used to receive and process the corresponding requests or responses.

[0018] The write request is sent from the protocol layer to the interface layer to request a write operation to be performed at the receiving end. It's important to note that multiple write requests can be sent consecutively. When the initiating protocol layer driver receives a write request, it generates a corresponding fake write response for each request. Each write request has its own unique identifier, which is directly inherited by the generated fake write response. To better simulate the out-of-order return behavior of actual write responses, the timing of the fake write response is configured to be random. This randomness includes both the randomness of the return order and the randomness of the return time interval. In other words, the return order will not follow the order in which the write requests were received; for example, a write request that was received first might have its fake write response returned fourth.

[0019] In one implementation, the initiating protocol layer driver and the interface layer are interconnected via an AXI bus. Other types of internal interconnection protocols and bus protocols capable of returning a response to release the bus in real time also fall within the scope of this invention.

[0020] It should be noted that in practical applications, the interface layer and protocol layer of the initiating end are interconnected through the AXI bus. After the protocol layer receives the write request sent by the interface layer and forwards the write request, the protocol layer will send a bus response to the interface layer to release the bus in accordance with the protocol requirements of the AXI bus.

[0021] In one implementation, the step of generating the fake write response includes: when the initiating protocol layer driver receives a write request, acquiring the bus response returned by the bus; using the bus response as the fake write response; wherein the bus response includes a unique identifier of the currently transmitted write request, the current transmission status, and data. The current transmission status includes an indicator indicating whether the transmission was successful. By utilizing the unique identifier of the write request in the bus response, a mapping relationship is established between the write request and the fake write response, solving the problem of misalignment between write requests and write responses.

[0022] It should be noted that when the initiating protocol layer driver receives a write request, it simulates bus behavior, causing it to generate and return a bus response to the interface layer after receiving the write request. The purpose is to simulate the behavior of the AXI protocol bus between the initiating interface layer and the initiating protocol layer, i.e., to simulate the logic of sending a Posted write request. The interface layer, according to its expected logic, will discard this bus response. Since this fake write response includes a unique identifier of the currently transmitted write request, the current transmission status, and the data, the unique identifier of the write request carried in the fake write response is mainly used to match the actual write response with the same unique identifier and to verify the functionality of the interface.

[0023] Furthermore, the initiator protocol layer monitor is connected to the data path between the initiator protocol layer driver and the interface layer. The initiator protocol layer monitor is used to monitor the spoofing response and forward the spoofing response.

[0024] It should be noted that the monitor is a passive observation component, which does not drive any signals, but only listens for responses on the corresponding data path and sends them to the behavior monitor.

[0025] Furthermore, the behavior predictor is connected to the initiating protocol layer monitor. The behavior predictor is used to receive and forward the fake write response; at the same time, it converts the fake write response into a write response request and sends it out.

[0026] It should be noted that a write response request is essentially a write request, not a write response, nor a new data packet. In this embodiment of the invention, this naming convention is used to distinguish between ordinary write requests and write requests derived from write responses.

[0027] Converting the dummy write response into a write response request means converting the write response format into a write request format to obtain the write response request. During this process, no data itself is processed. The dummy write response is essentially a bus response, occupying only one AXI write response channel. A write response request, however, requires one address channel and one data channel; the content of the dummy write response is converted into the data channel.

[0028] Specifically, the behavior predictor converts the spoofed write response into a write response request and sends it to the receiving protocol layer driver via a downstream sequence generator, simulating a write response request returning from the interconnect system to the initiator. Simultaneously, since this write response request is derived from the spoofed write response from the initiator's protocol layer driver, the behavior predictor sends the response to the corresponding queue on the scoring board for later comparison and verification.

[0029] Furthermore, the sequence generator is connected to the behavior predictor, and the sequence generator is used to receive and forward the write response request.

[0030] It's important to note that the sequence generator is responsible for receiving and forwarding write response requests without performing any other processing. Because the sequence generator contains not only sequences transformed from the current write response request but also sequences from other regular requests, it internally sorts and sends these sequences autonomously to avoid conflicts between different sequences that could disrupt the verification environment. Without a sequence generator, if the behavior predictor directly sends the sequence to the receiving protocol layer driver, resource contention would arise between the write response request and existing regular sequences, causing the receiving protocol layer driver to receive incorrect request signals.

[0031] In one implementation, the sequence generator is further configured to initiate a write request to the initiating driver. The system also includes an initiating driver connected to the interface layer, configured to initiate the write request to the interface layer. The interface layer translates the write request and sends it to the initiating protocol layer driver.

[0032] Furthermore, the receiving end protocol layer driver is connected to the sequence generator and the interface layer respectively. The receiving end protocol layer driver is used to receive and forward the write response request to the interface layer to trigger the interface layer to generate and return the actual write response out of order according to the write response request. The actual write response carries the unique identifier of the write request in its write response request.

[0033] The process involves using a fake write response as a prototype to generate a write response request. This request is then forwarded to the interface layer via a sequence generator and the receiver's protocol layer driver, prompting the interface layer to generate the actual write response. If the interface layer functions correctly, the generated actual write response should, as expected, be completely identical to the fake write response. If they are inconsistent, it indicates a problem with the interface layer's functionality, thus achieving the verification purpose.

[0034] It should be noted that the interface layer may receive multiple write response requests in succession. When generating the actual write response request, it will directly inherit the unique identifier of the write request in the write response request. When the interface layer returns the actual write response, it will return it in an out-of-order manner according to the actual situation of the interface layer.

[0035] Furthermore, the initiator monitor is connected to the data path between the initiator driver and the interface layer, and is also connected to the behavior predictor, for monitoring the actual write response and forwarding the actual write response to the behavior predictor.

[0036] Furthermore, the scoring board is connected to the behavior predictor and is used to receive the actual write response and fake write response forwarded by the behavior predictor. The actual write response and fake write response with the same unique identifier are compared. If they match, the verification is successful.

[0037] Specifically, when a write response request is converted into an actual write response by the initiator by the interface layer, the initiator monitor sends the actual write response of the initiator to the corresponding queue of the scoreboard through the behavior predictor for comparison, thereby verifying the correctness of the interface layer's functionality by comparing the fake write response with the actual write response.

[0038] In summary, the verification system provided by this invention enables the interface layer to predict and compare the conversion behavior of write responses, and further solves the problem that traditional verification platforms cannot simulate the generation of write response requests by the receiving end. This invention cleverly uses a fake write response as a prototype to generate a write response request, and then processes the write response request through the interface layer to generate the actual write response. Compared to conventional verification, which requires converting the write response request back into a response and then comparing it with the actual write response, this invention only needs to compare the fake write response with the actual write response to achieve functional verification. Therefore, the comparison channel in conventional transmission can be directly reused for comparison, reducing the number of comparison channels in the verification platform. It should be noted that, generally, a new comparison channel is established for different types of transmission to compare the actual value and the expected value. However, for the method provided by this invention, in conventional transmission, to verify whether the interface layer can correctly send the write response, it is necessary to compare whether the actual returned write response and the actual write response are consistent; that is, a comparison channel already exists to compare whether the two write responses are consistent. Since the write response request in this embodiment of the invention is converted from a fake write response, and the comparison is between the fake write response and the actual write response, the comparison channel can be directly reused, so there is no need to establish a new comparison channel for special comparison, thus reducing the number of comparison channels of the verification platform.

[0039] The above describes the functional verification of the initiating interface layer. The following describes the functional verification of the receiving interface layer. For the receiving end, the main verification is whether the write response request generated by the interface layer is correct.

[0040] Please see Figure 2 and Figure 4 For the functional verification of the receiver interface layer, the verification system needs to use the receiver driver, receiver monitor, initiator protocol layer driver, behavior predictor, sequence generator and scoring board.

[0041] Furthermore, the receiver driver, connected to the interface layer, is used to receive write requests from the interface layer and return a fake write response from the receiver to the interface layer.

[0042] It should be noted that, in order to simulate the behavior of the receiving end, the verification platform first sends a write request to the receiving end protocol layer driver through the sequence generator. The receiving end protocol layer driver then sends the write request to the interface layer. The interface layer, according to the logical requirements, sends a bus response, or a fake write response, to the receiving end protocol layer driver to complete the bus behavior. At the same time, the interface layer transforms the write request and sends it to the receiving end driver. After receiving the write request, the receiving end driver returns a fake write response to the interface layer.

[0043] In one embodiment, the receiver protocol layer driver is further configured to receive a write request sent by the sequence generator and send the write request to the interface layer. The interface layer is further configured to, upon receiving the write request, directly return a bus response as a spoof write response to the receiver protocol layer driver. The system further includes: a receiver protocol layer monitor, connected to the data path between the receiver protocol layer driver and the interface layer, configured to monitor the spoof write response and forward the spoof write response.

[0044] Furthermore, a receiver monitor, connected to the data path between the receiver driver and the interface layer, is used to monitor the receiver spoofing response and forward the receiver spoofing response to the behavior predictor.

[0045] Furthermore, the interface layer is also used to convert the receiver's spoof write response into an actual write response request and send it to the initiating protocol layer driver. To verify the functionality of the interface layer, it is necessary to perform the actual conversion through the interface layer to obtain the actual write response request, and then perform a comparison based on the actual write response request.

[0046] In one implementation, the initiating protocol layer driver is further configured to receive the actual write response request from the receiving end.

[0047] Furthermore, the initiating protocol layer monitor is also used to monitor the actual write response request of the receiving end and forward the actual write response request of the receiving end to the behavior predictor.

[0048] Furthermore, the behavior predictor is also used to convert the receiver's fake write response into a receiver's expected write response request, and to forward the receiver's actual write response request and the receiver's expected write response request to the scoring board, respectively.

[0049] Furthermore, the scoring board is also used to compare whether the actual write response request from the receiving end and the expected write response request from the receiving end are consistent. If they are consistent, the verification passes. That is, by verifying whether these two requests are consistent, the verification is completed to confirm whether the conversion behavior of the receiving end interface layer in converting the write response into a write request is correct.

[0050] In one implementation, the actual write response request from the receiving end includes a preset type identifier, which triggers the behavior predictor to capture the actual write response request from the receiving end through the initiating end protocol layer monitor. The mutual conversion and comparison of requests are implemented by the behavior predictor and the scoring board, and do not affect the sending and receiving of regular write requests between the interface layer and the driver layer, that is, they do not affect the transmission of regular write requests from the initiating end. Therefore, bidirectional verification can be performed simultaneously during the verification process, reducing verification time.

[0051] In summary, both the initiating and receiving interface layers can achieve bidirectional write response conversion verification by using a single interface layer as the target to be verified. This ensures that the write response conversion logic of both the initiating and receiving ends is verified simultaneously without mutual interference, significantly reducing verification time.

[0052] Embodiments of the present invention also provide a non-transitory computer-readable storage medium that can be disposed in an electronic device to store at least one instruction or at least one program related to implementing a method in the method embodiments, wherein the at least one instruction or the at least one program is loaded and executed by the processor to implement the method provided in the above embodiments.

[0053] Embodiments of the present invention also provide an electronic device, including a processor and the aforementioned non-transitory computer-readable storage medium.

[0054] Embodiments of the present invention also provide a computer program product including program code, which, when the program product is run on an electronic device, causes the electronic device to perform the steps of the methods described above in various exemplary embodiments of the present invention.

[0055] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is used as an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above.

[0056] While specific embodiments of the invention have been described in detail by way of example, those skilled in the art should understand that the examples are for illustrative purposes only and not intended to limit the scope of the invention. Those skilled in the art should also understand that various modifications can be made to the embodiments without departing from the scope and spirit of the invention. The scope of this invention is defined by the appended claims.

Claims

1. A verification system supporting response conversion function, characterized in that, The system includes: The initiating protocol layer driver, connected to the interface layer, is used to continuously receive multiple write requests, generate and randomly return fake write responses to the interface layer, wherein each fake write response carries a unique identifier of its write request; An initiating protocol layer monitor, connected to the data path between the initiating protocol layer driver and the interface layer, is used to monitor the spoofing response and forward the spoofing response; The behavior predictor, connected to the initiating protocol layer monitor, is used to receive and forward the fake write response to the scoreboard; at the same time, it converts the fake write response into a write response request and sends it out. A sequence generator, connected to the behavior predictor, is used to receive and forward the write response request to the receiving end protocol layer driver; The receiving end protocol layer driver is connected to the sequence generator and the interface layer respectively, and is used to receive and forward the write response request to the interface layer to trigger the interface layer to generate and return the actual write response out of order according to the write response request. The actual write response carries the unique identifier of the write request in its write response request. An initiator monitor is connected to the data path between the initiator driver and the interface layer, and is also connected to the behavior predictor. It is used to monitor the actual write response and forward the actual write response to the behavior predictor. The scoring board, connected to the behavior predictor, is used to receive the actual write response and fake write response forwarded by the behavior predictor, and compare the actual write response and fake write response with the same unique identifier. If they match, the verification is successful.

2. The system according to claim 1, characterized in that, The steps for generating the fake write response include: when the initiating protocol layer driver receives a write request, it obtains the bus response returned by the bus; and uses the bus response as the fake write response; wherein the bus response includes a unique identifier of the currently transmitted write request, the current transmission status, and data.

3. The system according to claim 1, characterized in that, The sequence generator is also used to initiate a write request to the initiating driver; The system also includes: The initiating driver, connected to the interface layer, is used to initiate write requests to the interface layer.

4. The system according to claim 3, characterized in that, The initiating protocol layer driver and the interface layer are interconnected via the AXI bus.

5. The system according to claim 1, characterized in that, The system also includes: A receiver driver, connected to the interface layer, is used to receive write requests from the interface layer and return a fake write response from the receiver to the interface layer. A receiver monitor, connected to the data path between the receiver driver and the interface layer, is used to monitor the receiver spoofing response and forward the receiver spoofing response to the behavior predictor. The interface layer is also used to convert the receiver's fake write response into an actual write response request and send it to the initiator's protocol layer driver. The initiating protocol layer monitor is also used to monitor the actual write response request of the receiving end and forward the actual write response request of the receiving end to the behavior predictor; The behavior predictor is also used to convert the receiver's fake write response into a receiver's expected write response request, and to forward the receiver's actual write response request and the receiver's expected write response request to the scoring board, respectively. The scoring board is also used to compare whether the actual write response request of the receiving end and the expected write response request of the receiving end are consistent. If they are consistent, the verification is successful.

6. The system according to claim 5, characterized in that, The receiving end protocol layer driver is also used to receive the write request sent by the sequence generator and send the write request to the interface layer; The interface layer is also used to return the bus response as a fake write response directly to the receiving end protocol layer driver when the write request is received. The system also includes: A receiver protocol layer monitor, connected to the data path between the receiver protocol layer driver and the interface layer, is used to monitor the spoofing response and forward the spoofing response.

7. The system according to claim 5, characterized in that, The actual write response request from the receiving end includes a preset type identifier, which is used to trigger the behavior predictor to capture the actual write response request from the receiving end through the initiating end protocol layer monitor.

8. The system according to claim 5, characterized in that, The initiating protocol layer driver is also used to receive the actual write response request from the receiving end.

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