Methods for data access, artificial intelligence chip, computing device, medium, and program product

Abstract

The application relates to a method, an artificial intelligence chip, a computing device, a medium and a program product for data access. The method comprises the following steps: configuring an address selection register at an interconnection interface module on a device side via a host, the address selection register being used for indicating a predetermined address mapping mode about an exception access; determining, via the interconnection interface module, whether an access initiated by a master in-module exists an exception access event; in response to determining that the access initiated by the master in-module exists the exception access event, mapping an original access address involved in the exception access event to a new access address of a slave in-module based on the predetermined address mapping mode; and providing response information about the access by the slave in-module to the master in-module. The application can flexibly configure a processing mode of the exception access, avoid system collapse caused by a burst of a large amount of exception information, and ensure working stability of a system cluster.

Description

Technical Field

[0001] The embodiments of the present invention generally relate to the field of artificial intelligence technology, and more specifically to a method for data access, an artificial intelligence chip, a computing device, a computer-readable storage medium, and a computer program product. Background Technology

[0002] In existing methods for data access, especially in computing clusters, fixed address identification and error handling procedures are typically used for abnormal access caused by user errors or other reasons. For example, abnormal logging of registers and interrupt reporting are used. In real-world scenarios, if a large number of abnormal messages are suddenly reported by different devices, the host will be unable to respond to the large number of abnormal messages reported by different devices, which will lead to a disconnection between the host and the artificial intelligence chip. Furthermore, it will lead to the loss of troubleshooting data.

[0003] In summary, the shortcomings of existing data access methods are that they are rigid in handling abnormal access, especially in computing cluster scenarios, where a sudden surge of abnormal information can easily lead to system crashes. Summary of the Invention

[0004] This invention provides a method for data access, an artificial intelligence chip, a computing device, a computer-readable storage medium, and a computer program product. This invention can flexibly configure the handling of abnormal access, avoid system crashes caused by a sudden surge of abnormal information, and ensure the working stability of the system cluster.

[0005] According to a first aspect of the present invention, a method for data access is provided. The method includes: configuring an address selection register at an interconnect interface module on a device side via a host, the address selection register indicating a predetermined address mapping method for abnormal access; determining, via the interconnect interface module, whether an abnormal access event exists in an access initiated by a master on-chip module; in response to determining that an abnormal access event exists in an access initiated by the master on-chip module, mapping the original access address involved in the abnormal access event to a new access address of a slave on-chip module based on the predetermined address mapping method; and providing response information regarding the access from the slave on-chip module to the master on-chip module.

[0006] According to a second aspect of the present invention, an artificial intelligence chip is provided, comprising: a main on-chip module configured to actively initiate access; an interconnect interface module configured with an address selection register; determining whether an abnormal access event exists in the access initiated by the main on-chip module; and, in response to determining that an abnormal access event exists in the access from the main on-chip module, mapping the original access address involved in the abnormal access event to a new access address of a slave on-chip module based on a predetermined address mapping method, wherein the address selection register is used to indicate the predetermined address mapping method for the abnormal access; and a slave on-chip module configured to provide response information regarding the access to the main on-chip module.

[0007] According to a third aspect of the present invention, a computing device is also provided. The computing device includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor to enable the computing device to perform the method of the first aspect of the present invention.

[0008] According to a fourth aspect of the present invention, a computer-readable storage medium is also provided. The computer-readable storage medium stores a computer program that, when executed by a machine, performs the method of the first aspect of the present invention.

[0009] According to a fifth aspect of the present invention, a computer program product is also provided, comprising a computer program that, when executed by a machine, performs the method of the first aspect of the present invention.

[0010] In some embodiments, the device is an artificial intelligence chip, and the method further includes: not generating a corresponding interrupt for an abnormal access event that maps the original access address to a new access address from an on-chip module.

[0011] In some embodiments, the predetermined address mapping method is associated with an exception type.

[0012] In some embodiments, the address of the address selection register indicates an exception type, and the information stored in the address of the address selection register indicates a new access address mapped to the exception type.

[0013] In some embodiments, different addresses in the address selection register correspond to different exception types.

[0014] In some embodiments, the master on-chip module is an on-chip module that actively initiates access. The access initiated by the master on-chip module is transmitted to the target on-chip module via the interconnect interface module. The slave on-chip module is the target on-chip module or a dedicated on-chip module for handling abnormal access.

[0015] In some embodiments, the master on-chip module is one or more of a computing core, a video encoder, or a video decoder, and the slave on-chip module is a memory or other on-chip module used to process access requests and generate responses.

[0016] In some embodiments, in response to determining that the on-chip module provides response information about the access to the main on-chip module indicating abnormal access, the corresponding error handling process of the main on-chip module is triggered.

[0017] In some embodiments, the slave on-chip module is a memory, and the slave on-chip module providing response information about the access to the master on-chip module includes: the slave on-chip module generating response information about the access based on the address of the address selection register and the operating mode of the memory, the response information indicating at least the exception type; the slave on-chip module providing the response information about the access to the master on-chip module; and the master on-chip module determining whether an abnormal access event exists and the type of abnormal access based on the response information.

[0018] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0019] The above and other features, advantages, and aspects of the various embodiments of the present invention will become more apparent from the accompanying drawings and the following detailed description. In the drawings, the same or similar reference numerals denote the same or similar elements.

[0020] Figure 1 The diagram illustrates a computing device for implementing a method for data access according to an embodiment of the present invention.

[0021] Figure 2 A flowchart of a method for data access according to some embodiments of the present invention is shown.

[0022] Figure 3 A flowchart illustrating a method for providing response information about an access from an on-chip module to a main on-chip module according to some embodiments of the present invention is shown.

[0023] Figure 4 A schematic diagram of an artificial intelligence chip according to some embodiments of the present invention is shown.

[0024] Figure 5 A schematic diagram illustrating the data access process in an artificial intelligence chip according to some embodiments of the present invention is shown.

[0025] In the various figures, the same or corresponding reference numerals indicate the same or corresponding parts. Detailed Implementation

[0026] Preferred embodiments of the invention will now be described in more detail with reference to the accompanying drawings. While preferred embodiments of the invention are shown in the drawings, it should be understood that the invention can be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that the invention will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

[0027] The term "comprising" and its variations as used herein signify open inclusion, i.e., "including but not limited to". Unless otherwise stated, the term "or" means "and / or". The term "based on" means "at least partially based on". The terms "one example embodiment" and "one embodiment" mean "at least one example embodiment". The term "another embodiment" means "at least one additional embodiment". The terms "first", "second", etc., may refer to different or the same objects.

[0028] As described above, the shortcomings of existing methods for data access are that they are rigid in handling abnormal access, especially in computing cluster scenarios, where a sudden surge of abnormal information can easily lead to system crashes.

[0029] To at least partially address one or more of the aforementioned problems and other potential issues, exemplary embodiments of the present invention propose a method for data access. In this method, an address selection register is configured at an interconnect interface module on the device side via a host. The address selection register indicates a predetermined address mapping method for abnormal access. The interconnect interface module determines whether an abnormal access event exists in an access initiated by a master on-chip module. In response to determining that an abnormal access event exists, the original access address involved in the abnormal access event is mapped to a new access address of a slave on-chip module based on the predetermined address mapping method. The slave on-chip module provides response information regarding the access to the master on-chip module. The present invention can utilize the address selection register to configure a predetermined address mapping method for abnormal access, flexibly configure the handling method for abnormal access, avoid system crashes caused by sudden large amounts of abnormal information, and thus ensure the operational stability of the system cluster.

[0030] Figure 1 A schematic diagram of a computing device 100 implementing a method for data access according to an embodiment of the present invention is shown. Figure 1As shown, the computing device 100 may have one or more processing units, including dedicated processing units such as graphics processing units (GPUs), field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), general-purpose computing on graphics processing units (GPGPUs), and general-purpose processing units such as CPUs. The computing device 100 also includes at least: an address selection register configuration unit 110, an abnormal access event determination unit 120, a new access address mapping unit 130, and a response information providing unit 140.

[0031] Regarding the address selection register configuration unit 110, it is used to configure the address selection register at the interconnect interface module on the device side via the host. The address selection register is used to indicate a predetermined address mapping method for abnormal access.

[0032] Regarding the abnormal access event determination unit 120, it is used to determine whether an abnormal access event exists in the access initiated by the module within the main chip via the interconnect interface module.

[0033] Regarding the new access address mapping unit 130, it is used to map the original access address involved in the abnormal access event to a new access address of the slave module based on a predetermined address mapping method in response to determining that an abnormal access event has occurred in the access initiated by the master on-chip module.

[0034] Regarding the response information providing unit 140, it is used to provide response information about the access from the on-chip module to the main on-chip module.

[0035] The following will combine Figure 2 A method 200 for data access, according to an embodiment of the present invention, is described. Figure 2 A flowchart of a method 200 for data access according to some embodiments of the present invention is shown. Method 200 may also include additional actions not shown and / or the actions shown may be omitted; the scope of the invention is not limited in this respect.

[0036] In step 202, the computing device 100 configures an address selection register at the interconnect interface module on the device side via the host. The address selection register is used to indicate a predetermined address mapping method for abnormal access.

[0037] Regarding the host, it includes, for example, a CPU, and the host is used to manage other devices. In some embodiments, the host is capable of managing other devices based on user configuration. In some embodiments, the host is used, for example, in a computing cluster to control / manage other devices in the computing cluster. These are devices for computing, storage, etc. In some embodiments, the host is capable of performing general-purpose computing.

[0038] Regarding the device, it is used, for example, for host-based management, to perform specific data access and data processing. In some embodiments, the device is an artificial intelligence chip, and the device includes at least: a main on-chip module, an interconnect interface module, and a slave on-chip module. It should be understood that "device side" refers to the device side or the device location.

[0039] The main chip modules and slave chip modules are described below and will not be repeated here.

[0040] Regarding the interconnect interface module, it is used, for example, for interconnection between master on-chip modules and slave on-chip modules. In some embodiments, the device side includes multiple master on-chip modules and multiple slave on-chip modules, and the interconnect interface module interconnects the multiple master on-chip modules and multiple slave on-chip modules to form an interconnect network. In some embodiments, the interconnect interface module performs, for example, protocol conversion and cloud transmission management. In some embodiments, the host can configure the interconnect interface module to manage the interconnection between master on-chip modules and slave on-chip modules. In some embodiments, the user configures the address selection register in the interconnect interface module via the host.

[0041] Regarding the address selection register, it is used, for example, to indicate a predetermined address mapping method for abnormal access. In some embodiments, the address selection register indicates how, for abnormal access, the original access address is mapped to a new access address from an on-chip module. Abnormal access indicates that an access has encountered an anomaly, specifically including an abnormal access event occurring in real time. Abnormal access events include, for example, the original access address not existing for the current access request, or lack of access permission.

[0042] In some embodiments, the predetermined address mapping method is associated with the exception type. For example, exception access of the same type is mapped to a new access address in the same on-chip module, and exception access of different types is mapped to new access addresses in different on-chip modules, specifically, to different on-chip modules or different access addresses in the same on-chip module.

[0043] In some embodiments, the address of the address selection register indicates the exception type, and the information stored at the address of the address selection register indicates the new access address mapped to the exception type. In some embodiments, different addresses of the address selection register correspond to different exception types. That is, exception access of the same type corresponds to the same address selection register, which stores the new access address mapped to that type of exception access. Different address selection registers are located at different addresses and store the new access addresses mapped to different types of exception access. It should be understood that the types of exception accesses can be mapped to different address selection registers based on predetermined rules.

[0044] In this way, users can configure the address selection register in the interconnect interface module via the host to map the original access address of abnormal access to a new access address from the on-chip module according to predetermined rules.

[0045] In step 204, the computing device 100 determines, via the interconnect interface module, whether there is an abnormal access event in the access initiated by the main chip module.

[0046] Regarding the master on-chip module, it is, for example, an on-chip module that actively initiates access. In some embodiments, the master on-chip module is, for example, one or more of a computing core, a video encoder, or a video decoder, which can, for example, actively initiate access requests to slave on-chip modules.

[0047] In some embodiments, the interconnect interface module can also determine whether an abnormal access event exists. Specifically, the interconnect interface module can determine whether an access initiated by a module within the main chip involves an abnormal access event. In this way, the interconnect interface module can first determine whether an abnormal access event exists and perform corresponding processing, such as whether to map the original access address via an address selection register.

[0048] In step 206, in response to determining that an abnormal access event has occurred in the access initiated by the main on-chip module, the computing device 100 maps the original access address involved in the abnormal access event to a new access address of the slave on-chip module based on a predetermined address mapping method.

[0049] Regarding the original access address involved in the abnormal access event, it may indicate, for example, the original access address of the access initiated by the module within the main chip.

[0050] Regarding the slave module, it is, for example, an on-chip module that processes and responds to access. In some embodiments, the slave module is memory or other on-chip modules used to process access requests and generate responses. Slave modules are, for example, caches, DDR (Double Data Rate SDRAM), etc. In some instances, access initiated by the master on-chip module is transmitted to the slave module via an interconnect interface module.

[0051] In some embodiments, the slave on-chip module is, for example, a target on-chip module. The target on-chip module is, for example, the on-chip module to which an access initiated by the master on-chip module is directed. The access initiated by the master on-chip module is transmitted to the target on-chip module via the interconnect interface module. It should be understood that the target on-chip module is not only an on-chip module that responds to the access, but also an on-chip module that stores response information for abnormal access events. The target on-chip module may also be able to perform other functions, such as calculations.

[0052] In some embodiments, the on-chip module is, for example, a dedicated on-chip module for handling abnormal access. Information stored at the corresponding address in the dedicated on-chip module includes, for example, information about a pre-defined handler for the abnormal access event. For instance, the information stored at the corresponding address in the dedicated on-chip module includes the exception type, the handler number, etc. For example, the dedicated on-chip module generates response information based on the exception type, the handler number, etc., and sends it to the main on-chip module so that the main on-chip module can perform appropriate processing based on the response information.

[0053] Regarding new access addresses from on-chip modules, these addresses may store information for generating response information about the access, such as exception type, handler number, etc. It should be understood that some exception types of abnormal access events may also be handled through interruption.

[0054] In other embodiments, the new access address is a predetermined valid address from an on-chip module. Different new access addresses may correspond to different exception types, for example.

[0055] Regarding the method of mapping the original access address to a new access address of the slave on-chip module, in some embodiments, in response to the interconnect interface module determining that an abnormal access event exists in the access initiated by the master on-chip module, the original access address is mapped to a new access address of the slave on-chip module via an address selection register using a predetermined address mapping method. In some embodiments, the address of the address selection register indicates the exception type, and the address selection register stores the mapped new access address. In other words, by determining the exception type of the abnormal access event to determine the corresponding address selection register, and reading the new access address stored in the address selection register, the mapping can be completed.

[0056] At step 208, the computing device 100 provides response information about the access from the slave on-chip module to the master on-chip module.

[0057] Regarding the response information, it is used, for example, to indicate whether abnormal access exists. In some embodiments, the response information is also used to provide information related to the abnormal access, such as the type of exception. In this way, the master on-chip module and the slave on-chip module complete the access initiation-response process even in the event of abnormal access, and the slave on-chip module also provides response information when responding to the access. Through the response information, it can be ensured that information about abnormal access can be returned to the master on-chip module. Based on this, the master on-chip module can determine the appropriate handling method according to the information about abnormal access, such as handling the exception or further reporting it to the host. In some embodiments, the response information, for example, indicates a specific abnormal access, which triggers the corresponding error handling process of the master on-chip module, such as interruption.

[0058] It should be understood that response information includes, for example, indications of an abnormal access event and details of the type of abnormal access. The following is a reference. Figure 3 The explanation will be provided separately and will not be repeated here.

[0059] It should be understood that in some embodiments, no corresponding interrupt is generated for abnormal access events that map the original access address to a new access address from an on-chip module. In this way, the above-mentioned abnormal access handling can replace the typical mechanism of generating an interrupt upon the occurrence of an abnormal access event. This ensures that even with a large number of abnormal access events, the system will not crash due to a large number of interrupts, which is beneficial for preserving troubleshooting data. Especially in scenarios where the processing scenario involves a computing cluster and the device side uses an artificial intelligence chip, it can guarantee the stability and normal operation of the computing cluster.

[0060] In traditional scenarios involving abnormal access events, the handling of such events is relatively rigid. Once an abnormal access event occurs, a corresponding interrupt is generated and reported to the host. Especially in computing cluster scenarios, a sudden surge of abnormal information can lead to system crashes. In contrast, the above-mentioned solution utilizes the address selection register to configure a predetermined address mapping method for abnormal access. Users can flexibly configure the handling method according to their needs, avoiding system crashes caused by a sudden surge of abnormal information. Specifically, firstly, by configuring the predetermined address mapping method for abnormal access in the address selection register, users can configure the handling method for abnormal access, improving flexibility. Furthermore, even if abnormal access occurs, the access initiation-response process is still completed, ensuring the overall stability of the system, without the typical interrupt generation and reporting to the host based on a large number of abnormal events, which could lead to host congestion or even crashes. Thirdly, the method of this application also provides response information, enabling the on-chip module on the device side to process the abnormal access according to its specific content. At least some abnormal accesses do not need to be reported to the host; they can be processed by the on-chip module on the device side, thereby improving the flexibility of abnormal handling and reducing the host's burden of handling abnormal accesses.

[0061] The following will combine Figure 3 This is a flowchart describing a method 300 of an embodiment of the present invention, in which a slave on-chip module provides response information about an access to a master on-chip module. The slave on-chip module is a memory.

[0062] In step 302, in computing device 100, response information about the access is generated from the on-chip module based on the address of the address selection register and the operating mode of the memory. The response information at least indicates the type of exception.

[0063] Regarding the address of the address selection register, in some embodiments, the address of the address selection register indicates the exception type.

[0064] In some embodiments, the on-chip module is, for example, memory. Regarding the memory's operating mode, it indicates, for example, the memory type, read / write mode, and memory address range. The memory type includes, for example, on-chip registers, Static Random Access Memory (SRAM), DDR, etc. The read / write mode includes, for example, read-write, read-only, write-only, etc.

[0065] The method of generating response information includes, for example, generating access response information from the on-chip module based on the address in the address selection register, the exception type it indicates, and the operating mode of the memory (e.g., memory in the on-chip module), so as to subsequently inform the main on-chip module. The main on-chip module determines whether an abnormal access exists and the corresponding handling method for the abnormal access based on the aforementioned response information. In some embodiments, the generated response information also includes the original access address involved in the abnormal access event. In this way, the main on-chip module can know which access request caused the current abnormal access event.

[0066] In step 304, in computing device 100, the slave on-chip module provides response information about the access to the master on-chip module.

[0067] Regarding the method of providing response information to the main chip module, in some embodiments, the response information is sent from the on-chip module to the interconnect interface module, and then sent to the main chip module via the interconnect interface module. In this way, even if abnormal access occurs, the process of initiating and responding to access, similar to normal access, is still completed.

[0068] In step 306, in the computing device 100, the main chip module determines whether an abnormal access event exists and the type of abnormal access based on the response information.

[0069] In some embodiments, the main chip module can determine whether there is an abnormal access event and the type of abnormal access based on the response information. Accordingly, the main chip module can determine the appropriate handling method, such as handling the abnormality or further reporting it to the host.

[0070] Figure 4 A schematic diagram of an artificial intelligence chip 400 according to some embodiments of the present invention is shown. The artificial intelligence chip 400 includes, for example, a general-purpose graphics processor (or "GPGPU"). Figure 4 As shown, the artificial intelligence chip 400 includes at least: a main on-chip module 410, an interconnect interface module 420, and a slave on-chip module 430.

[0071] In this case, the main chip module 410 is configured, for example, to actively initiate access. The main chip module 410 can also be referenced as described above, and will not be repeated here.

[0072] The interconnect interface module 420, for example, is configured with an address selection register 422. The interconnect interface module 420 is also configured to: determine whether an abnormal access event exists in the access initiated by the main on-chip module 410; and in response to determining that an abnormal access event exists from the main on-chip module 410, map the original access address involved in the abnormal access event to a new access address of the slave on-chip module based on a predetermined address mapping method, wherein the address selection register 422 is used to indicate the predetermined address mapping method for the abnormal access. Regarding the interconnect interface module 420, refer to the interconnect interface module described above, and it will not be repeated here.

[0073] The slave on-chip module 430 is configured, for example, to provide response information about the access to the master on-chip module 410. The slave on-chip module 430 is similar to the slave on-chip module described above, and will not be repeated here.

[0074] The following will combine Figure 5 A schematic diagram illustrating the data access process in an artificial intelligence chip according to an embodiment of the present invention.

[0075] refer to Figure 5 The AI ​​chip 500 includes a main on-chip module 510, an interconnect interface module 520, and a slave on-chip module 540. The AI ​​chip 500 also includes, for example, an on-chip interconnect module 530. The on-chip interconnect module 530 is used, for example, to further transmit access requests from the main on-chip module 510 transmitted by the interconnect interface module 520 to the slave on-chip module 540, and conversely, the on-chip interconnect module 530 transmits response information generated by the slave on-chip module 540 to the interconnect interface module 520, so as to further transmit it to the main on-chip module 510. In other words, the on-chip interconnect module 530 is used, for example, for interconnection between the interconnect interface module 520 and the slave on-chip module 540.

[0076] Furthermore, the host 600 can interact with the artificial intelligence chip 500. For example, the host 600 can configure the address selection register in the interconnect interface module 520 of the artificial intelligence chip 500 for a predetermined address mapping method regarding abnormal access.

[0077] In some embodiments, when the AI ​​chip 500 is running, the main on-chip module 510 initiates an access request to the interconnect interface module 520. The interconnect interface module 520 determines whether there is an abnormal access event in the initiated access to the original access address. If an abnormal access event is determined to exist, the original access address is mapped to a new access address through the address selection register 522 within the interconnect interface module 520. Thus, the interconnect interface module 520 forwards the access request for the original access address to the slave on-chip module 540 via the on-chip interconnect module 530 to access the new access address. The slave on-chip module 540 generates response information based on the access to the new access address. This response information is transmitted to the main on-chip module 510 via the on-chip interconnect module 530 and the interconnect interface module 520. The main on-chip module 510 receives the response information, thereby completing the processing of an abnormal access event in a data access operation.

[0078] This approach eliminates the need for additional interrupt design in the hardware, especially for AI chips, as it avoids the need for additional reporting or configuration wiring for the numerous on-chip modules, slave modules, and interconnect interface modules. Therefore, the above solution facilitates handling of abnormal accesses and reduces the hardware cost of AI chips.

[0079] The various processes and procedures described above, such as methods 200 and 300, can be executed at a computing device. This computing device may include, for example, at least one processor (at least one graphics processor and at least one central processing unit); and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor. In some embodiments, methods 200 and 300 may be implemented as a computer software program or program product tangibly contained in a machine-readable medium. In some embodiments, part or all of the computer program may be loaded and / or installed on the computing device via read-only memory (ROM) and / or a communication unit. When the computer program is loaded into random-access memory (RAM) and executed by the GPU and CPU, one or more actions of methods 200 and 300 described above can be performed.

[0080] This invention can be a method, an artificial intelligence chip, an apparatus, and / or a computer program product. A computer program product may include a computer-readable storage medium having computer-readable program instructions loaded thereon for performing various aspects of the invention. The computer-readable storage medium may be a tangible device capable of holding and storing instructions used by an instruction execution device. The computer-readable storage medium may be, for example, but not limited to, an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination thereof.

[0081] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to various computing / processing devices, or downloaded via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network, to an external computer or external storage device. Various aspects of the invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0082] These computer-readable program instructions can be provided to the central processing unit of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that, when executed by the central processing unit of the computer or other programmable data processing apparatus, they create means for implementing the functions / actions specified in one or more blocks of a flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium that causes a computer, programmable data processing apparatus, and / or other device to operate in a particular manner. Thus, the computer-readable medium storing the instructions comprises an article of manufacture that includes instructions for implementing aspects of the functions / actions specified in one or more blocks of a flowchart and / or block diagram.

[0083] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction, which contains one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0084] It should be understood that the various forms of processes shown above can be used to reorder, add, or delete steps. For example, the steps loaded in this application can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this application can be achieved, and this is not limited herein.

[0085] The specific embodiments described above do not constitute a limitation on the scope of protection of this application. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors.

Claims

1. A method for data access, characterized in that, include: An address selection register is configured at the interconnect interface module on the device side via the host. The address selection register is used to indicate a predetermined address mapping method for abnormal access. The device is an artificial intelligence chip. The address of the address selection register indicates the abnormal type. The information stored in the address of the address selection register indicates a new access address after mapping associated with the abnormal type. The interconnection interface module is used to determine whether there are any abnormal access events initiated by the modules within the main chip. In response to determining that an abnormal access event has occurred in the access initiated by the main chip module, the original access address involved in the abnormal access event is mapped to a new access address of the slave chip module based on the predetermined address mapping method. as well as The on-chip module provides response information about the access to the main on-chip module.

2. The method according to claim 1, characterized in that, The method further includes: For abnormal access events that map the original access address to a new access address from an on-chip module, no corresponding interrupt is generated.

3. The method according to claim 1, characterized in that, The predefined address mapping method is associated with the exception type.

4. The method according to claim 3, characterized in that, Different addresses in the address selection register correspond to different exception types.

5. The method according to claim 1, characterized in that, The main on-chip module is the on-chip module that actively initiates access. The access initiated by the main on-chip module is transmitted to the target on-chip module via the interconnect interface module. The slave on-chip module is the target on-chip module or a dedicated on-chip module for handling abnormal access.

6. The method according to claim 5, characterized in that, The main on-chip module is one or more of a computing core, a video encoder, or a video decoder, and the slave on-chip module is a memory or other on-chip modules used to process access requests and generate responses.

7. The method according to claim 1, characterized in that, Also includes: In response to determining that the on-chip module provides response information about the access to the main on-chip module indicating abnormal access, the corresponding error handling process of the main on-chip module is triggered.

8. The method according to claim 1, characterized in that, The slave on-chip module is a memory, and the response information provided by the slave on-chip module to the master on-chip module regarding the access includes: The on-chip module generates response information regarding the access based on the address of the address selection register and the memory's operating mode, and the response information at least indicates the exception type; The on-chip module provides response information about the access to the main on-chip module; The main module determines whether an abnormal access event exists and the type of abnormal access based on the response information.

9. An artificial intelligence chip, characterized in that, include: The main module is configured to initiate access proactively; The interconnect interface module is configured with an address selection register; The interconnect interface module determines whether there are any abnormal access events initiated by the modules within the main chip; In response to determining that an abnormal access event exists from the main on-chip module, the original access address involved in the abnormal access event is mapped to a new access address from the on-chip module based on a predetermined address mapping method. The address selection register is used to indicate the predetermined address mapping method for the abnormal access; wherein the address of the address selection register indicates the exception type, and the information stored in the address of the address selection register indicates the new access address after mapping associated with the exception type; and The on-chip module is configured to provide response information about the access to the main on-chip module.

10. A computing device, characterized in that, include: At least one processor; as well as A memory that is communicatively connected to the at least one processor; in The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-8.

11. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a machine, performs the method according to any one of claims 1-8.

12. A computer program product, characterized in that, Includes a computer program, which, when executed by a machine, performs the method according to any one of claims 1-8.

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