Cache space management method and storage device

Abstract

The application provides a cache space management method and a storage device. The method comprises the following steps: acquiring an index for adjusting the allocation of cache resources in a cache space, calculating a cache urgency factor of the cache space; determining a cache strategy of the cache space according to the cache urgency factor and preset first and second threshold values; in response to the cache strategy of the cache space being to adjust the cache capacity of the cache space, calculating a cache adjustment amount of the cache space according to the cache urgency factor; and adaptively adjusting the capacity allocation of a first cache area and a second cache area in the cache space according to the cache adjustment amount. The above method can optimize the utilization of cache resources and improve the overall performance of the storage device in random reading and other scenarios by monitoring the cache usage and access mode in real time and adaptively adjusting the allocation of cache resources.

Description

Technical Field

[0001] This application relates to the field of memory control, and in particular to a cache space management method and a storage device. Background Technology

[0002] In the NAND flash memory module (NAND Flash) storage system, logical address to physical address mapping (L2P) is one of the core mechanisms. It not only implements the basic address mapping function, but also solves problems such as the inability of NAND Flash to be overwritten, inconsistent erase and write units, and bad block management. However, L2P tables usually require a large amount of cache resources.

[0003] Memory cache resources are limited. Under the premise of ensuring stable system operation, the adjustable resources mainly include L2P cache and data cache. There is a trade-off between the two: a larger L2P cache results in faster address mapping, but may squeeze data cache space, especially in random access scenarios. If the data cache is insufficient, overall performance will significantly degrade. Therefore, dynamically balancing the cache resource usage of L2P cache and data cache in memory with a fixed cache size becomes a key issue in improving overall memory performance. Summary of the Invention

[0004] In view of this, this application provides a cache space management method and storage device to solve or partially solve the above problems.

[0005] In a first aspect, this application provides a cache space management method applied to a storage device, the storage device including a memory controller and a cache space, the cache space including a first cache area and a second cache area, wherein the first cache area is used to store a mapping table and the second cache area is used to store user data, the method comprising: acquiring an indicator for adaptively adjusting the cache resource allocation in the cache space, the indicator including a cache hit rate of the first cache area, an average cache miss penalty value of the first cache area, and a preset baseline miss penalty threshold; calculating a cache urgency factor of the cache space based on the cache hit rate, the average cache miss penalty value, and the baseline miss penalty threshold, the cache urgency factor being used to determine the caching strategy of the cache space; determining the caching strategy of the cache space based on the cache urgency factor and the preset first threshold and second threshold; in response to the caching strategy of the cache space being to adjust the cache capacity of the cache space, calculating a cache adjustment amount of the cache space based on the cache urgency factor; and adaptively adjusting the capacity allocation of the first cache area and the second cache area in the cache space based on the cache adjustment amount.

[0006] A second aspect of this application provides a storage device, comprising: a connection interface for electrically connecting to a host; a memory module including a plurality of planes, each plane including a plurality of blocks, each block including a plurality of physical pages; and a memory controller including error checking and correction circuitry, a buffer memory, and memory control circuitry, electrically connected to the connection interface and the memory module; and a cache space provided by one or more storage media, including the buffer memory, dynamic random access memory, and a host cache; wherein the memory control circuitry is configured to perform the cache space management method as described in the first aspect.

[0007] This application provides a cache space management method and storage device. By defining and calculating a cache urgency factor and using the expected performance loss of the mapping table cache as a decision input, it achieves adaptive and quantitative adjustment of the capacity of the first and second cache areas. Compared with fixed partitioning or schemes that rely solely on a single hit rate, this application can optimize cache space management in various scenarios such as random reads, sequential writes, and mixed loads, thereby improving cache hit rate, reducing the number of memory module accesses, lowering access latency and write amplification, and extending the lifespan of the storage device. Attached Figure Description

[0008] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments of this application will be briefly introduced below. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort, and these are all within the protection scope of this application.

[0009] Figure 1 This is a schematic diagram of a data storage system according to an embodiment of this application;

[0010] Figure 2 This is a schematic diagram of a memory controller according to an embodiment of this application;

[0011] Figure 3 This is a schematic diagram of a memory management module according to an embodiment of this application;

[0012] Figure 4 This is a schematic diagram of the cache space shown according to an embodiment of this application;

[0013] Figure 5 This is a flowchart illustrating a cache space management method according to an embodiment of this application;

[0014] Figure 6 This is a schematic diagram illustrating the cache space adjustment process according to an embodiment of this application;

[0015] Figure 7This is a schematic diagram of the cache space adjustment process shown in the embodiments of this application;

[0016] Figure 8 This is a flowchart illustrating the calculation and optimization of the cache urgency factor according to an embodiment of this application;

[0017] Figure 9 This is a schematic diagram illustrating the calculation of cache adjustment amount and update of cache capacity in an embodiment of this application. Detailed Implementation

[0018] The technical solution of this application will be clearly and completely described below with reference to the embodiments of this application. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0019] It should be particularly noted that similar substitutions and modifications made to this application are obvious to those skilled in the art, and they are all considered to be included in this application. Those skilled in the art can obviously make modifications or appropriate alterations and combinations to the methods and applications described herein without departing from the content, spirit, and scope of this application to implement and apply the technology of this application. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0020] Figure 1 This is a schematic diagram of a data storage system according to an embodiment of this application. Please refer to... Figure 1 The data storage system 10 includes a host 11 and a storage device 12. The storage device 12 can be connected to the host 11 and can be used to store data from the host 11. For example, the host 11 can be a smartphone, tablet computer, laptop computer, desktop computer, industrial computer, automotive infotainment system, advanced driver assistance system (ADAS), game console, server, or computer system set up in a specific carrier (such as a vehicle, aircraft, or ship), and the type of host 11 is not limited to these.

[0021] The host 11 includes a processor 111 and memory 112. The processor 111 is used to handle all or part of the operation of the host 11. For example, the processor 111 may include a central processing unit (CPU), a graphics processing unit (GPU), or other programmable general-purpose or special-purpose microprocessors, digital signal processors (DSPs), programmable controllers, application-specific integrated circuits (ASICs), programmable logic devices (PLDs), or other similar devices or combinations thereof.

[0022] Memory 112 is connected to processor 111 and used to cache data. For example, memory 112 may include random access memory (RAM) or a similar volatile storage device. It should be noted that memory 112 is located in host 11 (e.g., on the motherboard of host 11 or directly in processor 111), and not in storage device 12.

[0023] In one embodiment, the processor 111 may configure (e.g., partition) a cache area (also known as a host cache area) 1121 in the memory 112, and the storage device 12 may use the host cache area 1121 to write and read data in the memory module 122.

[0024] In addition, storage device 12 may include solid-state drives (SSDs), universal flash storage (UFS), embedded multi-media cards (eMMC), USB flash drives, memory cards, or other types of non-volatile storage devices. It is particularly suitable for industrial control, edge computing, and automotive electronics fields with stringent requirements for reliability, data integrity, environmental tolerance, and long-term stability.

[0025] In one embodiment, the storage device 12 includes a connection interface 121, a memory module 122, and a memory controller 123. The connection interface 121 is used to connect the storage device 12 to a host 11. For example, the connection interface 121 may support embedded multimedia cards, general-purpose flash memory, Peripheral Component Interconnect Express (PCI Express), Non-Volatile Memory Express (NVMexpress), Serial Advanced Technology Attachment (SATA), Universal Serial Bus (USB), or other types of connection interface standards. Therefore, the storage device 12 can communicate with the host 11 via the connection interface 121 (e.g., exchange signals, instructions, and / or data).

[0026] Memory module 122 is used to store data. For example, memory module 122 may include one or more rewritable non-volatile memory modules. Each rewritable non-volatile memory module may include one or more memory cell arrays. The memory cells in the memory cell array store data in the form of voltage (also known as threshold voltage). For example, memory module 122 may include single-level cell (SLC) NAND flash memory modules, multi-level cell (MLC) NAND flash memory modules, triple-level cell (TLC) NAND flash memory modules, quadruple-level cell (QLC) NAND flash memory modules, and / or other memory modules with the same or similar characteristics. For multi-level cell (MLC, TLC, QLC, and PLC) flash memory modules, specially selected and tested flash memory modules that meet the requirements of wide operating temperature (e.g., -40°C to 105°C or higher), high durability, and data retention can be used.

[0027] Memory controller 123 is connected to connection interface 121 and memory module 122. Memory controller 123 can be considered the control core of storage device 12 and used to control storage device 12. For example, memory controller 123 can be used to control or manage the overall or partial operation of storage device 12. For example, memory controller 123 may include a central processing unit (CPU), or other programmable general-purpose or special-purpose microprocessor, digital signal processor (DSP), programmable controller, application-specific integrated circuit (ASIC), programmable logic device (PLD), or other similar device or combination of these devices. In one embodiment, memory controller 123 may include a flash memory controller. In particular, for automotive functional safety requirements, the architecture of memory controller 123 may include safety islands, dual-core lockstep, or other redundancy and monitoring mechanisms to ensure the reliability of control logic.

[0028] The memory controller 123 can send instruction sequences to the memory module 122 to access the memory module 122. For example, the memory controller 123 can send a write instruction sequence to the memory module 122 to instruct the memory module 122 to store data in a specific memory cell. For example, the memory controller 123 can send a read instruction sequence to the memory module 122 to instruct the memory module 122 to read data from a specific memory cell. For example, the memory controller 123 can send an erase instruction sequence to the memory module 122 to instruct the memory module 122 to erase data stored in a specific memory cell. Furthermore, the memory controller 123 can also send other types of instruction sequences to the memory module 122 to instruct the memory module 122 to perform other types of operations, which are not limited in this application. The memory module 122 can receive instruction sequences from the memory controller 123 and access its internal memory cells according to these instruction sequences.

[0029] In one embodiment, the storage device 12 further includes a dynamic random access memory (DRAM) 124.

[0030] Figure 2 This is a schematic diagram of a memory controller according to an embodiment of this application. Please refer to... Figure 1 and Figure 2The memory controller 123 includes a host interface 21, a memory interface 22, and a memory control circuit 23. The host interface 21 is used to connect to the host 11 via the connection interface 121 for communication with the host 11. The memory interface 22 is used to connect to the memory module 122 for access to the memory module 122.

[0031] Memory control circuitry 23 is connected to host interface 21 and memory interface 22. Memory control circuitry 23 can be used to control or manage the overall or partial operation of memory controller 123. For example, memory control circuitry 23 can communicate with host 11 via host interface 21 and access memory module 122 via memory interface 22. For example, memory control circuitry 23 may include control circuitry such as embedded controllers or microcontrollers. In the following embodiments, the description of memory control circuitry 23 is equivalent to the description of memory controller 123.

[0032] In one embodiment, the memory controller 123 may further include a buffer memory 24. The buffer memory 24 is connected to the memory control circuitry 23 and controlled by the memory controller 123 to cache data. For example, the buffer memory 24 may be used to cache instructions from the host 11, data from the host 11, and / or data from the memory module 122. In particular, the logical-to-physical mapping table is typically resident or cached in the buffer memory 24 to support high-speed access and updates. To ensure the reliability and consistency of the mapping table data (described in detail below) in the event of sudden events such as abnormal power failures, the buffer memory 24 may employ a storage medium with power loss protection (PLP) or incorporate a backup capacitor design to ensure that critical metadata has sufficient time to be written into the memory module 122.

[0033] In one embodiment, the memory controller 123 may further include an error checking and correction circuit 25. The error checking and correction circuit 25 is connected to the memory control circuit 23 and is used to encode and decode data to ensure data integrity. For example, the error checking and correction circuit 25 may support various encoding / decoding algorithms such as Low Density Parity Check code (LDPC code), BCH code, Reed-solomon code (RS code), and Exclusive OR (XOR) code.

[0034] In one embodiment, the memory controller 123 may further include a power management circuit 26. The power management circuit 26 is connected to the memory control circuit 23 and is used to control the power supply of the storage device 12. The power management circuit 26 not only manages conventional power consumption, but also meets the complex power sequences and low static power consumption requirements of automotive electronics, and can handle voltage fluctuations during vehicle start-stop processes, ensuring that the storage device 12 operates stably in harsh power environments.

[0035] Figure 3 This is a schematic diagram illustrating a memory management module according to an embodiment of this application. Please refer to... Figures 1 to 3 The memory module 122 includes multiple physical units 301(0)-301(B). Each physical unit includes multiple storage cells for non-volatile data storage.

[0036] In one embodiment, an entity unit may include an entity programming unit. In one embodiment, an entity programming unit is also referred to as an entity programming unit. In one embodiment, an entity programming unit may be considered as an entity page.

[0037] In one embodiment, an entity programming unit may include multiple entity sectors. For example, the data capacity of an entity sector may be 512 bytes (B), and an entity programming unit may include 32 entity sectors. However, the data capacity of an entity sector and / or the total number of entity sectors included in an entity programming unit can be adjusted according to practical needs, and this application is not limited thereto. For example, the storage capacity of an entity programming unit may be 16 kilobytes, and this application is not limited thereto.

[0038] In one embodiment, a physical programming unit is the smallest unit of synchronously written data in memory module 122. For example, when performing a programming operation (also called a write operation) on a physical programming unit to write data to that physical programming unit, multiple memory cells in that physical programming unit can be synchronously programmed to store the corresponding data. For example, when programming a physical programming unit, a write voltage can be applied to that physical programming unit to change the threshold voltage of at least some of the memory cells in that physical programming unit. For example, the threshold voltage of a memory cell may reflect the bit data stored in that memory cell.

[0039] In one embodiment, an entity erasure unit may include multiple entity programmable units. In another embodiment, an entity erasure unit may be considered as an entity block.

[0040] In one embodiment, multiple programmed units in a physical erase unit can be erased simultaneously. For example, when performing an erase operation on a physical erase unit, an erase voltage can be applied to multiple programmed units in this physical erase unit to change the threshold voltage of at least some of the memory cells in these programmed units. By performing an erase operation on a physical erase unit, the data stored in this physical erase unit can be erased.

[0041] In one embodiment, the memory control circuit 23 can logically associate entity units 301(0)-301(A) and 301(A+1)-301(B) with the data area 31 and the idle area 32, respectively. Entity units 301(0)-301(A) in the data area 31 all store data (also referred to as user data) from the host 11. For example, any entity unit in the data area 31 can store valid data and / or invalid data. In addition, entity units 301(A+1)-301(B) in the idle area 32 do not store any data (e.g., valid data).

[0042] In one embodiment, if a physical unit does not store valid data, this physical unit can be associated with the free area 32. Furthermore, physical units in the free area 32 can be erased to clear the data within them. In one embodiment, physical units in the free area 32 are also referred to as idle physical units. In one embodiment, the free area 32 is also referred to as the free pool.

[0043] In one embodiment, in response to the requirements of predictable storage lifetime for industrial and automotive applications, the memory control circuit 23 can implement wear leveling and bad block management strategies, and monitor the number of erase / write cycles, read counts, and data retention time of each physical unit in real time, so as to provide the host 11 with a health status report and remaining lifetime prediction of the storage device 12, thereby meeting the diagnostic coverage requirements of relevant functional safety standards.

[0044] In one embodiment, when data needs to be stored (including new data in response to a write command from host 11 and the removal of old data during garbage collection), memory control circuitry 23 may select one or more physical units from idle area 32 and instruct memory module 122 to store data into the selected physical units. After data is stored in this physical unit, this physical unit can be associated with data area 31. In other words, one or more physical units can be used cyclically between data area 31 and idle area 32.

[0045] In one embodiment, the memory control circuit 23 may be configured with multiple logic units 302(0)-302(C) to map physical units (i.e., physical units 301(0)-301(A)) in the data area 31. For example, a logic unit may correspond to a logical block address (LBA) or other logical management unit. A logic unit may be mapped to one or more physical units.

[0046] In one embodiment, if a physical unit is currently mapped by any logical unit, the memory control circuit 23 can determine that the data currently stored in this physical unit includes valid data. Conversely, if a physical unit is not currently mapped by any logical unit, the memory control circuit 23 can determine that this physical unit does not currently store any valid data.

[0047] In one embodiment, the memory control circuit 23 may record the mapping relationship between logical units and physical units in at least one management table (also known as a logical-to-physical mapping table, or L2P table, mapping table). In one embodiment, the memory control circuit 23 may instruct the memory module 122 to perform data read, write, or erase operations based on the information in this management table (i.e., logical address to physical address mapping table).

[0048] In one embodiment, the aforementioned logical-to-physical mapping table is stored in the system area of ​​the memory module 122. Each mapping table includes multiple mapping entries, and each mapping entry records the mapping relationship between a logical address and a physical address. For example, mapping entry LBA0 records which physical address corresponds to logical address 0. Each mapping table contains multiple mapping entries; for example, a 4KB mapping table can contain 1024 mapping entries.

[0049] As mentioned above, mapping tables typically require a large amount of cache space (memory) resources. For example, if each physical page is 4KB in size and the L2P entry for indexing that page is typically 4 bytes, then the L2P table memory required to index 1GB of storage space is approximately 1MB, resulting in significant memory consumption.

[0050] To reduce cache space consumption, related technologies often employ a hierarchical mapping scheme, where the complete mapping table is stored in the memory module 122, and only the indexes pointing to the mapping table are cached in the cache space, thereby reducing the memory consumption of mapping 1GB of physical space to approximately 1KB. However, this scheme introduces new performance challenges. For example, the mapping table must be read before each data read. If the mapping table is not cached in the cache space, it must be loaded from the memory module 122, severely impacting read performance. Therefore, it is common practice to cache some frequently used mapping tables in the cache space and employ a cache replacement strategy to manage the mapping table cache in the cache space.

[0051] Furthermore, the cache space resources of storage device 12 are limited. In addition to the resources required for the operation of the storage device, they also need to be used to cache the mapping table, instructions, and user data. Under the premise of ensuring the stable operation of the storage device, how to dynamically balance the mapping table cache and the user data cache in a storage device with limited cache space resources becomes a key issue in improving the overall performance of the storage device.

[0052] To at least address the aforementioned issues, this application provides a cache space management method.

[0053] Figure 4 This is a schematic diagram of a cache space according to an embodiment of the present invention. The cache space 40 is provided by one or more physical storage media, such as a host cache 1121, a dynamic random access memory 124, and a buffer memory 24. The cache space 40 is logically divided into a first cache 402 and a second cache 404. The first cache 402 is used to store logical address to physical address mapping entries, and the second cache 404 is used to store user data. The mapping entries are used to convert logical addresses issued by the host 11 into physical addresses in the memory module 122. The second cache 404 further includes at least two data type sub-pools: a write cache sub-pool and a read cache sub-pool. When it is necessary to reduce the capacity of the second cache 404, the memory control circuit 23 can prioritize reducing sub-pools that do not match the dominant load mode according to the read / write ratio of the current load of the storage device 12. For example, during random reads, the write cache sub-pool is prioritized for reduction, thereby reducing the impact of cache capacity adjustments on foreground services.

[0054] During the operation of storage device 12, read and write requests from host 11 first reach memory controller 123. If the mapping table entry corresponding to the requested logical address is hit in the first cache 402, the physical address can be directly obtained and data access performed; if it is not hit, the corresponding mapping table needs to be loaded from memory module 122, which introduces a significant access latency, i.e., a miss penalty. At the same time, the cache hit status of user data also directly affects read and write performance. Therefore, how to dynamically balance the capacity of the first cache 402 and the second cache 404 within the limited cache space 40 is the key to improving the overall performance of storage device 12.

[0055] Figure 5 This is a flowchart of a cache space management method proposed in an embodiment of this application. The method is executed by the memory control circuit 23 and includes the following steps:

[0056] S501: Obtain metrics for adaptively adjusting cache resource allocation in cache space 40. These metrics include the cache hit rate H of the first cache area 402, the average cache miss penalty value P of the first cache area 402, and a preset baseline miss penalty threshold P0 (e.g., 20 μs).

[0057] Here, the cache hit rate H refers to the ratio of the number of times a logical address lookup directly hits the first cache 402 to the total number of lookups within a configurable sliding time window T (e.g., 50ms). The average cache miss penalty P refers to the average time delay in loading a mapping table entry from the memory module 122 each time a first cache miss occurs within the same window. The baseline miss penalty threshold P0 is a preset parameter representing the level of performance loss that the storage device 12 can tolerate. This threshold can be experimentally calibrated based on a typical workload or set or adjusted by the host 11 through configuration commands.

[0058] S502: Calculate the cache urgency factor β of cache space 40 based on cache hit rate H, average cache miss penalty value P, and baseline miss penalty threshold P0.

[0059] The cache urgency factor β is used to determine the caching strategy for cache space 40. The cache urgency factor is calculated as follows: subtract the cache hit rate from 1 to obtain the cache miss rate; divide the average cache miss penalty value by the baseline miss penalty threshold to obtain the penalty ratio; and then multiply the cache miss rate by this penalty ratio. This factor comprehensively reflects the severity of performance problems caused by insufficient first cache space: the larger the factor value, the higher the urgency of expanding the first cache space 402.

[0060] In one embodiment, the above-mentioned cache urgency factor It can be calculated using the following formula:

[0061] Formula 1;

[0062] Where H represents the cache hit rate of the first cache region. This indicates the cache miss rate of the first cache area (402). This represents the preset baseline miss penalty threshold, which can be calibrated based on typical workloads and used for normalization calculations. It represents the level of performance loss that the storage device can tolerate. P represents the average cache miss penalty value of the first cache area 402. This factor comprehensively reflects the severity of performance problems caused by insufficient mapping table caching: the larger the factor value, the greater the urgency to expand the first cache area 402.

[0063] Based on this, in order to eliminate the indicator jumps caused by instantaneous fluctuations in IO load, the calculated β is smoothed by Exponentially Weighted Moving Average (EWMA) to obtain the smoothed β. .

[0064] Formula 2;

[0065] After smoothing As input for subsequent strategy judgment and adjustment calculation, it effectively avoids erroneous adjustments caused by instantaneous jitter, making the trend of cache allocation change more stable.

[0066] in, It is a smoothing factor, with a value ranging from 0 to 1. The larger, The faster the response to current load changes; The smaller the value, the more historical information is retained, and the stronger the noise resistance.

[0067] S503: Determine the caching strategy for cache space 40 based on β and a preset first threshold TH (e.g., 1.2) and a second threshold TL (e.g., 0.8). Where TH > TL.

[0068] Specifically, when β > TH, it indicates that the first cache 402 is severely insufficient, and a strategy to expand the first cache 402 needs to be implemented. When β < TL, it indicates that the first cache 402 is relatively abundant, and a strategy to shrink the first cache 402 and make room for the second cache 404 can be implemented. When TL ≤ β ≤ TH, it indicates that the current allocation is in a balanced range, and the capacity remains unchanged.

[0069] S504: The caching policy in response to cache space 40 is to adjust the cache capacity of cache space 40, and calculate the cache adjustment amount of cache space 40 based on the cache urgency factor.

[0070] Specifically, if the strategy is to expand the first cache area 402, then the first cache adjustment amount Δ1 is calculated; if the strategy is to shrink the first cache area 402, then the second cache adjustment amount Δ2 is calculated. The adjustment amounts Δ1 and Δ2 are proportional to the degree to which β deviates from the corresponding threshold, and are also constrained by the proportionality coefficient K (e.g., 0.1), the total cache capacity C_Total, the minimum reserved mapping table capacity C_Lmin, and the minimum reserved user data capacity C_Dmin.

[0071] It should be emphasized that the initial first buffer capacity is defined as C_L and the initial second buffer capacity is defined as C_D.

[0072] The total cache capacity C_Total, the first cache capacity C_L, and the second cache capacity C_D satisfy C_L + C_D = C_Total.

[0073] Preset thresholds TL (lower limit, e.g., set to 0.8) and TH (higher limit, e.g., set to 1.2) are used to define the balance range. Additionally, the minimum reserved capacity C_Lmin for the first cache and the minimum reserved capacity C_Dmin for the second cache are used to ensure the basic functionality and stability of the storage device 12.

[0074] The proportional coefficient k is used to control the magnitude of a single adjustment (it can be set to 0.05≤k≤0.2) to prevent cache allocation oscillations caused by load fluctuations. The monitoring window T affects the real-time performance and smoothness of the metric statistics and can be set to support dynamic adaptation. The memory control circuit 23 periodically adjusts within a configurable sliding time window T (empirically set to 10ms–100ms). In some embodiments, the window T can be periodically triggered. In addition to periodic triggering, the memory control circuit 23 can also combine event-driven adjustments (such as sustained high miss rates or sudden load changes) for real-time adjustments.

[0075] As an optional embodiment, the metrics collected by window T may also include load characteristics, which can be used to represent the ratio of random / sequential access, read / write load intensity (IOPS / bandwidth), etc.

[0076] Where H represents the proportion of logical address lookups that directly hit the first cache within the window. The formula for calculating H is as follows:

[0077] Formula 3;

[0078] in, This indicates the number of times the cache is hit directly in the first cache within the window. This indicates the total number of accesses to the first cache within the same window.

[0079] The average cache miss penalty value P represents the average time delay or equivalent I / O overhead (which can be converted into the number of operations or clock cycles) caused by each cache miss in the first cache within the window, resulting in the loading of the mapping table from the memory module 122. It is used to measure the performance loss caused by each miss. By setting the average cache miss penalty value P, the cache hit rate is improved, the read operations on the memory module 122 are reduced, and the lifespan of the memory module 122 is extended.

[0080] S505: Adaptively adjust the capacity allocation of the first cache area 402 and the second cache area 404 in the cache space 40 according to the cache adjustment amount.

[0081] Specifically, if the strategy is to expand the first buffer 402, the current capacity of the first buffer 402 is increased by the first buffer adjustment amount Δ1, and meanwhile the current capacity of the second buffer 404 is decreased by the first buffer adjustment amount Δ1; if the strategy is to shrink the first buffer 402, the current capacity of the first buffer 402 is decreased by the second buffer adjustment amount Δ2, and meanwhile the current capacity of the second buffer 404 is increased by the second buffer adjustment amount Δ2. During the adjustment process, the memory control circuit 23 completes the cleaning of eliminated mapping table entries or user data, the release and reallocation of buffer space, and updates the internal buffer address range data structure. After the adjustment is completed, the storage device 12 enters the next monitoring cycle.

[0082] For example, the calculation formula of Δ1 (Formula 4) is as follows:

[0083]

[0084]

[0085] Wherein, represents the adjusted capacity of the first buffer, represents the adjusted capacity of the second buffer, and min is used to ensure that the minimum reserved capacity is not exceeded and the adjustment range is controlled.

[0086] For example, the memory control circuit 23 initially allocates 50% of the total capacity to C_L and C_D respectively. When running a random read-intensive application, the miss rate (1-H) of the first buffer increases, and the miss penalty P increases, causing the β value to quickly exceed TH. Then the first adjustment amount Δ1 is calculated according to Formula 4, and a part of the space is allocated from the second buffer 404 to the first buffer 402 to expand the first buffer, so as to avoid read blocking caused by uncached mapping table. After adjustment, the hit rate of the first buffer is improved, and the random read latency is significantly reduced.

[0087] In some embodiments, when β<TL, it indicates that the cache of the first buffer is sufficient or excessive. At this time, part of the space of the first buffer can be released to the second buffer. The calculation of the second buffer adjustment amount Δ2 of the first buffer (Formula 5) is as follows:

[0088]

[0089]

[0090] The foregoing Formula 4 and Formula 5 respectively calculate the buffer adjustment amounts for expanding and shrinking the first buffer. By taking the smaller value between the upper limit of releasable space and the proportion-driven adjustment amount, it is ensured that each adjustment will not break the safety bottom line of the minimum reserved capacity of each buffer, and the adjustment step size can be proportional to the deviation degree of the current urgency factor from the corresponding threshold, realizing adaptive step size control of large step for urgent adjustment and small step for gradual adjustment.

[0091] Figure 6 This is a schematic diagram of a cache space adjustment process proposed in an embodiment of this application, which is executed by the memory control circuit 23. Figure 6 As shown, when TL≤β≤TH, it indicates that the cache state is balanced. At this time, the current cache allocation can remain unchanged, and a stable state can be entered. It should be noted that the first threshold TH and the second threshold TL in this embodiment are also referred to as the upper limit threshold and the lower limit threshold, respectively, in the scheme description. The two together define the balanced range of cache space capacity allocation.

[0092] like Figure 6 As shown, after calculating the adjustment amount, cache adjustment is performed. This embodiment adaptively optimizes the first and second cache spaces, dynamically adjusting them according to the real-time load of the storage device 12, thereby improving the performance of the storage device 12 in different scenarios. Simultaneously, it avoids idle cache resources caused by fixed allocation of cache space resources, achieving efficient utilization of cache resources.

[0093] Figure 7 This application provides a schematic diagram of a cache space adjustment process. Figure 7 The dynamic variation trends of the first and second cache sizes are shown under different I / O load stages.

[0094] like Figure 7 As shown, the time axis T represents the load change during the operation of storage device 12.

[0095] In Phase 1: Random read load increases, mapping table access becomes more frequent, cache urgency factor β increases, triggering cache adjustment. The second cache area releases space to the first cache area, thereby expanding the first cache area and reducing the second cache area.

[0096] In phase 2: Sequential write load increases, the frequency of mapping table access decreases, the cache urgency factor β decreases, triggering cache adjustment. The first cache area releases space for the second cache area, thus shrinking the first cache area and expanding the second cache area.

[0097] In Phase 3: Mixed load, data is read and written simultaneously. The cache urgency factor β is in a balanced range, and the cache allocation remains stable (the capacities of the first and second caches are stable).

[0098] like Figure 7 As shown, in some embodiments, after the cache adjustment is completed, the next monitoring cycle can be entered to form a closed loop, continuously tracking the load changes of the storage device 12 and achieving adaptive optimization.

[0099] In some embodiments, load-aware adaptive settings can be configured to appropriately increase the weight of the first cache under high random read loads and prioritize the space of the second cache under high sequential write loads. Through the method of this embodiment, the storage device 12 can adaptively adjust the capacity allocation between the first and second caches based on real-time cache hit and miss penalties, achieving efficient utilization of cache space and improving overall performance under complex loads such as random reads.

[0100] In one embodiment, the specific process of determining the caching strategy of cache space 40 based on the cache urgency factor and preset first and second thresholds includes: in response to the cache urgency factor being greater than the first threshold, determining the caching strategy to allocate a portion of the capacity of the second cache 404 to the first cache 402; in response to the cache urgency factor being less than the second threshold, determining the caching strategy to allocate a portion of the capacity of the first cache 402 to the second cache 404; and in response to the cache urgency factor being greater than or equal to the second threshold and less than or equal to the first threshold, determining the caching strategy to maintain the current capacity allocation of the first and second caches unchanged. Here, the first threshold is greater than the second threshold. This forms a stable range, avoiding strategy jitter caused by minor fluctuations in the factor.

[0101] In one embodiment, the first threshold and the second threshold are not fixed values. The method further includes: recording the cache urgency factor over the past N consecutive monitoring periods to form a urgency time series; analyzing the trend of the urgency time series; if it is identified that the storage device 12 is continuously in a high urgency state, then simultaneously lowering the first threshold and the second threshold to make the storage device 12 more sensitive to the decision to expand the first cache area 402; if it is identified that the storage device 12 enters a continuous low load state, then simultaneously raising the first threshold and the second threshold to return to a conservative balance strategy.

[0102] It is important to emphasize that different storage devices, or even the same storage device at different stages of its lifespan, have varying baseline performance levels. A fixed threshold cannot adapt to all storage devices and usage scenarios. This embodiment automatically identifies the usage of storage devices by monitoring the trend of the urgency factor over a long period, allowing the threshold to periodically optimize cache space resources. Specifically, when storage device 12 operates under a high urgency state for an extended period, it indicates that the current threshold setting is too conservative, and the memory control circuit 23 is hesitant or rarely triggers the decision to expand the mapping table cache. In this case, the threshold is automatically lowered by two points to make the decision threshold more lenient. Conversely, when storage device 12 operates under a low urgency state for an extended period, it indicates that the mapping table cache is sufficient and does not require frequent adjustments; the threshold is automatically raised to maintain stability. The step size and frequency of threshold adjustments are limited to ensure that frequent changes in the threshold itself do not cause new oscillations. This allows storage device 12 to adapt to hardware platforms with different performance levels and memory modules 122 at different stages of their lifespan.

[0103] In one embodiment, the second cache 404 includes multiple data type sub-pools, which at least include a write cache sub-pool for caching sequential write data and a read cache sub-pool for caching random read data. When the caching strategy is determined to allocate part of the capacity of the second cache 404 to the first cache 402, when it is determined that the capacity of the second cache 404 needs to be reduced, the capacity of the data type sub-pools that do not match the current dominant load pattern are preferentially reduced according to the read / write ratio of the current workload.

[0104] Typically, when a large number of random read requests are received, the read cache sub-pool in the second cache area 404 has high utilization, while the write cache sub-pool is relatively idle. If the first cache area 402 needs to be expanded due to an excessively high urgency factor, uniformly reducing the sub-pools of the second cache area 404 might impair the performance of the high-frequency read requests being served. This embodiment, by sensing the type of current workload, selectively reclaims space from sub-pools that do not match the current dominant load pattern. For example, in a scenario dominated by random reads, the write cache sub-pool is reduced first; in a scenario dominated by sequential writes, the read cache sub-pool is reduced first. This minimizes the negative impact of cache space 400 capacity adjustments on foreground business performance and makes the reallocation of cache resources smoother.

[0105] In one embodiment, the aforementioned average cache miss penalty value includes a first statistical value and a second statistical value. The first statistical value is the average latency within the monitoring window, and the second statistical value is the percentile of the miss latency within the monitoring window (e.g., the 99th percentile latency). When calculating the cache urgency factor of the cache space, a penalty fluctuation coefficient is also calculated based on the first and second statistical values. This penalty fluctuation coefficient characterizes the jitter of the miss latency. The initial urgency factor is corrected using the penalty fluctuation coefficient, so that when the second statistical value exceeds a preset latency threshold, the cache urgency factor is increased to reflect the risk of user experience degradation caused by latency jitter.

[0106] In real-world storage devices, average latency does not fully reflect user experience. For example, while the average miss latency may be only 20 microseconds, an occasional 99th percentile latency could be as high as 200 microseconds. This long-tail latency can cause noticeable stuttering on the host side. This embodiment introduces tail latency information to construct a penalty fluctuation coefficient. When the tail latency exceeds a preset threshold, even if the average latency is acceptable, the cache urgency factor is increased, thereby prompting the system to more actively expand the first cache. This effectively guarantees the Quality of Service (QoS) of the storage device 12, reduces the risk of performance fluctuations caused by latency jitter, and is particularly suitable for embedded storage devices such as eMMC and UFS that have high latency consistency requirements.

[0107] Figure 8 This is a flowchart illustrating a cache urgency factor calculation and optimization method proposed in an embodiment of this application. The method is executed by the memory control circuit 23. Figure 8 As shown, the monitoring window simultaneously calculates the average miss latency (first statistic) and the percentile of miss latency (second statistic, e.g., P99). Basic urgency factor. The cache hit rate H and the average cache penalty P are calculated. Simultaneously, a penalty fluctuation coefficient is generated by comparing the second statistical value with a preset latency threshold. When the tail latency is too high, β is increased to reflect the risk of experience degradation caused by latency jitter. Finally, β is smoothed using an exponentially weighted moving average (EWMA) to output the final value. This serves as a basis for decision-making, preventing strategy oscillations caused by momentary fluctuations.

[0108] In one embodiment, the above-mentioned caching strategy in response to the cache space is to adjust the cache capacity of the cache space. The cache adjustment amount of the cache space is calculated based on the cache urgency factor, including: in response to the caching strategy, allocating part of the capacity of the second cache area 404 to the first cache area 402, calculating the first cache adjustment amount of the cache space 40 based on the cache urgency factor, the first threshold, the current capacity of the first cache area 402, the minimum reserved cache capacity of the second cache area 404, the total cache capacity of the cache space 40, and the proportional coefficient.

[0109] Specifically, the method for determining the first cache adjustment amount is as follows: calculate the difference between the current capacity of the second cache area 404 and its minimum reserved cache capacity, calculate the product of the proportional coefficient, the total cache capacity, and the portion of the cache urgency factor that exceeds the first threshold, and take the smaller of the difference and the product as the first cache adjustment amount.

[0110] The minimum reserved buffer capacity is a lower limit set to ensure the basic functions of the second buffer 404 (such as ensuring it can hold at least one complete data block). The proportional coefficient is a preset parameter used to control the magnitude of a single adjustment, typically ranging from 0.05 to 0.2. By using a smaller value, it ensures that the adjustment amount will not exceed the safety threshold of the second buffer 404. On the other hand, when the urgency factor deviates significantly from the threshold, it can make decisive adjustments in steps proportional to the degree of deviation, while when the deviation is relatively small, it can make fine adjustments in controlled, smaller steps, achieving adaptive step size control and effectively preventing oscillations caused by excessive single adjustments.

[0111] In one embodiment, the user data includes clean data and dirty data to be written back to the memory module 122 in the storage device 12. The method further includes: obtaining the proportion of dirty data in the second cache 404; when the caching strategy is determined to allocate part of the capacity of the second cache 404 to the first cache 402, if the proportion of dirty data exceeds a preset dirty data threshold, then a shrinking bias is applied to the calculated first cache adjustment amount to prioritize the residence space of dirty data and reduce additional write-back operations triggered by cache shrinkage.

[0112] When the proportion of dirty data in the second cache 404 is high, forcibly reducing its capacity would force the memory control circuit 23 to initiate a large number of write-back operations. This would not only occupy valuable memory module 122 bandwidth but also increase write amplification, offsetting or even exceeding the performance gains brought by expanding the first cache 402. In this embodiment, by applying a bias to the first cache adjustment amount, the adjustment magnitude is automatically reduced when the proportion of dirty data is high. This is equivalent to adding the consideration of adjustment cost to the decision-making chain, making the cache allocation decision more in line with the overall energy efficiency optimization principle of the storage device 12.

[0113] In one embodiment, the above-mentioned caching strategy in response to the cache space is to adjust the cache capacity of the cache space. The cache adjustment amount of the cache space is calculated based on the cache urgency factor, including: in response to the caching strategy, allocating a portion of the capacity of the first cache area 402 to the second cache area 404, calculating the second cache adjustment amount of the cache space 40 based on the cache urgency factor, the second threshold, the current capacity of the first cache area 402, the minimum reserved cache capacity of the first cache area 402, the total cache capacity of the cache space 40, and the scaling factor.

[0114] Specifically, the second cache adjustment amount is determined as follows: calculate the difference between the current capacity of the first cache area 402 and its minimum reserved cache capacity, calculate the product of the proportional coefficient, the total cache capacity, and the portion of the second threshold exceeding the cache urgency factor, and take the smaller of the difference and the product as the second cache adjustment amount.

[0115] This design principle corresponds to the adjustment calculation when expanding the first cache 402, ensuring that the reduction operation is also protected by the minimum reserved capacity, and that the adjustment step size is proportional to the degree to which the current urgency factor is lower than the second threshold. When the urgency factor is much smaller than the second threshold, it indicates that the mapping table cache has significant surplus, and a larger step size can be taken to release space for the data cache; when the urgency factor is close to the second threshold, only fine-tuning is performed or it remains unchanged to maintain the performance stability of the storage device 12.

[0116] In one embodiment, the aforementioned proportional coefficient K is not a fixed value. The method further includes: obtaining the current total bandwidth utilization of the cache space 40, and in response to the total bandwidth utilization exceeding a preset bandwidth threshold, reducing the proportional coefficient K to suppress the magnitude of a single adjustment, thereby avoiding increased load on the storage device 12 due to internal data migration and cache space access bandwidth competition caused by the reallocation of the cache space 40.

[0117] It is important to emphasize that adjusting the cache capacity itself consumes bus bandwidth resources of the cache space 40. When the storage device 12 is already heavily loaded and the total bandwidth utilization is high, if a large adjustment is still made according to the usual proportional coefficient, the resulting internal operations will compete with the host I / O for bus bandwidth, which may further degrade the overall performance, resulting in a situation where the more it is adjusted, the slower it becomes. This embodiment introduces a bandwidth-aware mechanism: the memory control circuit 23 continuously monitors the total bandwidth utilization of the cache space 40. When the utilization exceeds a preset bandwidth threshold (e.g., 80%, which is a high load), the proportional coefficient K is reduced by a certain proportion to reduce the magnitude of a single adjustment, allowing the adjustment operation to be completed gradually in smaller steps, avoiding impact on the foreground services; when the bandwidth utilization returns to normal, the original value of K is restored to ensure adjustment efficiency.

[0118] In one embodiment, the capacity allocation of the first cache area 402 and the second cache area 404 in the cache space is adaptively adjusted according to the cache adjustment amount. Specifically, this includes: when expanding the first cache area 402, determining the adjusted capacity of the first cache area based on the sum of the first cache adjustment amount and the current capacity of the first cache area; and determining the adjusted capacity of the second cache area based on the difference between the current capacity of the second cache area 404 and the first cache adjustment amount. When shrinking the first cache area 402, determining the adjusted capacity of the first cache area based on the difference between the current capacity of the first cache area and the second cache adjustment amount; and determining the adjusted capacity of the second cache area based on the sum of the second cache adjustment amount and the current capacity of the second cache area. The memory control circuit 23 updates the internally maintained capacity boundary registers or configuration parameters of the first cache area 402 and the second cache area 404 according to the adjusted capacity values, so that subsequent cache allocation and eviction operations are performed based on the new capacity allocation.

[0119] In one embodiment, the above-mentioned adaptive adjustment of the capacity allocation of the first cache area and the second cache area in the cache space 40 according to the first cache adjustment amount specifically includes: determining the adjusted capacity of the first cache area according to the sum of the first cache adjustment amount and the current capacity of the first cache area; determining the adjusted capacity of the second cache area according to the difference between the current capacity of the second cache area and the first cache adjustment amount; and adjusting the cache resource allocation in the cache space according to the adjusted capacity of the first cache area and the adjusted capacity of the second cache area.

[0120] In one embodiment, the adaptive adjustment of the capacity allocation of the first cache area and the second cache area in the cache space includes: determining the adjusted capacity of the first cache area based on the difference between the current capacity of the first cache area and the second cache adjustment amount; determining the adjusted capacity of the second cache area based on the sum of the second cache adjustment amount and the current capacity of the second cache area; and adjusting the cache resource allocation in the cache space based on the adjusted capacity of the first cache area and the adjusted capacity of the second cache area.

[0121] Figure 9 This is a schematic diagram of cache adjustment calculation and cache capacity update proposed in an embodiment of this application. The method is executed by the memory control circuit 23. Figure 9 This paper describes the calculation process of the first cache adjustment amount Δ1 and the second cache adjustment amount Δ2, as well as the cache capacity update. When the strategy is to expand the first cache, Δ1 is the smaller value between the available space of the second cache and the proportional adjustment amount, taking into account the proportion of dirty data: if the proportion of dirty data exceeds a threshold, a shrinking bias is applied to Δ1 to suppress write amplification. The capacities of both caches are then updated. When the strategy is to shrink the first cache, Δ2 is the smaller value between the available space of the first cache and the proportional adjustment amount, and the capacity is updated in reverse. All calculations are constrained by the minimum reserved capacity to prevent exceeding the safety threshold.

[0122] In one embodiment, before adaptively adjusting the capacity allocation of the first and second cache areas in the cache space according to the cache adjustment amount, the method further includes: estimating the additional overhead that will be introduced by performing this capacity adjustment operation itself, which includes at least the metadata update overhead triggered by the evicted entries and the dirty data write-back overhead that may be triggered; and comparing the additional overhead with the expected performance gains after performing this capacity adjustment. The performance gains are estimated based on the cache urgency factor and the cache adjustment amount, and the capacity adjustment operation is only performed if the performance gains are greater than the additional overhead.

[0123] Adjustment operations are not without cost. For example, shrinking the first buffer 402 requires evicting a batch of mapping table entries according to an eviction policy. If these entries are accessed again soon afterward, it will trigger new miss penalties. Similarly, shrinking the second buffer 404 may trigger dirty data write-backs. This embodiment establishes a simple overhead / benefit design, performing a net benefit judgment before each adjustment decision. If the estimated adjustment benefit (such as the total reduction in miss latency over a future period) cannot cover the adjustment cost itself, the adjustment is abandoned. This prevents meaningless or even harmful adjustments when load boundaries are ambiguous.

[0124] In one embodiment, before adaptively adjusting the capacity allocation of the first and second cache regions in the cache space according to the cache adjustment amount, the method further includes: maintaining a thrashing counter to record the number of times the caching strategy switches back and forth between expanding and shrinking the first cache region within a preset observation window. When the value of the thrashing counter exceeds a preset thrashing threshold, the current capacity adjustment operation is temporarily suspended, and the duration of the next monitoring cycle is extended; however, when the cache urgency factor exceeds a preset mandatory threshold, the thrashing counter is ignored, and the operation of allocating the capacity of the second cache region to the first cache region is forcibly executed. The mandatory threshold is significantly larger than the first threshold.

[0125] In practical applications, when the I / O load of storage device 12 is at a certain boundary state, the cache urgency factor in adjacent monitoring cycles may repeatedly fluctuate around the threshold, causing frequent switching between expanding and shrinking the cache adjustment strategy. This phenomenon itself consumes a lot of resources and is not conducive to cache space management. This embodiment introduces a thrashing counter. Each time a strategy switch occurs, the counter is incremented by 1. When the count value exceeds the thrashing threshold, protection is triggered, the current adjustment is suspended, and the monitoring cycle is extended, giving the storage device more time to observe the load trend and allowing the instantaneous fluctuations to subside naturally. Then, if the performance deteriorates severely during the suspension period, i.e., β exceeds the forced threshold (e.g., twice the first threshold), the protection is bypassed, and the cache capacity adjustment operation is forcibly executed. In this way, both stability and responsiveness in extreme cases are taken into account.

[0126] In one embodiment, a target entry is determined from the cache to be reduced according to the target algorithm, the cache space corresponding to the target entry is released and the cache space is allocated to the cache pool to be expanded, and the cache address range data structure corresponding to this cache pool to be expanded is updated.

[0127] The target algorithm described above can be the Least Recently Used (LRU) algorithm or other cache management algorithms; this embodiment does not limit this. The memory control circuit 23 traverses the entries in the cache to be reduced, determines the eviction priority based on the access history, and removes the selected entries one by one. The freed physical memory pages are relinked to the free page list of the cache pool to be expanded, thereby completing the transfer of space ownership. Simultaneously, the memory control circuit 23 updates the internal data structure used to manage the address ranges of each cache area to ensure that subsequent allocations are correct.

[0128] In one embodiment, releasing the cache space corresponding to the target entry and allocating the cache space to the cache pool to be expanded specifically includes: without moving the physical data of the cache entry, modifying the address mapping unit of the cache space to remap at least one released physical memory page from the first address space region to the second address space region; the modification operation of the address mapping unit is executed in parallel with the front-end read and write commands of the storage device.

[0129] Traditional cache space adjustments often require copying data from the old region to the new region, which is time-consuming and obstructs normal data flow. This embodiment utilizes the page table-level remapping capability of the memory address mapping unit in the buffer memory 24. Only one or a few page table entries need to be modified to quickly allocate several physical pages belonging to the first cache area 402 to the second cache area 404 (or vice versa), without any data movement. Simultaneously, this remapping operation, as an atomic register write operation, can be executed in parallel with the host 11's read and write commands without blocking the I / O path. This reduces the instantaneous impact of the adjustment operation on the performance of the storage device 12.

[0130] In one embodiment, determining target entries according to a target algorithm includes: obtaining the access frequency and most recent access time of each entry in the cache to be reduced; obtaining the cache urgency factor at the current moment; and dynamically adjusting the weights of access frequency and most recent access time in calculating the eviction priority based on the cache urgency factor. Specifically, when the cache urgency factor indicates that the first cache 402 is severely insufficient, the weight of access frequency is increased to prioritize the eviction of entries that have been recently accessed but have low frequency, reducing the risk of future false evictions of critical mappings.

[0131] Typical cache eviction strategies (such as LRU) determine the eviction order solely based on the most recent access time. When storage device 12 is in a high-urgency state of the mapping table cache, many mapping entries may have young timestamps due to recent loading, but their actual access frequency is not high. Conversely, some core mapping entries that are frequently accessed in the long term may be wrongly evicted because they were accessed just slightly earlier. This embodiment enables the eviction algorithm to be aware of the current urgency state of storage device 12: when the urgency factor is high, the algorithm tilts towards access frequency, approximating low-frequency priority eviction; when the urgency factor returns to normal, it reverts to the regular LRU logic. This mechanism of adaptive change with urgency effectively protects hot mappings and avoids secondary performance loss caused by eviction decision errors when performance is under pressure.

[0132] In one embodiment, it is also proposed to determine the target entry from the cache to be reduced according to the target algorithm, release the cache space corresponding to the target entry and allocate the cache space to the cache pool to be expanded; update the cache address range data structure corresponding to the cache pool to be expanded, and suspend related cache access through a locking mechanism or ensure data consistency and address mapping correctness during the cache adjustment process through atomic operations.

[0133] During cache capacity adjustment, the first cache area 402 and the second cache area 404 are being concurrently accessed by host I / O. Without protection, the following problem may occur: a mapping table entry has just been evicted, its cache space has been allocated to the second cache area, but an incomplete read request still attempts to perform address mapping through that entry. In this embodiment, during the critical operation of cache space reallocation, a spinlock or mutex is used to briefly suspend access to the relevant cache area, releasing the lock after the address mapping unit is updated; alternatively, an atomic page table remapping instruction is used, executing the release of the old space and allocation to the new pool as an indivisible operation unit. During operation execution, new cache access requests enter a waiting queue, while ongoing requests hold references to the old addresses to ensure completion. This ensures that the state of the cache space is logically consistent at any given time, preventing serious errors such as dangling pointers and data corruption.

[0134] In one embodiment, a sliding time window and metric acquisition embodiment are also proposed. The metric includes load characteristics. The steps for obtaining the metrics used to adaptively adjust the allocation of cache resources in the cache space 40 include: periodically acquiring the cache hit rate, average cache miss penalty value, and load characteristics based on the sliding time window.

[0135] A sliding window refers to a mechanism that, over a continuous timeline, calculates statistical metrics for all access samples within a fixed window size T (e.g., 50ms) after a preset step interval (e.g., T / 2, or 25ms) or a complete window. As time progresses, the window slides forward, discarding older samples and incorporating new ones. This mechanism allows the collected metrics to smoothly reflect recent load trends, avoiding the randomness of individual data points / values. Furthermore, the window size T is a configurable parameter that can be preset based on the storage device's application scenario (e.g., consumer, enterprise, industrial). Load characteristics can also include random / sequential access ratios, read / write IOPS or bandwidth intensity, and space utilization of each cache sub-pool, providing a data foundation for subsequent load-aware enhancement strategies.

[0136] In one embodiment, a method for dynamically adjusting the monitoring window is also proposed. The initial size T of the sliding time window is a preset value. The method further includes: dynamically adjusting the size T of the sliding time window based on the stability of the cache urgency factor over multiple consecutive periods; reducing T to improve response speed when drastic fluctuations in the cache urgency factor are detected; and increasing T to reduce monitoring overhead and improve statistical smoothness when the cache urgency factor is detected to be stable over a long period.

[0137] It is important to emphasize that when the load on storage device 12 changes drastically, an excessively large window can lead to sluggish response and miss the optimal adjustment opportunity; conversely, when the load remains stable for a long period, an excessively small window can increase unnecessary computational overhead, and the statistical structure may not be smooth enough. This embodiment extends the adaptive concept to the time dimension: the memory control circuit 23 continuously evaluates the variance or standard deviation of the β value over several recent periods. If the variance exceeds a preset fluctuation threshold, the load is determined to be unstable, and the window size T is automatically shortened to allow the statistical data to converge to the new load characteristics more quickly; if the variance remains low for a long period, the load is determined to be stable, and T is gradually lengthened to a preset upper limit to reduce the overhead of periodic statistical calculations on the memory control circuit 23. The adjustment of the window size is constrained by preset step size and upper and lower limits to prevent extreme contraction or expansion.

[0138] In one embodiment, a method for smoothing decision-making based on historical records is also proposed. The method further includes recording recent adjustment history and performance changes for use in smoothing adjustment decisions.

[0139] Specifically, a circular historical record buffer is maintained in buffer memory 24, storing basic information of each adjustment operation in chronological order: adjustment timestamp, adjustment direction, adjustment amount, cache urgency factor before and after the adjustment, and cache hit rate. Before making a new adjustment decision, the most recent M adjustment records are reviewed: if the direction of the recent adjustments is found to be repeatedly switching, it indicates that the current parameter configuration may be causing an oscillation trend. In this case, the adjustment trigger threshold can be appropriately increased or the monitoring period can be temporarily extended. If the urgency factor has not improved significantly after expanding the first buffer in recent times, it indicates that the first buffer may have approached the hit rate ceiling, and further expansion is not meaningful. In this case, further expansion operations can be suppressed. By utilizing the feedback information of historical records, the smooth decision-making has the ability to learn from the past adjustment effects, further improving the stability and efficiency of long-term operation.

[0140] In one embodiment, an embodiment in which the above parameters are loaded during power-on initialization of the storage device 12 is also proposed.

[0141] Specifically, in response to the power-on initialization of the storage device 12, a preset parameter configuration is loaded to set the initial parameters of the storage device 12. The initial parameters include at least the total cache capacity of the cache space 40, the initial capacity of the cache resources in the cache space, the minimum reserved cache capacity of the cache resources in the cache space, a preset baseline miss penalty threshold, a preset threshold, and a scaling factor.

[0142] For example, when the storage device 12 is powered on, it reads a factory-preset or user-defined parameter configuration file from the system area of ​​the memory module 122 or the ROM of the memory controller 123, and initializes the internal registers of the memory controller 123. For example, the total cache capacity C_Total of the cache space 40 is set to 64MB, the initial mapping table cache capacity C_L and the data cache capacity C_D are each allocated 50%, the minimum reservation C_Lmin is set to 8MB, C_Dmin is set to 16MB, the monitoring window T is initialized to 50ms, and the baseline miss penalty value is set to... The initial values ​​are set to 20 μs, the first threshold TH to 1.2, the second threshold TL to 0.8, and the scaling factor K to 0.1. These initial values ​​provide a validated starting state for the storage device 12 that operates well under most typical loads. As the storage device 12 operates, some parameters can be dynamically adjusted in subsequent monitoring cycles to adapt to actual load characteristics.

[0143] In one embodiment, an embodiment of adjusting weights based on load characteristics is also proposed. Specifically, load characteristics are obtained, and based on the load characteristics, the weight of the first cache 402 is increased under high random read load, while the space of the second cache 404 is prioritized under high sequential write load.

[0144] It is important to emphasize that the load characteristics here can be obtained from the aforementioned sliding window statistics, including the proportion of random reads and sequential writes. When the proportion of random read requests in the current window exceeds a preset threshold, it indicates that the storage device 12 is under a random read-intensive load, at which point the hit rate of the mapping table cache has a significant impact on performance. When calculating the cache adjustment amount, the memory control circuit 23 can apply a gain coefficient greater than 1 to the adjustment amount of expanding the first cache area, while reducing the adjustment amount of shrinking the first cache area, forming an allocation tendency tilted towards the first cache area 402. Conversely, when large-block sequential writes are detected as dominant, priority is given to ensuring that the space of the second cache area 404 is not over-compressed. This mechanism adds the ability to perceive load patterns to the adjustment strategy, which is driven by the basic urgency factor.

[0145] To more intuitively illustrate the technical solution of this application, the following description, using numerical examples, details the specific operation process of the cache space management method within a complete decision-making cycle. This includes initial state and parameter configuration, metric collection during the monitoring cycle, cache urgency factor calculation, strategy decision-making, adjustment calculation, and capacity update.

[0146] Initial state and parameter configuration: suppose after the storage device is powered on and initialized, the total capacity C_Total of the cache space is 64MB. According to the initial configuration, the current capacity C_L_cur of the first cache area 402 is 32MB, and the current capacity C_D_cur of the second cache area 404 is 32MB.

[0147] The values of each preset parameter are shown in Table 1:

[0148] Table 1:

[0149] Total cache capacity C_Total 64MB Total cache size Minimum reservation for the first cache area C_Lmin 8MB First Buffer Security Bottom Line Minimum reservation for the second cache area C_Dmin 16MB Second Buffer Security Bottom Line First threshold TH 1.2 Threshold for triggering expansion of the first cache Second threshold TL 0.8 Threshold for triggering the expansion of the second cache Baseline Miss Threshold P0 20μs Tolerable delay for a single miss proportionality coefficient K 0.1 Control the magnitude of a single adjustment Monitoring window T 50ms Indicator Statistical Period

[0150] Indicator collection within a monitoring cycle: within a certain monitoring window T=50ms, the memory control circuit 23 counts the data shown in Table 2:

[0151] Table 2:

[0152] Total number of queries to the mapping table (N_total) 100,000 times The number of hits in the first cache (N_hit) 85,000 times Number of misses (N_miss) 15,000 times Total delay time of misses 450,000μs

[0153] Based on the data in Table 2, substitute the above formula to calculate each indicator:

[0154] H=0.85, cache miss ratio=0.15, average cache miss penalty P=30μs.

[0155] and calculate the cache urgency factor β according to the above indicators:

[0156] Normalized penalty ratio=P / P0=30μs / 20μs=1.5, β=0.15×1.5=0.225.

[0157] Here, assuming that after EWMA smoothing processing (smoothing factor α=0.3, β_old of the previous cycle=0.20), then: β_smooth=0.3×0.225+0.7×0.20=0.0675+0.14=0.2075. This β_smooth value is used as the decision basis below.

[0158] Compare β_smooth(0.2075) with the first threshold TH(1.2) and the second threshold TL(0.8):

[0159] β_smooth (0.2075)<TL(0.8)

[0160] According to the policy rule, β_smooth<TL indicates that the current mapping table cache is sufficient, the performance pressure is low, and part of the capacity of the first cache area 402 can be appropriately released for the second cache area 404 to use.

[0161] Furthermore, the strategy in this case is to reduce the first cache 402 (allocate part of the capacity of the first cache to the second cache), and calculate the adjustment amount Δ2 of the second cache.

[0162] Determine the current values ​​of the relevant parameters: current capacity of the first cache C_L_cur = 32MB, minimum reserved capacity of the first cache C_L_min = 8MB, scaling factor k = 0.1, total cache capacity C_Total = 64MB, second threshold TL = 0.8, current urgency factor β = 0.2075.

[0163] Calculation process:

[0164] Calculate the maximum free space = C_L_cur - C_L_min = 32 - 8 = 24MB;

[0165] Calculate the proportional drive adjustment amount = k × C_Total × (TL−β) = 0.1 × 64 × (0.8 - 0.2075) = 6.4 × 0.5925 = 3.792 MB;

[0166] Δ2 = min(24MB, 3.792MB) = 3.792MB

[0167] Taking a smaller value ensures that the adjustment amount will not exceed the safety threshold (the first cache must retain at least 8MB), and that the adjustment step size is proportional to the degree to which the urgency factor is below the threshold—currently β is much lower than TL, thus providing relatively large adjustment space.

[0168] Furthermore, update the capacities of the two caches based on Δ2:

[0169] C_L_new=C_L_cur-Δ2=32-3.792=28.208MB

[0170] C_D_new=C_D_cur+Δ2=32+3.792=35.792MB

[0171] The capacity changes are summarized in Table 3:

[0172] Table 3:

[0173] 402 32MB -3.792MB 28.208MB 404 32MB +3.792MB 35.792MB total 64MB 0 64MB

[0174] Furthermore, to illustrate the adaptive characteristics of this solution, the following section shows the adjustment over several consecutive cycles under different load scenarios.

[0175] When there are a large number of random read requests, the first cache hit rate decreases, and the miss penalty increases. For a given period, with H=0.60, P=50μs, β=(1-0.60)×(50 / 20)=0.40×2.5=1.0.

[0176] Assume that after smoothing, β_smooth=1.0. Comparing with the threshold: TL(0.8)<β_smooth(1.0)<TH(1.2), it is in the equilibrium interval, and the capacity allocation remains unchanged.

[0177] As the random read load further intensifies, in the next cycle: H=0.45, P=55μs, β=(1-0.45)×(55 / 20)=0.55×2.75=1.5125.

[0178] At this time β_smooth (about 1.45, after smoothing) > TH(1.2), triggering the strategy of expanding the first buffer.

[0179] Currently C_L_cur=28.208MB, C_D_cur=35.792MB.

[0180] Calculate Δ1=min(C_D_cur-C_D_min,k×C_Total×(β-TH))

[0181] =min(35.792-16,0.1×64×(1.45-1.2))

[0182] =min(19.792,6.4×0.25)

[0183] =min(19.792,1.6)=1.6MB

[0184] After update: C_L_new=28.208+1.6=29.808MB, C_D_new=35.792-1.6=34.192MB.

[0185] Thereafter, if the high load continues, the first buffer will continue to expand gradually with a controlled step size until the hit rate rebounds or the capacity upper limit is reached.

[0186] Further, after the random reading is finished, the storage device returns to the normal load. In a certain cycle: H=0.92, P=18μs, β=(1-0.92)×(18 / 20)=0.08×0.9=0.072.

[0187] β_smooth<TL(0.8), triggering the strategy of reducing the first buffer, and gradually returning the previously expanded space to the second buffer.

[0188] Through the above numerical examples, it can be clearly seen that: the urgency factor β unifies the hit rate and the miss penalty into a unified decision scalar; the adjustment amount is proportional to the degree of deviation of β from the threshold, realizing adaptive step size control of large steps when urgent and small steps when slow; the minimum reservation constraint ensures that any adjustment will not endanger the basic operation of the storage device 12.

[0189] Furthermore, Table 4 provides a comparison of adjustment behaviors in several typical scenarios:

[0190] Table 4:

[0191] Scene H P β_smooth Strategy Special conditions Adjustment amount correction Normal load 0.85 30μs 0.21 Reduce 402 none 2=3.79MB Random load 0.45 55μs 1.45 Expand 402 none 1=1.6MB Random reads + highly dirty data 0.45 55μs 1.45 Expand 402 Dirty data accounts for 70% > threshold 50% 1. Apply a bias, in fact 1 = 0.8MB High load + tight bandwidth 0.50 50μs 1.35 Expand 402 Bandwidth utilization is 85% > threshold 80% The proportionality coefficient K is halved. 1 = 0.8MB Tail delay deterioration 0.80 25μs 1.15 Keep P99 delay > threshold, tail delay correction β increased to 1.35 The strategy becomes expanding 402. 1 = 0.96MB

[0192] In one embodiment, the mapping table adopts a multi-level mapping structure, including at least first-level mapping entries cached in the first cache area 402 and second-level mapping entries located in the memory module 122. The cache urgency factor is a global urgency factor. The method further includes: calculating the second-level mapping urgency factor based on the local hit rate of the first-level mapping entries and the additional penalty for loading the second-level mapping entries. After determining that the capacity of the first cache area 402 needs to be expanded based on the global urgency factor, the newly added first cache area capacity is allocated proportionally to the area used for caching first-level mapping entries and the area used for caching second-level mapping entries based on the ratio of the second-level mapping urgency factor to the global urgency factor.

[0193] When the storage device 12 is a large-capacity SSD, a multi-level mapping table is often used to save cache space. The first-level mapping table is resident or partially cached in the first cache area 402, while the second-level mapping table is loaded from the memory module 122 when a cache miss occurs. This embodiment expands a single urgency factor into a multi-level urgency system. When it is determined that the total mapping table cache capacity needs to be increased, further analysis is conducted to determine whether the bottleneck is a first-level mapping miss or a second-level mapping slow loading, and the new space is allocated proportionally. For example, if the urgency factor of the second-level mapping is higher, more new capacity will be used to cache second-level mapping entries.

[0194] In one embodiment, the method further includes: the cache space 40 being at least partially provided by the host cache 1121; the memory control circuit 23 initiating a negotiation request to the host 11 carrying a desired capacity of the host cache 1121, which is calculated based on a cache urgency factor; receiving an allocation response returned by the host 11, which includes the actual approved capacity of the host cache 1121 by the host 11; and adjusting the capacity allocation of the first cache 402 and the second cache 404 according to the actual approved capacity of the host cache 1121 by the host 11.

[0195] For example, when the memory control circuit 23 detects that the capacity of the buffer memory 24 is insufficient to meet the mapping table cache requirements, and the cache urgency factor remains above the first threshold, it calculates the desired size of the host cache area 1121 to be requested from the host 11 based on the value of the urgency factor, and sends a request to the host 11 via HMB (Host Memory Buffering) related commands of protocols such as NVMe. The host 11 approves all or part of the capacity according to its own memory 112 usage and returns the physical memory address descriptor to the memory control circuit 23. The memory control circuit 23 incorporates the obtained HMB space into the cache space for unified management and prioritizes its allocation to the first cache area 402 to alleviate the mapping table cache pressure. This mechanism extends the adaptive cache management capability of the storage device 12 to the host 11, realizing dynamic resource allocation across the bus.

[0196] In one embodiment, the method further includes: monitoring the depth change trend of the submission queue of the host 11, and when the queue depth is detected to surge in a short period of time and exceed a preset queue threshold, before the monitoring period ends and the cache hit rate within the current period window is calculated, actively triggering an operation to pre-allocate the capacity of the second cache area to the first cache area.

[0197] A surge in host commit queue depth is a priori signal of impending random read load. Preemptively expanding the first cache area helps to reconfigure cache resources before the hit rate deteriorates, thus compensating for the lag in periodic monitoring. The aforementioned pre-allocated cache adjustment amount is determined based on the increase in queue depth and a preset mapping relationship.

[0198] In practical applications, a sharp increase in the host's I / O queue depth is often a precursor to increased random read demand. If we wait until the end of a full monitoring cycle to react based on the calculated hit rate change, we may have already missed the optimal adjustment window. This embodiment utilizes queue depth as a priori signal to anticipate upcoming load changes before the hit rate deteriorates, preemptively allocating some data cache capacity to the mapping table cache, thereby preparing for the upcoming random read peak with lower response latency. This effectively compensates for the lag inherent in periodic monitoring, giving the adjustment strategy both reactive and predictive advantages.

[0199] In one embodiment, when the number of blank blocks in the free pool is less than a threshold (e.g., 20 or 5% of the total number of blocks in memory module 122) and garbage collection needs to be initiated, the operation of allocating the capacity of the first cache 402 to the second cache 404 is suppressed. When the number of blank blocks in the free pool is greater than this threshold, if the storage device 12 is currently in a high-pressure state of the first cache, an operation of allocating the capacity of the second cache to the first cache is actively triggered.

[0200] Garbage collection operations consume a significant amount of bus bandwidth in the memory module 122. If the capacity of the first cache is further reduced to expand the data cache at this time, it may further congest data write-back and flash memory access. This embodiment links cache adjustment with garbage collection operations, freezing the adjustment operations that tilt towards the data cache when garbage collection is active, ensuring the smooth execution of garbage collection. Once garbage collection is complete, the operation to expand the first cache is then performed. This approach adapts the cache space management method to the actual needs of the storage device 12, because a smaller number of free blocks will cause a sharp drop in data write speed. The ultimate goal of the algorithm is to optimize the data read and write speed of the storage device 12.

[0201] In one embodiment, the method further includes: continuously monitoring the total available capacity of the cache space 40, and triggering an emergency mode when the total available capacity is lower than a preset critical water shortage threshold; in the emergency mode, marking the key metadata, directory structure, and logical-to-physical address mapping entries related to the currently processed host command of the storage device 12 in the first cache area 402 as locked; any subsequent capacity adjustment operations shall prohibit the eviction of entries marked as locked.

[0202] Under extreme memory pressure, without protection, conventional eviction mechanisms may remove critical mapping entries and / or bad block management tables (including block erase / write count tables) that maintain the basic operation of storage device 12 from the cache, causing storage device 12 to enter an unrecoverable error state. This embodiment sets up a last line of defense: once emergency mode is triggered, these core entries are immediately identified and locked, and they are not allowed to be evicted subsequently, regardless of changes in the urgency factor. This ensures that the basic functions and data integrity of storage device 12 are not lost under the worst memory conditions, significantly improving the reliability of storage device 12.

[0203] Figures 5 to 9 Each step has been explained in detail above and will not be repeated here. It is worth noting that... Figures 5 to 9 Each step can be implemented as multiple program codes or circuits, and this application does not impose any limitations. Furthermore, Figures 5 to 9 The method can be used in conjunction with the above examples and embodiments, or it can be used alone; this application does not impose any restrictions.

[0204] In summary, the cache space management method and storage device provided in the embodiments of this application, by defining and calculating the cache urgency factor and using the expected performance loss of the mapping table cache as the decision input, achieve adaptive and quantitative adjustment of the capacity of the first and second cache areas. Compared with fixed partitioning or schemes that rely solely on a single hit rate, this application can optimize cache space management in various scenarios such as random reads, sequential writes, and mixed loads, thereby improving the cache hit rate, reducing the number of accesses to the memory module, reducing access latency and write amplification, and extending the lifespan of the storage device.

[0205] The above description of the embodiments is only for the purpose of helping to understand the method and core ideas of this application. It should be noted that, for those skilled in the art, several improvements and modifications can be made to this application without departing from the principles of this application, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A cache space management method, characterized in that, Applied to a storage device, the storage device including a memory controller and a cache space, the cache space including a first cache area and a second cache area, wherein the first cache area is used to store a mapping table and the second cache area is used to store user data, the method includes: Obtain metrics for adaptively adjusting cache resource allocation in the cache space, including cache hit rate of the first cache area, average cache miss penalty value of the first cache area, and preset baseline miss penalty threshold; Based on the cache hit rate, the average cache miss penalty value, and the baseline miss penalty threshold, a cache urgency factor for determining the cache space caching strategy is calculated. The cache urgency factor is calculated as follows: subtract the cache hit rate from 1 to obtain the cache miss rate, divide the average cache miss penalty value by the baseline miss penalty threshold to obtain the penalty ratio, and then multiply the cache miss rate by the penalty ratio. The caching strategy for the cache space is determined based on the cache urgency factor and the preset first and second thresholds. In response to the caching strategy of allocating a portion of the capacity of the second cache to the first cache, the difference between the current capacity of the second cache and the minimum reserved cache capacity of the second cache is calculated, and the product of the scaling factor, the total cache capacity of the cache space, and the portion of the cache urgency factor exceeding the first threshold is calculated. The smaller of the difference and the product is taken as the first cache adjustment amount. Alternatively, in response to the caching strategy of allocating a portion of the capacity of the first cache to the second cache, the difference between the current capacity of the first cache and the minimum reserved cache capacity of the first cache is calculated, and the product of the scaling factor, the total cache capacity of the cache space, and the portion of the second threshold exceeding the cache urgency factor is calculated. The smaller of the difference and the product is taken as the second cache adjustment amount. The capacity allocation of the first cache area and the second cache area in the cache space is adaptively adjusted according to the first cache adjustment amount or the second cache adjustment amount.

2. The method according to claim 1, characterized in that, The step of determining the caching strategy for the cache space based on the cache urgency factor and preset first and second thresholds includes: In response to the cache urgency factor being greater than the first threshold, the cache policy is determined to allocate a portion of the capacity of the second cache area to the first cache area; In response to the cache urgency factor being less than the second threshold, the cache policy is determined to allocate a portion of the capacity of the first cache area to the second cache area; In response to the cache urgency factor being greater than or equal to the second threshold and less than or equal to the first threshold, the cache strategy is determined to maintain the current capacity allocation of the first cache area and the second cache area unchanged. Wherein, the first threshold is greater than the second threshold.

3. The method according to claim 2, characterized in that, The step of determining the caching strategy to allocate a portion of the capacity of the second cache to the first cache in response to the cache urgency factor being greater than the first threshold includes: Determine the capacity of the second cache area that needs to be reduced, and based on the read / write ratio of the current workload, prioritize reducing the capacity of data type sub-pools that do not match the current dominant load pattern. The second cache area includes multiple data type sub-pools, and the data type sub-pools include at least a write cache sub-pool for caching sequential write data and a read cache sub-pool for caching random read data.

4. The method according to claim 1, characterized in that, The method includes: The average cache miss penalty value includes a first statistical value and a second statistical value. The first statistical value is the average latency within the monitoring window, and the second statistical value is the percentile of the miss latency within the monitoring window. The calculation of the cache urgency factor of the cache space includes: The penalty fluctuation coefficient is calculated based on the first statistical value and the second statistical value, wherein the penalty fluctuation coefficient represents the jitter amplitude of the miss delay; The initial urgency factor calculated by the penalty fluctuation coefficient is corrected so that when the second statistical value exceeds the preset latency threshold, the cache urgency factor is increased to reflect the risk of user experience degradation caused by latency jitter.

5. The method according to claim 1, characterized in that, The user data includes clean data and dirty data to be written back to the memory module in the storage device; the method further includes: Obtain the proportion of dirty data in the second cache area; When the caching strategy is determined to allocate part of the capacity of the second cache area to the first cache area, if the proportion of dirty data exceeds a preset dirty data threshold, a shrinking bias is applied to the calculated first cache adjustment amount to prioritize the residence space of dirty data and reduce additional write-back operations triggered by cache shrinkage.

6. The method according to claim 1, characterized in that, The step of adaptively adjusting the capacity allocation of the first cache area and the second cache area in the cache space according to the first cache adjustment amount includes: The adjusted capacity of the first cache is determined based on the sum of the first cache adjustment amount and the current capacity of the first cache. The adjusted capacity of the second cache is determined based on the difference between the current capacity of the second cache and the adjustment amount of the first cache. The allocation of cache resources in the cache space is adjusted based on the adjusted capacities of the first and second cache areas.

7. The method according to claim 1, characterized in that, The adaptive adjustment of the capacity allocation of the first and second cache regions in the cache space includes: The adjusted capacity of the first cache is determined based on the difference between the current capacity of the first cache and the adjustment amount of the second cache. The adjusted capacity of the second cache is determined based on the sum of the second cache adjustment amount and the current capacity of the second cache. The allocation of cache resources in the cache space is adjusted based on the adjusted capacities of the first and second cache areas.

8. The method according to claim 1, characterized in that, The method further includes: Before adaptively adjusting the capacity allocation of the first and second cache areas in the cache space according to the cache adjustment amount, the additional overhead that will be introduced by performing this capacity adjustment operation is estimated. The additional overhead includes at least the metadata update overhead triggered by the evicted entries and the dirty data write-back overhead that may be triggered. The additional overhead is compared with the expected performance gains after performing this capacity adjustment, which are estimated based on the cache urgency factor and the cache adjustment amount. The capacity adjustment operation is performed only if the performance gain outweighs the additional overhead.

9. The method according to claim 1, characterized in that, The method further includes: The mapping table adopts a multi-level mapping structure, and includes at least a first-level mapping entry cached in the first cache area and a second-level mapping entry located in the memory module of the storage device; the cache urgency factor is a global urgency factor; The method further includes: Calculate the secondary mapping urgency factor based on the local hit rate of the primary mapping entry and the additional penalty for loading the secondary mapping entry; After determining that the capacity of the first cache area needs to be expanded based on the global urgency factor, the newly added capacity is allocated proportionally to the first-level mapping entry area and the second-level mapping entry cache area according to the ratio of the second-level mapping urgency factor to the global urgency factor.

10. The method according to claim 1, characterized in that, The method further includes: The cache space is at least partially provided by the host cache. Initiate a negotiation request to the host, the request carrying the desired host cache size, the desired host cache size being calculated based on the cache urgency factor; Receive an allocation response returned by the host, the allocation response containing the actual memory buffer capacity approved by the host; Adjust the capacity allocation of the first cache and the second cache based on the actual approved memory buffer capacity of the host.

11. The method according to claim 1, characterized in that, The method further includes: Monitor the depth change trend of the host's submission queue; When a surge in queue depth is detected within a short period of time and exceeds a preset queue threshold, before the monitoring period ends and the cache hit rate within the current period window is calculated, an operation is actively triggered to pre-allocate the capacity of the second cache area to the first cache area. The pre-allocated cache adjustment amount is determined based on the increase in the queue depth and a preset mapping relationship.

12. A storage device, characterized in that, include: A connection interface for electrically connecting to a host computer; The memory module includes multiple planes, each plane includes multiple blocks, and each block includes multiple physical pages; as well as The memory controller includes an error checking and correction circuit, a buffer memory, and a memory control circuit, and is electrically connected to the connection interface and the memory module; The cache space is provided by one or more storage media, including the buffer memory, dynamic random access memory, and host cache. The memory control circuit is configured to perform the cache space management method as described in any one of claims 1 to 11.

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