A server backplane level connectivity system

Abstract

This application provides a server backplane cascading system, including motherboards and N backplanes cascaded sequentially. A master device is connected to the first end of a motherboard interface expander and the motherboard connector via a bus. The second end of the motherboard interface expander is connected to the ID signal terminal of the motherboard connector. In the i-th backplane, the first connector is connected to the second connector via a bus, and slave modules are mounted on the bus between the first and second connectors. The ID signal terminal of the first connector is connected to the address terminal of the slave module and the input terminal of the cascading logic circuit, respectively. The output terminal of the cascading logic circuit is connected to the ID signal terminal of the second connector via the slave module. After the master device determines that each backplane is in place, it provides an initial ID signal to the first backplane via the motherboard interface expander. The cascading logic circuit in each backplane controls the ID of each backplane to automatically increment, ensuring that the addresses of slave modules in different backplanes do not conflict.

Description

Technical Field

[0001] This application relates to the field of server technology, and more specifically, to a server backplane cascading system. Background Technology

[0002] Existing server hard drive backplanes often employ a modular design. Furthermore, to save on design and development costs and BOM (Bill of Materials) maintenance costs, each hard drive backplane uses the same model number. The current connection scheme between the server motherboard and multiple backplanes is as follows: the motherboard has an I2C (Inter-Integrated Circuit) master device, an I2C switch chip, and multiple motherboard connectors; each backplane has an I2C slave device and a backplane connector. The I2C master device connects to the I2C switch chip, which in turn connects to multiple motherboard connectors. Each motherboard connector connects to a backplane connector on a separate backplane via a dedicated long cable to communicate with the I2C slave devices on each backplane. The addresses of the I2C slave devices on each backplane are isolated by the I2C switch chip to avoid conflicts.

[0003] However, the existing solution has the following problems: On the one hand, the I2C switching chip and multiple motherboard connectors on the motherboard will occupy more motherboard PCB (Printed Circuit Board) area, resulting in increased costs; on the other hand, the cables inside the server chassis will occupy the heat dissipation airflow, which is not conducive to the heat dissipation of high-heat system components such as the central processing unit and graphics processor, and the existing solution requires the use of multiple long cables to connect the motherboard and backplane, which is not conducive to the overall heat dissipation of the system. Summary of the Invention

[0004] The purpose of this application is to provide a server backplane cascading system to solve the problems existing in the prior art.

[0005] To achieve the above objectives, the technical solution adopted in this application is as follows: This application provides a server backplane cascading system, including a motherboard and N backplanes; the motherboard includes a master device, a motherboard interface expander, and a motherboard connector; each backplane includes a first connector, a second connector, a slave device module, and cascading logic circuitry; The main device is connected to the first end of the motherboard interface expander and the motherboard connector via a bus. The second end of the motherboard interface expander is connected to the ID signal end of the motherboard connector. N backplanes are cascaded in sequence. The first connector of the first backplane is connected to the motherboard connector, and the first connectors of the remaining backplanes are connected to the second connectors of the previous backplane. In the i-th backplane, the first connector is connected to the second connector via a bus, and the slave module is mounted on the bus between the first connector and the second connector; the ID signal terminal of the first connector is connected to the address terminal of the slave module and the input terminal of the cascaded logic circuit, respectively, and the output terminal of the cascaded logic circuit is connected to the ID signal terminal of the second connector via the slave module; where 1≤i≤N, N≥2; After the master device determines that each level of backplane is in place, the master device provides an initial ID signal to the first backplane through the motherboard interface expander, and controls the ID of each level of backplane to automatically increment through the cascaded logic circuit in each level of backplane, so that the addresses of slave device modules in different backplanes do not conflict with each other.

[0006] Furthermore, the motherboard also includes a first upper bias circuit, each backplane also includes a lower bias circuit and a second upper bias circuit, and the slave device module includes a backplane interface expander; One end of the first upper bias circuit is connected to the ID signal terminal of the motherboard connector, and the other end of the first upper bias circuit is connected to the power supply. In the i-th backplane, the backplane interface extender is mounted on the bus between the first connector and the second connector; the ID signal terminal of the first connector is connected to the address terminal of the backplane interface extender, the input terminal of the cascaded logic circuit, and one end of the lower bias circuit, respectively. The other end of the lower bias circuit is grounded. The output terminal of the cascaded logic circuit is connected to the first end of the backplane interface extender, and the second end of the backplane interface extender is connected to the ID signal terminal of the second connector; one end of the second upper bias circuit is connected to the ID signal terminal of the second connector, and the other end of the second upper bias circuit is connected to the power supply. Under the action of the first upper bias circuit, the lower bias circuit, and the second upper bias circuit, the master device is used to read the level status of the second terminal of the motherboard interface expander and each backplane interface expander through the bus to detect the presence status of each level of backplane.

[0007] Furthermore, when the master device reads that the second terminal of the motherboard interface expander is low via the bus, the master device determines that the first backplane is in place; When the master device reads that the second terminal of the motherboard interface expander is high through the bus, the master device determines that the first backplane is not in place; When the master device reads through the bus that the second terminal of the backplane interface extender of the xth backplane is low, the master device determines that the (x+1)th backplane is in place; When the master device reads through the bus that the second terminal of the backplane interface extender of the xth backplane is at a high level, the master device determines that the (x+1)th backplane is not in place; where 1≤x≤N-1.

[0008] Furthermore, each connector includes a bus signal terminal and M ID signal terminals; the first end of the motherboard interface expander includes a bus signal interface, and the second end includes M IO interfaces; the first end of the backplane interface expander includes M IO interfaces, and the second end includes M IO interfaces; wherein, M≥2; The motherboard interface expander is connected to the first connector of the first backplane, and the second connectors of the two adjacent backplanes are connected to the first connector via cables to transmit bus signals and M-bit ID signals.

[0009] Furthermore, M=2, and the cascaded logic circuit includes an XOR gate and an inverter; In the i-th backplane, the first ID signal terminal and the second ID signal terminal of the first connector are respectively connected to the first address terminal and the second address terminal of the backplane interface extender to set the lowest 2 bits of the backplane interface extender address; wherein, the ID value of the i-th backplane is equal to the lowest 2 bits of its backplane interface extender address. The first ID signal terminal of the first connector is also connected to the first input terminal of the XOR gate and the input terminal of the inverter, respectively; the second ID signal terminal of the first connector is also connected to the second input terminal of the XOR gate. The output of the XOR gate is connected to the first IO interface of the backplane interface expander, and the output of the inverter is connected to the second IO interface of the backplane interface expander. The third I / O interface of the backplane interface extender is connected to the second ID signal terminal of the second connector, and the fourth I / O interface of the backplane interface extender is connected to the first ID signal terminal of the second connector.

[0010] Furthermore, when the main device is in the backplane presence detection state, the main device sets all four IO interfaces of the backplane interface expander in the xth backplane to be input interfaces, and determines whether the (x+1)th backplane is in place by reading the input level values ​​of the third and fourth IO interfaces; where 1≤x≤N-1; After the master device determines that the (x+1)th backplane is in place, the master device changes the third and fourth IO interfaces of the backplane interface extender in the xth backplane to output interfaces, and sets the output level of the third IO interface to be equal to the input level of the first IO interface, and sets the output level of the fourth IO interface to be equal to the input level of the second IO interface, so as to transmit the output level values ​​of the third and fourth IO interfaces to the (x+1)th backplane, which is used to set the ID value of the (x+1)th backplane and the lowest two bits of its backplane interface extender address.

[0011] Furthermore, M=3, and the cascaded logic circuit includes an XOR gate, an inverter, an AND gate, and an OR gate; In the i-th backplane, the first ID signal terminal, the second ID signal terminal, and the third ID signal terminal of the first connector are respectively connected to the first address terminal, the second address terminal, and the third address terminal of the backplane interface extender to set the lowest 3 bits of the backplane interface extender address; wherein, the ID value of the i-th backplane is equal to the lowest 3 bits of its backplane interface extender address; The first ID signal terminal of the first connector is also connected to the first input terminal of the XOR gate, the input terminal of the inverter, and the first input terminal of the AND gate, respectively. The second ID signal terminal of the first connector is also connected to the second input terminal of the XOR gate and the second input terminal of the AND gate, respectively. The output terminal of the AND gate is connected to the first input terminal of the OR gate, and the third ID signal terminal of the first connector is connected to the second input terminal of the OR gate. The output of the XOR gate is connected to the first IO interface of the backplane interface expander, the output of the inverter is connected to the second IO interface of the backplane interface expander, and the output of the OR gate is connected to the fifth IO interface of the backplane interface expander. The third IO interface of the backplane interface extender is connected to the second ID signal terminal of the second connector, the fourth IO interface of the backplane interface extender is connected to the first ID signal terminal of the second connector, and the sixth IO interface of the backplane interface extender is connected to the third ID signal terminal of the second connector.

[0012] Furthermore, when the main device is in the backplane presence detection state, the main device sets all 6 IO interfaces of the backplane interface expander in the xth backplane to be input interfaces, and determines whether the (x+1)th backplane is in place by reading the input level values ​​of the third, fourth, and sixth IO interfaces; where 1≤x≤N-1; After the master device determines that the (x+1)th backplane is in place, the master device changes the third, fourth, and sixth IO interfaces of the backplane interface extender in the xth backplane to output interfaces, and sets the output level of the third IO interface to be equal to the input level of the first IO interface, sets the output level of the fourth IO interface to be equal to the input level of the second IO interface, and sets the output level of the sixth IO interface to be equal to the input level of the fifth IO interface, so as to transmit the output level values ​​of the third, fourth, and sixth IO interfaces to the (x+1)th backplane, which is used to set the ID value of the (x+1)th backplane and the lowest 3 bits of its backplane interface extender address.

[0013] Furthermore, the bus signal terminal of the motherboard connector and the bus signal interface of the motherboard interface expander are both connected to the host device, each IO interface of the motherboard interface expander is connected to the corresponding ID signal terminal of the motherboard connector, and each ID signal terminal of the motherboard connector is connected to the first upper bias circuit. In the i-th backplane, the bus signal terminal of the first connector is connected to the bus signal terminal of the second connector; each ID signal terminal of the first connector is connected to the lower bias circuit, the address terminal of the backplane interface expander, and the input terminal of the cascaded logic circuit, respectively; each IO interface of the first end of the backplane interface expander is connected to the output terminal of the cascaded logic circuit, each IO interface of the second end is connected to the corresponding ID signal terminal of the second connector, and each ID signal terminal of the second connector is connected to the second upper bias circuit.

[0014] Furthermore, the slave device module also includes a temperature sensor, a memory, and a complex programmable logic device; In the i-th backplane, the temperature sensor, the memory, and the complex programmable logic device are all mounted on the bus between the first connector and the second connector; the ID signal terminal of the first connector is also connected to the address terminal of the temperature sensor, the address terminal of the memory, and the address terminal of the complex programmable logic device, respectively.

[0015] Compared with the prior art, this application has the following advantages: The server backplane cascading system provided in this application includes a motherboard and N backplanes. The motherboard includes a master device, a motherboard interface expander, and a motherboard connector. Each backplane includes a first connector, a second connector, a slave device module, and cascading logic circuitry. The master device is connected to the first end of the motherboard interface expander and the motherboard connector via a bus. The second end of the motherboard interface expander is connected to the ID signal terminal of the motherboard connector. The N backplanes are cascaded sequentially. The first connector of the first backplane is connected to the motherboard connector, and the first connectors of the remaining backplanes are connected to the second connector of the previous backplane. In the i-th backplane, the first connector is connected to the second connector via a bus, and the slave device module is mounted on the bus between the first and second connectors. The ID signal terminal of the first connector is connected to the address terminal of the slave device module and the input terminal of the cascading logic circuitry, respectively. The output terminal of the cascading logic circuitry is connected to the ID signal terminal of the second connector via the slave device module. Where 1 ≤ i ≤ N, and N ≥ 2. After the master device confirms that each level of backplane is in place, the master device provides an initial ID signal to the first backplane through the motherboard interface expander. The master device controls the ID of each level of backplane to automatically increment through the cascaded logic circuits in each level of backplane, so that the addresses of slave device modules in different backplanes do not conflict with each other.

[0016] Because this application uses a cascaded backplane configuration, adjacent backplanes can be connected with extremely short cables, thereby reducing the space occupied by cables inside the chassis and improving heat dissipation. Furthermore, the motherboard does not require an I2C switch chip or multiple motherboard connectors; only one motherboard connector is needed to connect multiple backplanes, reducing the motherboard PCB area and lowering costs. In addition, this application uses cascaded logic circuitry to automatically increment the ID values ​​of each backplane level and automatically set the addresses of slave device modules in each backplane level, thus avoiding conflicts caused by identical addresses between different backplanes. This ensures that even without an I2C switch chip, the master device can directly address and access slave device modules on any level of backplane via the cascaded bus. Attached Figure Description

[0017] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0018] Figure 1 A circuit diagram showing the connection between an existing server motherboard and multiple backplanes; Figure 2 One of the circuit diagrams of a server backplane cascading system provided in this application; Figure 3 A second circuit diagram of a server backplane cascading system provided in this application; Figure 4 A schematic diagram illustrating the process of the main equipment for detecting whether the first backplane is in place, as provided in this application; Figure 5 A schematic diagram illustrating the process of the main equipment for detecting whether the second backplane is in place, provided in this application; Figure 6 The third circuit diagram of a server backplane cascading system provided in this application.

[0019] Icons: 100 - Motherboard; 110 - Master device; 120 - Motherboard interface expander; 130 - Motherboard connector; 140 - First upper bias circuit; 200 - Backplane; 210 - First connector; 220 - Second connector; 230 - Slave module; 231 - Backplane interface expander; 232 - Temperature sensor; 233 - Memory; 234 - Complex programmable logic device; 240 - Cascaded logic circuit; 250 - Lower bias circuit; 260 - Second upper bias circuit; U1 - XOR gate; U2 - Inverter; U3 - AND gate; U4 - OR gate. Detailed Implementation

[0020] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0021] In the description of this application, it should be noted that relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. The term "connection" should be interpreted broadly, for example, it can refer to a direct connection or an indirect connection through an intermediate medium. The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0022] As described in the background section, existing server hard drive backplanes often employ a modular design, such as 8-bay or 4-bay backplanes per backplane. The front panel of a 2U chassis typically accommodates 12 3.5-inch hard drives or 24 2.5-inch hard drives. When using 3.5-inch hard drives, a 4-bay backplane is used; depending on the configuration requirements, one, two, or three backplanes can be installed, supporting 4, 8, or 12 hard drives respectively. When using 2.5-inch hard drives, an 8-bay backplane is used; depending on the configuration requirements, one, two, or three backplanes can be installed, supporting 8, 16, or 24 hard drives respectively. To save on design and development costs and BOM maintenance costs, backplanes of the same model are usually used.

[0023] Existing server motherboard and multiple backplane connection solutions, such as Figure 1 As shown, backplanes 1 through m are all identical hard drive backplanes, each with a backplane connector and multiple I2C slave devices. Since backplanes 1 through m are all the same model, all I2C slave devices share the same address. To resolve address conflicts, the motherboard includes an I2C master device, an I2C switch chip, and m motherboard connectors. The I2C master device connects to the I2C switch chip, which in turn connects to each of the m motherboard connectors. Each motherboard connector connects to a backplane connector on a separate backplane via a dedicated long cable, allowing communication with the I2C slave devices on each backplane. The I2C slave device addresses on each backplane are isolated by the I2C switch chip to avoid address conflicts. Specifically, the I2C switch chip time-division multiplexes the I2C bus of the I2C master device to different backplanes, ensuring that only one backplane communicates with the I2C master device at any given time, thus preventing conflicts between I2C slave devices with the same address.

[0024] However, the existing solutions have the following problems: (1) As CPUs (Central Processing Units) integrate more and more functions, their size and number of pins increase. Simultaneously, PCIe signal rates have upgraded from 16G in 4.0 to 32G in 5.0 and even higher rates in 6.0 and 7.0, leading to a continuous increase in PCB material costs. To control costs, the smaller the PCB area of ​​the motherboard, the better. However, in existing solutions, the I2C switching chip and multiple motherboard connectors occupy more PCB area, resulting in increased costs.

[0025] (2) As the power consumption of modern CPUs increases, their TDP (thermal design power) reaches 500W or even higher, while the power consumption of components such as GPUs (Graphics Processing Units) is also constantly increasing. Cables inside the server chassis will occupy the heat dissipation airflow, affecting the heat dissipation effect of high-heat system components such as CPUs and GPUs. However, existing solutions require the use of multiple long cables to connect the motherboard and backplate, which exacerbates the occupation of airflow by cables and is not conducive to the overall heat dissipation of the system.

[0026] In view of this, please refer to Figure 2 This application provides a server backplane cascading system, which includes a motherboard 100 and N backplanes 200, wherein N ≥ 2.

[0027] The motherboard 100 includes a master device 110, a motherboard interface expander 120, and a motherboard connector 130. Each backplane 200 includes a first connector 210, a second connector 220, a slave device module 230, and cascaded logic circuitry 240.

[0028] Optionally, the master device 110 can be an I2C master device, such as a BMC (Baseboard Management Controller).

[0029] The master device 110 is connected to the first end of the motherboard interface expander 120 and the motherboard connector 130 via a bus (such as an I2C bus). The second end of the motherboard interface expander 120 is connected to the ID signal terminal of the motherboard connector 130. N backplanes 200 are cascaded in sequence. The first connector 210 on the first backplane 200 is connected to the motherboard connector 130 via a cable. The first connectors 210 of the remaining backplanes 200 are connected to the second connectors 220 of the previous backplane 200 via cables.

[0030] In the i-th backplane 200, the first connector 210 is connected to the second connector 220 via a bus, and the slave device module 230 is mounted on the bus between the first connector 210 and the second connector 220. The ID signal terminal of the first connector 210 is connected to the address terminal of the slave device module 230 and the input terminal of the cascaded logic circuit 240, respectively. The output terminal of the cascaded logic circuit 240 is connected to the ID signal terminal of the second connector 220 via the slave device module 230. Where 1 ≤ i ≤ N.

[0031] After the master device 110 determines that each level of backplane 200 is in place, the master device 110 provides an initial ID signal to the first backplane 200 through the motherboard interface expander 120, and controls the ID of each level of backplane 200 to automatically increment through the cascaded logic circuit 240 in each level of backplane 200, so that the addresses of the slave device modules 230 in different backplanes 200 do not conflict with each other.

[0032] Understandably, the server backplane cascading system provided in this application replaces the star topology of the prior art, where the motherboard is connected to multiple backplanes via I2C switching chips, by means of backplane cascading. This application has the following advantages: (1) There is no need to set up an I2C switching chip and multiple motherboard connectors 130 on the motherboard 100. Only one motherboard connector 130 is needed to connect multiple backplanes 200, thereby reducing the area occupied by the motherboard PCB and reducing the overall cost.

[0033] (2) This application adopts the form of backplane cascading, which not only meets the needs of server modular design, but also enables the connection between adjacent backplanes 200 with extremely short cables, thereby reducing the space occupied by cables inside the chassis, improving heat dissipation conditions, and reducing the difficulty and complexity of system structure and heat dissipation design.

[0034] (3) The automatic increment of the ID value of each backplane and the automatic setting of the address of the slave device module 230 in each backplane 200 are realized through the cascaded logic circuit 240, thereby avoiding the conflict caused by the same address between different backplanes 200; ensuring that in the absence of an I2C switching chip, the master device 110 can directly address and access the slave device module 230 on any level of backplane 200 through the cascaded bus.

[0035] In one alternative implementation, please refer to Figure 3 The motherboard 100 also includes a first upper bias circuit 140, each backplane 200 also includes a lower bias circuit 250 and a second upper bias circuit 260, and the slave module 230 includes a backplane interface expander 231.

[0036] One end of the first upper bias circuit 140 is connected to the ID signal terminal of the motherboard connector 130 (that is, one end of the first upper bias circuit 140 is connected to the signal line between the second end of the motherboard interface expander 120 and the ID signal terminal of the motherboard connector 130), and the other end of the first upper bias circuit 140 is connected to the power supply VCC.

[0037] In the i-th backplane 200 (equivalent to in each backplane 200), the backplane interface extender 231 is connected to the bus between the first connector 210 and the second connector 220. The ID signal terminal of the first connector 210 is connected to the address terminal of the backplane interface extender 231, the input terminal of the cascaded logic circuit 240, and one end of the lower bias circuit 250. The other end of the lower bias circuit 250 is grounded. The output terminal of the cascaded logic circuit 240 is connected to the first end of the backplane interface extender 231, and the second end of the backplane interface extender 231 is connected to the ID signal terminal of the second connector 220. One end of the second upper bias circuit 260 is connected to the ID signal terminal of the second connector 220 (i.e., one end of the second upper bias circuit 260 is connected to the signal line between the second end of the backplane interface extender 231 and the ID signal terminal of the second connector 220), and the other end of the second upper bias circuit 260 is connected to the power supply VCC.

[0038] Under the action of the first upper bias circuit 140, the lower bias circuit 250, and the second upper bias circuit 260, the master device 110 is used to read the level status of the second terminal of the motherboard interface expander 120 and each backplane interface expander 231 through the bus to detect the presence status of each level of backplane 200.

[0039] For the first backplane 200, the in-situ detection method is as follows: When the first backplane 200 is in place, the second end of the motherboard interface expander 120 is connected to the lower bias circuit 250 in the first backplane 200 via the ID signal terminal of the motherboard connector 130, the cable, and the ID signal terminal of the first connector 210 in the first backplane 200, and is thus pulled low to a low level by the lower bias circuit 250.

[0040] When the first backplane 200 is not in place, the first backplane 200 is not connected to the system, and there is no electrical connection between its lower bias circuit 250 and the motherboard 100. The second end of the motherboard interface expander 120 is connected to the power supply VCC through the first upper bias circuit 140, and is thus pulled high.

[0041] Therefore, when the master device 110 reads that the second terminal of the motherboard interface expander 120 is low through the bus, the master device 110 determines that the first backplane 200 is in place; when the master device 110 reads that the second terminal of the motherboard interface expander 120 is high through the bus, the master device 110 determines that the first backplane 200 is not in place.

[0042] For the (x+1)th backplane 200 (where 1≤x≤N-1, i.e., for the 2nd to Nth backplanes 200), its in-situ detection method is as follows: When the (x+1)th backplane 200 is in place, the second end of the backplane interface extender 231 in the xth backplane 200 is connected to the lower bias circuit 250 in the (x+1)th backplane 200 via the ID signal terminal of the second connector 220 in the xth backplane 200, the cable, and the ID signal terminal of the first connector 210 in the x+1th backplane 200, thereby being pulled low to a low level.

[0043] When the (x+1)th backplane 200 is not in place, the (x+1)th backplane 200 is not connected to the system, and there is no electrical connection between its lower bias circuit 250 and the xth backplane 200. The second end of the backplane interface extender 231 in the xth backplane 200 is connected to the power supply VCC through the second upper bias circuit 260, and is thus pulled high.

[0044] Therefore, when the master device 110 reads through the bus that the second terminal of the backplane interface expander 231 of the xth backplane 200 is low, the master device 110 determines that the (x+1)th backplane 200 is in place; when the master device 110 reads through the bus that the second terminal of the backplane interface expander 231 of the xth backplane 200 is high, the master device 110 determines that the (x+1)th backplane 200 is not in place.

[0045] It should be noted that since N backplanes 200 are cascaded sequentially, the (x+1)th backplane 200 is in place only if all its preceding backplanes 200 are in place. Therefore, when the master device 110 detects that the (x+1)th backplane 200 is in place, it means that all backplanes 200 from the first to the (x+1)th backplane are in place.

[0046] Optionally, both the first upper bias circuit 140 and the second upper bias circuit 260 are composed of multiple pull-up resistors, and the lower bias circuit 250 is composed of multiple pull-down resistors. The resistance value of the pull-up resistors is greater than the resistance value of the pull-down resistors to ensure that each interface expander can correctly recognize the low level after voltage division. For example, the resistance value of the pull-up resistors is 10KΩ, and the resistance value of the pull-down resistors is 1KΩ.

[0047] In an alternative implementation, the device module 230 further includes a temperature sensor 232, a memory 233, and a complex programmable logic device (CPLD) 234.

[0048] In the i-th backplane 200, the temperature sensor 232, the memory 233, and the complex programmable logic device 234 are all connected to the bus between the first connector 210 and the second connector 220. The ID signal terminal of the first connector 210 is also connected to the address terminals of the temperature sensor 232, the memory 233, and the complex programmable logic device 234, respectively.

[0049] Understandably, each backplane 200 is equipped with I2C slave devices such as a backplane interface expander 231, a temperature sensor 232, a memory 233, and a complex programmable logic device 234. The backplane interface expander 231 is used to implement backplane presence detection (e.g., the master device 110 reads the level state of the second terminal of the backplane interface expander 231 in its own backplane via the bus to determine whether the next-level backplane is present) and backplane ID transmission (e.g., receiving the backplane ID signal as its own address and outputting the next-level backplane ID signal processed by the cascaded logic circuit 240). The temperature sensor 232 is used to monitor the temperature of the backplane 200, the memory 233 is used to store the backplane 200 configuration information, and the complex programmable logic device 234 is used to control the hard disk power supply, reset timing, etc. When a backplane 200 is in place, the ID value of the backplane 200 and the address of its I2C slave device are set by the ID signal transmitted from the first connector 210 in the backplane 200. Different backplanes 200 have different backplane ID values ​​(the backplane ID value automatically increases step by step), and their slave device addresses are also different, thereby avoiding address conflicts across backplanes.

[0050] In one alternative implementation, each connector (i.e., motherboard connector 130, each first connector 210, and each second connector 220) includes one bus signal terminal and M ID signal terminals. The first end of the motherboard interface expander 120 includes one bus signal interface, and the second end of the motherboard interface expander 120 includes M I / O interfaces. The first end of the backplane interface expander 231 includes M I / O interfaces, and the second end of the backplane interface expander 231 also includes M I / O interfaces. Where M ≥ 2.

[0051] The motherboard interface expander 120 is connected to the first connector 210 of the first backplane 200, and the second connector 220 of the two adjacent backplanes 200 is connected to the first connector 210 via cables to transmit bus signals and M-bit ID signals.

[0052] With the above connection method, only one cable is needed to transmit bus signals and M-bit ID signals between the motherboard 100 and the first backplate 200, as well as between the two adjacent backplates 200. No additional signal lines are required, which simplifies cable connection and reduces cost and space occupation.

[0053] Furthermore, the bus signal terminals of the motherboard connector 130 and the bus signal interfaces of the motherboard interface expander 120 are both connected to the master device 110. Each IO interface of the motherboard interface expander 120 is connected to the corresponding ID signal terminal of the motherboard connector 130, and each ID signal terminal of the motherboard connector 130 is connected to the first upper bias circuit 140. Optionally, the first upper bias circuit 140 includes M pull-up resistors.

[0054] In the i-th backplane 200, the bus signal terminal of the first connector 210 is connected to the bus signal terminal of the second connector 220. Each ID signal terminal (there are M ID signal terminals in total) of the first connector 210 is connected to the lower bias circuit 250, the address terminal of the backplane interface expander 231 (i.e., the address terminal of the I2C slave device in the backplane), and the input terminal of the cascaded logic circuit 240, respectively. Each IO interface of the first end of the backplane interface expander 231 is connected to the output terminal of the cascaded logic circuit 240, and each IO interface of the second end of the backplane interface expander 231 is connected to the corresponding ID signal terminal of the second connector 220, and each ID signal terminal of the second connector 220 is connected to the second upper bias circuit 260. Optionally, the second upper bias circuit 260 includes M pull-up resistors, and the lower bias circuit 250 includes M pull-down resistors.

[0055] Through the circuit design described above, under the action of each bias circuit, the master device 110 can read the level value of the IO interface at the second end of each interface expander via the bus, thereby accurately determining the presence status of each backplane 200 without the need for additional presence detection devices. After the master device 110 determines that each backplane 200 is in place, it provides an initial M-bit ID signal to the first backplane 200 through the motherboard interface expander 120, and performs logical operations on the received M-bit ID signals through the cascaded logic circuits 240 in each backplane 200, which enables the automatic incremental increment of the M-bit ID value, thereby automatically assigning different ID values ​​to each backplane 200 and ensuring that the slave device addresses on each backplane 200 do not conflict.

[0056] To better understand the technical solution of this application, the working principle of the entire server backplane cascade system will be explained below using two cases, M=2 and M=3, as examples.

[0057] In one alternative implementation, such as Figure 3 As shown, M=2. The second end of the motherboard interface expander 120 includes the first IO interface GPIO1 and the second IO interface GPIO2. The first end of the backplane interface expander 231 includes the first IO interface GPIO1 and the second IO interface GPIO2. The second end of the backplane interface expander 231 includes the third IO interface GPIO3 and the fourth IO interface GPIO4. The cascaded logic circuit 240 includes an XOR gate U1 and an inverter U2.

[0058] The first IO interface GPIO1 and the second IO interface GPIO2 of the motherboard interface expander 120 are respectively connected to the first ID signal terminal ID0 and the second ID signal terminal ID1 of the motherboard connector 130.

[0059] In the i-th backplane 200, the first ID signal terminal ID0 and the second ID signal terminal ID1 of the first connector 210 are respectively connected to the first address terminal ADDR0 and the second address terminal ADDR1 of the backplane interface extender 231 to set the lowest two bits of the address of the backplane interface extender 231 (i.e., the lowest two bits of the address of the I2C slave device). The ID value of the i-th backplane 200 is equal to the lowest two bits of the address of its backplane interface extender 231.

[0060] The first ID signal terminal ID0 of the first connector 210 is also connected to the first input terminal of the XOR gate U1 and the input terminal of the inverter U2, respectively. The second ID signal terminal ID1 of the first connector 210 is also connected to the second input terminal of the XOR gate U1. The output terminal OUT1 of the XOR gate U1 is connected to the first IO interface GPIO1 of the backplane interface expander 231, and the output terminal OUT0 of the inverter U2 is connected to the second IO interface GPIO2 of the backplane interface expander 231. The third IO interface GPIO3 of the backplane interface expander 231 is connected to the second ID signal terminal nxt_ID1 of the second connector 220, and the fourth IO interface GPIO4 of the backplane interface expander 231 is connected to the first ID signal terminal nxt_ID0 of the second connector 220.

[0061] When the master device 110 is in the backplane presence detection state, the master device 110 sets all four IO interfaces of the backplane interface expander 231 in the x-th backplane 200 to be input interfaces, and determines whether the (x+1)-th backplane 200 is present by reading the input level values ​​of the third IO interface GPIO3 and the fourth IO interface GPIO4 of the backplane interface expander 231. Where 1 ≤ x ≤ N-1.

[0062] After the master device 110 determines that the (x+1)th backplane 200 is in place, the master device 110 changes the third IO interface GPIO3 and the fourth IO interface GPIO4 of the backplane interface expander 231 in the xth backplane 200 to output interfaces, and sets the output level value of the third IO interface GPIO3 to be equal to the input level value of the first IO interface GPIO1, and sets the output level value of the fourth IO interface GPIO4 to be equal to the input level value of the second IO interface GPIO2, so as to pass the output level values ​​of the third IO interface GPIO3 and the fourth IO interface GPIO4 to the (x+1)th backplane 200, which is used to set the ID value of the (x+1)th backplane 200 and the lowest 2 bits of the address of its backplane interface expander 231.

[0063] Therefore, the entire working process of a server backplane cascading system can be divided into two stages: the backplane presence detection stage and the backplane ID value and slave device address setting stage. For better understanding, the backplane presence detection stage will be explained in detail below.

[0064] Please see Figure 3 and Figure 4The principle for detecting the presence of the first backplane 200 is as follows: First, the master device 110 initializes the motherboard interface expander 120 and reads the level values ​​of the first IO interface GPIO1 and the second IO interface GPIO2 of the motherboard interface expander 120. If the first backplane 200 is present, GPIO1 and GPIO2 of the motherboard interface expander 120 are pulled low by pull-down resistors R4 and R3 respectively, and the master device 110 reads the ID1 and ID0 values ​​on the motherboard 100 as 00; if the first backplane 200 is not present, GPIO1 and GPIO2 of the motherboard interface expander 120 are pulled high by pull-up resistors R1 and R2 respectively, and the master device 110 reads the ID1 and ID0 values ​​on the motherboard 100 as 11.

[0065] Please see Figure 3 and Figure 5 The presence detection principle for the second backplane 200 is as follows: First, the master device 110 initializes the backplane interface expander 231 in the first backplane 200, setting all four IO interfaces of the backplane interface expander 231 to be input interfaces. Next, the master device 110 reads the voltage levels of the third IO interface GPIO3 and the fourth IO interface GPIO4 of the backplane interface expander 231 in the first backplane 200. If the second backplane 200 is in place, GPIO3 and GPIO4 of the backplane interface expander 231 of the first backplane 200 are pulled low by pull-down resistors R7 and R8 respectively, and the master device 110 reads the values ​​of nxt_ID1 and nxt_ID0 on the first backplane 200 as 00; if the second backplane 200 is not in place, GPIO3 and GPIO4 of the backplane interface expander 231 of the first backplane 200 are pulled high by pull-up resistors R6 and R5 respectively, and the master device 110 reads the values ​​of nxt_ID1 and nxt_ID0 on the first backplane 200 as 11.

[0066] The in-situ detection principle for the third to Nth backplates 200 is similar to that for the second backplate 200, and will not be repeated here.

[0067] Once the master device 110 confirms that each level of backplane 200 is in place, it enters the backplane ID value and slave device address setting stage. The specific setting process is as follows: First, for each backplane interface expander 231 in the backplane 200, the master device 110 changes GPIO3 and GPIO4 of the backplane interface expander 231 to output interfaces (GPIO1 and GPIO2 remain unchanged and are still input interfaces), and sets the output level of GPIO3 to be equal to the input level of GPIO1, and sets the output level of GPIO4 to be equal to the input level of GPIO2.

[0068] Next, GPIO1 and GPIO2 of the motherboard interface expander 120 output an initial ID signal (i.e., 00) to the first backplane 200. This initial ID signal serves as the ID value of the first backplane 200 and is also connected to the address terminals of slave devices such as the backplane interface expander 231, temperature sensor 232, memory 233, and complex programmable logic device 234 in the first backplane 200, so as to set the ID value of the first backplane 200 and the lowest two bits of the I2C address of its slave devices to 00.

[0069] The XOR gate U1 and inverter U2 (i.e., cascaded logic circuit 240) in the first backplane 200 perform logical operations based on the received backplane ID signal (ID1=0, ID0=0) to generate the next-level backplane ID signal (OUT1=0, OUT0=1), i.e., binary 01. This next-level backplane ID signal is output to GPIO1 and GPIO2 of the backplane interface expander 231 in the first backplane 200. The relationship between the output terminal OUT1 of XOR gate U1 and the output terminal OUT0 of inverter U2 and the second ID signal terminal ID1 and the first ID signal terminal ID0 of the first connector 210 is shown in Table 1.

[0070] Table 1 Truth Table of the First Type of Cascaded Logic Circuit

[0071] Since the main device 110 has changed GPIO3 and GPIO4 of the backplane interface expander 231 to output interfaces, and set the output level of GPIO3 to be equal to the input level of GPIO1 (i.e., nxt_ID1=OUT1=0), and the output level of GPIO4 to be equal to the input level of GPIO2 (i.e., nxt_ID0=OUT0=1), the next-level backplane ID signal output by GPIO3 and GPIO4 is nxt_ID1=0 and nxt_ID0=1, which is binary 01. This ID signal is transmitted to the ID signal terminal of the first connector 210 in the second backplane 200 via the second connector 220 in the first backplane 200 and the cable.

[0072] Similarly, after receiving the ID signal (i.e., 01), the second backplane 200 uses it as its own ID value and sets the lowest two bits of the address of all I2C slave devices on it to 01. At the same time, the XOR gate U1 and inverter U2 in the second backplane 200 calculate and generate the next-level backplane ID signal (i.e., 10) based on the received ID signal (i.e., 01), and pass it to the third backplane 200 through the backplane interface extender 231.

[0073] Similarly, when M=2, a maximum of four backplanes 200 can be cascaded. Each backplane 200 sequentially obtains an incrementing ID value (i.e., 00, 01, 10, 11), and sets the lowest two bits of its slave device address accordingly. Since different backplanes 200 have different ID values, their lowest two bits of slave device addresses are also different, thus achieving automatic and non-conflicting allocation of slave device addresses for each backplane 200.

[0074] In another alternative implementation, such as Figure 6 As shown, M=3. The first end of the backplane interface expander 231 includes a first IO interface GPIO1, a second IO interface GPIO2, and a fifth IO interface GPIO5. The second end of the backplane interface expander 231 includes a third IO interface GPIO3, a fourth IO interface GPIO4, and a sixth IO interface GPIO6. The cascaded logic circuit 240 includes an XOR gate U1, an inverter U2, an AND gate U3, and an OR gate U4.

[0075] In the i-th backplane 200, the first ID signal terminal ID0, the second ID signal terminal ID1, and the third ID signal terminal ID2 of the first connector 210 are respectively connected to the first address terminal ADDR0, the second address terminal ADDR1, and the third address terminal ADDR2 of the backplane interface expander 231 to set the lowest 3 bits of the address of the backplane interface expander 231. The ID value of the i-th backplane 200 is equal to the lowest 3 bits of the address of its backplane interface expander 231.

[0076] The first ID signal terminal ID0 of the first connector 210 is also connected to the first input terminal of the XOR gate U1, the input terminal of the inverter U2 and the first input terminal of the AND gate U3 respectively. The second ID signal terminal ID1 of the first connector 210 is also connected to the second input terminal of the XOR gate U1 and the second input terminal of the AND gate U3 respectively. The output terminal of the AND gate U3 is connected to the first input terminal of the OR gate U4. The third ID signal terminal ID2 of the first connector 210 is connected to the second input terminal of the OR gate U4.

[0077] The output terminal OUT1 of XOR gate U1 is connected to the first IO interface GPIO1 of backplane interface expander 231; the output terminal OUT0 of inverter U2 is connected to the second IO interface GPIO2 of backplane interface expander 231; and the output terminal OUT2 of OR gate U4 is connected to the fifth IO interface GPIO5 of backplane interface expander 231. The third IO interface GPIO3 of backplane interface expander 231 is connected to the second ID signal terminal nxt_ID1 of second connector 220; the fourth IO interface GPIO4 of backplane interface expander 231 is connected to the first ID signal terminal nxt_ID0 of second connector 220; and the sixth IO interface GPIO6 of backplane interface expander 231 is connected to the third ID signal terminal nxt_ID2 of second connector 220.

[0078] The relationship between the output terminal OUT2 of OR gate U4, the output terminal OUT1 of XOR gate U1, and the output terminal OUT0 of inverter U2 and the third ID signal terminal ID2, the second ID signal terminal ID1, and the first ID signal terminal ID0 of the first connector 210 is shown in Table 2.

[0079] Table 2 Truth Table for the Second Type of Cascaded Logic Circuit

[0080] When the master device 110 is in the backplane presence detection state, the master device 110 sets all six IO interfaces of the backplane interface expander 231 in the x-th backplane 200 to be input interfaces, and determines whether the (x+1)-th backplane 200 is present by reading the input level values ​​of the third IO interface GPIO3, the fourth IO interface GPIO4, and the sixth IO interface GPIO6. Where 1 ≤ x ≤ N-1.

[0081] After the master device 110 confirms that the (x+1)th backplane 200 is in place, the master device 110 changes the third IO interface GPIO3, the fourth IO interface GPIO4, and the sixth IO interface GPIO6 of the backplane interface expander 231 in the xth backplane 200 to output interfaces. The master device 110 sets the output level value of the third IO interface GPIO3 to be equal to the input level value of the first IO interface GPIO1, sets the output level value of the fourth IO interface GPIO4 to be equal to the input level value of the second IO interface GPIO2, and sets the output level value of the sixth IO interface GPIO6 to be equal to the input level value of the fifth IO interface GPIO5. This is to transmit the output level values ​​of the third IO interface GPIO3, the fourth IO interface GPIO4, and the sixth IO interface GPIO6 to the (x+1)th backplane 200, which is used to set the ID value of the (x+1)th backplane 200 and the lowest 3 bits of the address of its backplane interface expander 231.

[0082] Similar to the working principle when M=2, when M=3, up to eight backplanes 200 can be cascaded. Each backplane 200 sequentially obtains an incrementing ID value (i.e., 000, 001, 010, 011, 100, 101, 110, 111), and sets the lowest 3 bits of its slave device's I2C address accordingly. Since different backplanes 200 have different ID values, their slave device addresses are also different, thus achieving automatic and non-conflicting allocation of slave device addresses for each backplane 200.

[0083] Of course, M can also be equal to 4, 5, or a larger integer. By designing the cascaded logic circuit 240 and the backplane interface expander 231 accordingly, up to 16, 32, or even more backplanes can be cascaded. That is, this application does not limit the specific value of M, as long as M is a positive integer greater than or equal to 2.

[0084] In summary, the server backplane cascading system provided in this application replaces the star topology of the prior art, where the motherboard is connected to multiple backplanes via I2C switching chips, with the following advantages: (1) Reduced motherboard PCB area. There is no need to set up I2C switching chip and multiple motherboard connectors on the motherboard. Only one motherboard connector is needed to connect multiple backplanes, thereby reducing the motherboard PCB area and lowering costs.

[0085] (2) Improved system heat dissipation. The use of cascaded backplanes allows for extremely short cable connections between adjacent backplanes, thereby reducing the space occupied by cables inside the chassis and improving the heat dissipation of high-power components such as CPU and GPU.

[0086] (3) Backplane presence detection is achieved. Through the cooperation of the upper bias circuit (such as pull-up resistor) and the lower bias circuit (such as pull-down resistor), when the backplane is in place, the ID signal terminal is pulled low to a low level, and when the backplane is not in place, the ID signal terminal is pulled high to a high level; the master device can accurately determine whether the backplane at each level is in place by reading the level status of the second terminal of each interface expander through the bus.

[0087] (4) Multi-backplane cascading is achieved and the I2C addresses of slave devices do not conflict with each other. The cascading logic circuit realizes the automatic increment of the ID value of each backplane and the automatic setting of the slave device address on each backplane, so that the master device can communicate directly with the slave devices on each backplane without the need for an I2C switching chip, and the slave device addresses on different backplanes do not conflict with each other due to the different ID values.

[0088] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

[0089] It will be apparent to those skilled in the art that this application is not limited to the details of the exemplary embodiments described above, and that this application can be implemented in other specific forms without departing from the spirit or essential characteristics of this application. Therefore, the embodiments should be considered illustrative and non-limiting in all respects, and the scope of this application is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within this application. No reference numerals in the claims should be construed as limiting the scope of the claims.

Claims

1. A server backplane cascading system, characterized in that, It includes a motherboard and N backplanes; the motherboard includes a master device, a motherboard interface expander, and a motherboard connector; each backplane includes a first connector, a second connector, a slave device module, and cascaded logic circuitry. The main device is connected to the first end of the motherboard interface expander and the motherboard connector via a bus. The second end of the motherboard interface expander is connected to the ID signal end of the motherboard connector. N backplanes are cascaded in sequence. The first connector of the first backplane is connected to the motherboard connector, and the first connectors of the remaining backplanes are connected to the second connectors of the previous backplane. In the i-th backplane, the first connector is connected to the second connector via a bus, and the slave module is mounted on the bus between the first connector and the second connector; the ID signal terminal of the first connector is connected to the address terminal of the slave module and the input terminal of the cascaded logic circuit, respectively, and the output terminal of the cascaded logic circuit is connected to the ID signal terminal of the second connector via the slave module; where 1≤i≤N, N≥2; After the master device determines that each level of backplane is in place, the master device provides an initial ID signal to the first backplane through the motherboard interface expander, and controls the ID of each level of backplane to automatically increment through the cascaded logic circuit in each level of backplane, so that the addresses of slave device modules in different backplanes do not conflict with each other. The motherboard also includes a first upper bias circuit, each backplane also includes a lower bias circuit and a second upper bias circuit, and the slave device module includes a backplane interface expander. One end of the first upper bias circuit is connected to the ID signal terminal of the motherboard connector, and the other end of the first upper bias circuit is connected to the power supply. In the i-th backplane, the backplane interface extender is mounted on the bus between the first connector and the second connector; the ID signal terminal of the first connector is connected to the address terminal of the backplane interface extender, the input terminal of the cascaded logic circuit, and one end of the lower bias circuit, respectively. The other end of the lower bias circuit is grounded. The output terminal of the cascaded logic circuit is connected to the first end of the backplane interface extender, and the second end of the backplane interface extender is connected to the ID signal terminal of the second connector; one end of the second upper bias circuit is connected to the ID signal terminal of the second connector, and the other end of the second upper bias circuit is connected to the power supply. Each connector includes one bus signal terminal and M ID signal terminals; the first end of the motherboard interface expander includes one bus signal interface, and the second end includes M IO interfaces; the first end of the backplane interface expander includes M IO interfaces, and the second end includes M IO interfaces; wherein, M≥2; The motherboard interface expander is connected to the first connector of the first backplane, and the second connectors of the two adjacent backplanes are connected to the first connector via cables to transmit bus signals and M-bit ID signals. When M=2, the cascaded logic circuit includes an XOR gate and an inverter; In the i-th backplane, the first ID signal terminal and the second ID signal terminal of the first connector are respectively connected to the first address terminal and the second address terminal of the backplane interface extender to set the lowest 2 bits of the backplane interface extender address; wherein, the ID value of the i-th backplane is equal to the lowest 2 bits of its backplane interface extender address. The first ID signal terminal of the first connector is also connected to the first input terminal of the XOR gate and the input terminal of the inverter, respectively; the second ID signal terminal of the first connector is also connected to the second input terminal of the XOR gate. The output of the XOR gate is connected to the first IO interface of the backplane interface expander, and the output of the inverter is connected to the second IO interface of the backplane interface expander. The third IO interface of the backplane interface extender is connected to the second ID signal terminal of the second connector, and the fourth IO interface of the backplane interface extender is connected to the first ID signal terminal of the second connector. When the main device is in the backplane presence detection state, the main device sets all four IO interfaces of the backplane interface expander in the xth backplane to be input interfaces, and determines whether the (x+1)th backplane is in place by reading the input level values ​​of the third and fourth IO interfaces; where 1≤x≤N-1; After the master device determines that the (x+1)th backplane is in place, the master device changes the third and fourth IO interfaces of the backplane interface extender in the xth backplane to output interfaces, and sets the output level of the third IO interface to be equal to the input level of the first IO interface, and sets the output level of the fourth IO interface to be equal to the input level of the second IO interface, so as to transmit the output level values ​​of the third and fourth IO interfaces to the (x+1)th backplane, which is used to set the ID value of the (x+1)th backplane and the lowest two bits of its backplane interface extender address.

2. The server backplane cascading system according to claim 1, characterized in that, When the master device reads that the second terminal of the motherboard interface expander is low through the bus, the master device determines that the first backplane is in place; When the master device reads that the second terminal of the motherboard interface expander is high through the bus, the master device determines that the first backplane is not in place; When the master device reads through the bus that the second terminal of the backplane interface extender of the xth backplane is low, the master device determines that the (x+1)th backplane is in place; When the master device reads through the bus that the second terminal of the backplane interface expander of the xth backplane is high, the master device determines that the (x+1)th backplane is not in place; Where 1≤x≤N-1.

3. The server backplane cascading system according to claim 1, characterized in that, When M=3, the cascaded logic circuit includes an XOR gate, an inverter, an AND gate, and an OR gate; In the i-th backplane, the first ID signal terminal, the second ID signal terminal, and the third ID signal terminal of the first connector are respectively connected to the first address terminal, the second address terminal, and the third address terminal of the backplane interface extender to set the lowest 3 bits of the backplane interface extender address; wherein, the ID value of the i-th backplane is equal to the lowest 3 bits of its backplane interface extender address; The first ID signal terminal of the first connector is also connected to the first input terminal of the XOR gate, the input terminal of the inverter, and the first input terminal of the AND gate, respectively. The second ID signal terminal of the first connector is also connected to the second input terminal of the XOR gate and the second input terminal of the AND gate, respectively. The output terminal of the AND gate is connected to the first input terminal of the OR gate, and the third ID signal terminal of the first connector is connected to the second input terminal of the OR gate. The output of the XOR gate is connected to the first IO interface of the backplane interface expander, the output of the inverter is connected to the second IO interface of the backplane interface expander, and the output of the OR gate is connected to the fifth IO interface of the backplane interface expander. The third IO interface of the backplane interface extender is connected to the second ID signal terminal of the second connector, the fourth IO interface of the backplane interface extender is connected to the first ID signal terminal of the second connector, and the sixth IO interface of the backplane interface extender is connected to the third ID signal terminal of the second connector.

4. The server backplane cascading system according to claim 3, characterized in that, When the main device is in the backplane presence detection state, the main device sets all 6 IO interfaces of the backplane interface expander in the xth backplane to be input interfaces, and determines whether the (x+1)th backplane is in place by reading the input level values ​​of the third, fourth and sixth IO interfaces; where 1≤x≤N-1; After the master device determines that the (x+1)th backplane is in place, the master device changes the third, fourth, and sixth IO interfaces of the backplane interface extender in the xth backplane to output interfaces, and sets the output level of the third IO interface to be equal to the input level of the first IO interface, sets the output level of the fourth IO interface to be equal to the input level of the second IO interface, and sets the output level of the sixth IO interface to be equal to the input level of the fifth IO interface, so as to transmit the output level values ​​of the third, fourth, and sixth IO interfaces to the (x+1)th backplane, which is used to set the ID value of the (x+1)th backplane and the lowest 3 bits of its backplane interface extender address.

5. The server backplane cascading system according to claim 1, characterized in that, The bus signal terminal of the motherboard connector and the bus signal interface of the motherboard interface expander are both connected to the host device. Each IO interface of the motherboard interface expander is connected to the corresponding ID signal terminal of the motherboard connector. Each ID signal terminal of the motherboard connector is connected to the first upper bias circuit. In the i-th backplane, the bus signal terminal of the first connector is connected to the bus signal terminal of the second connector; each ID signal terminal of the first connector is connected to the lower bias circuit, the address terminal of the backplane interface expander, and the input terminal of the cascaded logic circuit, respectively; each IO interface of the first end of the backplane interface expander is connected to the output terminal of the cascaded logic circuit, each IO interface of the second end is connected to the corresponding ID signal terminal of the second connector, and each ID signal terminal of the second connector is connected to the second upper bias circuit.

6. The server backplane cascading system according to claim 1, characterized in that, The slave device module also includes a temperature sensor, a memory, and a complex programmable logic device; In the i-th backplane, the temperature sensor, the memory, and the complex programmable logic device are all mounted on the bus between the first connector and the second connector; The ID signal terminal of the first connector is also connected to the address terminal of the temperature sensor, the address terminal of the memory, and the address terminal of the complex programmable logic device, respectively.

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