An interlayer alignment method and device for a multilayer circuit board and a storage medium

Abstract

The application discloses a kind of interlayer alignment method, device and storage medium of multilayer circuit board, for improving the interlayer alignment efficiency and alignment accuracy of multilayer circuit board.The application includes: based on the lamination design data and material attribute parameters of target multilayer circuit board, the theoretical deformation field generated by each layer circuit board under preset process condition is calculated;According to the theoretical deformation field, generate the first compensation instruction set and the first compensation plan;Scan the actual spatial coordinates of alignment mark on each layer circuit board, and calculate the measured deformation field of each layer circuit board;The measured deformation field of each layer circuit board is compared with the corresponding theoretical deformation field, and the first compensation instruction set is corrected according to the comparison result;According to the first compensation instruction set after correction, control pre-lamination pre-alignment equipment to adjust the displacement and attitude of corresponding layer circuit board;Scan the surface alignment mark of pressing plate, and calculate the integrated offset field;According to the integrated offset field and the first compensation plan, generate dynamic compensation file.

Description

Technical Field

[0001] This application relates to the field of circuit board manufacturing, and more particularly to a method, apparatus and storage medium for interlayer alignment of a multilayer circuit board. Background Technology

[0002] With the continuous improvement of electronic equipment performance and the increasing complexity of its functions, increasingly stringent requirements are being placed on the interlayer alignment accuracy of multilayer circuit boards. Interlayer alignment accuracy is directly related to the electrical performance and reliability of multilayer circuit boards. If there is a deviation in interlayer alignment, it may lead to poor signal transmission, poor electrical connection, or even serious problems such as short circuits and open circuits, thereby affecting the normal operation of the entire electronic equipment.

[0003] Currently, the main methods for interlayer alignment of multilayer circuit boards include traditional mechanical positioning and conventional visual alignment. Traditional mechanical positioning relies on mechanical structures such as locating pins and guide sleeves for interlayer alignment, and alignment is achieved through manual adjustment. This method has low equipment cost, but it is greatly affected by mechanical wear, human operation errors, and environmental factors, resulting in low alignment accuracy. It is difficult to meet the manufacturing requirements of high-precision multilayer circuit boards, and its production efficiency is low, making it unsuitable for mass production scenarios.

[0004] Conventional visual alignment methods scan alignment marks on circuit boards using industrial cameras, calculate offsets, and then drive equipment for adjustment. While this offers some improvement in accuracy and efficiency compared to traditional mechanical positioning methods, it typically only handles simple rigid offsets such as translation and rotation. However, during the production of multilayer circuit boards, various factors such as differences in stack-up design, material property fluctuations, and lamination process conditions cause not only rigid offsets but also complex non-rigid deformations such as warping, localized stretching, or shrinkage. Furthermore, the deformations of each inner layer during lamination can overlap, creating a complex combined deformation effect. Conventional visual alignment methods lack effective means to predict and handle these complex deformations, making it difficult to achieve accurate compensation throughout the entire process. This results in a bottleneck in improving interlayer alignment accuracy, failing to meet the stringent requirements of high-end electronic devices for multilayer circuit boards. Summary of the Invention

[0005] This application discloses a method, apparatus, and storage medium for interlayer alignment of multilayer circuit boards, which can improve the efficiency and accuracy of interlayer alignment of multilayer circuit boards.

[0006] The first aspect of this application discloses a method, apparatus, and storage medium for interlayer alignment of a multilayer circuit board, including:

[0007] Based on the stack-up design data and material property parameters of the target multilayer circuit board, the theoretical deformation field generated by each layer of the circuit board under the preset process conditions is calculated. Based on the theoretical deformation field, a first compensation instruction set and a first compensation plan are generated. The first compensation instruction is a control signal for driving the pre-alignment device before lamination, and the first compensation plan is a control signal for driving the post-lamination processing device. Scan the actual spatial coordinates of the alignment marks on each layer of the circuit board and calculate the measured deformation field of each layer of the circuit board; The measured deformation field of each circuit board layer is compared with the corresponding theoretical deformation field, and the first compensation instruction set is corrected according to the comparison result. According to the revised first compensation instruction set, the pre-alignment device before lamination is controlled to adjust the displacement and attitude of the circuit board of the corresponding layer. The alignment marks on the surface of the press plate are scanned, and the comprehensive offset field is calculated. The press plate is a type of board material formed by alternating stacking and pressing of multilayer circuit boards and insulating media. A dynamic compensation file is generated based on the comprehensive offset field and the first compensation plan.

[0008] Optionally, the calculation of the theoretical deformation field of each layer of the circuit board under preset process conditions based on the stack-up design data and material property parameters of the target multilayer circuit board includes: The stack-up design data of the target multilayer circuit board is analyzed to extract the geometric structure information of each layer of the circuit board; Based on the structural information, material property parameters, and preset process conditions, a three-dimensional finite element model is constructed. The three-dimensional finite element model is meshed, and deformed elements in the mesh are eliminated; Based on the processed finite element model, the stress-strain relationship of the multilayer circuit board under the preset process conditions is calculated; The stress-strain relationship is converted into a theoretical deformation field, which is the displacement vector field of each layer of the circuit board in three-dimensional space.

[0009] Optionally, the step of constructing a three-dimensional finite element model based on the structural information, material property parameters, and preset process conditions includes: Based on the structural information and material property parameters, a three-dimensional finite element model is constructed. Boundary conditions and load conditions are set in the three-dimensional finite element model according to the preset process conditions.

[0010] Optionally, the step of constructing a three-dimensional finite element model based on the structural information, material property parameters, and preset process conditions includes: Based on the structural information and material property parameters, a three-dimensional finite element model is constructed. Boundary conditions and load conditions are set in the three-dimensional finite element model according to the preset process conditions.

[0011] Optionally, the step of generating a dynamic compensation file based on the comprehensive offset field and the first compensation plan, wherein the dynamic compensation file is a summary of the compensation amounts for subsequent processes, further includes: Based on the dynamic compensation file, the multilayer circuit board is processed, and the actual alignment accuracy data of the processed multilayer circuit board is obtained. The three-dimensional finite element model is optimized based on the actual alignment accuracy data.

[0012] Optionally, generating the first compensation instruction set and the first compensation plan based on the theoretical deformation field includes: The theoretical deformation field of each circuit board layer is decomposed into rigid displacement components and non-rigid deformation components. Displacement control parameters in the first compensation instruction set are generated based on the rigid displacement components, and attitude adjustment parameters in the first compensation instruction set are generated based on the non-rigid deformation components. Based on the non-rigid deformation components and the laminated design data, predict the superposition effect of deformation of each inner layer during the lamination process; The first compensation plan is generated based on the prediction results.

[0013] Optionally, comparing the measured deformation field of each circuit board layer with the corresponding theoretical deformation field, and correcting the first compensation instruction set based on the comparison result, includes: For each layer of the circuit board, the displacement vector difference between the measured deformation field and the corresponding theoretical deformation field is calculated to generate the corresponding deformation difference field. Based on a preset deformation tolerance threshold, key difference regions exceeding the deformation tolerance threshold are identified from the deformation difference field. Based on the geometric location, magnitude of difference, and degree of impact on accuracy of the key difference regions, corresponding correction weight coefficients are assigned; A compensation mapping relationship is generated based on the modified weight coefficients of the deformation difference field and the key difference region; The first compensation instruction set is modified according to the compensation mapping relationship.

[0014] Optionally, the scanning of the alignment marks on the surface of the pressed plate to calculate the comprehensive offset field includes: Images are acquired from multiple pre-set alignment marks on the surface of the press plate, and the actual center coordinates of each alignment mark are extracted. The actual center coordinates are compared with the theoretical design coordinates to calculate the position offset vector of the alignment mark; Based on the position offset vector, a comprehensive offset field is constructed, which is used to describe the estimated offset and direction at any position on the plate surface.

[0015] Optionally, generating a dynamic compensation file based on the integrated offset field and the first compensation plan includes: Based on the comprehensive offset field, a compensation strategy is selected from the first compensation plan, and the application parameters of the compensation strategy are determined; Based on the selected compensation strategy and the application parameters, the integrated offset field is converted into an instruction sequence, and the instruction sequence is encapsulated into a dynamic compensation file.

[0016] A second aspect of this application provides an interlayer alignment device for a multilayer circuit board, comprising: The first calculation unit is used to calculate the theoretical deformation field of each layer of the circuit board under preset process conditions based on the stack-up design data and material property parameters of the target multilayer circuit board. The first generation unit is used to generate a first compensation instruction set and a first compensation plan based on the theoretical deformation field. The first compensation instruction is a control signal for driving the pre-alignment device before lamination, and the first compensation plan is a control signal for driving the post-lamination processing device. The second calculation unit is used to scan the actual spatial coordinates of the alignment marks on each layer of the circuit board and calculate the measured deformation field of each layer of the circuit board. The correction unit is used to compare the measured deformation field of each layer of the circuit board with the corresponding theoretical deformation field, and correct the first compensation instruction set according to the comparison result. The adjustment unit is used to control the pre-alignment device before lamination to adjust the displacement and attitude of the circuit board of the corresponding layer according to the modified first compensation instruction set. The processing unit is used to scan the alignment marks on the surface of the press plate and calculate the comprehensive offset field. The press plate is a type of board material formed by alternating stacking and pressing of multilayer circuit boards and insulating media. The second generation unit is used to generate a dynamic compensation file based on the integrated offset field and the first compensation plan.

[0017] A third aspect of this application also provides an interlayer alignment device for a multilayer circuit board, comprising: Processor, memory, input / output units, and bus; The processor is connected to memory, input / output units, and a bus; The memory holds a program, which the processor calls to execute, as in the first aspect and any optional method of the first aspect.

[0018] The fourth aspect of this application provides a computer-readable storage medium on which a program is stored, which, when executed on a computer, performs the methods of the first aspect and any optional methods of the first aspect.

[0019] As can be seen from the above technical solutions, the embodiments of this application have the following advantages: First, based on the laminated design data, material property parameters, and preset process conditions, the theoretical deformation field is calculated in advance to understand the rigid offsets and non-rigid deformations (such as warping, local stretching / shrinkage) that may occur in each layer of the circuit board during production, providing core data support for precise alignment throughout the entire process. A targeted first compensation instruction set and a first compensation contingency plan are generated, constructing a comprehensive solution of "active correction before lamination and precise compensation after lamination," avoiding alignment deviations that may result from the superposition of deformations during lamination.

[0020] By scanning to obtain the measured deformation field, comparing the theoretical deformation field with the measured deformation field, and correcting the first compensation instruction set, the effects of uncertainties in actual production, such as material property fluctuations, equipment errors, and environmental interference, are effectively offset. This makes the first compensation instruction set more closely match the actual deformation state of the circuit board, significantly improving the accuracy of pre-alignment before lamination. Based on the corrected compensation instruction set, the pre-alignment equipment is controlled to complete automated displacement and attitude adjustments. This not only significantly reduces errors caused by manual intervention and improves alignment efficiency, but also ensures the consistency of alignment adjustments between different batches and different layers, solving the pain points of low efficiency and poor consistency of traditional methods.

[0021] By scanning the laminated plate and calculating the overall offset field, the superposition effect of additional deformation introduced during lamination and residual deviation from pre-alignment was obtained. This allows subsequent compensation to specifically cover deformation throughout the entire process, further reducing interlayer alignment errors. Combining the overall offset field with the first compensation plan, a dynamic compensation file is generated to ensure that subsequent processing steps can accurately offset the overall deformation, effectively avoiding problems such as short circuits, open circuits, and signal crosstalk caused by interlayer offset. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 A schematic diagram of an embodiment of the interlayer alignment method for multilayer circuit boards provided in this application; Figure 2 A schematic diagram of an embodiment of the method for calculating theoretical deformation fields provided in this application; Figure 3 A schematic diagram of an embodiment of the method for constructing a three-dimensional finite element model provided in this application; Figure 4A schematic diagram of an embodiment of the method for converting theoretical deformation fields provided in this application; Figure 5 A schematic diagram of an embodiment of the method for optimizing a three-dimensional finite element model provided in this application; Figure 6 A schematic diagram of an embodiment of the method for generating a first compensation instruction set and a first compensation plan provided in this application; Figure 7 A schematic diagram of an embodiment of the method for modifying the first compensation instruction set provided in this application; Figure 8 A schematic diagram of an embodiment of the method for calculating the composite offset field provided in this application; Figure 9 A schematic diagram of an embodiment of the method for modifying the first compensation instruction set provided in this application; Figure 10 A schematic diagram of the interlayer alignment device for the multilayer circuit board provided in this application; Figure 11 Another structural schematic diagram of the interlayer alignment device for the multilayer circuit board provided in this application; Detailed Implementation The interlayer alignment method for multilayer circuit boards disclosed in this application is not limited to specific hardware devices or software systems, and can be flexibly configured according to actual production scenarios. Specifically, it can be implemented by an independent industrial control system (such as a PLC controller or a dedicated CNC system) as the core execution entity, coordinating visual scanning equipment, pre-alignment equipment, laminating equipment, and subsequent processing equipment to complete each step of the operation; or it can be implemented by computer equipment (such as an industrial PC or server) by running preset computer program instructions, that is, by using software algorithms to complete core logical operations such as theoretical deformation field calculation, compensation instruction generation, and data comparison and correction, and sending control signals and data instructions to each hardware device through communication interfaces (such as Ethernet or bus interfaces) to drive the hardware device to perform corresponding physical operations; or it can adopt a distributed execution architecture of "software algorithm module + hardware execution module", in which different functional modules undertake data processing, equipment control, and other tasks respectively, and each module completes the entire interlayer alignment process through data interaction and collaboration. As long as the steps, logic, and technical effects defined in this claim can be achieved, any execution entity with corresponding data processing and equipment control capabilities is applicable to this method, and this embodiment does not further limit its specific form.

[0024] To facilitate a precise understanding of the technical solutions of this application by those skilled in the art, the following definitions are provided for key terms used in this application: Layer stack-up design data: refers to the core stack-up data determined during the design phase of the target multilayer circuit board, including but not limited to the number of circuit boards in each layer, stack-up order, substrate type and specifications, two-dimensional coordinates and line width / spacing of the circuit pattern, material type and thickness of the interlayer dielectric, design coordinates and geometric dimensions of the alignment marks, overall board dimensions and shape structure, etc.

[0025] Material property parameters: These refer to the physical and mechanical properties of various materials that make up multilayer circuit boards, including but not limited to coefficient of thermal expansion, elastic modulus, Poisson's ratio, curing shrinkage rate, thermal conductivity, viscosity change curve, stress-strain characteristic curve, etc. They are the core basic data for constructing finite element models and deformation prediction.

[0026] Preset process conditions: These refer to the standardized process parameters preset during the production of multilayer circuit boards. They mainly include parameters related to the lamination process, pretreatment process parameters, and basic process parameters for subsequent processing steps. They are key input conditions for simulating the actual production environment and calculating the theoretical deformation field.

[0027] Theoretical deformation field: refers to the description of the deformation state of each layer of the circuit board during the production process, which is predicted by finite element simulation and other methods based on the stack-up design data, material property parameters and preset process conditions. Specifically, it is the displacement vector field of each layer of the circuit board in three-dimensional space, which includes the displacement components of each key node on the board. It can comprehensively reflect the deformation characteristics of the circuit board such as translation, rotation, warping and local stretching / shrinkage.

[0028] The first compensation instruction set refers to the set of control signals used to drive the pre-alignment equipment before lamination to perform precise adjustment actions. It is generated based on the rigid displacement components and non-rigid deformation components after theoretical deformation field decomposition, and includes displacement control parameters and attitude adjustment parameters. It can be directly recognized and executed by the control system of the pre-alignment equipment.

[0029] The first compensation plan refers to a set of pre-set compensation strategies for post-lamination processing equipment. It is formulated based on the non-rigid deformation components in the theoretical deformation field and the stacking design data, combined with the prediction results of the superposition effect of deformation of each inner layer during the lamination process. It includes a standard compensation rule library for different offset modes, providing a pre-set solution for accurate compensation of post-lamination processing procedures.

[0030] Measured deformation field: refers to the actual deformation state data of each layer of the circuit board obtained by detection methods such as visual scanning. It is calculated based on the difference between the actual spatial coordinates and the design coordinates of the alignment mark. It is also presented in the form of a three-dimensional displacement vector field, which can truly reflect the actual deformation of the circuit board in the actual production environment caused by factors such as material differences, equipment errors, and environmental fluctuations.

[0031] Alignment marks: These are feature patterns that are pre-set on the surface of each layer of the circuit board (including inner and outer layers) for positioning and deformation detection. They include, but are not limited to, high-precision geometric patterns such as crosses, circles, and irregular shapes. They are usually evenly distributed on the edge of the board and in key areas within the board, with no fewer than three. They have the characteristics of high contrast and strong anti-interference, and are the core reference benchmark for visual scanning equipment to identify the position and deformation of the circuit board.

[0032] Laminated board: refers to an integrated board formed by stacking pre-aligned circuit boards and insulating media alternately in a preset stacking order, applying specific temperature and pressure through lamination equipment and maintaining it for a certain time to allow the materials of each layer to cure and bond together. It is an intermediate product for transforming multilayer circuit boards from a layered state into the core structure of the finished product, and the alignment accuracy between its layers directly determines the quality of the final product.

[0033] Overall offset field: refers to the superimposed deformation field calculated by scanning the alignment marks on the surface of the laminate after it is formed. It is the superposition result of the residual deviation after the pre-alignment adjustment before lamination and the additional deformation introduced during the lamination process. It is used to describe the overall and local offset amount and offset direction of the laminate and is the core input for generating the dynamic compensation file after lamination.

[0034] Dynamic compensation file: refers to a standardized file generated based on the comprehensive offset field and the first compensation plan, which summarizes the compensation amounts of each subsequent processing step. It includes the compensation parameters, application scope and execution logic corresponding to each step, and can be directly imported into the control system of the subsequent processing equipment to achieve accurate compensation in the processing process.

[0035] Three-dimensional finite element model: refers to a three-dimensional digital model of a multilayer circuit board constructed based on the geometric structure information, material property parameters and preset process conditions in the stack-up design data. It can accurately replicate the spatial distribution, geometric features and mechanical properties of each layer of material. Through mesh generation and boundary / load condition settings, it provides a digital carrier for stress-strain relationship calculation and theoretical deformation field prediction.

[0036] Stress-strain relationship: refers to the relationship between the stress and strain of each material element in a multilayer circuit board under preset process conditions, obtained by thermodynamic simulation calculation of a three-dimensional finite element model.

[0037] Rigid displacement component: refers to the displacement component of the circuit board as a whole that is decomposed from the theoretical deformation field and has no overall deformation. It only includes translational motion in the X / Y direction and rotational motion around a specific axis. It does not involve the stretching, contraction or warping of the circuit board itself. It is the core basis for the translational and rotational adjustment of the pre-alignment equipment before lamination.

[0038] Non-rigid deformation components refer to the deformation components that change the shape of the circuit board itself, which are decomposed from the theoretical deformation field. These include board warping, local stretching / contraction, irregular distortion, etc., which cannot be offset by simple translation or rotation. They are the core basis for generating attitude adjustment parameters and post-lamination compensation plans.

[0039] Deformation difference field: refers to the vector field that reflects the deviation between the measured deformation field and the theoretical deformation field obtained by comparing them point by point for the same layer of circuit board. It includes the displacement deviation amount, deviation direction and deviation distribution characteristics of each node.

[0040] Actual alignment accuracy data: refers to the actual alignment deviation data between layers obtained after the multilayer circuit board has undergone subsequent processing, including the continuity accuracy of interlayer circuits, the coincidence of alignment marks, and the offset of key hole positions.

[0041] Based on this, this application discloses a method, apparatus and storage medium for interlayer alignment of multilayer circuit boards, which can improve the interlayer alignment efficiency and alignment accuracy of multilayer circuit boards.

[0042] The technical solutions of this application will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0043] The method of this application can be applied to servers, devices, terminals, or other devices with logical processing capabilities; therefore, this application does not limit its application. For ease of description, the following description uses a system as the executing entity.

[0044] Please see Figure 1 This application provides an embodiment of an interlayer alignment method for a multilayer circuit board, comprising: 101. Based on the stack-up design data and material property parameters of the target multilayer circuit board, calculate the theoretical deformation field generated by each layer of the circuit board under the preset process conditions; Import the stack-up design files (such as Gerber files or CAD design drawings) of the target multilayer circuit board and extract the core design information, including the number of circuit boards in each layer, the stack-up order, the overall dimensions of the board, the specifications of the substrates for each layer, the distribution range of the circuit patterns, the type and thickness of the interlayer dielectric, and the design position of the alignment marks. At the same time, collect the core property parameters of various materials that make up the circuit board (substrate, copper foil, interlayer bonding materials, insulating dielectric, etc.), covering physical and mechanical properties related to deformation such as the coefficient of thermal expansion, elastic modulus, Poisson's ratio, and curing shrinkage rate.

[0045] Clearly define the preset process conditions, focusing on the heating rate, constant temperature and holding time, cooling rate, lamination pressure and application method of the lamination process, as well as production process parameters such as the ambient temperature and humidity control range of the pretreatment stage.

[0046] Using engineering analysis methods such as finite element simulation, the above-mentioned layer design data, material property parameters and preset process conditions are used as input to construct a simulation model adapted to the actual production scenario. By simulating physical processes such as temperature change, pressure transmission and material curing, the theoretical deformation law of each layer of the circuit board in the entire production process is calculated, and finally a theoretical deformation field that can fully reflect the characteristics of each layer is formed.

[0047] 102. Based on the theoretical deformation field, generate a first compensation instruction set and a first compensation plan. The first compensation instruction is the control signal for driving the pre-alignment equipment before lamination, and the first compensation plan is the control signal for driving the post-lamination processing equipment. The theoretical deformation field is analyzed to distinguish the influence of different deformation types on interlayer alignment, and to clarify the offset trend and attitude change law of each layer of circuit board in space.

[0048] Based on the above analysis results, a first compensation instruction set is generated. The first compensation instruction set is a set of control signals specifically designed to drive the pre-alignment equipment before lamination. It includes displacement adjustment parameters and attitude correction parameters required to achieve precise alignment of each layer of circuit boards, ensuring that the pre-alignment equipment can specifically counteract the initial deformation of each layer.

[0049] Simultaneously, by combining theoretical deformation field predictions of potential deformation superposition effects during lamination, a first compensation plan is generated. This plan is a pre-set compensation strategy for post-lamination processing equipment, clarifying the parameter adjustment direction and basic principles of processing equipment under different deformation scenarios, providing a pre-set basis for subsequent precise post-lamination processing.

[0050] 103. Scan the actual spatial coordinates of the alignment marks on each layer of the circuit board and calculate the measured deformation field of each layer of the circuit board; The scanning equipment is used to scan each layer of the circuit board one by one to obtain the actual spatial coordinates of all alignment marks on each layer of the circuit board. During the scanning process, multiple acquisitions are taken and the average value is taken to reduce the impact of random errors on the detection results.

[0051] The original design coordinates of the alignment marks of each layer of the circuit board are retrieved. The displacement data of each mark point is obtained by calculating the difference between the actual spatial coordinates and the design coordinates. Combined with the overall deformation trend of the board, the displacement information of each mark point is integrated to form a measured deformation field. The measured deformation field can truly reflect the actual deformation state of each layer of the circuit board.

[0052] 104. Compare the measured deformation field of each circuit board with the corresponding theoretical deformation field, and correct the first compensation instruction set based on the comparison results; The measured deformation fields of each layer of the circuit board are compared and analyzed region by region and feature by feature to clarify the magnitude and distribution of the deviations between the two in key deformation parameters such as translation, rotation angle and warpage.

[0053] Based on the deviation results obtained from the comparison, it is determined whether the first compensation command set can meet the requirements for accurate alignment. If the deviation is within the allowable range, the first compensation command set can remain unchanged; if the deviation exceeds the allowable range, the displacement adjustment parameters and attitude correction parameters in the first compensation command set are adjusted accordingly, so that the corrected command set can better match the actual deformation state of the circuit board, providing a precise control basis for subsequent pre-alignment adjustments.

[0054] 105. According to the revised first compensation instruction set, control the pre-alignment equipment before lamination to adjust the displacement and attitude of the circuit board of the corresponding layer. The revised first compensation instruction set is transmitted to the control system of the pre-alignment equipment before lamination, establishing a connection between the instruction set and the equipment actuator to ensure that the equipment can accurately respond to the control signals.

[0055] According to the first compensation instruction set, the pre-alignment equipment first performs translation adjustment to offset the overall offset in the X and Y directions; then it performs rotation adjustment to correct the rotation deviation between layers; and finally it corrects posture problems such as local warping to ensure that the spatial position and posture of each layer of circuit board are completely matched.

[0056] During the adjustment process, the position changes of the alignment marks are monitored in real time. Once the alignment accuracy of each layer of circuit board is confirmed to meet the preset standard, the pre-alignment adjustment is completed to prepare for the subsequent lamination process.

[0057] 106. Scan the alignment marks on the surface of the laminated plate and calculate the comprehensive offset field. The laminated plate is a type of board material made by alternately stacking and pressing multiple layers of circuit boards and insulating media. The pre-aligned circuit boards and insulating media are stacked alternately in a preset stacking order and fed into a laminating equipment. They are then pressed and cured under preset process conditions to form an integrated laminate.

[0058] Marking scanning: After the press plate has cooled to room temperature, a vision scanning device is used to scan the alignment marks (including outer layer marks and inner layer marks that can be identified through the insulating medium) on the surface of the press plate to accurately collect the actual spatial coordinates of each alignment mark.

[0059] Offset field generation: Combining the theoretical coordinates of each layer of circuit board after pre-alignment, the actual offset of each alignment mark is calculated, the distribution law of the offset is analyzed, and the residual deviation of pre-alignment before lamination and the additional deformation introduced during lamination are integrated to finally form a comprehensive offset field that can fully reflect the overall deformation state of the laminate.

[0060] 107. Generate a dynamic compensation file based on the integrated offset field and the first compensation plan.

[0061] Based on the deformation characteristics of the press plate reflected by the comprehensive offset location, a suitable compensation strategy is selected from the first compensation plan to clarify the core parameters and adjustment directions that need to be adjusted in the subsequent processing.

[0062] Based on the selected compensation strategy and combined with the specific offset data of the comprehensive offset field, the compensation amount required for each subsequent processing step (such as drilling, etching, solder resist, etc.) is calculated. The compensation amount can effectively offset the deformation deviation of the press plate.

[0063] Information such as the compensation amount, compensation execution logic, and applicable scope of each process is summarized and a dynamic compensation file is generated in a standardized format.

[0064] In this embodiment, firstly, based on the laminated design data, material property parameters, and preset process conditions, the theoretical deformation field is calculated to understand in advance the rigid offsets and non-rigid deformations (such as warping, local stretching / shrinkage) that may occur in each layer of the circuit board during production, providing core data support for precise alignment throughout the entire process. A first compensation instruction set and a first compensation plan are then generated to construct a comprehensive solution of "active correction before lamination and precise compensation after lamination," avoiding alignment deviations that may result from the superposition of deformations during lamination.

[0065] By scanning to obtain the measured deformation field, comparing the theoretical deformation field with the measured deformation field, and correcting the first compensation instruction set, the effects of uncertainties in actual production, such as material property fluctuations, equipment errors, and environmental interference, are effectively offset. This makes the first compensation instruction set more closely match the actual deformation state of the circuit board, significantly improving the accuracy of pre-alignment before lamination. Based on the corrected compensation instruction set, the pre-alignment equipment is controlled to complete automated displacement and attitude adjustments. This not only significantly reduces errors caused by manual intervention and improves alignment efficiency, but also ensures the consistency of alignment adjustments between different batches and different layers, solving the pain points of low efficiency and poor consistency of traditional methods.

[0066] By scanning the laminated plate and calculating the overall offset field, the superposition effect of additional deformation introduced during lamination and residual deviation from pre-alignment was obtained. This allows subsequent compensation to specifically cover deformation throughout the entire process, further reducing interlayer alignment errors. Combining the overall offset field with the first compensation plan, a dynamic compensation file is generated to ensure that subsequent processing steps can accurately offset the overall deformation, effectively avoiding problems such as short circuits, open circuits, and signal crosstalk caused by interlayer offset.

[0067] In step 101 above, based on the stack-up design data and material property parameters of the target multilayer circuit board, the specific implementation method for calculating the theoretical deformation field generated by each layer of the circuit board under preset process conditions can be found in [reference needed]. Figure 2 , Figure 2 An embodiment of the method for calculating theoretical deformation fields provided in this application includes: 201. Analyze the stack-up design data of the target multilayer circuit board and extract the geometric structure information of each layer of the circuit board; Import the stack-up design file into the analysis software and extract key information one by one according to the layer sequence. Key information includes: the planar dimensions and thickness tolerance of each layer of the circuit board, the stack-up order and the distribution range and thickness parameters of the interlayer dielectric, the design coordinates and geometric parameters of the alignment marks, and the position coordinates and diameter of the key holes. The extracted geometric structure information is then standardized and organized, redundant data is removed, and a hierarchical and categorized structured data list is formed.

[0068] 202. Based on the structural information, material property parameters, and preset process conditions, construct a three-dimensional finite element model; Using the solid modeling function of finite element simulation software, three-dimensional geometric entities of each layer of substrate, circuit copper foil, interlayer dielectric and alignment marks are constructed sequentially according to the stacking order, replicating the spatial positional relationship of each structure to ensure that the geometric features of the model are consistent with those of the actual product; material property parameters are assigned values ​​according to the corresponding structural units to ensure that the mechanical and thermal properties of different material regions match those of the actual product. The preset process conditions are transformed into boundary conditions and load parameters, which are then input into the three-dimensional finite element model to constrain the model in simulating the stress and temperature and other environmental conditions during the actual production process.

[0069] 203. Mesh the three-dimensional finite element model and eliminate distorted elements in the mesh; The three-dimensional finite element model is divided into fine sections by using a partitioning method to ensure that local stress and deformation can be accurately captured in each region. After performing the mesh generation operation, the generated mesh is comprehensively inspected, with a focus on identifying malformed elements. Malformed elements are those with excessively high distortion rates, unbalanced aspect ratios, or Jacobian determinants that do not meet the requirements. For the detected malformed elements, a local mesh reconstruction method is used to eliminate them, ensuring that the quality of all mesh elements meets the convergence requirements of stress-strain calculations.

[0070] 204. Based on the processed finite element model, the stress-strain relationship of the multilayer circuit board under the preset process conditions is calculated; In the finite element simulation software, set the solver type, calculation step size, and convergence criterion. Then, start the simulation calculation, and based on the model's material properties, boundary conditions, and load parameters, solve for the stress and strain values ​​of each element at different process stages using numerical calculation methods. After calculation, stress-strain data for key areas of each circuit board layer are extracted to form stress and strain distribution cloud maps. Key areas include densely packed circuit areas, edge areas, and alignment marker areas. Simultaneously, stress and strain tensor data for each element are compiled to provide foundational data for subsequent deformation field conversion.

[0071] 205. Convert the stress-strain relationship into a theoretical deformation field, which is the displacement vector field of each layer of the circuit board in three-dimensional space.

[0072] The strain tensor data of each element are converted into corresponding displacement components (including linear displacements in the X, Y, and Z directions), and the three-dimensional displacement data of all nodes in the three-dimensional finite element model are obtained by solving. The three-dimensional displacement data of all nodes are integrated according to spatial coordinates to form a full-field displacement vector dataset, which contains the displacement magnitude and direction information of each node on the plate. Interpolation processing is performed on the full-field displacement vector dataset to form a continuous and smooth three-dimensional displacement vector field, i.e., the theoretical deformation field. The theoretical deformation field can intuitively reflect the various deformation characteristics of each layer of the circuit board under preset process conditions, such as translation, rotation, warping, and local stretching / shrinkage, providing accurate data support for the subsequent compensation strategy formulation.

[0073] In step 202 above, for a detailed implementation method of constructing a three-dimensional finite element model based on structural information, material property parameters, and preset process conditions, please refer to [reference needed]. Figure 3 , Figure 3 An embodiment of the method for constructing a three-dimensional finite element model provided in this application includes: 301. Based on the structural information and material property parameters, construct a three-dimensional finite element model; The parametric modeling function of finite element simulation software was used to reconstruct the physical structure of the multilayer circuit board layer by layer. Three-dimensional solids of each substrate layer were constructed, and then the solid structure of the copper foil circuitry was built according to the distribution coordinates and dimensions of the circuit pattern. Finally, key features such as alignment marks, vias, and positioning holes were added.

[0074] According to the material type of each structural unit in the model, the corresponding material property parameters are matched and assigned one by one. For the substrate, its thermodynamic and mechanical parameters such as thermal expansion coefficient, elastic modulus, Poisson's ratio, and thermal conductivity coefficient are entered; for copper foil circuits, corresponding conductivity and mechanical parameters are assigned; for interlayer bonding materials, core parameters related to deformation such as curing shrinkage rate, elastic modulus, and viscosity change curve are entered.

[0075] After modeling is completed, check whether there are geometric defects in each layer structure, whether the dimensions of key features are consistent with the design data, and whether the spatial relationship between the layers meets the stacking requirements, so as to ensure that the model can truly reflect the physical structure and material distribution of the multilayer circuit board.

[0076] 302. Set boundary conditions and load conditions in the three-dimensional finite element model according to the preset process conditions.

[0077] Based on preset process conditions, the X / Y translational degrees of freedom of the model edges are constrained, while the Z-axis stretching degree of freedom is retained to ensure that the model can simulate the thickness deformation of the sheet material during lamination. Simultaneously, the initial temperature conditions of the model are set according to preset environmental parameters.

[0078] Regarding the thermal load of the lamination process, the temperature change pattern of each process stage is defined step by step through the temperature load function according to the preset heating rate, constant temperature and holding time, and cooling rate. Regarding the pressure load, the model surface is applied with a uniform load according to the preset lamination pressure. At the same time, local load correction is performed in areas with dense lines, edge areas and other areas where pressure is easily unevenly distributed, based on the pressure transmission characteristics in the actual lamination process.

[0079] For a detailed implementation of converting the stress-strain relationship into a theoretical deformation field in step 205 above, please refer to [link to relevant documentation]. Figure 4 , Figure 4 An embodiment of the method for converting theoretical deformation fields provided in this application includes: 401. Extract the stress tensor and strain tensor of each element under preset process conditions from the three-dimensional finite element model; For each element in the 3D finite element model, stress and strain tensor data under preset process conditions are extracted one by one. The stress tensor contains the components of normal stress and shear stress, and the strain tensor contains the components of normal strain and shear strain. During the extraction process, the magnitude, direction, and corresponding element coordinates of each tensor component are preserved. The extracted stress and strain tensor data are classified and stored according to the element's layer and structural type, generating a structured data table, and the geometric parameters of the element are associated with it.

[0080] 402. Based on the strain tensor, solve for the displacement components of all nodes in the three-dimensional finite element model in three-dimensional space; Using nodes of a three-dimensional finite element model as computational units, and based on the strain tensor data of the units to which they belong, the displacement components of the nodes in three-dimensional space are solved, including translational displacement in the X direction, translational displacement in the Y direction, and translational displacement in the Z direction.

[0081] 403. Combine the displacement components of all nodes to generate a full-field displacement vector dataset; For each node, its 3D displacement vector is associated with its spatial coordinates, forming a one-to-one correspondence between coordinates and displacement vectors. Based on the spatial topology of the 3D finite element model, the coordinate-displacement vector data of all nodes are integrated globally to generate a full-field displacement vector dataset. This dataset is then preliminarily cleaned to remove invalid data and correct outliers.

[0082] 404. Process the full-field displacement vector dataset to generate the theoretical deformation field.

[0083] An interpolation algorithm is used to process the full-field displacement vector dataset, filling in the gaps in displacement data between nodes and generating a continuous and smooth displacement distribution field. Key deformation features are extracted from the continuous displacement distribution field, and then the continuous displacement distribution field is combined with deformation feature parameters to generate a theoretical deformation field with a three-dimensional displacement vector field as its core.

[0084] Please see Figure 5 , Figure 5 An embodiment of the method for optimizing a three-dimensional finite element model provided in this application includes: 501. Based on the dynamic compensation file, process the multilayer circuit board and obtain the actual alignment accuracy data of the processed multilayer circuit board; The dynamic compensation file generated in step 107 is imported into subsequent processing equipment (such as CNC drilling machine, laser etching machine, solder resist exposure machine, etc.). The equipment automatically adds compensation parameters in the corresponding processing steps based on the imported dynamic compensation file.

[0085] After processing, the multilayer circuit board undergoes comprehensive inspection, including: continuity accuracy of interlayer vias / blind / buried vias, alignment accuracy of trace intersection areas, and coincidence accuracy of alignment marks. The inspection data is quantified and recorded to generate actual alignment accuracy data.

[0086] 502. Optimize the three-dimensional finite element model based on the actual alignment accuracy data.

[0087] The actual alignment accuracy data is compared with the theoretical deformation data predicted by the 3D finite element model, region by region and feature by feature, and the deviation value between the two is calculated. Based on the comparative analysis of the deviation values, the key input parameters of the 3D finite element model are optimized accordingly. If the deviation originates from material property parameters, the core parameters such as the coefficient of thermal expansion, curing shrinkage rate, and elastic modulus of the actual material are re-measured experimentally and replaced with the original material parameters in the model. If the deviation originates from boundary conditions, the constraint degrees of freedom, friction coefficient, and other boundary parameters of the model are adjusted in conjunction with the positioning accuracy and pressure transmission characteristics of the actual lamination tooling. If the deviation originates from process parameter mapping, the application curves of temperature load and pressure load are optimized to make the process simulation in the model more closely match the actual production process. The adjustment process adopts the "single variable" principle to avoid difficulties in tracing the source of deviation caused by adjusting multiple parameters simultaneously.

[0088] In step 102 above, for the specific implementation of generating the first compensation instruction set and the first compensation plan based on the theoretical deformation field, please refer to [reference needed]. Figure 6 , Figure 6 An embodiment of the method for generating a first compensation instruction set and a first compensation plan provided in this application includes: 601. Decompose the theoretical deformation field of each layer of the circuit board into rigid displacement components and non-rigid deformation components. Rigid displacement refers to the spatial movement of the circuit board without any change in its overall shape, and includes only two basic forms: translation and rotation. Non-rigid deformation refers to deformation in which the shape of the circuit board itself changes, including forms such as warping, local stretching, local shrinkage, and twisting.

[0089] A rigid body transformation algorithm is used to fit and calculate the theoretical deformation field data of each circuit board layer. By solving for the common translation and rotation angles of the global displacement, the rigid displacement components of each circuit board layer are extracted. Then, the extracted rigid displacement components are subtracted from the original displacement vector data in the theoretical deformation field to obtain the remaining differential displacement data, which are the non-rigid deformation components.

[0090] 602. Generate displacement control parameters in the first compensation command set based on rigid displacement components, and generate attitude adjustment parameters in the first compensation command set based on non-rigid deformation components. Displacement control parameters are generated by combining the translation and rotation angles in the rigid displacement components with the motion control precision of the pre-alignment equipment before lamination. For the warping, local stretching, and other deformation forms corresponding to the non-rigid deformation components, attitude adjustment parameters are generated by combining the attitude adjustment capability of the pre-alignment equipment.

[0091] The generated displacement control parameters and attitude adjustment parameters are formatted and integrated according to the instruction protocol of the pre-alignment device, and parameter activation conditions and parameter verification thresholds are added to form a complete first compensation instruction set.

[0092] 603. Based on the non-rigid deformation components and the laminated design data, predict the superposition effect of deformation of each inner layer during the lamination process; Retrieve the stack-up design data extracted in step 201 to clarify key parameters such as material type, thickness, circuit distribution density, and interlayer dielectric type and thickness for each circuit board layer. Analyze the non-rigid deformation component characteristics of different layers and, in conjunction with the bonding characteristics of the interlayer dielectric, determine the deformation interaction mode between adjacent layers.

[0093] The interlayer coupling simulation algorithm is adopted, taking the non-rigid deformation components of each layer as input, and combining the influence of lamination process conditions on interlayer interaction to simulate the deformation transmission and superposition process of each layer during lamination. It also predicts the superposition effect of deformation of each inner layer during lamination and the comprehensive non-rigid deformation characteristics of the laminate after lamination.

[0094] 604. Generate the first compensation plan based on the prediction results.

[0095] Based on the prediction results of the superposition effect and the post-lamination processing steps, the key links requiring compensation in each process are analyzed. Differentiated compensation strategies are formulated for the compensation needs of different processing steps. For example, for the drilling process, based on the predicted hole position offset, the specific correction parameters for the drilling coordinates in different areas are determined; for the etching process, based on the predicted line misalignment, the offset direction and amount of line etching are determined.

[0096] The compensation strategies, parameters, execution order, and effectiveness verification standards for each process are integrated to form a standardized primary compensation plan. The plan outlines the correspondence between each compensation parameter and the predicted superposition effect, prioritizes key compensation areas, and provides parameter adjustment interfaces for subsequent precise correction based on comprehensive offset field data, ensuring the plan's relevance and flexibility.

[0097] In step 104 above, the measured deformation field of each circuit board layer is compared with the corresponding theoretical deformation field, and the specific implementation method of the first compensation instruction set is modified based on the comparison results. (See also: [link to relevant documentation]). Figure 7 , Figure 7An embodiment of the method for modifying the first compensation instruction set provided in this application includes: 701. For each layer of the circuit board, calculate the displacement vector difference between the measured deformation field and the corresponding theoretical deformation field to generate the corresponding deformation difference field. The measured deformation fields of each circuit board layer are aligned with the corresponding theoretical deformation fields in spatial coordinates. During the alignment process, the reference alignment marks on the circuit board are used as reference anchor points to correct any possible coordinate offsets and avoid calculation errors caused by coordinate mismatch.

[0098] Based on each aligned circuit board layer, all corresponding nodes in the measured deformation field and the theoretical deformation field are traversed, and the displacement vector difference between the two is calculated point by point. The displacement vector difference data of all nodes in each circuit board layer are integrated according to their spatial coordinates to form a deformation difference field covering the entire domain.

[0099] 702. Based on a preset deformation tolerance threshold, identify key difference regions that exceed the deformation tolerance threshold from the deformation difference field; Considering the interlayer alignment accuracy requirements of multilayer circuit boards, the adjustment capability of pre-alignment equipment, and the error tolerance of subsequent processing steps, a reasonable deformation tolerance threshold is manually set. All nodes in the deformation difference field are traversed, and the displacement vector difference amplitude of each node is compared with the preset deformation tolerance threshold one by one, marking all abnormal nodes that exceed the threshold. During the screening process, the coordinate information, displacement vector difference data, and regional characteristics of the abnormal nodes are retained to avoid missing key deviation nodes.

[0100] Spatial clustering analysis is performed on the marked anomalous nodes to integrate adjacent anomalous nodes into continuous regions, which are the key difference regions. The contour range and area of ​​each key difference region are determined by the boundary extraction algorithm, the spatial distribution of each region is clarified, and the maximum and average deviation values ​​within each key difference region are calculated.

[0101] 703. Assign corresponding correction weight coefficients based on the geometric location, magnitude of difference, and degree of impact on accuracy of key difference regions; A comprehensive analysis of the core factors influencing the weighting of corrections reveals the following: First, the importance of geometric location, with key areas such as the perimeter of critical holes, line intersections, and the perimeter of benchmark alignment marks having higher weights than ordinary areas; second, the magnitude of the difference, with areas having larger deviation amplitudes having higher weight coefficients; third, the degree of impact on accuracy, with areas having a greater impact on core functions such as interlayer conduction and line connection having higher weight coefficients; and fourth, the area of ​​the region, with larger, continuous areas of difference having higher weights than scattered, small areas.

[0102] Based on the aforementioned influencing factors, a weighting coefficient grading standard is established, dividing the modified weighting coefficients into multiple levels (e.g., a range of 0.1-1.0, with intervals of 0.1). For example, the weighting coefficient for the area surrounding critical well locations with a deviation amplitude > 2 μm is set to 1.0, and the weighting coefficient for ordinary areas with a deviation amplitude of 0.6-1 μm is set to 0.3. The combination conditions of influencing factors corresponding to each level are clearly defined to ensure the standardization of weight allocation.

[0103] By comparing the key difference regions, we analyze the geometric location, size of the difference, degree of impact on accuracy, and area characteristics of each region, and assign a corresponding correction weight coefficient to each key difference region according to the established grading criteria.

[0104] 704. Generate a compensation mapping relationship based on the modified weight coefficients of the deformation difference field and the key difference region; Based on error compensation theory, a compensation calculation model is constructed. The model uses the displacement vector difference in the deformation difference field as the basic variable and the correction weight coefficient as the adjustment variable. The coefficient of the adjustment variable is determined according to the adjustment accuracy of the pre-alignment equipment to ensure that the calculated compensation adjustment amount is within the adjustment capability range of the equipment.

[0105] The displacement vector difference data of each node in the deformation difference field and the corresponding correction weight coefficients are substituted into the compensation amount calculation model to calculate the compensation adjustment amount of each node in the entire domain point by point. The coordinate information, displacement vector difference data, correction weight coefficients and corresponding compensation adjustment amounts of each node are correlated and integrated to form a compensation mapping relationship.

[0106] 705. Modify the first compensation instruction set according to the compensation mapping relationship.

[0107] The first compensation command set is parsed to extract displacement control parameters and attitude adjustment parameters. Based on the compensation mapping relationship, the compensation adjustment amounts of each node are integrated into the original compensation command parameters. For displacement control parameters, the original translation parameters are corrected based on the X and Y direction compensation adjustment amounts for the corresponding regions, and the original rotation parameters are corrected based on the Z direction rotation compensation adjustment amounts. For attitude adjustment parameters, the original support point adjustment amounts, vacuum adsorption strength, and other parameters are corrected based on the compensation adjustment amounts for key difference regions. During the correction process, it is ensured that the new parameter values ​​do not exceed the equipment's adjustment range, and that the logical relationships between the parameters remain consistent.

[0108] The corrected compensation parameters are substituted into the deformation prediction model to simulate and calculate the corrected pre-alignment effect, verifying whether the corrected parameters can reduce the deviation in key difference areas to within the tolerance range. If the verification is successful, the corrected displacement control parameters and attitude adjustment parameters are re-integrated according to the equipment instruction protocol, and the parameter activation conditions and verification thresholds are updated to form the corrected first compensation instruction set; if the verification fails, the compensation mapping relationship and parameter correction process are re-checked until the pre-alignment effect meets the requirements.

[0109] For a detailed implementation of step 106 above, which involves scanning the alignment marks on the surface of the press plate and calculating the comprehensive offset field, please refer to [link to relevant documentation]. Figure 8 , Figure 8 An embodiment of the method for calculating the composite offset field provided in this application includes: 801. Acquire images of multiple pre-set alignment marks on the surface of the press plate and extract the actual center coordinates of each alignment mark; First, the pressing plate is positioned and fixed, placed stably on the stage, and secured with mechanical clamps to prevent displacement during acquisition that could lead to image blurring or coordinate deviation. The vision inspection system is then activated, and images are acquired one by one from multiple alignment marks evenly distributed on the surface of the pressing plate, following a preset acquisition path.

[0110] After preprocessing each acquired alignment mark image, a contour extraction algorithm is used to obtain the complete contour of the alignment mark, and then the actual center coordinates of each alignment mark are calculated.

[0111] 802. Compare the actual center coordinates with the theoretical design coordinates to calculate the position offset vector of the alignment mark; Retrieve the theoretical design coordinates of each alignment mark on the surface of the laminated plate from the laminated design database. Match the theoretical design coordinates with the actual center coordinates extracted in step 801 according to the mark number to ensure that the actual coordinates of each alignment mark are accurately associated with the corresponding theoretical coordinates and avoid comparison errors caused by number confusion.

[0112] For each matched alignment mark, calculate the offset of its actual center coordinates from its theoretical design coordinates in the X and Y directions, and mark the offset direction. Combine the X and Y offsets of each alignment mark to form the position offset vector of that mark.

[0113] 803. Based on the position offset vector, construct a comprehensive offset field. The comprehensive offset field is used to describe the estimated offset and direction at any position on the plate.

[0114] The position offset vector dataset generated in step 802 is preprocessed to remove abnormal offset vectors caused by damaged markers or acquisition errors. If the offset vector of the alignment marker in a certain area has obvious dispersion, the alignment marker images around the area are acquired and the offset vector is calculated to ensure that the basic data can reflect the continuity of regional deformation.

[0115] Using the position offset vectors of each alignment mark as known sample points, interpolation calculations are performed across the entire surface of the press-fit plate. Through interpolation, the estimated offset of any pixel or any preset grid point on the plate surface is obtained. The estimated offset data obtained from the global interpolation are then integrated to construct a comprehensive offset field.

[0116] For a detailed implementation method of generating a dynamic compensation file based on the integrated offset field and the first compensation plan in step 107 above, please refer to [link to relevant documentation]. Figure 9 , Figure 9 An embodiment of the method for modifying the first compensation instruction set provided in this application includes: 901. Based on the comprehensive offset field, select a compensation strategy from the first compensation plan and determine the application parameters of the compensation strategy; The standard compensation rule library in the first compensation plan is retrieved, and the comprehensive offset field characteristics obtained from the analysis are compared one by one with the applicable conditions of each compensation strategy in the rule library to select the optimal compensation strategy that is suitable for the current deformation state.

[0117] Based on the quantized data of the comprehensive offset field, and combined with the selected compensation strategy, specific application parameters are calculated and determined. The selected compensation strategy and determined application parameters are then substituted into the deformation simulation model to simulate the processing effect after compensation and predict the residual offset in each region after compensation. If the residual offset does not meet the preset accuracy requirements (e.g., ≤0.2μm), the compensation strategy is readjusted or the application parameters are optimized until the simulated compensation effect meets the requirements, ensuring the effectiveness of the strategy and parameters.

[0118] 902. Based on the selected compensation strategy and application parameters, convert the composite offset field into an instruction sequence, and encapsulate the instruction sequence into a dynamic compensation file.

[0119] Based on the control protocol and instruction format of the subsequent processing equipment, the application parameters corresponding to the compensation strategy are converted into an instruction sequence that the equipment can recognize. During the conversion process, the instructions need to be ordered according to the sequence of processing steps, and the execution conditions and triggering times of each instruction need to be clearly defined. At the same time, a parameter check code is added to each instruction to ensure that the equipment can verify the integrity and accuracy of the parameters after receiving the instruction, avoiding errors in instruction transmission or parsing.

[0120] The instruction sequence is encapsulated according to a standardized file format to generate a dynamic compensation file. In addition to the instruction sequence, the file must also include header information, file verification information, and parameter descriptions. After encapsulation, the file is compressed to reduce its size, facilitating transmission and storage.

[0121] Please see Figure 10 This application provides an embodiment of an interlayer alignment device for a multilayer circuit board, comprising: The first calculation unit 1001 is used to calculate the theoretical deformation field of each layer of the circuit board under preset process conditions based on the stack-up design data and material property parameters of the target multilayer circuit board. The first generation unit 1002 is used to generate a first compensation instruction set and a first compensation plan based on the theoretical deformation field. The first compensation instruction is a control signal for driving the pre-alignment equipment before lamination, and the first compensation plan is a control signal for driving the post-lamination processing equipment. The second calculation unit 1003 is used to scan the actual spatial coordinates of the alignment marks on each layer of the circuit board and calculate the measured deformation field of each layer of the circuit board. The correction unit 1004 is used to compare the measured deformation field of each layer of the circuit board with the corresponding theoretical deformation field, and correct the first compensation instruction set according to the comparison result. The adjustment unit 1005 is used to control the pre-alignment device before lamination to adjust the displacement and attitude of the circuit board of the corresponding layer according to the corrected first compensation instruction set. Processing unit 1006 is used to scan the alignment marks on the surface of the press plate and calculate the comprehensive offset field. The press plate is a kind of board material made of alternating stacking and pressing of multilayer circuit boards and insulating media. The second generation unit 1007 is used to generate a dynamic compensation file based on the integrated offset field and the first compensation plan.

[0122] Optionally, the first computing unit 1001 is also used for: The stack-up design data of the target multilayer circuit board is analyzed to extract the geometric structure information of each layer of the circuit board; Based on structural information, material property parameters, and preset process conditions, a three-dimensional finite element model is constructed. Mesh the 3D finite element model and eliminate distorted elements in the mesh; Based on the processed finite element model, the stress-strain relationship of the multilayer circuit board under the preset process conditions is calculated. The stress-strain relationship is converted into a theoretical deformation field, which is the displacement vector field of each layer of the circuit board in three-dimensional space.

[0123] Optionally, the interlayer alignment device also includes: The acquisition unit 1008 is used to process the multilayer circuit board according to the dynamic compensation file and acquire the actual alignment accuracy data of the processed multilayer circuit board. The optimization unit 1009 is used to optimize the three-dimensional finite element model based on the actual alignment accuracy data.

[0124] Optionally, the first generating unit 1002 is also used for: The theoretical deformation field of each layer of the circuit board is decomposed into rigid displacement components and non-rigid deformation components. Displacement control parameters in the first compensation instruction set are generated based on rigid displacement components, and attitude adjustment parameters in the first compensation instruction set are generated based on non-rigid deformation components. Based on the non-rigid deformation components and the laminated design data, the superposition effect of deformation of each inner layer during the lamination process is predicted. The first compensation plan is generated based on the prediction results.

[0125] Optionally, the correction unit 1004 is also used for: For each circuit board layer, the displacement vector difference between the measured deformation field and the corresponding theoretical deformation field is calculated to generate the corresponding deformation difference field. Based on a preset deformation tolerance threshold, key difference regions exceeding the deformation tolerance threshold are identified from the deformation difference field; Based on the geometric location of the key difference regions, the magnitude of the difference, and the degree to which they affect accuracy, assign corresponding correction weight coefficients; Based on the modified weight coefficients of the deformation difference field and the key difference region, a compensation mapping relationship is generated; Based on the compensation mapping relationship, modify the first compensation instruction set.

[0126] Optionally, the processing unit 1006 is also used for: Images are acquired from multiple pre-set alignment marks on the surface of the press plate, and the actual center coordinates of each alignment mark are extracted. By comparing the actual center coordinates with the theoretical design coordinates, the position offset vector of the alignment mark is calculated. Based on the position offset vector, a comprehensive offset field is constructed, which is used to describe the estimated offset and direction at any position on the plate surface.

[0127] Optionally, the second generating unit 1007 is also used for: Based on the comprehensive offset field, a compensation strategy is selected from the first compensation plan, and the application parameters of the compensation strategy are determined. The first compensation plan contains a standard compensation rule library for different offset modes. Based on the selected compensation strategy and application parameters, the composite offset field is converted into a command sequence, and the command sequence is encapsulated into a dynamic compensation file.

[0128] For detailed implementation methods, please refer to... Figures 1 to 9 Examples are not detailed here.

[0129] Please see Figure 11 This application provides an interlayer alignment device for a multilayer circuit board, comprising: Processor 1101, memory 1102, input / output unit 1103 and bus 1104.

[0130] The processor 1101 is connected to the memory 1102, the input / output unit 1103 and the bus 1104.

[0131] The memory 1102 stores a program, and the processor 1101 calls the program to execute it, such as... Figures 1 to 9 The method in the middle.

[0132] This application provides a computer-readable storage medium on which a program is stored, and when the program is executed on a computer, it performs the following... Figures 1 to 9 The method in the middle.

[0133] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0134] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces, or indirect coupling or communication connection between apparatuses or units, and may be electrical, mechanical, or other forms.

[0135] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0136] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0137] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

Claims

1. A method for interlayer alignment of a multilayer circuit board, characterized in that, include: Based on the stack-up design data and material property parameters of the target multilayer circuit board, the theoretical deformation field generated by each layer of the circuit board under the preset process conditions is calculated. Based on the theoretical deformation field, a first compensation instruction set and a first compensation plan are generated. The first compensation instruction is a control signal for driving the pre-alignment device before lamination, and the first compensation plan is a control signal for driving the post-lamination processing device. Scan the actual spatial coordinates of the alignment marks on each layer of the circuit board and calculate the measured deformation field of each layer of the circuit board; The measured deformation field of each circuit board layer is compared with the corresponding theoretical deformation field, and the first compensation instruction set is corrected according to the comparison result. According to the revised first compensation instruction set, the pre-alignment device before lamination is controlled to adjust the displacement and attitude of the circuit board of the corresponding layer. The alignment marks on the surface of the press plate are scanned, and the comprehensive offset field is calculated. The press plate is a type of board material formed by alternating stacking and pressing of multilayer circuit boards and insulating media. Based on the comprehensive offset field and the first compensation plan, a dynamic compensation file is generated; The step of generating a first compensation instruction set and a first compensation plan based on the theoretical deformation field includes: The theoretical deformation field of each circuit board layer is decomposed into rigid displacement components and non-rigid deformation components. Displacement control parameters in the first compensation instruction set are generated based on the rigid displacement components, and attitude adjustment parameters in the first compensation instruction set are generated based on the non-rigid deformation components. Based on the non-rigid deformation components and the laminated design data, predict the superposition effect of deformation of each inner layer during the lamination process; A first compensation plan will be generated based on the prediction results; The process of decomposing the theoretical deformation field of each circuit board layer into rigid displacement components and non-rigid deformation components includes: A rigid body transformation algorithm is used to fit and calculate the theoretical deformation field of each layer of the circuit board. By solving the common translation and common rotation angle of the global displacement, the rigid displacement components of each layer of the circuit board are extracted. The rigid displacement components are then subtracted from the original displacement vector data in the theoretical deformation field to obtain the non-rigid deformation components.

2. The interlayer alignment method according to claim 1, characterized in that, The calculation of the theoretical deformation field of each layer of the circuit board under preset process conditions, based on the stack-up design data and material property parameters of the target multilayer circuit board, includes: The stack-up design data of the target multilayer circuit board is analyzed to extract the geometric structure information of each layer of the circuit board; Based on the structural information, material property parameters, and preset process conditions, a three-dimensional finite element model is constructed. The three-dimensional finite element model is meshed, and deformed elements in the mesh are eliminated; Based on the processed finite element model, the stress-strain relationship of the multilayer circuit board under the preset process conditions is calculated; The stress-strain relationship is converted into a theoretical deformation field, which is the displacement vector field of each layer of the circuit board in three-dimensional space.

3. The interlayer alignment method according to claim 2, characterized in that, The construction of a three-dimensional finite element model based on the structural information, material property parameters, and preset process conditions includes: Based on the structural information and material property parameters, a three-dimensional finite element model is constructed. Boundary conditions and load conditions are set in the three-dimensional finite element model according to the preset process conditions.

4. The interlayer alignment method according to claim 2, characterized in that, The process of converting the stress-strain relationship into a theoretical deformation field, wherein the theoretical deformation field is the displacement vector field of each layer of the circuit board in three-dimensional space, includes: Extract the stress tensor and strain tensor of each element under the preset process conditions from the three-dimensional finite element model; Based on the strain tensor, solve for the displacement components of all nodes in the three-dimensional finite element model in three-dimensional space. The displacement components of all nodes are combined to generate a full-field displacement vector dataset; The full-field displacement vector dataset is processed to generate a theoretical deformation field.

5. The interlayer alignment method according to claim 2, characterized in that, The step of generating a dynamic compensation file based on the comprehensive offset field and the first compensation plan, wherein the dynamic compensation file is a summary of the compensation amounts for subsequent processes, further includes: Based on the dynamic compensation file, the multilayer circuit board is processed, and the actual alignment accuracy data of the processed multilayer circuit board is obtained. The three-dimensional finite element model is optimized based on the actual alignment accuracy data.

6. The interlayer alignment method according to claim 1, characterized in that, The step of comparing the measured deformation field of each circuit board layer with the corresponding theoretical deformation field, and correcting the first compensation instruction set based on the comparison result, includes: For each layer of the circuit board, the displacement vector difference between the measured deformation field and the corresponding theoretical deformation field is calculated to generate the corresponding deformation difference field. Based on a preset deformation tolerance threshold, key difference regions exceeding the deformation tolerance threshold are identified from the deformation difference field. Based on the geometric location, magnitude of difference, and degree of impact on accuracy of the key difference regions, corresponding correction weight coefficients are assigned; A compensation mapping relationship is generated based on the modified weight coefficients of the deformation difference field and the key difference region; The first compensation instruction set is modified according to the compensation mapping relationship.

7. The interlayer alignment method according to any one of claims 1 to 6, characterized in that, The alignment marks on the surface of the scanning press plate are used to calculate the comprehensive offset field, including: Images are acquired from multiple pre-set alignment marks on the surface of the press plate, and the actual center coordinates of each alignment mark are extracted. The actual center coordinates are compared with the theoretical design coordinates to calculate the position offset vector of the alignment mark; Based on the position offset vector, a comprehensive offset field is constructed, which is used to describe the estimated offset and direction at any position on the plate surface.

8. The interlayer alignment method according to claim 1, characterized in that, The step of generating a dynamic compensation file based on the integrated offset field and the first compensation plan includes: Based on the comprehensive offset field, a compensation strategy is selected from the first compensation plan, and the application parameters of the compensation strategy are determined; Based on the selected compensation strategy and the application parameters, the integrated offset field is converted into an instruction sequence, and the instruction sequence is encapsulated into a dynamic compensation file.

9. A multilayer circuit board interlayer alignment device, applied to the interlayer alignment method according to any one of claims 1-8, characterized in that, include: The first calculation unit is used to calculate the theoretical deformation field of each layer of the circuit board under preset process conditions based on the stack-up design data and material property parameters of the target multilayer circuit board. The first generation unit is used to generate a first compensation instruction set and a first compensation plan based on the theoretical deformation field. The first compensation instruction is a control signal for driving the pre-alignment device before lamination, and the first compensation plan is a control signal for driving the post-lamination processing device. The second calculation unit is used to scan the actual spatial coordinates of the alignment marks on each layer of the circuit board and calculate the measured deformation field of each layer of the circuit board. The correction unit is used to compare the measured deformation field of each layer of the circuit board with the corresponding theoretical deformation field, and correct the first compensation instruction set according to the comparison result. The adjustment unit is used to control the pre-alignment device before lamination to adjust the displacement and attitude of the circuit board of the corresponding layer according to the modified first compensation instruction set. The processing unit is used to scan the alignment marks on the surface of the press plate and calculate the comprehensive offset field. The press plate is a type of board material formed by alternating stacking and pressing of multilayer circuit boards and insulating media. The second generation unit is used to generate a dynamic compensation file based on the integrated offset field and the first compensation plan.

10. A multilayer circuit board interlayer alignment device, characterized in that, include: The processor, memory, input / output unit, and bus are connected to the memory, the input / output unit, and the bus. The memory stores a program, and the processor calls the program to execute the interlayer alignment method for a multilayer circuit board as described in any one of claims 1 to 8.

11. A computer-readable storage medium, characterized in that, The computer-readable storage medium contains a program that, when executed on a computer, performs the interlayer alignment method for a multilayer circuit board as described in any one of claims 1 to 8.

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