Method and apparatus for obtaining timing path optimization information

Abstract

This application provides a method and apparatus for obtaining timing path optimization information, relating to the field of computer technology. The method includes: determining an initial path group from timing path groups obtained through a preset grouping method; for each initial path group, calculating a second quantity corresponding to the initial path group based on a first quantity of violation timing paths in the initial path group, and determining a target timing path based on the second quantity corresponding to the initial path group and the path information of each violation timing path included therein, wherein the path information includes timing margin, and the number of target timing paths determined from an initial path group is not greater than the corresponding second quantity; obtaining the target weight corresponding to the target timing path, and using optimization information to indicate the target timing path and its corresponding target weight. In this way, path optimization information can be automatically obtained, and the poor optimization effect caused by extracting a fixed number of target timing paths can be avoided.

Description

Technical Field

[0001] This application relates to the field of computer technology, and more specifically, to a method and apparatus for obtaining time-series path optimization information. Background Technology

[0002] In current VLSI (Integrated Circuit) logic synthesis (e.g., using EDA tools like Synopsys Design Compiler), when faced with a massive number of timing violations (often exceeding 5000), engineers typically rely on experience to manually identify a fixed number of violation timing paths and assign them high optimization weights. Path optimization is then performed based on this timing path optimization information. However, this method heavily depends on the engineer's experience, consumes a significant amount of time, and is essentially unreusable. Summary of the Invention

[0003] This application provides a method, apparatus, electronic device, and readable storage medium for obtaining timing path optimization information. It can automatically obtain path optimization information, saving a lot of manpower and time. Furthermore, since the target timing path to be optimized is determined based on the number of current violation timing paths, it can avoid the situation where the optimization effect is poor due to a large or small number of target timing paths.

[0004] The embodiments of this application can be implemented as follows: In a first aspect, embodiments of this application provide a method for obtaining timing path optimization information, the method comprising: The initial path group is determined from the time-series path group obtained through a preset grouping method; For each initial path group, the second number corresponding to the initial path group is calculated based on the first number of violation timing paths in the initial path group; For each initial path group, a target timing path is determined based on the second quantity corresponding to the initial path group and the path information of each violation timing path included therein. The path information includes timing margin, and the number of target timing paths determined from an initial path group is not greater than the corresponding second quantity. Obtain the target weight corresponding to the target timing path, wherein the optimization information is used to indicate the target timing path and the corresponding target weight, and the target weight is greater than the default weight corresponding to the logic synthesis tool used.

[0005] Secondly, embodiments of this application provide a timing path optimization information acquisition device, the device comprising: The preprocessing module is used to determine the initial path group from the time-series path group obtained through a preset grouping method; The calculation module is used to calculate the second number corresponding to each initial path group based on the first number of violation timing paths in the initial path group. The filtering module is used to determine the target timing path for each initial path group based on the second quantity corresponding to the initial path group and the path information of each violation timing path included therein. The path information includes timing margin, and the number of target timing paths determined from an initial path group is not greater than the corresponding second quantity. The weight acquisition module obtains the target weight corresponding to the target time sequence path. The optimization information is used to indicate the target time sequence path and the corresponding target weight. The target weight is greater than the default weight corresponding to the logic synthesis tool used.

[0006] Thirdly, embodiments of this application provide an electronic device, including a processor and a memory, wherein the memory stores machine-executable instructions that can be executed by the processor, and the processor can execute the machine-executable instructions to implement the timing path optimization information acquisition method described in the foregoing embodiments.

[0007] Fourthly, embodiments of this application provide a readable storage medium storing a computer program thereon, which, when executed by a processor, implements the timing path optimization information acquisition method as described in the foregoing embodiments.

[0008] The timing path optimization information acquisition method, apparatus, electronic device, and readable storage medium provided in this application, for each initial path group determined from timing path groups obtained through a preset grouping method, calculates a second quantity corresponding to the initial path group based on a first quantity of violation timing paths in the initial path group. Then, based on the second quantity corresponding to the initial path group and the path information of each violation timing path included, a target timing path is determined, and a target weight corresponding to the target timing path is obtained. The path information includes timing margins, and the number of target timing paths determined from an initial path group is not greater than the corresponding second quantity. Optimization information is used to indicate the target timing path and its corresponding target weight, and the target weight is greater than the default weight corresponding to the logic synthesis tool used. In this way, path optimization information can be automatically obtained, saving a significant amount of manpower and time. Furthermore, since the target timing path to be optimized is determined based on the current number of violation timing paths, the poor optimization effect caused by extracting a fixed number of target timing paths due to a large or small fixed number can be avoided. Attached Figure Description

[0009] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0010] Figure 1 A block diagram illustrating an electronic device provided in an embodiment of this application; Figure 2 A flowchart illustrating the method for obtaining timing path optimization information provided in an embodiment of this application; Figure 3 for Figure 2 A flowchart illustrating the sub-steps included in step S120; Figure 4 for Figure 2 A flowchart illustrating the sub-steps included in step S130; Figure 5 for Figure 4 A flowchart illustrating the sub-steps included in the neutron step S131; Figure 6 for Figure 5 A flowchart illustrating the sub-steps included in the neutron step S1313; Figure 7 for Figure 4 A flowchart illustrating the sub-steps included in the neutron step S132; Figure 8 for Figure 2 A flowchart illustrating the sub-steps included in step S140; Figure 9 A block diagram of a timing path optimization information acquisition device provided in an embodiment of this application.

[0011] Icons: 100 - Electronic device; 110 - Memory; 120 - Processor; 130 - Communication unit; 200 - Timing path optimization information acquisition device; 210 - Preprocessing module; 220 - Calculation module; 230 - Filtering module; 240 - Weight acquisition module. Detailed Implementation

[0012] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0013] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0014] It should be noted that relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0015] The inventors of this application have discovered that, when faced with a massive number of timing violations (often exceeding 5000), the following two processing schemes may be used to determine the timing paths to be optimized and their corresponding weights (i.e., optimization information). The weights are explained below. Timing paths are generally divided according to clock domains, resulting in clock path groups. The weight represents the degree of optimization to be applied by the tool. Each timing path group has a weight value. The timing optimization algorithm for the entire chip design essentially aims to minimize the "loss function." For example, if the timing violation of the entire module is 20ns (tns = -20ns, tns is an abbreviation for total negative slack), the ultimate goal is to make tns as close to 0 as possible. That is, to reduce the cost function. The cost function is generally equal to the sum of the "weight x tns of the clock group" of all clock path groups; it is a weighted sum concept. The weight of all clock path groups is 1 by default. That is, for the module mentioned above with a timing violation of 20ns, the default cost function value is 20ns. If you increase the weight of a certain clock path group, for example, by changing it from the default 1 to 10, the tool will focus on optimizing this path group with higher weight.

[0016] Option 1: Based on their experience, engineers extract a fixed number of worst-performing violation paths or all violation paths as the time-series paths to be prioritized for optimization, assigning them a uniformly high optimization weight. The fixed number may be very large or very small.

[0017] The following example illustrates Scheme 1, based on the aforementioned explanation of weights.

[0018] After the tool's optimization results with default weight settings are displayed, engineers review the corresponding timing reports. For example, the timing report might show five clock path groups: A, B, C, D, and E. Suppose path group A has 1000 timing violation paths, but the worst violation is only -0.01ns. Based on experience, engineers judge this path group to be generally acceptable and can be optimized using the default weight of 1 without updating its weight. On the other hand, suppose path group B has 100 timing violation paths, with the worst violation being -0.15ns. This path group is likely quite problematic, and based on experience, engineers would set its weight to 10 to allow the tool to optimize it aggressively. Then, engineers might discover that path group C has a staggering 1000 timing violations, with the worst violation being -0.2ns. This path group is likely even worse, so a higher weight, such as 20, would be set to allow the tool to optimize it more forcefully. Paths D and E have no timing violations, so their default weights are not considered for modification.

[0019] Based on the above analysis, the following optimization information is obtained: `group_path -weight 10 -name B -to [get_clocks B]`; `group_path -weight 20 -name C -to [get_clocks C]`. This optimization information can be applied to EDA tools for optimization. The above optimization information indicates that the weights corresponding to all violations in path group B are modified to 10, and the weights corresponding to all paths in path group C are modified to 20. In this method, violations within a path group share the same optimization weight; however, within the same clock path group, there may be many timing paths, but some paths have violation values ​​of -0.2ns, while others are only -0.05ns. Their severity differs, and they should not be optimized with the same optimization weight.

[0020] The above-mentioned Scheme 1 has the following shortcomings under extreme scales or specific complex topologies.

[0021] 1. Solver computational power dilution (gradient divergence). Manually assigning extremely high weights to a wide range of paths can cause cognitive overload in the underlying matrix solver of the synthesis tool. The tool's limited computational power is severely diluted by the massive number of long-tailed paths, causing the truly worst-case timing violation paths to fail to converge. Simultaneously, blindly expanding the high-optimal range results in significant area and leakage redundancy. These issues tend to occur when a fixed number of values ​​are used, or when the weights of the entire clock path group are directly modified.

[0022] 2. The waterbed effect is incompatible with wide-depth topologies. Methods that extract a fixed number of paths (e.g., the Top 100) are highly prone to causing severe overfitting in deep logic cones or wide datapath designs. To forcibly fix these few 100 paths, tools may violently preempt physical or logical resources from other related logic, causing a "whack-a-mole" effect of waterbed extraction. Furthermore, a fixed, very small number cannot completely cover all endpoints of a wide datapath, leading to optimization tearing. These issues tend to occur when the fixed number is used at a relatively small value.

[0023] 3. Manual processing methods rely on experience and are time-consuming. The traditional process of manually reading reports, determining the value of an optimization weight, and manually writing an optimization script relies heavily on the engineer's experience, consumes a lot of time during the iteration process, and may not be able to reuse the experience at all due to differences in the design logic itself.

[0024] Option 2: For example, use the native `create_auto_path_groups` command of the Synopsys Design Compiler synthesis tool to evenly split timing paths by module or design level and assign default weights. In this method, the weight of all modules and all clock path groups automatically split by the tool (a timing path in a clock path corresponds to a clock domain) is 1 by default.

[0025] The second approach described above suffers from a local masking effect. The purely automated approach of splitting the process into modules results in extremely low optimization weights for each path group. When performing global optimization, the tool lacks a clear focus, and severely problematic timing paths are submerged in a massive number of ordinary paths.

[0026] To address the above issues, this application provides a method, apparatus, electronic device, and readable storage medium for obtaining timing path optimization information. This method can automatically obtain path optimization information, saving significant manpower and time. Furthermore, since the target timing path to be optimized is determined based on the current number of non-compliant timing paths, it avoids the poor optimization effect caused by extracting a fixed number of target timing paths due to a large or small fixed number. It also avoids the dilution of solver computing power caused by directly fixing the weights of the entire clock path group to high weights. Additionally, it prevents severely non-compliant timing paths from being submerged in a massive number of ordinary paths.

[0027] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0028] Please refer to Figure 1 , Figure 1 This is a block diagram of an electronic device 100 provided in an embodiment of this application. The electronic device 100 may be, but is not limited to, a computer, a server, etc. The electronic device 100 may include a memory 110, a processor 120, and a communication unit 130. The memory 110, processor 120, and communication unit 130 are electrically connected to each other directly or indirectly to achieve data transmission or interaction. For example, these components can be electrically connected to each other through one or more communication buses or signal lines.

[0029] The memory 110 is used to store programs or data. The memory 110 may be, but is not limited to, random access memory (RAM), read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), etc.

[0030] The processor 120 is used to read / write data or programs stored in the memory 110 and execute corresponding functions. For example, the memory 110 stores a timing path optimization information acquisition device 200, which includes at least one software function module that can be stored in the memory 110 in the form of software or firmware. The processor 120 executes various functional applications and data processing by running the software programs and modules stored in the memory 110, such as the timing path optimization information acquisition device 200 in this embodiment, thereby implementing the timing path optimization information acquisition method in this embodiment.

[0031] The communication unit 130 is used to establish a communication connection between the electronic device 100 and other communication terminals through the network, and to send and receive data through the network.

[0032] It should be understood that, Figure 1 The structure shown is only a schematic diagram of the electronic device 100. The electronic device 100 may also include components that are larger than... Figure 1 The more or fewer components shown, or having the same Figure 1 The different configurations shown. Figure 1 The components shown can be implemented using hardware, software, or a combination thereof.

[0033] Please refer to Figure 2 , Figure 2 This is a flowchart illustrating a method for obtaining timing path optimization information provided in an embodiment of this application. The method can be applied to the aforementioned electronic device. The specific flow of the method for obtaining timing path optimization information is described in detail below. In this embodiment, the method may include steps S110 to S140.

[0034] Step S110: Determine the initial path group from the time-series path groups obtained through a preset grouping method.

[0035] In this embodiment, a preset grouping method is used to group timing paths. The specific method can be set according to actual needs, such as grouping by clock domain or using other methods. A timing path group may include only violation timing paths, or it may include both violation timing paths and normal timing paths (i.e., non-violation timing paths), which can be determined according to the actual situation.

[0036] Optionally, all determined timing path groups including violation timing paths can be used as initial path groups, or a subset of timing path groups including violation timing paths can be used as initial path groups. For example, initial path groups can be determined based on received user selection operations. The specific method for determining the initial path groups can be determined according to actual needs. Subsequently, for each initial path group, a subset of violation timing paths can be selected as target timing paths to be optimized, thereby facilitating subsequent optimization of the target timing paths by logic synthesis tools.

[0037] Step S120: For each initial path group, calculate the second number corresponding to the initial path group based on the first number of violation timing paths in the initial path group.

[0038] In this embodiment, for each initial path group, the total number of violation timing paths included in the initial path group is used as a first quantity, and a second quantity corresponding to the initial path group is dynamically calculated based on the first quantity. That is, the second quantity corresponding to each initial path group is dynamically calculated based on the first quantity corresponding to the initial path group, and is not a fixed quantity directly used as the second quantity corresponding to each initial path group.

[0039] Step S130: For each initial path group, determine the target timing path based on the second quantity corresponding to the initial path group and the path information of each violation timing path included.

[0040] The path information includes timing margins. If the timing margin of a timing path is less than 0, then that timing path can be identified as a violation timing path. For an initial path group, based on the timing margins of each violation timing path in the initial path group and the second quantity corresponding to the initial path group, a certain number of violation timing paths can be selected as target timing paths to be optimized. The number of target timing paths selected from the initial path group is no greater than the second quantity corresponding to the initial path group. The target timing paths to be optimized are the timing paths that will be the focus of subsequent optimization. For the remaining initial path groups, the above operation is repeated to determine the target timing paths corresponding to each remaining initial path group, thus obtaining the target timing paths for each initial path group.

[0041] Optionally, the specific method for determining the target timing path from an initial path group, combining timing margin and the second quantity, can be determined according to actual needs and is not specifically limited here. For example, selecting target timing paths in ascending order of timing margin can ensure that severely violated timing paths are selected.

[0042] Step S140: Obtain the target weight corresponding to the target time-series path.

[0043] Optionally, a pre-set value can be used as the target weight for the target timing path; alternatively, the target weight can be determined based on the timing margin of the target timing path—for example, a smaller timing margin corresponds to a larger target weight; other methods can also be used in conjunction with the timing margin of the target timing path to determine the target weight. The specific method for determining the target weight can be tailored to actual needs and is not specifically limited here. The target weight is greater than the default weight corresponding to the logic synthesis tool used. In this way, optimization information can be obtained, which is used to indicate the target timing path and its corresponding target weight. As described above, in this embodiment, after determining each initial path group, a corresponding second quantity can be determined for each initial path group. Then, based on this second quantity and the path information of the violation timing paths in the initial path group, target timing paths are filtered out and determined. The above process is repeated for the remaining initial path groups to obtain the target timing paths and target weights corresponding to each initial path group. Optimization information can indicate the target timing paths and target weights corresponding to each initial path group. In this way, path optimization information can be automatically obtained, saving significant manpower and time. Furthermore, since the target timing paths to be optimized are determined based on the current number of violation timing paths, it avoids the poor optimization effect caused by extracting a fixed number of target timing paths due to a large or small fixed number, and avoids the dilution of solver computing power caused by directly fixing the weights of the entire clock path group to high weights. It also prevents severely violation timing paths from being submerged in a massive number of ordinary paths.

[0044] One possible implementation is to first obtain the worst-case timing margin (WNS) for each timing path group obtained through a preset grouping method. Then, determine whether the worst-case timing margin is greater than (i.e., better than) the preset timing margin. If the worst-case timing margin is greater than the preset timing margin, then the timing path group is not used as an initial path group, meaning the weights of the non-violation timing paths in the initial path group are not modified. If the worst-case timing margin is less than or equal to the preset timing margin, then the timing path group is used as an initial path group. In this way, the initial path group can be determined through noise floor filtering, skipping the special weighting of timing path groups with minor violations, thus avoiding invalid involution.

[0045] The preset timing margin serves as the physical noise floor threshold for the process node. The specific value of the preset timing margin can be set according to actual needs. One possible implementation is to set the preset timing margin based on the clock jitter and setup time margin characteristics of the target chip's process node; for example, setting the preset timing margin to -0.05ns. The preset grouping method can be based on clock domain grouping.

[0046] As one possible implementation, for an initial path group, the product of the first number of violation timing paths in the initial path group and a pre-set coefficient greater than 0 and less than 1 can be used as the second number corresponding to the initial path group. In this way, the second number corresponding to the initial path group can be determined quickly.

[0047] As another possible implementation, it can be achieved through... Figure 3 The method shown obtains the second quantity corresponding to an initial path group. Please refer to... Figure 3 , Figure 3 for Figure 2 A flowchart illustrating the sub-steps included in step S120. In this embodiment, step S120 may include sub-steps S121 to S122.

[0048] Sub-step S121: Calculate the reference quantity based on the first preset coefficient and the first quantity.

[0049] Sub-step S122: Obtain the second quantity based on the larger of the first preset quantity and the reference quantity.

[0050] In this embodiment, the product of a first quantity corresponding to an initial path group (i.e., the total number of violation time-series paths in the initial path group) and the first preset coefficient can be calculated, and this product is used as the reference quantity corresponding to the initial path group. The first preset coefficient, as the degradation perception coefficient R, enables the capacity of high-priority groups (i.e., groups composed of target time-series paths selected from an initial path group) to adaptively track the violation scale of the current initial path group, allowing the severe violation domain to have a larger optimization pool.

[0051] The first preset coefficient is a pre-set value greater than 0 and less than 1, which can be determined according to actual needs. Assume the preset grouping method is based on clock domains. During the synthesis phase, if a timing path group in a clock domain has a large number of violation paths (e.g., Total_FEP = 10000, where Total_FEP represents the total number of violation timing paths in a clock domain's timing path group), these violations are usually highly correlated. That is, they often pass through the same few clusters of logic (such as a complex ALU or a shared MUX tree). Experience shows that as long as the worst 2% of core paths in this cluster of logic are identified and repaired, the remaining 98% of paths will usually be automatically repaired (and benefit incidentally) due to the reconstruction of this common logic (such as leveling, cloning, or replacing cells with larger ones). If 20% or even 50% of the violation timing paths are listed as VIPs (VIP represents the target timing path, for example, stuffing 2000 VIPs into the tool), it will actually mask the truly worst few "spikes". Therefore, the first preset coefficient can be set to 0.02 to prevent "equal distribution" or gradient dilution. Understandably, the first preset coefficient can also be set to other values ​​depending on the specific needs.

[0052] After obtaining a reference number corresponding to an initial path group, this reference number can be compared with a first preset number. The larger value between the two is taken as the first larger value, and then a second number corresponding to the initial path group is determined based on this first larger value. For example, the first larger value can be directly used as the second number. The first preset number serves as the lower limit T_min of the bus width, and its specific setting can be tailored to actual needs, for example, set to 100. Determining the second number based on the first larger value ensures that the basic bit width of a typical wide data bus can be covered, preventing optimization tearing.

[0053] By setting a first preset number T_min as the lower limit of bus width, we can prevent the "band-aid" approach caused by insufficient samples. If a time-series path group has only 1000 violations, with a first preset coefficient of 2%, only 20 VIPs can be selected based on 2%. However, if the synthesis tool's solver only focuses on fixing these 20 paths each time, the paths originally ranked 21st to 100th may deteriorate into new worst paths, causing the tool to fluctuate in the next iteration (Ping-Pong effect). Showing the tool the Top 100 paths simultaneously (even if Total_FEP * 0.02 calculates less than 100) allows DCNXT's optimization engine to see a broader gradient profile when constructing the Cost Function. This ensures that the synthesis tool, during logic structuring, does not destroy a large area of ​​surrounding logic in order to fix a single violation.

[0054] As one possible implementation, the second quantity can be obtained based on a first larger value as follows: The second quantity is determined by the smaller of the first larger value and the corresponding computing power saturation threshold of the logic synthesis tool used. The second quantity is not greater than the computing power saturation threshold. The selection of the computing power saturation threshold T_max depends on the convergence limit of the underlying matrix solver of the selected logic synthesis tool. For example, if testing determines that the most efficient physical computing power limit of the underlying matrix solver of the EDA tool is 500, then the computing power saturation threshold T_max can be set to 500. The smaller of the computing power saturation threshold and the first larger value can be used as the second quantity. In this way, the upper limit of the dynamic capacity of the optimization pool containing the target time-series path selected in an initial path group is firmly anchored by this physical limit, completely preventing computing power dilution.

[0055] In this embodiment, a dynamic expansion and absolute upper limit control mechanism anchored to the computing power limit can be introduced: based on the total number of violation paths (Total_FEP) in the current time-series path group, the upper limit of the critical path (VIP, i.e., target time-series path) pool is dynamically calculated, thereby resolving the contradiction between computing power dilution and time-series path squeezing. The calculation method is as follows: dynamic_cap = min(T_max, max(T_min, int(Total_FEP * R))), where dynamic_cap represents the second quantity, T_max represents the computing power saturation threshold, T_min represents the first preset quantity, Total_FEP represents the total number of violation time-series paths in an initial path group, and R represents the first preset coefficient.

[0056] Optionally, as a possible implementation, after obtaining the second number corresponding to an initial path group, a second number of violation timing paths can be selected from the initial path group in ascending order of timing margin as the target timing paths corresponding to the initial path group. Optionally, if the number of violation timing paths in the initial path group is less than the second number, then all violation timing paths in the initial path group are used as the corresponding target timing paths.

[0057] Alternatively, as another possible implementation, it can be achieved through... Figure 4 The target timing path is determined as shown. Please refer to... Figure 4 , Figure 4 for Figure 2 A flowchart illustrating the sub-steps included in step S130. In this embodiment, step S130 may include sub-steps S131 to S133.

[0058] Sub-step S131: Calculate the path score of each violation timing path based on the path information of each violation timing path in the initial path group.

[0059] In this embodiment, for each violation timing path in an initial path group, a path score can be calculated based on the path information of that violation timing path. The path information includes timing margins; the larger the absolute value of the timing margin, the larger the path score. The specific method for calculating the path score based on the timing margin can be determined according to actual needs and is not specifically limited here.

[0060] As one possible implementation, the preset grouping method is used to indicate grouping according to the clock domain, and the path information also includes the clock period clock_period, which can be obtained through... Figure 5 The path score is calculated as shown. Please refer to... Figure 5 , Figure 5 for Figure 4 A flowchart illustrating the sub-steps included in neutron step S131. In this embodiment, sub-step S131 may include sub-steps S1311 to S1313.

[0061] Sub-step S1311: Calculate the reference value based on the third preset coefficient and the clock period corresponding to the initial path group.

[0062] Sub-step S1312: For each violation timing path, determine the initial score of the violation timing path based on the minimum value among the absolute value of the timing margin of the violation timing path, the second preset value, and the reference value.

[0063] In this embodiment, the timing paths in an initial path group are located within a clock domain. For an initial path group, a value can be calculated as a reference value based on the clock period of the clock domain in which the initial path group resides and a third preset coefficient. The third preset coefficient is greater than 0 and less than 1, for example, it can be set to 0.5, and the specific value can be determined according to actual needs. Optionally, the product of the third preset coefficient and the clock period corresponding to the initial path group can be directly used as the reference value for the initial path group.

[0064] For each violation timing path in the initial path group, the absolute value of the timing margin, the second preset value, and the reference value corresponding to the initial path group of the violation timing path are compared to determine the minimum value among the three. The initial score of the violation timing path is then obtained based on the determined minimum value. Optionally, the minimum value can be directly used as the initial score, or the minimum value can be slightly increased or decreased to obtain the initial score. Alternatively, the initial score can be obtained based on the minimum value in other ways, depending on the actual needs.

[0065] As one possible implementation, the minimum value is used as the initial score. If the path score is directly calculated based on the timing margin of the violation path, i.e., the input timing margin slack is unrestricted, the subsequent scoring algorithm will be broken by malformed data. To prevent the scoring system from becoming distorted, this application's embodiment introduces a dual data truncation mechanism to calculate the initial score. The dual data truncation mechanism includes a first truncation condition and a second-stage condition.

[0066] The first cutoff condition uses a reference value, which serves as a dynamic cycle ratio threshold. This threshold is obtained by taking a certain percentage of the clock cycle, such as 50% of the clock cycle in the example above. When the absolute value of the timing margin of the violation path exceeds the reference value, it usually stems from RTL architecture design flaws (such as excessively deep levels) or missing constraints, exceeding the physical optimization capabilities of the tool. Strictly limiting the violation value to this threshold can, to some extent, eliminate architectural dead zones and prevent the tool from falling into a computational black hole.

[0067] The second cutoff condition uses a second preset value, which serves as an absolute process limit threshold, also known as the cross-frequency reference alignment upper limit. This second preset value can be set according to the extreme physical delay of the process node, for example, it can be set to 1.0ns. In a hybrid SOC (System on Chip) design, this prevents large absolute value violations in the low-frequency clock domain from creating a "numerical monopoly" in the squaring operation, thus masking fatal minor violations in the high-frequency domain. This, to some extent, smooths out the significant numerical differences between high and low frequency clocks on the absolute time scale.

[0068] With the third preset coefficient being 0.5 and the second preset value being 1, the above process can be represented by a truncation formula, resulting in the initial score: score_slack = min(abs(slack), clock_period *0.5, 1.0), where score_slack represents the initial score, abs(slack) represents the absolute value of the timing margin of a violation timing path, and clock_period represents the clock period. Thus, by truncating slack in relation to the clock period, we can prevent a single, excessively large violation (such as a -100ns violation caused by a false path) from distorting the scoring system and causing subsequent path scores to become inaccurate. Sub-step S1313: Calculate the path score of the violation timing path based on the initial score of the violation timing path.

[0069] Optionally, the method for obtaining the path score based on the initial score can be configured according to actual needs. For example, a linear or non-linear increasing function can be set, the initial score of the violation time series path can be substituted into the function, and the calculation result can be used as the path score of the violation time series path.

[0070] As one possible implementation, the path information also includes a logical depth (logic_depth), which can be achieved through... Figure 6 The path score is obtained as shown. Please refer to [the provided text]. Figure 6 , Figure 6 for Figure 5 A flowchart illustrating the sub-steps included in neutron step S1313. In this embodiment, sub-step S1313 may include sub-steps S13131 to S13133.

[0071] Sub-step S13131: Calculate the first score based on the initial score and the preset penalty mechanism.

[0072] The preset penalty mechanism is used to instruct the first score to increase non-linearly as the initial score increases. The specific calculation method can be determined according to actual needs. For example, the cube of the initial score can be used as the corresponding first score. In this way, larger errors (here, more serious timing violations) can be penalized more severely, thereby widening the score gap between them and minor violations.

[0073] Sub-step S13132 calculates the second score based on the logical depth of the violation timing path.

[0074] The rate at which the second score increases decreases as the logic depth increases. The specific calculation method can be determined based on actual needs. For example, the logic depth can be squared or cubed, and the result can be used as the second score.

[0075] Sub-step S13133: Based on the first score and the second score, the path score of the violation timing path is calculated by multiplication.

[0076] Optionally, the product of the first score and the second score can be used as the path score for the violation sequence path. This path score is the pain score for the violation sequence path. In this way, the path score of the violation sequence path can be obtained through the penalty mechanism and the diminishing marginal effect.

[0077] The difficulty and cost of fixing timing violations increase exponentially. Fixing a violation from -0.1ns to 0ns typically only requires replacing the driver with a larger cell in the timing violation path or inserting one or two stages of buffering, with minimal penalty to area and power consumption. However, fixing a violation from -0.5ns to -0.4ns might already involve using the largest cell and shortest connections in the timing path. To squeeze out another 0.1ns of timing, the tool might need to perform a larger-scale architectural reconfiguration (such as cloning registers, flattening logic, etc.), which introduces significant area and power penalties.

[0078] If only linear exponentiation is used, then one -0.4ns path is equivalent to two -0.2ns paths. However, in reality, the "effort (cost)" required by the synthesis tool to fix one -0.4ns path is far greater than fixing two -0.2ns paths. The squaring operation (**2) amplifies the weight of the worst-performing time-series paths, forcing the algorithm to focus its attention on the worst individual paths, much like in least squares regression, rather than being distracted by a large number of minor-performing paths.

[0079] The longer the path, the more points there are for optimization, but the advantage growth will slow down after a certain length. logic_depth refers to the number of units on this timing path.

[0080] Assume both paths have a slack of -0.2ns. Path A (logic_depth = 2): has only 2 levels of logic gates, leaving very little room for tool adjustments (only the driving capability of these 2 gates can be adjusted), making it a "tough nut to crack." Path B (logic_depth = 40): has 40 levels of gates, meaning that each level only needs slight optimization (averaging a 5ps improvement) to resolve the overall -0.2ns violation. The tool has a lot of room for maneuver, making it a "softer" option.

[0081] Therefore, under the same slack conditions, the longer the logical level, the greater the "pain index" of this path should be, so as to attract tools to drastically refactor it (because it has a large optimization space).

[0082] If we directly use multiplication (linear): pain = slack^2 * depth, then a level 50 path will have a score 10 times higher than a level 5 path. This would cause the algorithm to over-favor very long paths, ignoring those "hard nuts to crack" paths with fewer levels but more serious violations.

[0083] The square root operation (math.sqrt) achieves "diminishing marginal utility": changing from depth=1 to depth=4 doubles the score (doubles the optimization space, and the tool is happy to fix it); changing from depth=36 to depth=49 (adding 13 levels) only increases the score from 6 to 7 (the optimization space is large, but the added weights gradually converge).

[0084] Based on the above considerations, as a possible implementation, the path score of each violation time-series path can be calculated based on the quadratic penalty mechanism combining the least squares principle and the nonlinear formula of diminishing marginal returns. The calculation process is shown in the following formula: pain_score = (score_slack ** 2) * math.sqrt(logic_depth), where pain_score represents the path score, score_slack represents an initial score, and logic_depth represents the logic depth.

[0085] In this embodiment, a nonlinear evaluation function that integrates the square of timing margin and the square root of logic depth is used to obtain the path score. Before substituting the values ​​into the function formula, an innovative dual numerical truncation mechanism is introduced: a "dynamic cycle ratio threshold" (i.e., the reference value mentioned above) is used to eliminate architectural dead zones, and an "absolute process limit threshold" (i.e., the second preset value mentioned above) is used to smooth out the numerical gap between high and low frequency clocks, thereby completely preventing distorted data from warping the overall scoring scale. Therefore, the above-mentioned scoring mode for obtaining the path score can also be called a nonlinear pain point scoring model with a dual anti-distortion and explosion-proof shield.

[0086] Sub-step S132: For each violation timing path, determine whether the violation timing path is a candidate timing path based on the path score and timing margin of the violation timing path.

[0087] In this embodiment, a pre-set candidate timing path filtering method can be used to filter corresponding candidate timing paths from an initial path group based on the path score and timing margin of each violation timing path. The specific filtering method can be set according to actual needs.

[0088] As one possible implementation method, it can be achieved through Figure 7 Candidate timing paths are obtained as shown. Please refer to... Figure 7 , Figure 7 for Figure 4 A flowchart illustrating the sub-steps included in neutron step S132. In this embodiment, sub-step S132 may include sub-steps S1321 to S1325.

[0089] Sub-step S1321: Calculate the target score based on the second preset coefficient and the maximum path score in the initial path group.

[0090] Sub-step S1322: For each violation timing path, determine whether the path score of the violation timing path is not less than the target score.

[0091] Sub-step S1323: For each violation timing path, determine whether the absolute value of the timing margin of the violation timing path is not less than the first preset value.

[0092] Wherein, the first preset value is greater than 0.

[0093] If the path score of the violation timing path is greater than the target score and the absolute value of the timing margin of the violation timing path is greater than the first preset value, then sub-step S1324 is executed.

[0094] Sub-step S1324: Do not include the violation timing path as a candidate timing path.

[0095] If the path score of the violation timing path is not less than the target score or the absolute value of the timing margin of the violation timing path is not less than the first preset value, then execute sub-step S1325.

[0096] Sub-step S1325: The violation timing path is selected as a candidate timing path.

[0097] In this embodiment, the second preset coefficient is used as the relative degradation envelope coefficient α. The second preset coefficient is greater than 0 and less than 1, and can be set according to actual needs, for example, 0.4. For an initial path group, the maximum path score in the initial path group can be determined, and then the product of the maximum path score and the second preset coefficient can be calculated as a target score. Then, for each violation time-series path in the initial path group, the path score of the violation time-series path is compared with the above target score. If the path score of the violation time-series path is greater than or equal to the target score, then the violation time-series path is regarded as a candidate time-series path. In this way, based on the relative gradient screening of the main lesion perception, an adaptive relative network can be opened below the maximum pain point to accurately peel off the first type of key candidates that share physical resources with the main bottleneck, thereby determining a portion of candidate time-series paths. The candidate time-series paths determined by the above relative gradient screening method based on the main lesion perception satisfy: pain_score ≥ α * P_max, where P_max represents the maximum path score in an initial path group.

[0098] In this embodiment, the first preset value, β, serves as the physical red line threshold for the process node. It can be determined based on the intrinsic delay of multi-level standard gate cells, for example, it can be set to 0.2 ns. For each violation timing path in an initial path group, it can be determined whether the absolute value of the timing margin of the violation timing path is greater than or equal to the first preset value. If the absolute value of the timing margin of the violation timing path is greater than or equal to the first preset value, then the violation timing path is considered a candidate timing path. Thus, through the absolute physical red line fallback mechanism, any severe violation exceeding the red line will ignore the relative gradient and be forcibly merged into the second type of critical candidate, ensuring that no primary or secondary bottleneck is overlooked. The candidate timing paths determined by the above absolute physical red line fallback mechanism satisfy: abs(slack) ≥ β.

[0099] The dual-track filtering strategy based on union (OR) can solve the "suboptimal bottleneck masking" effect caused by the presence of extremely large outliers in time series distributions.

[0100] In this embodiment, an initial path group can be determined through noise floor filtering to avoid invalid involution. A union candidate strategy, as shown above, of "the worst peak percentage relative to the clock domain" (corresponding to the second preset coefficient) and "absolute severe physical violation" (corresponding to the first preset value), is used to select candidate timing paths from the initial path group, ensuring that the truly critical timing paths are not locally masked. Thus, candidate timing paths can be determined based on the noise floor filtering and dual-track candidate selection mechanism.

[0101] Sub-step S133: Determine the target timing path based on the third number and the corresponding second number of candidate timing paths determined from the initial path group.

[0102] In this embodiment, for an initial path group, it is determined whether the third quantity corresponding to the initial path group is greater than the corresponding second quantity. If the third quantity is greater than the second quantity, the second number of candidate time-series paths are selected as the target time-series paths from the candidate time-series paths corresponding to the initial path group in descending order of path scores. That is, the second number of candidate time-series paths when the candidate time-series paths are arranged in descending order are selected as the target time-series paths. The target time-series paths determined from an initial path group can be extracted from the initial path group to form a VIP group, which can also be called a target path group.

[0103] If the third quantity is less than the second quantity, it can be determined whether the second quantity is greater than the second preset quantity. The second preset quantity can be determined based on actual needs; for example, it can be set to 5 to limit the minimum number of target timing paths determined from an initial path group. If the third quantity is less than the second quantity but greater than the second preset quantity, all candidate timing paths corresponding to the initial path group are considered as target timing paths.

[0104] If the third quantity is less than the second preset quantity, with the target number of target timing paths selected from the initial path group as the second preset quantity, all candidate timing paths corresponding to the initial path group are taken as target timing paths, and violation timing paths are selected as target timing paths from the remaining violation timing path group in the initial path group according to their path scores. Optionally, target timing paths can be selected from the remaining violation timing path group in descending order of path scores.

[0105] In this embodiment, to prevent the tool from applying high weights to a very small number of isolated paths and falling into "single-point overfitting", a "minimum optimization baseline fallback mechanism" is introduced (in this embodiment, the lower limit for extraction is the second number). When the number of qualified high-optimal paths (i.e., candidate timing paths) is lower than this baseline, similar secondary critical paths can be added above the process noise floor red line (i.e., the preset timing margin mentioned above).

[0106] The Dynamic ProportionalCap mechanism used in this embodiment, which anchors to the limits of computing power, proposes a dynamic scaling model that links the extraction capacity to the scale of design violations. On one hand, a rigid "computing power saturation threshold" is applied to prevent computing power dilution caused by blindly expanding the high-optimization range. On the other hand, a "minimum optimization base number" (i.e., the second preset number mentioned above) is introduced as a safety net, providing sufficient local computational samples for the solver and completely avoiding the time-series ping-pong effect caused by single-point overfitting. This two-way constraint mechanism solves the problems of wide bus tearing and local oscillations during the optimization process caused by a fixed number of extractions.

[0107] Optionally, the preset grouping method is used to indicate grouping according to clock domains, and the path information also includes clock cycles. After determining the target timing path, it can be... Figure 8 The target weights corresponding to the target time-series path are obtained as shown. Please refer to... Figure 8 , Figure 8 for Figure 2 A flowchart illustrating the sub-steps included in step S140. In this embodiment, step S140 may include sub-steps S141 to S146.

[0108] Sub-step S141: For each initial path group, calculate the ratio of the absolute value of the worst timing margin of the target path group corresponding to the initial path group to the clock cycle corresponding to the initial path group, and use it as a reference ratio.

[0109] In this embodiment, for each initial path group, target timing paths selected from that initial path group are grouped into a target path group. The timing margins of each timing path in the target path group are compared to determine the worst timing margin, i.e., the smallest timing margin. Then, the ratio of the absolute value of the worst timing margin to the clock period of the clock domain in which the initial path group is located is calculated, and the obtained ratio is used as a reference ratio. The reference ratio table indicates the relative timing violation severity. This process can be expressed as: Ratio = abs(WNS_VIP) / clock_period), where WNS_VIP represents the minimum timing margin among the target timing paths determined from an initial path group, and Ratio represents the reference ratio.

[0110] Sub-step S142: Calculate the basic weight based on the preset weight scaling value and the reference ratio.

[0111] Wherein, the preset weight scaling value K represents the weight scaling coefficient, which is obtained based on the maximum weight value corresponding to the logic synthesis tool (i.e., the legal upper limit of the weight for the synthesis attack, Weight_Max) and the fourth preset coefficient, Critical_Ratio. The fourth preset coefficient is less than 1, and it represents the preset design catastrophic violation waterline, which can be determined according to actual needs, for example, set to 50%. Optionally, the preset weight scaling value can be obtained by dividing the maximum weight value corresponding to the logic synthesis tool by the fourth preset coefficient. For example, if the maximum weight value Weight_Max corresponding to the logic synthesis tool is 100 and the fourth preset coefficient is 50%, then K = Weight_Max / Critical_Ratio = 100 / 0.5 = 200.

[0112] The product of the preset weight scaling value and the reference ratio can be calculated, and the resulting product is used as the base weight corresponding to the target path group. This dynamic linear mapping method can uniformly normalize absolute violations in different frequency clock domains and smoothly map them to the tool weight range.

[0113] Sub-step S143: Determine whether the absolute value of the worst timing margin of the target path group is greater than the third preset value.

[0114] If the absolute value of the worst timing margin of the target path group is greater than the third preset value, then sub-step S144 is executed.

[0115] Sub-step S144: Obtain the initial weight based on the first preset weight and the second larger value among the basic weights.

[0116] If the absolute value of the worst timing margin of the target path group is not greater than the third preset value, then sub-step S145 is executed.

[0117] Sub-step S145: Use the base weights as the initial weights.

[0118] Sub-step S146: Determine the target weight based on the initial weight and the preset weight range.

[0119] In this embodiment, for the initial path group, it can be determined whether the absolute value of the worst-case timing margin of the target path group corresponding to the initial path group is greater than a third preset value. If it is greater, the larger of the base weight and the first preset weight (i.e., the second larger value mentioned above) corresponding to the target path group can be used as the initial weight corresponding to the target path group. If it is not greater, the calculated base weight is used as the initial weight corresponding to the target path group. In this way, by applying the low-frequency trap breakthrough mechanism (absolute physical severity coverage) described above, the phenomenon that severe violations in the low-frequency clock domain are easily diluted by weight due to the large period base is avoided.

[0120] The third preset value serves as the threshold for extremely severe physical violations, representing the number of severely bloated logic levels accumulated on the physical topology. It can be set according to actual conditions, for example, to 0.4 ns. The first preset weight can be a large value, specifically set according to actual needs. For example, it can be set to the maximum legal weight limit of the synthesis tool, Weight_Max. For instance, assuming Weight_Max is 100, the first preset weight can be set to 100.

[0121] The above description represents the following mechanism: triggering a fallback weighting based on the absolute physical violation value. Assuming the first preset weight is the maximum legal weight limit (Weight_Max) of the aggregation tool, the mechanism can be expressed as follows: when abs(WNS_VIP) > the extremely severe physical violation threshold, a forced overweighting is applied, assigning full weight: raw_weight = max(raw_weight, Weight_Max). Here, abs(WNS_VIP) represents the absolute value of the worst-case time margin in a target path group, and raw_weight represents the weight of a target path group.

[0122] After determining the initial weight of a target path group, the initial weight can be compared with the maximum and minimum values ​​of a preset weight range. The minimum value of the preset weight range is greater than the default weight of the time-series path, and the specific value can be determined according to actual needs. For example, if the default weight of the time-series path is 1, the preset weight range can be set to [10, 100].

[0123] If the initial weight is greater than the maximum value of the preset weight range, then the maximum value of the preset weight range is used as the target weight of the target path group; if the initial weight is less than the minimum value of the preset weight range, then the minimum value of the preset weight range is used as the target weight of the target path group. If the initial weight is within the preset weight range, then the initial weight is used as the target weight of the target path group. In this way, the initial weight can be determined by a dynamic weight mapping method that overcomes the low-frequency trap, and the target weight can be restricted to the preset weight range by a closed interval constraint mechanism.

[0124] The above approach employs a closed-interval constraint mechanism at upper and lower boundaries, which includes lower boundary protection (priority isolation bottom edge) and upper boundary restriction (cost function saturation upper limit). Lower boundary protection refers to comparing the weight with the isolation bottom edge and taking the larger value. For example, if the isolation bottom edge is set to 10, this forces a minimum order of magnitude "minimum optimization resolution" between the high-priority group (i.e., the target path group) and the massive number of low-priority paths in the background, ensuring that the absolute priority exemption right of the VIP is not masked.

[0125] The upper bound constraint refers to comparing the weights with the saturation upper limit and taking the smaller value. Mathematically, this truncates the optimization gradient, preventing the solver from diverging due to extremely high weights (i.e., "size expansion regardless of cost"), and safeguarding the physical limits of chip area and leakage power consumption.

[0126] It is worth noting that one target path group corresponds to one target weight, that is, the weight of all target time-series paths in a target path group is the target weight.

[0127] In this embodiment, a fixed weighting mode is not used in obtaining the target weights. Instead, the absolute timing violations across frequency clock domains are uniformly normalized to relative severity by deriving the "weight scaling factor (K)". At the same time, for the "low-frequency trap" with an excessively large base, an "absolute physical severity coverage mechanism" is introduced to force weighting. To ensure smooth scheduling, the final result is clamped into a closed interval constraint composed of the "priority isolation bottom edge" (maintaining gradient resolution) and the "cost function saturation upper limit" (preventing area penalty divergence), thus balancing the global optimization priority and power consumption area cost between heterogeneous clock domains without any blind spots.

[0128] After obtaining the target weights corresponding to each target path group, a high-quality TCL (Tool Command Language) grouping script can be generated that can be directly used by EDA tools. This grouping script can include the target timing paths and their corresponding target weights for each target path group. In the method of timing path optimization based on the grouping script, the target timing paths can be extracted from each initial path group as the target path groups corresponding to each initial path group. The remaining timing paths in the initial path groups use their original weights, and the target path groups use their corresponding target weights. Optimization is then performed based on this information.

[0129] The method for obtaining time-series path optimization information provided in this application is an adaptive time-series path grouping method based on dynamic capacity control. It is used to select target time-series paths from each initial path group to form target path groups corresponding to each initial path group, and to determine the target weights corresponding to each target path group.

[0130] In testing deep logic cone modules containing a massive number of severe timing violations, the approach of extracting a fixed number of critical paths (e.g., the Top 100) as target timing paths can lead to extremely severe local resource contention, further deteriorating the global time-of-flight (WNS) and causing a surge in the number of violation paths in the most affected areas. In this embodiment, however, a reasonable dynamic capacity is adaptively calculated, precisely distributing the optimization pressure. This allows for optimal global time-of-flight (TNS) without worsening the WNS, while significantly reducing the number of violation paths in the most affected areas, perfectly balancing the timing optimization process and completely avoiding resource crowding. This method solves the "timing crowding effect" in deep logic cone design, achieving global TNS optimization.

[0131] In typical high-frequency wide bus topologies, low capacity limits often fail to cover the full bus width, leading to data path optimization tearing and minimal TNS improvement. However, the dynamic capping mechanism used in this embodiment allows for smooth release of physical truncation to the computing power limit, successfully encompassing the full bus width. Thus, at the cost of negligible WNS (Wide Noise Level) within the physical noise floor, a significant reduction in global TNS (improvement of tens of percentage points) is achieved, resulting in a precipitous decrease in the number of severely violated endpoints. This method adapts to wide data buses and enables "anti-tearing optimization."

[0132] In a comparative test verifying a large clock domain (thousands of violations), the practice of blindly increasing the weight of the entire system manually leads to severe dilution of the solver's computing power, causing the worst-case timing path (WNS) to stagnate and the number of violations in severely affected areas to remain high. In contrast, this embodiment relies on pain point scoring and a dynamic hard upper limit mechanism to precisely anchor the critical path (VIP) size within the optimal range. With the same or even lower physical computing power expenditure, it greatly controls and reduces the number of endpoints with severe violations, fully verifying the algorithm's absolute advantage in focusing on the underlying computing power of EDA tools. This method can completely eliminate computing power dilution; furthermore, determining the initial path group through noise filtering avoids invalid involution.

[0133] To perform the corresponding steps in the above embodiments and various possible methods, an implementation of a timing path optimization information acquisition device 200 is given below. Optionally, the timing path optimization information acquisition device 200 can adopt the above-described... Figure 1 The device structure of the electronic device 100 shown. Further, please refer to... Figure 9 , Figure 9This is a block diagram of a timing path optimization information acquisition device 200 provided in an embodiment of this application. It should be noted that the basic principle and technical effects of the timing path optimization information acquisition device 200 provided in this embodiment are the same as those in the above embodiments. For the sake of brevity, any parts not mentioned in this embodiment can be referred to the corresponding content in the above embodiments. In this embodiment, the timing path optimization information acquisition device 200 may include: a preprocessing module 210, a calculation module 220, a filtering module 230, and a weight acquisition module 240.

[0134] The preprocessing module 210 is used to determine an initial path group from the time-series path group obtained by a preset grouping method.

[0135] The calculation module 220 is used to calculate, for each initial path group, a second number corresponding to the initial path group based on the first number of violation timing paths in the initial path group.

[0136] The filtering module 230 is used to determine target timing paths for each initial path group based on the second quantity corresponding to the initial path group and the path information of each violation timing path included therein. The path information includes timing margins, and the number of target timing paths determined from an initial path group is no greater than the corresponding second quantity.

[0137] The weight acquisition module 240 obtains the target weight corresponding to the target timing path. The optimization information indicates the target timing path and its corresponding target weight, wherein the target weight is greater than the default weight corresponding to the logic synthesis tool used.

[0138] Optionally, the above modules can be stored in the form of software or firmware. Figure 1 The memory 110 shown is either stored in or embedded in the operating system (OS) of the electronic device 100, and can be used by... Figure 1 The processor 120 executes the program. Meanwhile, the data and program code required to execute the above modules can be stored in the memory 110.

[0139] This application also provides a readable storage medium storing a computer program thereon, which, when executed by a processor, implements the timing path optimization information acquisition method.

[0140] In summary, this application provides a method, apparatus, electronic device, and readable storage medium for obtaining timing path optimization information. For each initial path group determined from timing path groups obtained through a preset grouping method, a second quantity corresponding to the initial path group is calculated based on a first quantity of non-compliant timing paths in the initial path group. Then, based on the second quantity corresponding to the initial path group and the path information of each non-compliant timing path included, a target timing path is determined, and a target weight corresponding to the target timing path is obtained. The path information includes timing margins, and the number of target timing paths determined from an initial path group is not greater than the corresponding second quantity. Optimization information is used to indicate the target timing path and its corresponding target weight, and the target weight is greater than the default weight corresponding to the logic synthesis tool used. In this way, path optimization information can be automatically obtained, saving significant manpower and time. Furthermore, since the target timing path to be optimized is determined based on the current number of non-compliant timing paths, the poor optimization effect caused by extracting a fixed number of target timing paths due to an excessively large or small fixed number can be avoided.

[0141] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can also be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram and / or flowchart, and combinations of blocks in block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0142] In addition, the functional modules in the various embodiments of this application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0143] If the aforementioned functions are implemented as software functional modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0144] The above description is merely an optional embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A method for obtaining time-series path optimization information, characterized in that, The method includes: The initial path group is determined from the time-series path group obtained through a preset grouping method; For each initial path group, the second number corresponding to the initial path group is calculated based on the first number of violation timing paths in the initial path group; For each initial path group, a target timing path is determined based on the second quantity corresponding to the initial path group and the path information of each violation timing path included therein. The path information includes timing margin, and the number of target timing paths determined from an initial path group is not greater than the corresponding second quantity. Obtain the target weight corresponding to the target timing path, wherein the optimization information is used to indicate the target timing path and the corresponding target weight, and the target weight is greater than the default weight corresponding to the logic synthesis tool used; The preset grouping method is used to indicate grouping according to the clock domain, the path information also includes the clock period, and obtaining the target weight corresponding to the target timing path includes: For each initial path group, the ratio of the absolute value of the worst timing margin of the target path group corresponding to the initial path group to the clock cycle corresponding to the initial path group is calculated as a reference ratio. The target path group corresponding to the initial path group consists of the target timing paths determined from the initial path group. The basic weight is calculated based on the preset weight scaling value and the reference ratio. The preset weight scaling value is obtained based on the maximum weight value corresponding to the logic synthesis tool and the fourth preset coefficient, where the fourth preset coefficient is less than 1. Determine whether the absolute value of the worst-case timing margin of the target path group is greater than the third preset value; If the absolute value of the worst-case time margin of the target path group is greater than the third preset value, the initial weight is obtained according to the larger of the first preset weight and the second larger value of the basic weight; If the absolute value of the worst-case time margin of the target path group is not greater than the third preset value, then the basic weight is used as the initial weight. The target weight is determined based on the initial weight and the preset weight range, wherein the target weight is within the preset weight range, and the minimum value of the preset weight range is greater than the default weight of the time sequence path.

2. The method according to claim 1, characterized in that, For each initial path group, the second quantity corresponding to that initial path group is calculated based on the first quantity of violation timing paths in that initial path group, including: The reference quantity is calculated based on the first preset coefficient and the first quantity, wherein the first preset coefficient is less than 1; The second quantity is obtained based on the larger of the first preset quantity and the reference quantity.

3. The method according to claim 2, characterized in that, The step of obtaining the second quantity based on the larger of the first preset quantity and the reference quantity includes: The second quantity is determined based on the smaller of the computing power saturation threshold corresponding to the logic synthesis tool used and the first larger value, wherein the second quantity is not greater than the computing power saturation threshold.

4. The method according to claim 1, characterized in that, For each initial path group, the target timing path is determined based on the second quantity corresponding to the initial path group and the path information of each violation timing path included therein, including: Based on the path information of each violation timing path in the initial path group, the path score of each violation timing path is calculated, wherein the larger the absolute value of the timing margin, the larger the path score. For each violation timing path, determine whether the violation timing path is a candidate timing path based on the path score and timing margin of the violation timing path. The target timing path is determined based on the third number and the corresponding second number of candidate timing paths identified from the initial path group.

5. The method according to claim 4, characterized in that, For each violation timing path, determining whether the violation timing path is a candidate timing path based on its path score and timing margin includes: The target score is calculated based on the second preset coefficient and the maximum path score in the initial path group; For each violation timing path, it is determined whether the path score of the violation timing path is not less than the target score, and whether the absolute value of the timing margin of the violation timing path is not less than a first preset value, wherein the first preset value is greater than 0. If the path score of the violation timing path is not less than the target score or the absolute value of the timing margin of the violation timing path is not less than the first preset value, the violation timing path is regarded as a candidate timing path.

6. The method according to claim 4, characterized in that, The step of determining the target time-series path based on the third number and the corresponding second number of candidate time-series paths determined from the initial path group includes: If the third number is greater than the second number, the second number of candidate time-series paths are selected from the candidate time-series paths corresponding to the initial path group as the target time-series paths in descending order of path scores. If the third quantity is less than the second quantity but greater than the second preset quantity, all candidate time-series paths corresponding to the initial path group shall be taken as the target time-series paths. If the third quantity is less than the second preset quantity, the second preset quantity is used as the target quantity, and all candidate time paths corresponding to the initial path group are used as target time paths. Then, violation time paths are selected from the remaining violation time path groups in the initial path group as target time paths based on the path score.

7. The method according to claim 4, characterized in that, The step of calculating the path score for each violation timing path based on the path information of each violation timing path in the initial path group includes: The reference value is calculated based on the third preset coefficient and the clock period corresponding to the initial path group; For each violation timing path, the initial score of the violation timing path is determined based on the minimum value among the absolute value of the timing margin of the violation timing path, the second preset value, and the reference value. Based on the initial score of the violation sequence path, the path score of the violation sequence path is calculated.

8. The method according to claim 7, characterized in that, The path information also includes logical depth. The calculation of the path score for the violation timing path based on its initial score includes: Based on the initial score and the preset penalty mechanism, a first score is calculated, wherein the preset penalty mechanism is used to indicate that the first score increases in a non-linear manner as the initial score increases; The second score is calculated based on the logic depth of the violation timing path, wherein the rate of increase of the second score decreases as the logic depth increases; Based on the first score and the second score, the path score of the violation sequence path is calculated by multiplication.

9. A device for obtaining time-series path optimization information, characterized in that, The device includes: The preprocessing module is used to determine the initial path group from the time-series path group obtained through a preset grouping method; The calculation module is used to calculate the second number corresponding to each initial path group based on the first number of violation timing paths in the initial path group. The filtering module is used to determine the target timing path for each initial path group based on the second quantity corresponding to the initial path group and the path information of each violation timing path included therein. The path information includes timing margin, and the number of target timing paths determined from an initial path group is not greater than the corresponding second quantity. The weight acquisition module obtains the target weight corresponding to the target time path. The optimization information is used to indicate the target time path and the corresponding target weight. The target weight is greater than the default weight corresponding to the logic synthesis tool used. The preset grouping method is used to indicate grouping according to clock domain. The path information also includes clock cycles. The weight acquisition module is specifically used to: for each initial path group, calculate the ratio of the absolute value of the worst timing margin of the target path group corresponding to the initial path group to the clock cycle corresponding to the initial path group, as a reference proportion, wherein the target path group corresponding to the initial path group consists of target timing paths determined from the initial path group; calculate the basic weight according to the preset weight scaling value and the reference proportion, wherein the preset weight scaling value is based on the maximum weight value corresponding to the logic synthesis tool and the fourth... The fourth preset coefficient is less than 1; it is determined whether the absolute value of the worst-case timing margin of the target path group is greater than the third preset value; if the absolute value of the worst-case timing margin of the target path group is greater than the third preset value, the initial weight is obtained according to the larger of the first preset weight and the second larger of the basic weights; if the absolute value of the worst-case timing margin of the target path group is not greater than the third preset value, the basic weight is used as the initial weight; the target weight is determined according to the initial weight and the preset weight range, wherein the target weight is within the preset weight range, and the minimum value of the preset weight range is greater than the default weight of the timing path.

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