A multi-path adjustable bias current source layout layout array under deep sub-micron process

Abstract

The application discloses a multi-path adjustable bias current source layout layout array under a deep submicron process, and relates to the field of analog integrated circuits. The array is composed of n rows and m columns of basic units, and contains bias units and virtual units; the edge columns are all virtual units, the non-central columns are bias units, and the central columns are locally provided with virtual units. The bias unit contains PMOS tubes M1-M4 and a unit metal layer M5; M1 and M3 form a main current path, M2 and M4 are switch tubes, and are connected with a digital module through M5 and M6. The gate electrode adopts multi-layer metal low-resistance interconnection, and the active region is continuous; the bias unit layout is arranged in an inclined gradient mode, and six paths of currents are formed. The application has the effects of inhibiting the secondary effect of the layout, reducing current mismatch, realizing high-precision matching, and cooperating with digital adjustable calibration.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuits, specifically relating to a multi-channel adjustable bias current source layout array under deep submicron technology. Background Technology

[0002] With the rapid development of deep submicron processes (such as 28nm, 16nm, 7nm and below), the feature size of integrated circuits is constantly shrinking. Non-ideal effects such as process fluctuations, lithography distortion, uneven etching, and stress gradients are becoming more and more significant. This leads to problems such as large current mismatch, poor consistency, low stability, and severe layout effects in traditional bias current source arrays. They are difficult to meet the matching degree, adjustability, and robustness requirements of high-precision analog circuits and high-speed mixed-signal circuits for multiple bias currents.

[0003] Existing multi-bias current sources typically employ fixed cell layouts, simple edge dummy isolation, and single metal interconnects, which have the following drawbacks: insufficient layout symmetry, failing to effectively offset global errors caused by process gradients, and low current matching accuracy among different channels; simple cell interconnect structures with inconsistent gate interconnect resistances, easily generating gate voltage gradients and exacerbating current mismatch; and a lack of systematic layout optimization design, particularly for deep submicron boards such as WPE, LOD, OSE, and PSE. Figure 2 Poor suppression of stage effects leads to poor current stability and low yield; the current adjustment method is singular, making it difficult to achieve precise digital calibration; the ability to compensate for process deviations is weak, and it is difficult to guarantee mass production consistency. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a multi-channel adjustable bias current source layout array under deep submicron process to improve the consistency and proportional accuracy of multi-channel current.

[0005] A layout array of multi-channel adjustable bias current sources using deep submicron technology includes: The array consists of n rows × m columns of basic units, where n is 49 and m is 13. Each basic unit includes bias units and virtual units. When column x = 1 or m, the basic unit of row x is a virtual unit; When column x satisfies 1 < column x < (m+1) / 2, or (m+1) / 2 < column x < m, the basic cell of row x is an offset cell; When x = (m+1) / 2 columns, the distribution of the x-th row is as follows: rows 1 to x+4 and rows x+31 to n are virtual cells, and the remaining rows are bias cells.

[0006] Optionally, the biasing unit includes a center biasing branch, a first auxiliary biasing branch, a second auxiliary biasing branch, a third auxiliary biasing branch, a fourth auxiliary biasing branch, and a reference biasing branch. The center biasing branch is located at the intersection of row (m+1) / 2 and column (n+1) / 2. The first auxiliary biasing branch consists of 5 standard current units connected in parallel, the reference biasing branch consists of 10 standard current units connected in parallel, the second and third auxiliary biasing branches consist of 128 standard current units, the fourth auxiliary biasing branch consists of 126 standard current units, and the center biasing branch consists of 1 standard current unit. The number of standard current units is 10. μA Standard current unit.

[0007] Optionally, when column x satisfies 1 < column x < (m+1) / 2, or (m+1) / 2 < column x < m, the row containing the center of all bias cells is the reference bias branch; Above the reference bias branch, the bias units in row x alternate sequentially in the order of the third auxiliary bias branch, the second auxiliary bias branch, and the first auxiliary bias branch. Below the reference bias branch, the bias units in row x alternate sequentially in the order of the first auxiliary bias branch, the second auxiliary bias branch, and the third auxiliary bias branch. When x = (m+1) / 2 columns, the arrangement of the bias cells is as follows: rows x+5, x+6, x+30 to x+32 are the first auxiliary bias branches; rows x+7 to x+15 are arranged in a cyclical alternation according to the order of the third auxiliary bias branch, the second auxiliary bias branch, and the fourth auxiliary bias branch; rows x+15 to x+19 are arranged in a cyclical alternation according to the order of the third auxiliary bias branch, the second auxiliary bias branch, the center bias branch, and the second auxiliary bias branch; rows x+20 to x+28 are arranged in a cyclical alternation according to the order of the third auxiliary bias branch, the fourth auxiliary bias branch, and the second auxiliary bias branch; and row x+29 is the third auxiliary bias branch.

[0008] Optional, including: Each bias unit PMOS includes transistors M1, M2, M3, M4 and a unit metal layer M5; M1 and M3 are parallel main current transistors. Their sources are connected to each other and connected to the power supply VDD. Their gates are connected to each other and connected to the common bias voltage VPB. Their drains are connected to each other and lead out a 10μA reference current path.

[0009] Optionally, M2 and M4 are parallel switching transistors. Their sources are connected to each other and connected to the common drain of M1 and M3. Their gates are connected to each other and connected to the unit metal layer M5. Their drains are connected to each other and serve as the root unit current output terminal. The on / off control of the single root unit current is achieved by turning on or off.

[0010] Optionally, one end of the unit metal layer M5 is fixedly connected to the common gate of M2 and M4, and the other end extends and is connected to the global metal bus M6. The global metal bus M6 aggregates all unit metal layers M5 and connects to the external digital module.

[0011] Optionally, the gates of all standard current cells are connected to form a low-resistance interconnect network through multiple metal layers M1, M3, and M4.

[0012] Optionally, one end of each unit metal line M5 is connected to the gate of the corresponding PMOS switch M2 and M4 in the root unit, and the other end is connected to the global metal bus M6. The global metal bus M6 connects to an external digital control module. The digital control module outputs a multi-bit control word, which controls the conduction or cutoff of M2 and M4 in each root unit through the layered metal lines M6 and M5. This changes the number of root units that are connected in parallel, thereby enabling digital adjustment and error calibration of the bias current for each path.

[0013] Optionally, all bias cells have continuous active regions.

[0014] Optionally, each current is controlled by a PMOS switch connected to a digital module via M5 and M6 metal wires to achieve adjustable calibration of the control word. Each current is transmitted in layers via M6 and M5 and the conduction state of M2 and M4 in each root unit is independently controlled. The total parallel current is adjusted by changing the number of bias units. Each current is a bias current formed by multiple bias units connected in parallel.

[0015] The beneficial effects of this invention are: The layout is regular and symmetrical with high matching accuracy. The array adopts a regular row and column arrangement, with local virtual cell isolation in the center column and full dummy shielding in the edge columns. Combined with the cyclical alternation of bias cells to form a tilted gradient distribution, it effectively offsets the process non-uniformity caused by photolithography, etching, and stress gradients, and significantly improves the consistency and proportional accuracy of multi-channel current.

[0016] The unit structure is uniform and the layout effect is strongly suppressed. All bias units adopt the same 10μA standard current unit structure, and the virtual unit structure is completely consistent with the bias unit structure; at the same time, the active regions of all units are continuous and gapless, effectively suppressing deep submicron patterns such as WPE, LOD, OSE, and PSE. Figure 2 Level effect, improves current stability and chip yield.

[0017] The gate interconnects are low-resistance and uniform, resulting in minimal current mismatch. The gates of each bias cell M1 and M3 form a global low-resistance interconnect network through multiple layers of metal, M1, M3, and M4, ensuring consistent gate voltage across all cells, eliminating current deviations caused by gate voltage gradients, and further reducing multi-path current mismatch.

[0018] Digitally controllable, calibrated flexibly, and with a wide adjustable range. Each bias unit is connected to the digital module by PMOS switches M2 and M4, unit metal layer M5, and global metal bus M6. The on / off state of each unit can be independently controlled by multiple control words. By changing the number of parallel units, the currents of I1, I2, Iref, I3, I4, and I5 can be flexibly adjusted to achieve automatic compensation for process deviations and high-precision calibration, adapting to the needs of different application scenarios.

[0019] It features a simple structure, good manufacturability, and high reliability. The overall array is modular and standardized, with high layout density and compact layout, reducing design complexity and manufacturing costs. The symmetrical shielding structure and continuous active area design ensure uniform stress distribution, improving the long-term reliability of the chip. It is suitable for mass production applications of 28nm, 16nm, 7nm and below deep submicron processes. Attached Figure Description

[0020] Figure 1 This is a circuit diagram of the multi-channel bias current of the present invention; Figure 2 This is the layout of the root component bias current of the present invention; Figure 3 This is a layout array diagram of a multi-channel adjustable bias current source under deep submicron process according to the present invention; Figure 4 This is a complete root component layout diagram of the present invention. Detailed Implementation

[0021] A layout array of multi-channel adjustable bias current sources using deep submicron technology includes: Specifically, a multi-channel adjustable bias current source layout array using deep submicron technology is applied to multi-channel bias current circuits. The multi-channel bias current circuit diagram is shown below. Figure 1 As shown.

[0022] Specifically, the circuit consists of multiple current branches connected in parallel. Each current branch is composed of a main current transistor group (M1 and Mn...) and multiple switching transistors cascaded together, forming a PMOS common-source structure.

[0023] The source of all main current transistors is connected to the power supply VDD, the gate is connected to the common bias voltage VPB, and the drain is connected to the source of the corresponding switching transistor.

[0024] The gate of each switch is driven by an independent control signal: the switch M2 in the reference current branch is controlled by a fixed bias VBCAS, while the switches in the other I1~I5 branches are driven by digital control signals ctrl1~ctrl5. The layout of the root component bias current is as follows. Figure 2 As shown.

[0025] The drain of each switching transistor is the output terminal of that current, outputting six bias currents: Iref, I1, I2, I3, I4, and I5 respectively.

[0026] Specifically, by Figure 1 and Figure 2 As can be seen, the 10uA bias current of the root component is in the middle position. The magnitude of the current is controlled by fixing the gate voltage VPB, combining the process device mismatch curve, and selecting an appropriate device width-to-length ratio (W / L). It can also be provided by other zero-temperature coefficient modules. Other currents that need to be replicated and generated can be adjusted through control words to achieve the designed current ratio.

[0027] The root component current is 10uA, so Iref consists of 10 root component units with a bias current of 100uA, I1 consists of 5 root component units with a bias current of 50uA, I2 consists of 1 root component unit with a bias current of 10uA, I3 consists of 128 root component units with a bias current of 1280uA, I4 consists of 128 root component units with a bias current of 1280uA, and I5 consists of 126 root component units with a bias current of 1260uA, for a total of 398 root components.

[0028] The array consists of n rows × m columns of basic units, where n is 49 and m is 13. Each basic unit includes bias units and virtual units. When column x = 1 or m, the basic unit of row x is a virtual unit; When column x satisfies 1 < column x < (m+1) / 2, or (m+1) / 2 < column x < m, the basic cell of row x is an offset cell; When x = (m+1) / 2 columns, the distribution of the x-th row is as follows: rows 1 to x+4 and rows x+31 to n are virtual cells, and the remaining rows are bias cells.

[0029] Specifically, the basic unit is the smallest layout unit of the array, which is divided into bias units (effective root units) and virtual units (dummy root units).

[0030] Specifically, the total number of root components in this application is 10+5+1+128+128+126, of which the largest current branch is 128, and the greatest common divisor of 128 is 11, which is closest to a square layout of 1:1. 11, so the number of columns in the array is 11 + 2 dummy columns, a total of 13 columns. We determine m=13. Then, 128 + 128 + 126, the greatest common divisor of the 3 branches that are close to a square layout of 1:1 is 11. The number of rows in the array is 10 + 5 + 1 + 11 + 11 + 11 = 49 rows. We determine the number of rows to be 49, which already includes the dummy columns.

[0031] Bias unit (effective root unit / standard current unit): The functional unit that outputs current and constitutes multiple bias currents. It is a 10μA standard current unit, containing PMOS transistors M1, M2, M3, M4 and unit metal layer M5.

[0032] Dummy cell: The structure is exactly the same as the bias cell, but it does not output current. It is used for layout matching and suppressing secondary effects (WPE, LOD, OSE, PSE) in deep submicron processes.

[0033] Root element: Same as "bias element", refers to the 10μA standard current element, which is the smallest current generating element of the current source array.

[0034] The biasing unit includes a center biasing branch I2, a first auxiliary biasing branch I1, a second auxiliary biasing branch I3, a third auxiliary biasing branch I4, a fourth auxiliary biasing branch I5, and a reference biasing branch Iref. The center biasing branch is located at the intersection of row (m+1) / 2 and column (n+1) / 2. The first auxiliary biasing branch consists of 5 standard current units connected in parallel, the reference biasing branch consists of 10 standard current units connected in parallel, the second and third auxiliary biasing branches consist of 128 standard current units, the fourth auxiliary biasing branch consists of 126 standard current units, and the center biasing branch consists of 1 standard current unit. The number of standard current units is 10. μA Standard current unit.

[0035] When column x satisfies 1 < column x < (m+1) / 2, or (m+1) / 2 < column x < m, the row containing the center of all bias cells is the reference bias branch; Above the reference bias branch, the bias units in row x alternate sequentially in the order of the third auxiliary bias branch, the second auxiliary bias branch, and the first auxiliary bias branch. Below the reference bias branch, the bias units in row x alternate sequentially in the order of the first auxiliary bias branch, the second auxiliary bias branch, and the third auxiliary bias branch. When x = (m+1) / 2 columns, the arrangement of the bias cells is as follows: rows x+5, x+6, x+30 to x+32 are the first auxiliary bias branches; rows x+7 to x+15 are arranged in a cyclical alternation according to the order of the third auxiliary bias branch, the second auxiliary bias branch, and the fourth auxiliary bias branch; rows x+15 to x+19 are arranged in a cyclical alternation according to the order of the third auxiliary bias branch, the second auxiliary bias branch, the center bias branch, and the second auxiliary bias branch; rows x+20 to x+28 are arranged in a cyclical alternation according to the order of the third auxiliary bias branch, the fourth auxiliary bias branch, and the second auxiliary bias branch; and row x+29 is the third auxiliary bias branch.

[0036] Specifically, in this embodiment, n is 49 and m is 13. The current Iref (reference bias branch) is distributed with a gradient at the very center of the array, with 10 of them. I3 (second auxiliary bias branch) / I4 (third auxiliary bias branch) / I5 (fourth auxiliary bias branch) are distributed vertically along the gradient of Iref, with 128 / 128 / 126 of them. I2 (center bias branch) is one distributed at the very center, and I1 is placed symmetrically above and below I2.

[0037] I3 and I4 are a pair of "twin" high-current branches, their layout positions are diagonally symmetrical about the array center. On the wafer, process parameters such as photolithography, etching, and stress exhibit slow changes (i.e., gradients) from the center to the edge, causing deviations in the actual performance of cells at different locations on the layout. If I3 and I4 are located at opposite ends of the gradient change direction, the process deviations they experience will also be in opposite directions. Averaging or comparing the current values ​​of I3 and I4 can effectively offset this unidirectional gradient error, achieving higher current accuracy and consistency than a single branch. I3 and I4 are identical in circuit specifications, both being 1.28mA high-current bias branches; their core difference lies in their diagonally symmetrical distribution on the layout, the purpose of which is to offset process gradient errors through an averaging effect, thereby improving overall current accuracy.

[0038] Specifically, in this embodiment, the central bias branch consists of one standard current unit, the first auxiliary bias branch consists of five standard current units connected in parallel, the reference bias branch consists of ten standard current units connected in parallel, the second and third auxiliary bias branches consist of 128 standard current units, and the fourth auxiliary bias branch consists of 126 standard current units.

[0039] Each bias unit PMOS includes transistors M1, M2, M3, M4 and a unit metal layer M5; M1 and M3 are parallel main current transistors. Their sources are connected to each other and connected to the power supply VDD. Their gates are connected to each other and connected to the common bias voltage VPB. Their drains are connected to each other and lead out a 10μA reference current path.

[0040] Specifically, the layout diagram of the multi-bias current source is as follows: Figure 3 As shown, the bias current sources of all I1 / I2 / I3 / I4 / I5 are based on the root cell current data of 10uA, and are increased exponentially. Specifically, the method is... The ratio of currents is equal to the aspect ratio of the device dimensions, hence the statement... , The current data size of Iref is the parallel combination of 10 root components. The total number of root components needed is 10+5+1+128+128+126=398, plus 239 dummy root components, for a total of 398+239=637 root components.

[0041] The common centroid of all 637 cells in the table is I2. The Iref is a sloping gradient distribution, which can reduce mismatch caused by process gradient errors. Each column also has a center point, which is Iref. I1 consists of 5 root devices, distributed in the middle column of the table, and placed symmetrically along the centroid I2.

[0042] Dummy devices surround multiple current sources, which can reduce the aforementioned WPE, PSE and other effects. The data ODs of each channel are interconnected without being disconnected, which helps to reduce LOD and OSE effects.

[0043] M2 and M4 are parallel switching transistors. Their sources are connected to each other and connected to the common drain of M1 and M3. Their gates are connected to each other and connected to the unit metal layer M5. Their drains are connected to each other and serve as the root unit current output terminal. The on / off control of the single root unit current is achieved by turning them on or off.

[0044] Specifically, PMOS transistors M1 and M3 (main current transistors): PMOS transistors are connected in parallel, with the source connected to VDD and the gate connected to the common bias VPB, generating a 10μA reference current.

[0045] PMOS transistors M2 and M4 (switching transistors): PMOS transistors connected in parallel to control the current on and off of a single cell, with the gate driven by M5.

[0046] Unit metal layer M5: The internal metal wiring of each root unit is connected to the gate of M2 / M4 at one end and to the global bus M6 at the other end to transmit digital control signals.

[0047] Specifically, such as Figure 4 As shown, one end of the PMOS device (M1 / M3) is connected to the common terminal VDD, so it can be shared by multiple channels and there is no problem with OD continuity, thus eliminating the impact of process level two effect (LOD). However, the PMOS device (M2 / M4) cannot share OD continuity by multiple channels, so a Dummy device needs to be added. One end of the Dummy is connected to the signal line, and the other end is connected to VDD together with the gate. In this way, the outer drain terminals are all connected to VDD, which can enable multiple modules to reuse OD continuity.

[0048] Global Metal Bus M6: Top-level metal bus, which aggregates all M5s and connects digital modules.

[0049] One end of the unit metal layer M5 is fixedly connected to the common gate of M2 and M4, and the other end extends and is connected to the global metal bus M6. The global metal bus M6 aggregates all unit metal layers M5 and connects to the external digital module.

[0050] Specifically, the digital module outputs a multi-bit digital control word, which independently controls the conduction / cutoff of each root unit through the gates of M6→M5→M2 / M4, adjusts the number of parallel units, and achieves current calibration.

[0051] The gates of all standard current cells form a low-resistance interconnect network through multiple metal layers M1, M3, and M4.

[0052] Specifically, the gates of all root cells M1 / M3 are densely connected through multiple layers of metal, M1, M3, and M4, to ensure that the VPB of all cells is consistent and to suppress gate voltage gradient mismatch.

[0053] One end of each unit metal line M5 is connected to the gate of the corresponding PMOS switch M2 and M4 in the root unit, and the other end is connected to the global metal bus M6. The global metal bus M6 connects to an external digital control module. The digital control module outputs a multi-bit control word, which controls the conduction or cutoff of M2 and M4 in each root unit through the layered metal lines M6 and M5. This changes the number of root units that are connected in parallel, thereby enabling digital adjustment and error calibration of the bias current for each path.

[0054] All bias cells have continuous active regions.

[0055] Specifically, continuous active region (OD): the active regions (OD) of all adjacent root elements are connected into one piece without gaps or breaks, ensuring a consistent stress / etching environment and suppressing secondary effects.

[0056] Each current path is controlled by a PMOS switch connected to a digital module via metal wires M5 and M6 to achieve adjustable calibration of the control word. Each current path is transmitted in layers via M6 and M5 and the conduction state of each root unit M2 and M4 is independently controlled. The total parallel current is adjusted by changing the number of bias units. Each current path is a bias current formed by multiple bias units connected in parallel.

[0057] Specifically, such as Figure 2As shown, the gates of the PMOS devices (M1 / M3) are connected together. It is essential to ensure that the Vgs of each path is equal and that the resistance of the connection lines is not too high. Both sides of the gates are connected to M3 via CT via M1, and then densely interconnected via M4 to form a low-resistance gate interconnection network. The PMOS devices (M2 / M4) are the control lines for the digital module. Based on the actual test data of the chip, the control lines of the digital module are used to turn these two PMOS devices (M2 / M4) on or off to adjust the bias current source size, approximating the ideal design value. In this embodiment, there are 5 data paths, requiring 5 control lines. 22 metal lines M5 are pre-laid on the PMOS devices (M1 / M3) for the control lines. For example, if I3 has 128 root components, then there are 128 VIA4s, which are connected to different M5s through a gradient arrangement. All the metal M5s are then connected to the same M6 via multiple VIA5s. M6 is connected to the digital module for control.

[0058] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of protection of this application is limited to these examples; within the framework of this application, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of one or more embodiments of this application as described above, which are not provided in detail for the sake of brevity.

[0059] One or more embodiments in this application are intended to cover all such substitutions, modifications, and variations that fall within the broad scope of this application. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of one or more embodiments in this application should be included within the protection scope of this application.

Claims

1. A layout array of multi-channel adjustable bias current sources using deep submicron technology, characterized in that, include: The array consists of n rows × m columns of basic units, where n is 49 and m is 13. Each basic unit includes bias units and virtual units. Columns 1 and 13 are virtual cells; When column x satisfies 1 < column x < (m+1) / 2, or (m+1) / 2 < column x < m, the basic cells from row x to row x+36 are bias cells; When x = (m+1) / 2 columns, the distribution of the x-th column is as follows: rows 1 to 11 and rows 40 to 49 are virtual cells, and the remaining rows are offset cells; The bias unit includes a center bias branch, a first auxiliary bias branch, a second auxiliary bias branch, a third auxiliary bias branch, a fourth auxiliary bias branch, and a reference bias branch. The center bias branch is located at the intersection of (m+1) / 2 columns and (n+1) / 2 rows. The first auxiliary bias branch consists of 5 standard current units connected in parallel, the reference bias branch consists of 10 standard current units connected in parallel, the second and third auxiliary bias branches consist of 128 standard current units, the fourth auxiliary bias branch consists of 126 standard current units, and the center bias branch consists of 1 standard current unit. The number of standard current units is 10. μA Standard current unit; When column x satisfies 1 < column x < (m+1) / 2, or (m+1) / 2 < column x < m, the row containing the center of all bias cells is the reference bias branch; Above the reference bias branch, the bias units in column x alternate sequentially in the order of the fourth auxiliary bias branch, the third auxiliary bias branch, and the second auxiliary bias branch. Below the reference bias branch, the bias units in column x alternate sequentially in the order of the second auxiliary bias branch, the third auxiliary bias branch, and the fourth auxiliary bias branch. When x = (m+1) / 2 columns, the arrangement of the bias cells is as follows: rows 12, 13, and 37 to 39 are the first auxiliary bias branches; rows 14 to 22 are arranged in a cyclical alternation of the third, second, and fourth auxiliary bias branches; rows 23 to 26 are arranged in a cyclical alternation of the third, second, center bias branches, and second auxiliary bias branches; rows 27 to 35 are arranged in a cyclical alternation of the third, fourth, and second auxiliary bias branches; and row 36 is the third auxiliary bias branch.

2. The multi-channel adjustable bias current source layout array under deep submicron process according to claim 1, characterized in that, include: Each bias unit includes PMOS transistors M1, M2, M3, M4 and a unit metal layer M5; M1 and M3 are parallel main current transistors. Their sources are connected to each other and connected to the power supply VDD. Their gates are connected to each other and connected to the common bias voltage VPB. Their drains are connected to each other and lead out a 10μA reference current path.

3. The multi-channel adjustable bias current source layout array under deep submicron process according to claim 2, characterized in that, M2 and M4 are parallel switching transistors. Their sources are connected to each other and connected to the common drain of M1 and M3. Their gates are connected to each other and connected to the unit metal layer M5. Their drains are connected to each other and serve as the current output terminal of the bias unit. The current of the bias unit is controlled by turning it on or off.

4. The multi-channel adjustable bias current source layout array under deep submicron process according to claim 2, characterized in that, One end of the unit metal layer M5 is fixedly connected to the common gate of M2 and M4, and the other end extends and is connected to the global metal bus M6. The global metal bus M6 aggregates all unit metal layers M5 and connects to the external digital module.

5. The multi-channel adjustable bias current source layout array under deep submicron process according to claim 4, characterized in that, One end of the unit metal line of the unit metal layer M5 is connected to the gate of the PMOS switch M2 and M4 in the corresponding bias unit, and the other end is connected to the global metal bus M6. The global metal bus M6 connects to an external digital module. The external digital module outputs a multi-bit control word, which controls the conduction or cutoff of M2 and M4 in each bias unit through the layered metal lines M6 and M5. This changes the number of bias units that are connected in parallel, thereby enabling digital adjustment and error calibration of the bias current for each path.

6. The multi-channel adjustable bias current source layout array under deep submicron process according to claim 2, characterized in that, All bias cells have continuous active regions.

7. The multi-channel adjustable bias current source layout array under deep submicron process according to claim 4, characterized in that, Each current path is controlled by a PMOS switch, which, together with the unit metal line of the unit metal layer M5 and the global metal bus M6, connects to an external digital module to achieve adjustable calibration of the control word. Each current path is transmitted layer by layer through M6 and M5 and independently controls the conduction state of M2 and M4 in each bias unit. The total parallel current is adjusted by changing the number of bias units. Each current path is a bias current formed by multiple bias units connected in parallel.

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