A low power consumption shipping mode circuit

Abstract

The application relates to the technical field of electronic circuits, and provides a low-power consumption shipping mode circuit, which comprises a low-power consumption clock circuit, a low-power consumption analog comparator, a frequency divider circuit, a digital delay circuit and a switch S1; the low-power consumption clock circuit is electrically connected with the digital delay circuit and is used for providing a working clock for the digital delay circuit; the low-power consumption analog comparator is electrically connected with the digital delay circuit and is used for detecting a photocell node VSI voltage and outputting a detection signal; the frequency divider circuit is electrically connected with the low-power consumption clock circuit and the digital delay circuit respectively and is used for transmitting the clock to the digital delay circuit after frequency division; the digital delay circuit is electrically connected with the switch S1 and is used for outputting a flag signal to control the on-off of the switch S1; and the power supply control is realized through the on-off. The application realizes automatic switching of the shipping mode according to ambient light, does not need an external button, has extremely low self-power consumption of the circuit, effectively prolongs the battery life, and is compatible with an external control mode.

Description

Technical Field

[0001] This application relates to the field of low-power circuits, and more particularly to a low-power shipping mode circuit. Background Technology

[0002] With the development of IoT technology and portable electronic devices, products such as remote controls and electronic price tags widely adopt low-energy harvesting systems. These systems collect energy from the environment, such as light, heat, and electromagnetic waves, and convert it into electrical energy. This energy, combined with a storage battery, enables the device to operate autonomously, meeting environmental protection requirements and extending product lifespan. The storage batteries in these products are mostly lithium-ion batteries. Lithium-ion batteries have inherent characteristics: if over-discharged or left uncharged for an extended period, the reversibility of the active materials at the positive and negative electrodes is damaged, making the battery unable to be recharged. Even if it can be recharged, its capacity will significantly decrease, severely impacting the user experience and battery lifespan. To address these issues, a shipping mode has emerged. This mode represents the device's lowest static current operating mode. Activating this mode at the factory disconnects the storage battery from the backend system, significantly reducing battery power consumption and preventing damage from prolonged depletion during transportation and storage.

[0003] In existing technologies, the shipping mode is triggered by external control, i.e., by triggering a dedicated button on the product or other active operation. However, in this implementation scheme, the battery stage is often connected to multiple power ICs or chips in the device circuit. Although their standby current is small, it still consumes a considerable amount of battery power over a long period of time. Moreover, additional external buttons are required for manual triggering, which not only increases labor costs but also increases the risk of missed operations leading to battery damage. Summary of the Invention

[0004] This application provides a low-power shipping mode circuit, which solves the technical problem that the long-term use of the shipping mode in the prior art still consumes a lot of battery power and requires operation through an external button.

[0005] To achieve the above objectives, this application adopts the following technical solution: In a first aspect, a low-power shipping mode circuit is provided, comprising: a low-power clock circuit, a low-power analog comparator, a frequency divider circuit, a digital delay circuit, and a switch S1. The low-power clock circuit is electrically connected to the digital delay circuit and is used to provide the operating clock for the digital delay circuit. The low-power analog comparator is electrically connected to the digital delay circuit and is used to detect the VSI voltage of the photovoltaic cell node and output a detection signal to the digital delay circuit. The digital delay circuit is also compatible with external control signal input. The frequency divider circuit is electrically connected to the ultra-low power clock circuit and the digital delay circuit respectively. The frequency divider circuit is used to divide the clock output by the low power clock circuit and transmit it to the digital delay circuit, providing a frequency-divided clock for the digital delay circuit. The digital delay circuit is electrically connected to the switch S1, and the digital delay circuit is used to output a flag signal to control the on / off state of the switch S1. The switch S1 is connected in series in the power supply circuit between the energy storage battery VBAT and the back-end system VSYS. The switching of S1 controls the power supply of the energy storage battery VBAT to the back-end system VSYS, thereby switching the circuit between the shipping mode and the normal operation mode. In the shipping mode, the circuit enters a low-power state.

[0006] In conjunction with the first aspect above, in one possible implementation, the low-power clock circuit has a self-power consumption of 20nA and outputs a clock signal with a frequency of 2K Hz to the digital delay circuit and the frequency divider circuit.

[0007] In conjunction with the first aspect above, in one possible implementation, the low-power analog comparator has a self-power consumption of 20nA and is used to detect the magnitude relationship between the VSI voltage and the reference voltage VREF and output a VSI VALID detection signal, wherein the reference voltage VREF has a value of 0.8V.

[0008] In conjunction with the first aspect above, in one possible implementation, the frequency divider circuit controls the division factor by a frequency division selection register. The frequency division selection register is an 8-bit register. When the register value is 0000, the frequency divider circuit outputs a low level. When the register value is 0001, the 2K Hz clock is divided by 128 times and a 16Hz divided clock is output.

[0009] In conjunction with the first aspect above, in one possible implementation, the digital delay circuit has a built-in counter data register, and the delay time satisfies the formula T=(data+1)×Tclk, where data is the 8-bit data of the counter data register, and Tclk is the frequency division clock period output by the frequency divider circuit. When the input signal received by the digital delay circuit goes high, the shipping mode flag signal it outputs goes low; when the input signal goes low, the shipping mode flag signal it outputs goes high after a delay of T.

[0010] In conjunction with the first aspect above, in one possible implementation, the shipping mode circuit automatically detects and triggers the shipping mode in the absence of light through a low-power analog comparator. When the VSI voltage is greater than VREF, the shipping mode flag signal is at a low level, the switch S1 is closed, and the energy storage battery VBAT provides normal power to the backend system VSYS. When the low-power analog comparator is in a dark environment, the VSI voltage drop is less than VREF, the output VSI VALID detection signal decreases, the digital delay circuit starts counting, and after the counting is completed, the shipping mode flag signal is pulled high, the switch S1 is opened, the energy storage battery VBAT stops, power is supplied to the back-end system VSYS, and the system enters shipping mode.

[0011] In conjunction with the first aspect above, in one possible implementation, the 8-bit data of the counter data register is configured to be any configuration from 00 to FF, i.e., decimal 255, and marked as the counting threshold of the digital delay circuit.

[0012] In conjunction with the first aspect above, in one possible implementation, the digital delay circuit also receives an input of an external GPI interface control signal; The external GPI interface is used to trigger the shipping mode. The external GPI interface is electrically connected to the digital delay circuit and serves as the external control signal input terminal of the digital delay circuit. It is compatible with GPI interface pull-up, pull-down, and pulse width time exceeding the set time triggering mode, and the external control triggering process does not affect the normal energy harvesting function of the circuit.

[0013] In conjunction with the first aspect above, in one possible implementation, when the external GPI interface is in a high state, the shipping mode flag signal is at a low level, switch S1 is closed, and the energy storage battery VBAT provides normal power to the backend system VSYS.

[0014] In conjunction with the first aspect above, in one possible implementation, when the external GPI interface is pulled low, the digital delay circuit starts counting. After the counting is completed, the shipping mode flag signal is pulled high, the switch S1 is opened, the energy storage battery VBAT stops supplying power to the backend system VSYS, and the circuit enters shipping mode.

[0015] This application provides a low-power shipping mode circuit that uses a low-power analog comparator to detect the VSI voltage of the photovoltaic cell, enabling automatic identification of dark environments. This eliminates the need for external buttons and manual triggering, simplifying the product manufacturing process without affecting the product's appearance or layout. It is compatible with various portable low-power electronic products. Upon entering shipping mode, switch S1 disconnects the energy storage battery from the backend system, fundamentally reducing battery energy loss and preventing damage to the active materials of lithium-ion batteries due to prolonged depletion or over-discharge, thus extending battery life. Furthermore, the digital delay circuit achieves precise delay triggering through a counter data register and a frequency divider clock. Shipping mode is only triggered when the dark environment or external control signal continuously reaches the set delay time, effectively preventing false triggering of shipping mode due to instantaneous environmental changes (such as brief shading) or external signal interference, thus improving the stability of the circuit operation.

[0016] It should be understood that the descriptions of technical features, technical solutions, beneficial effects, or similar language in this application do not imply that all features and advantages can be achieved in any single embodiment. Rather, it is understood that the description of a feature or beneficial effect means that a specific technical feature, technical solution, or beneficial effect is included in at least one embodiment. Therefore, the descriptions of technical features, technical solutions, or beneficial effects in this specification do not necessarily refer to the same embodiment. Furthermore, the technical features, technical solutions, and beneficial effects described in this embodiment can be combined in any suitable manner. Those skilled in the art will understand that embodiments can be implemented without one or more specific technical features, technical solutions, or beneficial effects of a particular embodiment. In other embodiments, additional technical features and beneficial effects may be identified in specific embodiments that do not embody all embodiments. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the overall architecture of the shipping mode circuit provided in the embodiments of this application; Figure 2 A typical timing diagram for automatically detecting shipping modes in a dark environment, as provided in the embodiments of this application; Figure 3 A schematic diagram of the frequency division parameters of the frequency divider circuit provided in the embodiments of this application; Figure 4 A schematic diagram of the clock source corresponding to the shipping mode clock selection provided in the embodiments of this application; Figure 5 A typical timing diagram for external GPI control triggering shipping mode provided in the embodiments of this application. Detailed Implementation

[0018] In the description of this application, unless otherwise stated, " / " means "or," for example, A / B can mean A or B. The "and / or" in this document is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, and B alone. Furthermore, "at least one" means one or more, and "multiple" means two or more. The terms "first," "second," etc., do not limit the quantity or order of execution, and "first," "second," etc., do not necessarily imply differences.

[0019] It should be noted that, in this application, the terms "exemplary" or "for example" are used to indicate that something is being described as an example, illustration, or illustration. Any embodiment or design described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or design solutions. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0020] Combined with appendix Figure 1-5 The preferred technical parameters of the present invention are described in detail below for the shipping mode circuit of the present invention. In this embodiment, the 8-bit data of the counter data register is configured arbitrarily from 00 to FF (decimal 255), the reference voltage VREF=0.8V, the ultra-low power clock circuit outputs a 2K Hz base clock, the frequency division selection register is configured as 0001 (frequency division 128 times, output 16Hz frequency division clock), the overall self-power consumption of the circuit is 200nA, and it is suitable for electronic price tag products equipped with a light energy harvesting system.

[0021] The low-power shipping mode circuit provided in this application includes: a low-power clock circuit, a low-power analog comparator, a frequency divider circuit, a digital delay circuit, and a switch S1. The low-power clock circuit has a self-power consumption of 20nA and continuously outputs a 2K Hz square wave base clock. One path is transmitted to the digital delay circuit as the base working clock, and the other path is transmitted to the frequency divider circuit as the frequency divider source clock, providing the clock basis for the timing control of the entire circuit.

[0022] The low-power analog comparator has a self-power consumption of 20nA. It continuously monitors the relationship between the VSI voltage of the photovoltaic cell node and the 0.8V reference voltage VREF. When VSI > 0.8V, it outputs a high-level VSI VALID detection signal; when VSI < 0.8V, it outputs a low-level VSI VALID detection signal. The detection signal is transmitted to the digital delay circuit in real time to realize automatic detection in the absence of light.

[0023] It's important to note that the low-power clock circuit and low-power analog comparator supply power to the backend system vsys via vbat during normal operation. This is a high-power operation. Upon entering shipping mode, this operation is disabled, leaving only essential modules to continue working. For example, the analog comparator here detects the presence or absence of light. If it were also disabled in shipping mode, it wouldn't be able to detect light, thus exiting shipping mode. However, shipping mode itself requires minimal chip power consumption; therefore, this module requires a low-power comparator. Similarly, the low-power clock circuit operates only for necessary internal timing circuitry.

[0024] The frequency divider circuit is controlled by an 8-bit frequency divider selection register. In this embodiment, the register is configured as 0001, which divides the 2KHz base clock by 128 times and outputs a 16Hz divided clock (clock period Tclk=62.5ms), which is transmitted to the digital delay circuit as a counting clock. If the delay time needs to be adjusted, the frequency of the divided clock can be changed by modifying the value of the frequency divider selection register. The digital delay circuit has a built-in 8-bit counter data register, which is configured as FF (255) in this embodiment. According to the delay formula T=(data+1)×Tclk, the delay time is calculated to be T=(255+1)×62.5ms=16s. This module supports dual input signal sources, namely the VSI VALID signal in automatic detection mode and the GPI signal in external control mode. When the input signal goes high, the shipping mode flag signal goes low immediately; when the input signal goes low, the shipping mode flag signal goes high after a 16s delay; the final output shipping mode flag signal directly controls the on / off state of switch S1. Switch S1 is a low-power analog switch connected in series between the energy storage battery VBAT of the electronic price tag and the back-end system VSYS. When the shipping mode flag signal is high, switch S1 is open, cutting off the power supply circuit; when the shipping mode flag signal is low, switch S1 is closed, restoring normal power supply.

[0025] In this embodiment, taking the dark environment during the transportation phase of electronic price tags as an example, the complete workflow of automatically detecting the departure shipping mode is illustrated as follows: Initial normal operating state: Before leaving the factory, the product is in a light environment, the light energy harvesting system is working normally, the VSI voltage is >0.8V, the low-power analog comparator outputs a high-level VSI VALID detection signal to the digital delay circuit; the input signal of the digital delay circuit is high-level, and its output shipping mode flag signal is low-level; switch S1 remains closed under low-level control, the energy storage battery VBAT supplies power to the back-end system VSYS normally, and the circuit is in normal operating mode.

[0026] No-light environment detection: When the product enters the transportation / warehousing stage, it is in a no-light environment. The light energy harvesting system stops working, and the VSI voltage gradually decreases and eventually reaches 0V. At this time, the VSI voltage is <0.8V. The output signal of the low-power analog comparator flips, and the VSI VALID detection signal becomes low and is transmitted to the digital delay circuit.

[0027] Digital delay counting: When the digital delay circuit detects that the input VSI VALID signal has gone low, it immediately starts the internal counter. The counter is based on the 16Hz frequency division clock output by the frequency divider circuit and starts counting according to the 255 threshold of the counter data register. The timing duration is 16s. This delay design can avoid false triggering of the shipping mode due to instantaneous changes in the environment such as brief shading.

[0028] Triggering Shipping Mode: After the digital delay circuit completes a 16-second count, the shipping mode flag signal it outputs flips from low to high. Switch S1 is opened under high-level control, the energy storage battery VBAT stops supplying power to the back-end system VSYS, the back-end system stops working, and the entire circuit enters an extremely low-power shipping mode with an overall self-power consumption of only 200nA.

[0029] Exiting Shipping Mode: When the product arrives at the user end and is in a light environment, the light energy harvesting system restarts, the VSI voltage rises to >0.8V, and the VSI VALID detection signal of the low-power analog comparator immediately flips to a high level; the digital delay circuit detects that the input signal has become high, and its output shipping mode flag signal immediately goes low, switch S1 closes, the energy storage battery resumes power supply to the back-end system, the circuit exits shipping mode, and resumes normal operation.

[0030] Based on the above embodiments, this embodiment also provides a solution for manually triggering the shipping mode. This solution's shipping mode circuit is compatible with external GPI control triggering mode, requiring no changes to the circuit hardware architecture. Only the input signal source of the digital delay circuit needs to be switched to the external GPI interface. The specific workflow is as follows: Initial normal operating state: The external GPI interface is in the high state, and the high-level GPI signal is transmitted to the digital delay circuit; the input signal of the digital delay circuit is high level, and its output shipping mode flag signal is low level; switch S1 remains closed, the energy storage battery VBAT supplies power to the back-end system VSYS normally, the circuit is in normal operating mode, and the photovoltaic energy harvesting system can work normally in this state, and the external GPI high does not affect energy harvesting.

[0031] External control signal input: If the shipping mode needs to be manually triggered, pull the external GPI interface low. The low-level GPI signal is transmitted to the digital delay circuit. This triggering method can be achieved through the product's main control chip or external testing equipment, without the need to set a dedicated external button.

[0032] Digital delay counting: When the digital delay circuit detects that the input GPI signal has gone low, it immediately starts the internal counter, using a 16Hz frequency division clock as the counting reference, and starts counting for 16 seconds according to a threshold of 255; this delay design can avoid false triggering caused by external signal interference.

[0033] Triggering Shipping Mode: After the digital delay circuit completes the 16s count, the shipping mode flag signal flips to a high level, switch S1 opens, the energy storage battery stops supplying power to the back-end system, and the circuit enters the ultra-low power shipping mode. During this process, the solar energy harvesting system can still work normally and does not affect the harvesting of ambient energy.

[0034] Exiting Shipping Mode: To manually exit shipping mode, pull the external GPI interface high again. The high-level GPI signal is transmitted to the digital delay circuit. When the digital delay circuit detects that the input signal has become high, its output shipping mode flag signal immediately becomes low, switch S1 closes, the energy storage battery resumes power supply to the back-end system, and the circuit exits shipping mode.

[0035] The outputs of the external GPS and the low-power analog comparator are each one of the two inputs to a selector. The selector's output serves as the input to a digital delay circuit, meaning they function as a two-to-one choice. The selector can choose to use the internal low-power analog comparator to determine the light intensity and automatically trigger the logic for entering shipping mode, or it can choose to use an external signal input via the GPS to directly control whether to enter shipping mode. The former can be considered the chip's own logic function, while the latter can receive and process signals from other chips.

[0036] The counter data register value (FF), frequency divider selection register value (0001), and reference voltage (0.8V) used in this embodiment are all preferred parameters. If it is necessary to adjust the delay trigger time or the no-light detection threshold of the shipping mode according to the actual application scenario of the product, it can be achieved in the following ways: Adjusting the delay trigger time: The frequency division clock can be changed by modifying the 8-bit data (00~FF) of the counter data register or by modifying the value of the frequency division selection register. Both methods can adjust the delay time T of the digital delay circuit to adapt to the delay trigger requirements of different products. Adjusting the no-light detection threshold: The detection threshold in a no-light environment can be changed by adjusting the value of the reference voltage VREF of the low-power analog comparator, thus adapting to the characteristics of the photovoltaic cells in different light energy harvesting systems.

[0037] Although this application has been described herein in conjunction with various embodiments, those skilled in the art, by reviewing the accompanying drawings, disclosure, and appended claims, will understand and implement other variations of the disclosed embodiments in carrying out the claimed application. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude multiple instances. A single processor or other unit can implement several functions listed in the claims. While different dependent claims may recite certain measures, this does not mean that these measures cannot be combined to produce good results.

[0038] Although this application has been described in conjunction with specific features and embodiments, it is obvious that various modifications and combinations can be made thereto without departing from the spirit and scope of this application. Accordingly, this specification and drawings are merely exemplary illustrations of this application as defined by the appended claims, and are considered to cover any and all modifications, variations, combinations, or equivalents within the scope of this application. Clearly, those skilled in the art can make various alterations and modifications to this application without departing from the spirit and scope of this application. Thus, if such modifications and modifications of this application fall within the scope of the claims of this application and their equivalents, this application is also intended to include such modifications and modifications.

Claims

1. A low-power shipping mode circuit, characterized in that, include: Low-power clock circuit, low-power analog comparator, frequency divider circuit, digital delay circuit, switch S1 and selector; The low-power clock circuit is electrically connected to the digital delay circuit and is used to provide the operating clock for the digital delay circuit; the low-power clock circuit outputs a clock signal with a frequency of 2K Hz to the digital delay circuit and the frequency divider circuit; The low-power analog comparator is electrically connected to the digital delay circuit and is used to detect the VSI voltage of the photovoltaic cell node and output a detection signal to the digital delay circuit; the low-power analog comparator is used to detect the relationship between the VSI voltage and the reference voltage VREF and output a VSI VALID detection signal. The frequency divider circuit is electrically connected to the ultra-low power clock circuit and the digital delay circuit respectively. The frequency divider circuit is used to divide the clock output by the low power clock circuit and transmit it to the digital delay circuit, providing a frequency-divided clock for the digital delay circuit. The frequency divider circuit uses a frequency division selection register to control the frequency division factor, and divides the clock signal to obtain a frequency-divided clock. The input terminal of the selector is connected to the output of the low-power analog comparator and the output of the external GP interface, respectively, and the output terminal of the selector is connected to the input terminal of the digital delay circuit. The digital delay circuit is electrically connected to switch S1. The digital delay circuit is used to output a flag signal to control the on / off state of switch S1. The data in the built-in counter data register of the digital delay circuit is configured as the counting threshold. The delay time satisfies the formula T=(data+1)×Tclk, where data is the 8-bit data of the counter data register and Tclk is the frequency division clock period output by the frequency divider circuit. When the low-power analog comparator is in a dark environment, it triggers the shipping mode. The VSI voltage is greater than VREF, the shipping mode flag signal is low, the switch S1 is closed, and the energy storage battery VBAT supplies power to the back-end system VSYS normally. When the low-power analog comparator is in a dark environment, the VSI voltage drops to less than VREF, the output VSIVALID detection signal decreases, the digital delay circuit starts counting, and after the counting is completed, the shipping mode flag signal is pulled high, the switch S1 is opened, the energy storage battery VBAT stops and supplies power to the back-end system VSYS, and enters shipping mode. The digital delay circuit also includes an external GPI interface control signal input; the external GPI interface is used to trigger the shipping mode, and the external GPI interface is electrically connected to the digital delay circuit. The switch S1 is connected in series in the power supply circuit between the energy storage battery VBAT and the back-end system VSYS. The switching of S1 on and off enables the energy storage battery VBAT to control the power supply to the back-end system VSYS, thereby switching the circuit between shipping mode and normal operation mode. In the shipping mode, the low-power analog comparator and the low-power clock circuit remain operational to detect the conditions for exiting the shipping mode.

2. The low-power shipping mode circuit according to claim 1, characterized in that, The frequency divider selection register is an 8-bit register. When the register value is 0000, the frequency divider circuit outputs a low level. When the register value is 0001, the 2K Hz clock is divided by 128 times and outputs a 16Hz divided clock.

3. The low-power shipping mode circuit according to claim 1, characterized in that, The 8-bit data configuration of the counter data register can be any configuration from 00 to FF.

4. The low-power shipping mode circuit according to claim 1, characterized in that, When the external GPI interface is in the high state, the shipping mode flag signal is at a low level, switch S1 is closed, and the energy storage battery VBAT provides normal power to the backend system VSYS.

5. A low-power shipping mode circuit according to claim 1, characterized in that, When the external GPI interface is pulled low, the digital delay circuit starts counting. After the counting is completed, the shipping mode flag signal is pulled high, the switch S1 is opened, the energy storage battery VBAT stops supplying power to the backend system VSYS, and the circuit enters shipping mode.

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