A double-parallel three-level inverter circulating current suppression method based on equivalent five-level

Abstract

The application provides a double-parallel three-level inverter circulating current suppression method based on equivalent five-level, comprising: obtaining three-phase reference voltage; determining a center positioning vector based on the three-phase reference voltage; determining a normalized triangle region based on the center positioning vector; determining an equivalent five-level switching sequence based on the normalized triangle region; decomposing the equivalent five-level switching sequence according to a preset restriction principle to determine three-level switching signals of the double-parallel three-level inverter. The method provided by the application effectively reduces the excitation source of zero sequence circulating current from the modulation mechanism by reasonably designing the modulation and switching sequence, effectively suppresses the zero sequence circulating current of the double-parallel three-level inverter, and has higher practical value without introducing additional current sensors and control loops.

Description

Technical Field

[0001] This application relates to the field of power electronics technology, and in particular to a circulating current suppression method for dual parallel three-level inverters based on an equivalent five-level circuit. Background Technology

[0002] Three-level neutral point clamped (NPC) inverters are widely used in practical engineering due to their mature structure and simple control. In high-power applications, due to the limited capacity of a single inverter, paralleling multiple inverters has become an inevitable trend to increase capacity. However, parallel inverter systems generally face the problem of zero-sequence circulating current, which significantly increases the current stress on devices and system losses, reduces system operating efficiency and reliability, and in severe cases may even trigger overcurrent protection or damage to devices.

[0003] Existing methods for suppressing zero-sequence circulating current mainly fall into two categories. One category is control compensation-based suppression methods, which actively suppress zero-sequence circulating current at the control level by introducing a closed-loop controller for the zero-sequence circulating current, virtual impedance, or additional compensation voltage. These methods offer intuitive suppression effects, but significantly increase system complexity and control computation, and make control parameter tuning difficult. To simplify the system structure, structural optimization methods based on the modulation strategy itself have gained attention. These methods eliminate the excitation voltage of zero-sequence circulating current at the modulation source by rationally designing the switching sequence and modulation symmetry. These methods require no additional control loops, have a simple structure, and low implementation cost, making them more suitable for high reliability and high power density applications. However, most of these methods rely on independent control of the inverters, neglecting the overall integrity of parallel inverters. For multi-inverter parallel systems, existing modulation strategies typically use the same drive signal for independent control of each converter. This approach requires high hardware consistency and is difficult to avoid instability caused by control deviations, leading to non-negligible errors between inverters, thus making it easier to generate zero-sequence circulating current and affecting the stable operation of the system.

[0004] Existing modulation methods are mainly designed for single inverters and lack unified modeling and modulation constraints for the coupling mechanism of common-mode voltage difference and zero-sequence circulating current in parallel systems, making it difficult to suppress circulating current from the source of modulation. Summary of the Invention

[0005] This application provides a circulating current suppression method for dual parallel three-level inverters based on an equivalent five-level circuit. To solve the above-mentioned technical problems, this application adopts the following technical method: This application provides a circulating current suppression method for dual parallel three-level inverters based on an equivalent five-level circuit, including: Obtain the three-phase reference voltage; Based on the three-phase reference voltage, determine the center positioning vector; Based on the central positioning vector, a normalized triangular region is determined; Based on the normalized triangular region, an equivalent five-level switch sequence is determined; The equivalent five-level switch sequence is decomposed according to a preset constraint principle to determine the switching signals of the dual parallel three-level inverter.

[0006] Optionally, determining the center positioning vector based on the three-phase reference voltage includes: The base level is determined based on the three-phase reference voltage; Obtain a dual-parallel three-level inverter system; Based on the aforementioned dual-parallel three-level inverter system, the equivalent five-level space vector diagram of the dual-parallel three-level inverter is determined; Based on the base level and the equivalent five-level space vector diagram of the dual parallel three-level inverter, the center positioning vector is determined.

[0007] Optionally, determining the center positioning vector based on the base level and the equivalent five-level space vector diagram of the dual-parallel three-level inverter includes: Based on the base level, determine the voltage vector corresponding to it in the equivalent five-level space vector diagram of the dual parallel three-level inverter, and record this voltage vector as the center positioning vector.

[0008] Optionally, determining the normalized triangular region based on the central positioning vector includes: Based on the central positioning vector, determine multiple triangular regions corresponding to it in the equivalent five-level space vector diagram of the dual parallel three-level inverter; A three-phase stationary coordinate system is established using the central positioning vector as the origin. In the three-phase stationary coordinate system, the multiple triangular regions are normalized and classified based on the central positioning vector to obtain normalized triangular regions; the normalized triangular regions include the first two-level active vector triangular region and the second two-level active vector triangular region.

[0009] Optionally, determining the equivalent five-level switch sequence based on the normalized triangular region includes: Using the nearest three-vector principle, the normalized triangle region is further divided to obtain six reference vector sub-regions, and the first two-level active vector triangle region and the second two-level active vector triangle region each include three reference vector sub-regions; Determine continuous vectors based on reference vector sub-regions; The continuous vector and the center positioning vector are superimposed to determine the equivalent five-level vector; Based on the equivalent five-level vector, the equivalent five-level switching sequence is determined.

[0010] Optionally, determining continuous vectors based on reference vector sub-regions includes: Based on the three-phase reference voltage, determine the equivalent reference voltage vector corresponding to it in the equivalent five-level space vector diagram of the dual parallel three-level inverter; Based on the reference vector sub-region where the equivalent reference voltage vector is located, determine the two-level action vector and its action time corresponding to the reference vector sub-region; Based on the two-level action vector and its action time, a continuous vector is determined.

[0011] Optionally, the equivalent five-level switch sequence includes the symmetrical action order of each switch state and the corresponding action time of each switch state; determining the equivalent five-level switch sequence based on the equivalent five-level vector includes: Based on the equivalent five-level vector, determine the five-level switch states that participate in the synthesis of the continuous vector and the corresponding duration of each switch state; Based on the reference vector sub-region where the equivalent five-level vector is located, the symmetrical action order of the switching states is determined.

[0012] Optionally, the preset limiting principles include: The common-mode voltage difference is controlled within ±1 by allocating the voltage levels according to the parity of the equivalent five-level vector, with even-numbered levels being evenly distributed and odd-numbered levels being distributed. Alternating between opposite common-mode voltages within one half-carrier cycle Vector combination; Using two carrier cycles as one modulation period, the sequence combination of the preceding and following carrier cycles is reversed.

[0013] This application has the following beneficial effects: The method proposed in this application effectively reduces the excitation source of zero-sequence circulating current from the modulation mechanism through reasonable design of modulation and switching sequences, thereby effectively suppressing zero-sequence circulating current in dual parallel three-level inverters. Moreover, it does not require the introduction of additional current sensors and control loops, thus having greater practical value. Attached Figure Description

[0014] Figure 1 A flowchart illustrating a circulating current suppression method for a dual-parallel three-level inverter based on an equivalent five-level circuit is provided in this application embodiment. Figure 2 This is a topology diagram of a dual-parallel three-level inverter provided in an embodiment of this application; Figure 3 This is a spatial vector diagram of the equivalent five-level space vector of a dual-parallel three-level inverter provided in the embodiments of this application; Figure 4 The equivalent five-level vector synthesis diagram provided in the embodiments of this application; Figure 4 (a) Base level L X Equivalent five-level vector synthesis diagram at =320; Figure 4 (b) Base level L X Equivalent five-level vector synthesis diagram at =310; Figure 5 This is a schematic diagram of the normalized triangular region and its division provided in an embodiment of this application; Figure 5 (a) is F e The first two-level active vector triangle region diagram when =1; Figure 5 (b) is F e The second two-level active vector triangle region diagram when =2; Figure 6 This is a schematic diagram of the equivalent five-level decomposition provided in the embodiments of this application; Figure 7 This is a conventional SVPWM output voltage waveform diagram provided in an embodiment of this application; Figure 8 This is a conventional SVPWM output current waveform diagram provided in an embodiment of this application; Figure 9 This is a traditional SVPWM zero-sequence circulating current waveform diagram provided in an embodiment of this application; Figure 10 The output voltage waveform diagram of the method proposed in this application is provided for the embodiments of this application; Figure 11 The output current waveform diagram of the method proposed in this application is provided for the embodiments of this application; Figure 12 The zero-sequence circulating waveform diagram of the method proposed in this application is provided for the embodiments of this application. Detailed Implementation

[0015] To facilitate understanding by those skilled in the art, the present application will be further described below in conjunction with embodiments and accompanying drawings. The content mentioned in the embodiments is not intended to limit the present application.

[0016] To solve the above technical problems, such as Figure 1 As shown, this application proposes a circulating current suppression method for dual-parallel three-level inverters based on an equivalent five-level circuit. The topology of the dual-parallel three-level inverter system to which this method is applied is as follows: Figure 2 As shown. The dual-parallel three-level inverter consists of two common three-phase loads and a DC-side voltage... V dcThe three-level NPC inverters are connected in parallel, with eight IGBTs per phase. S ixj and four diodes D xj ( i = 1, 2; x = a , b , c ; j =1, 2, 3, 4), where ( S 1x1 , S 1x3 ), ( S 1x2 , S 1x4 ), ( S 2x1 , S 2x3 )and( S 2x2 , S 2x4 ) are complementary switch pairs; L f Indicates the filter inductance. C 1. C 2 indicates the upper and lower bus capacitors on the DC side; V dc Indicates the DC side voltage; i ix For inverter i of x Phase current, i x Dual-parallel three-level inverter x Phase output current, i ZSCC This indicates the zero-sequence circulating current between parallel inverters; N represents the line neutral point, which is connected to the midpoint of the two NPC inverters; the positive direction of the current is shown in the figure.

[0017] The output voltage per phase of a single inverter, the total output voltage, and the system common-mode voltage difference can be expressed as: (1) (2) (3) in, V xiO Indicates inverter i The x Phase output voltage, S xi Indicates inverter i middle xSwitching status of phase bridge arm ( S xi =0, 1, 2).

[0018] The method proposed in this application includes the following steps: Step S101: Obtain the three-phase reference voltage; This step is mainly to obtain the three-phase reference voltage. v xN This facilitates the generation of switching signals later.

[0019] Step S102: Determine the center positioning vector based on the three-phase reference voltage; The above three-phase reference voltage v xN It can be decomposed into two components, as shown in the following equation: (4) in, L X For a sampling period, it represents v xN The constant value of the basic voltage level characteristic determines the five-level hierarchy of the reference voltage. ξ X express v xN The average active component.

[0020] according to Figure 2 The dual-parallel three-level inverter system shown is illustrated. An equivalent five-level space vector diagram of the dual-parallel three-level inverters is constructed. When the dual-parallel three-level inverters operate in parallel, an additional 42 voltage vectors are obtained, such as... Figure 3 As shown. Given that the common-mode voltage difference drives the zero-sequence circulating current, a vector with a common-mode voltage difference of 0 is selected in the equivalent five-level vector diagram, and the corresponding region is delineated. The value at the center of the triangular region is... L X ,according to L X The vector region can be divided into two types of triangles.

[0021] like Figure 4 As shown, the synthesis process of the equivalent five-level circuit is as follows: Three-phase reference voltage v xN It can be decomposed into two components, which correspond to the equivalent reference voltage vector in the equivalent five-level space vector diagram of the dual parallel three-level inverter. v s It can also be broken down into l X and s X ,in l X It is the basic level.L X The vector representation of the voltage vector, which directly locates the voltage vector within the divided triangular region, is therefore defined as the center positioning vector. Figure 4 (a) and Figure 4 (b) respectively showed L X =320 and L X Equivalent five-level vector synthesis diagram at =310. s X Represents the average active component ξ X The vector, which is the continuous modulation component inside the triangle, is used to ensure the sinusoidal characteristic of the output voltage and is defined as a continuous vector. Basic level L X and average active component ξ X The expression is: (5) (6) Positioning represented by equation (5) v xN Basic level L X This allows you to find the equivalent five-level space vector diagram. l X The initial and final positions are located in the triangular region.

[0022] Step S103: Determine the normalized triangular region based on the central positioning vector; According to equation (5), the three-phase reference voltage can be determined. v xN Different values ​​are obtained, and thus different base levels are determined based on these values. Each base level has a corresponding center positioning vector. Based on this center positioning vector, multiple triangular regions are determined in the equivalent five-level space vector diagram of the dual-parallel three-level inverter. Figure 4 It can be seen that, s X As the average activity component ξ X The continuous vector lies within a triangular region centered on the central positioning vector. Therefore, a three-phase stationary coordinate system can be established using the central positioning vector as the origin. Within this system, multiple triangular regions are normalized and classified using the central positioning vector as a reference, resulting in normalized triangular regions, such as... Figure 5 As shown. There are two types of normalized triangular regions: the first two-level active vector triangular region with vertices (0,1,0), (1,0,0), and (0,0,1), as shown... Figure 5As shown in (a), and the second two-level active vector triangle region with vertices (0,1,1), (1,0,1), and (1,1,0), as... Figure 5 As shown in (b). Definition F L Three-phase base level (i.e.) L A , L B , L C The sum of these terms yields the following relationship: (7) (8) in, F e This represents the magnitude normalization of the reference vector to the center.

[0023] In this normalized triangular region, after the three vertices of the triangle are normalized to the central positioning vector, s X This can be equivalently viewed as utilizing three-phase vectors S a , S b , S c It was synthesized. Therefore s X It can be viewed as a two-level active vector that serves as the vertices of a triangle. s a , s b , s c Synthesis, its scalar value S a , S b , S c .

[0024] Step S104: Based on the normalized triangular region, determine the equivalent five-level switch sequence; To more effectively reduce current ripple and harmonics, based on the nearest three-vector principle, the first two-level active vector triangle region and the second two-level active vector triangle region are finely divided into six reference vector sub-regions. The corresponding region division conditions are shown in Table 1. Table 1. Criteria for Regional Division ; As shown in Table 1, the first two-level active vector triangle region includes three reference vector sub-regions I, II, and III, and the second two-level active vector triangle region includes three reference vector sub-regions IV, V, and VI.

[0025] Since formulas (5) and (6) only complete the hierarchical positioning and component decomposition of the reference voltage, they cannot determine the precise region of the continuous vector within the triangle, the combination of the nearest three vectors, and the action time of each vector. Therefore, it is necessary to further perform region discrimination, selection of the nearest three vectors, and volt-second balance calculation on the continuous vector in order to generate a switching sequence and drive command that meet the modulation requirements. The calculation process is as follows: First, determine the normalized triangle region where the equivalent reference voltage vector is located. Then, determine the reference vector sub-region where the equivalent reference voltage vector is located according to Table 1. This will give you the two-level action vector corresponding to the reference vector sub-region. V 0、 V 1. V 2, V 0 represents the

[000] vector. V 1. V 2 represents the two vertex vectors of the small triangular region excluding the

[000] vector. In one sampling period... T s In the middle, three two-level vectors V 0、 V 1. V The duration of action of 2 are respectively T 0、 T 1. T 2, T 0 represents the time of action of the center positioning vector normalized to the

[000] vector. Then, based on the two-level action vectors and their action times, the continuous vector is determined, as shown in equation (9): (9) To facilitate understanding, the above calculation process is illustrated with an example: by L A L B L C Taking 320 as an example, the equivalent reference voltage vector v s Located within a triangle with vertices

[010] ,

[100] , and

[001] , its specific position is determined according to Table 1. If three two-level vectors can be obtained in region I... V 0 is

[000] , V 1 is

[010] , V 2 is

[100] , if three two-level vectors can be obtained in region II. V0 is

[000] , V 1 is

[001] , V 2 is

[010] , if three two-level vectors can be obtained in region III. V 0 is

[000] , V 1 is

[100] , V 2 is

[001] . After obtaining the action time of the three vectors according to equation (9), a continuous vector is synthesized.

[0026] Therefore, given the center positioning vector, the output reference space vector of the synthesized five-level inverter can be simplified to the output reference space vector of the two-level inverter after extracting the base level. After obtaining the two-level vectors through two types of triangular region division, a continuous vector can be synthesized based on the action time of each vector. Combining this vector with the center positioning vector yields the precise position of the reference voltage vector in the space vector diagram, i.e., the corresponding equivalent five-level vector.

[0027] Given that the center positioning vector operates continuously within one cycle, the switching state changes of the equivalent five-level vector are determined by the two-level vectors of the synthesized continuous vector, and the order of action of the two-level vectors within one carrier cycle is as follows: V 1- V 2- V 0- V 0- V 2- V 1. The equivalent five-level switch sequence includes the symmetrical action order of each switch state and the corresponding action time of each switch state. Therefore, based on the equivalent five-level vector, the five-level switch states participating in the synthesis of the continuous vector and the corresponding action time of each switch state can be determined. Based on the reference vector sub-region where the equivalent five-level vector is located, the symmetrical action order of the switch states can be determined. Subsequently, the action time corresponding to the vector is allocated to the corresponding switch state to complete the control of the switching device. Figure 3 Table 2 shows the corresponding switch sequences for the regions centered at 320 and 310 in the I-th major sector. All other major sectors can be mapped to the I-th major sector. Table 2 Switching sequences for each region ; Step S105: Decompose the equivalent five-level switch sequence according to a preset constraint principle to determine the switching signals of the dual parallel three-level inverter.

[0028] After obtaining the symmetrical five-level modulation sequence, it needs to be decomposed into two sets of three-level signals, which are then distributed to the two parallel NPC inverters. To select the optimal combination, the following preset constraints are set for the decomposition: 1) The voltage levels are allocated based on the parity of the equivalent five-level vector: even-numbered levels are evenly distributed; odd-numbered levels control the common-mode voltage difference within ±1, specifically divided into ("0", "1") and ("1", "2"). Within the same time interval, V cmd The smaller the value, the smaller the ZSCC peak value.

[0029] 2) Alternate between opposite common-mode voltages within one half-carrier cycle. V cmd The vector combination is done to keep the average common-mode voltage difference at 0 over one cycle, thus ensuring that the average ZSCC is zero.

[0030] 3) Using two carrier cycles as one modulation period, reverse the sequence combination of the preceding and following carrier cycles to ensure that the average ZSCC is zero.

[0031] by L A L B L C =320, taking region I as an example, the three vectors acting are 330, 420, and 320, and the duration of each vector's action is as follows. T 0、 T 1. T 2. The modulation period is T s Its switching sequence and equivalent five-level decomposition are shown in [reference needed]. Figure 6 .

[0032] Based on the above limiting principles, the equivalent five-level switching sequence of each region can be decomposed to obtain two sets of three-level switching sequences, which are then assigned to the parallel three-level NPC inverter to control its switching state, ultimately achieving zero-sequence circulating current suppression.

[0033] Experimental verification A simulation model of a dual-parallel three-level NPC inverter was built in MATLAB / Simulink, and the results of the proposed modulation method were compared with those of the traditional SVPWM method to verify the effectiveness of the proposed modulation method. Specific circuit simulation parameters are shown in Table 3. Table 3 Main circuit simulation parameters ; Figure 7This is a waveform diagram of the output phase voltage under traditional SVPWM control. Under traditional SVPWM control, the output phase voltage of the dual parallel three-level inverter exhibits a standard three-level stepped waveform with good overall waveform symmetry, conforming to the inherent voltage output characteristics of the basic three-level inverter topology. However, the number of voltage steps is relatively small, the number of level switching times within the fundamental cycle is limited, the sine approximation of the voltage waveform is low, and it is impossible to reduce voltage harmonic content through more level subdivision.

[0034] like Figure 8 As shown, under the traditional SVPWM strategy, the three-phase output current of the dual-parallel inverter is a high-quality sine wave with a stable current amplitude of around 40A. The three phases have consistent amplitude and synchronized phase, with no obvious distortion or imbalance. The total harmonic distortion (THD) of the output current is only 0.84%, and the current waveform has high smoothness. This demonstrates the excellent current modulation performance of traditional SVPWM under three-phase balanced operating conditions, effectively ensuring the output power quality of a single three-level inverter.

[0035] like Figure 9 As shown, traditional SVPWM does not perform any active suppression design for zero-sequence components, resulting in zero-sequence circulating current between the two parallel inverters. The amplitude of the circulating current is significant, and the circulating current is superimposed with obvious high-frequency pulsation components, which seriously restricts the stable operation and power density improvement of the two parallel inverters.

[0036] Figure 10 The output five-level voltage waveform is shown under the control of the proposed method. Based on the proposed equivalent five-level vector synthesis method, the system can maintain stability throughout the entire fundamental cycle, with smooth level switching and good symmetry, verifying the correctness and feasibility of synthesizing the equivalent five-level vector based on "fundamental level + two-level active vector". Furthermore, the introduction of the equivalent five-level voltage vector provides higher voltage degrees of freedom for subsequent modulation decomposition, laying the foundation for zero-sequence circulating current suppression.

[0037] Figure 11 The three-phase output current waveforms of the 3L-1 and 3L-2 inverters are shown. It can be seen that the output current amplitude of both inverters is around 15A, with consistent amplitude and synchronized phase, and no obvious current imbalance is observed, indicating that the modulation decomposition process did not introduce additional current asymmetry problems. Meanwhile, the three-phase current output waveform quality of the dual-parallel three-level inverters is good. Harmonic analysis shows that under the proposed modulation strategy, the total harmonic distortion (THD) of the output current is 1.53%, meeting the power quality requirements of parallel systems. This demonstrates that the proposed method achieves equivalent five-level voltage synthesis and circulating current suppression while ensuring current quality, highlighting the practicality of the proposed method.

[0038] Figure 12The diagram shows the zero-sequence circulating current waveform of a dual-parallel three-level inverter. Without introducing any current closed-loop control or virtual impedance, the amplitude of the zero-sequence circulating current in the parallel inverter is effectively suppressed, with the steady-state circulating current approaching zero. Only a small high-frequency pulsation component exists during switching, verifying the effectiveness of the introduction of the equivalent five-level vector and the proposed modulation method. This method can effectively suppress the zero-sequence circulating current in a dual-parallel system, significantly reducing system losses and equipment failure risks, and improving the operational reliability and stability of the dual-parallel inverter.

[0039] In summary, the method proposed in this application effectively reduces the excitation source of zero-sequence circulating current from the modulation mechanism through reasonable design of modulation and switching sequences, thereby effectively suppressing zero-sequence circulating current in dual parallel three-level inverters. Moreover, it does not require the introduction of additional current sensors and control loops, thus having greater practical value.

[0040] In some embodiments, this application also provides a computer system including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps in the above-described method embodiments.

[0041] This application also provides a computer-readable storage medium for storing a computer program. This computer-readable storage medium can be applied to a computer device, and the computer program causes the computer device to execute the corresponding processes in the methods described above in the embodiments of this application; for brevity, further details are omitted here.

[0042] The above embodiments are preferred implementations of this application. In addition, this application can be implemented in other ways. Any obvious substitutions without departing from the concept of this technical solution are within the protection scope of this application.

[0043] To facilitate understanding by those skilled in the art of the improvements made by this application compared to the prior art, some of the accompanying drawings and descriptions have been simplified, and for clarity, some other elements have been omitted from this application. Those skilled in the art should realize that these omitted elements may also constitute the content of this application.

Claims

1. A method for circulating current suppression of a dual parallel three-level inverter based on equivalent five-level, characterized in that, include: Obtain the three-phase reference voltage; Based on the aforementioned three-phase reference voltage, determine the base level: ； wherein is a constant value representing the base level characteristic for one sampling period, represents the average active component; Obtain a dual-parallel three-level inverter system; Based on the aforementioned dual-parallel three-level inverter system, the equivalent five-level space vector diagram of the dual-parallel three-level inverter is determined; Based on the aforementioned base level, determine the voltage vector corresponding to it in the equivalent five-level space vector diagram of the dual parallel three-level inverter, and denote this voltage vector as the center positioning vector: ； ； Based on the central positioning vector, determine multiple triangular regions corresponding to it in the equivalent five-level space vector diagram of the dual parallel three-level inverter; A three-phase stationary coordinate system is established using the central positioning vector as the origin. In the three-phase stationary coordinate system, the multiple triangular regions are normalized and classified based on the central positioning vector to obtain normalized triangular regions; the normalized triangular regions include a first two-level active vector triangular region and a second two-level active vector triangular region. ； ； in, Three-phase base level (i.e.) , , ) and, This represents the magnitude normalization of the reference vector to the center; Based on the normalized triangular region, an equivalent five-level switch sequence is determined; The equivalent five-level switch sequence is decomposed according to a preset constraint principle to determine the switching signals of the dual parallel three-level inverter.

2. The method according to claim 1, characterized in that, The determination of the equivalent five-level switch sequence based on the normalized triangular region includes: Using the nearest three-vector principle, the normalized triangle region is further divided to obtain six reference vector sub-regions, and the first two-level active vector triangle region and the second two-level active vector triangle region each include three reference vector sub-regions; Determine continuous vectors based on reference vector sub-regions; The continuous vector and the center positioning vector are superimposed to determine the equivalent five-level vector; Based on the equivalent five-level vector, the equivalent five-level switching sequence is determined.

3. The method according to claim 2, characterized in that, The determination of continuous vectors based on reference vector sub-regions includes: Based on the three-phase reference voltage, determine the equivalent reference voltage vector corresponding to it in the equivalent five-level space vector diagram of the dual parallel three-level inverter; Based on the reference vector sub-region where the equivalent reference voltage vector is located, determine the two-level action vector and its action time corresponding to the reference vector sub-region; Based on the two-level action vector and its action time, a continuous vector is determined.

4. The method according to claim 3, characterized in that, The equivalent five-level switch sequence includes the symmetrical action order of each switch state and the corresponding action time of each switch state; determining the equivalent five-level switch sequence based on the equivalent five-level vector includes: Based on the equivalent five-level vector, determine the five-level switch states that participate in the synthesis of the continuous vector and the corresponding duration of each switch state; Based on the reference vector sub-region where the equivalent five-level vector is located, the symmetrical action order of the switching states is determined.

5. The method according to claim 4, characterized in that, The preset limiting principles include: The common-mode voltage difference is controlled within ±1 by allocating the voltage levels according to the parity of the equivalent five-level vector, with even-numbered levels being evenly distributed and odd-numbered levels being distributed. Alternating between opposite common-mode voltages within one half-carrier cycle Vector combination; Using two carrier cycles as one modulation period, the sequence combination of the preceding and following carrier cycles is reversed.

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