A low-dropout voltage regulator circuit based on low-voltage devices adapted to high-voltage power supplies

Abstract

This invention relates to the field of power management technology. This application discloses a low-dropout voltage regulator circuit based on low-voltage devices adapted to high-voltage power supplies. To solve the problems of existing solutions requiring high-voltage devices, high cost, and inability to reuse low-voltage designs, this invention uses only low-voltage process devices. Overvoltage protection is achieved through a common-gate transistor with fixed gate bias, clamping the high-voltage input to a safe range. The control signal voltage is limited through a voltage divider clamping network. During power down, a voltage divider design is used to simultaneously turn off the power supply and ground switches. A pull-up start-up circuit to prevent degeneracy is also integrated. This circuit can directly convert a high-voltage input into a stable low-voltage output, driving ordinary low-voltage circuits without any modification, realizing the direct reuse of low-voltage designs in high-voltage scenarios. This solution has the advantages of extremely low cost, high security, low power consumption, reliable startup, and full compatibility with standard low-voltage CMOS processes, greatly expanding the application boundaries of low-voltage processes.

Description

Technical Field

[0001] This invention relates to the field of power management technology, and in particular to low dropout voltage regulator (LDO) technology. Specifically, it is a low dropout voltage regulator circuit based on low-voltage devices adapted to high-voltage power supplies. Background Technology

[0002] Low-dropout regulators (LDOs) have become an indispensable cornerstone of power management in modern electronic devices due to their simple structure, low output ripple, and fast response speed. Their applications are extremely widespread in both production and daily life. For example, in consumer electronics, smartphones, wearable devices, and wireless headphones integrate a large number of high-performance digital, analog, and radio frequency chips. These chips are mostly fabricated using state-of-the-art low-voltage processes (such as 28nm, 16nm, 7nm, and below), with extremely low core voltages (such as 0.9V, 1.2V, 1.8V, and 3.3V), but they have stringent requirements for power supply stability and noise performance. LDOs are responsible for efficiently and stably converting the voltage provided by the battery (such as 4.2V for lithium batteries) or a pre-regulated voltage into the operating voltage required by these low-voltage chips. In industrial control, devices such as PLCs (Programmable Logic Controllers), data acquisition systems, and motor drivers often need to operate on industrial bus voltages of 24V or higher, while their internal core controllers and sensor interface circuits may use low-voltage processes such as 5V or 3.3V. LDOs (Low Voltage Controllers) play a crucial role in converting and isolating high-voltage inputs to a low-voltage safe domain. In Internet of Things (IoT) devices, such as environmental sensors, smart water meters, and asset trackers, devices are often powered by batteries or energy harvesters. This requires power management chips with extremely low quiescent current (IQ) to extend battery life, while also being able to adapt to a wide range of battery voltage variations from full charge to near depletion, providing a stable power supply for low-power MCUs and RF transceivers. In summary, converting high-voltage inputs to stable low-voltage outputs and driving low-voltage process circuits that are not resistant to high voltages is a common requirement across multiple fields, including consumer, industrial, and IoT sectors.

[0003] Despite the urgent need, existing technologies have significant shortcomings in realizing the "high-voltage input → low-voltage output → driving ordinary low-voltage designs" chain. The mainstream solutions and their problems are as follows:

[0004] Option 1: Employing a multi-voltage integrated process (such as BCD process); this option solves the problem by integrating high-voltage LDMOS, medium-voltage, and low-voltage CMOS devices on the same chip. Its technical challenge lies in:

[0005] (a) Complex process and high cost: The manufacturing process requires multiple sets of high-voltage photomasks, and the number of process steps and photolithography layers increases significantly, resulting in a tape-out cost that is several times or even tens of times higher than that of standard low-voltage CMOS process.

[0006] (b) Complex design rules and increased area: High-voltage devices have special layout design rules and isolation requirements, which occupy a larger chip area;

[0007] (c) Reliability risks: There are potential reliability risks such as electric field concentration and hot carrier injection in the transition area between different voltage-resistant devices.

[0008] Option 2: Implement off-chip voltage reduction at the system level; use an independent, high-voltage-resistant power management chip (such as a DC-DC or LDO) for pre-regulation. The technical problem is:

[0009] (a) Increased system cost: Additional power chips, inductors, capacitors and other peripheral components are required, which increases BOM cost and PCB area;

[0010] (b) Poor flexibility: The low-voltage core chip becomes a "passive" part, which must rely on a specific external power supply solution and cannot achieve "plug and play";

[0011] (c) Complex design: System engineers need to consider issues such as power chip selection, layout and routing, and EMI, which increases the complexity of system integration.

[0012] Option 3: Transfer the low-voltage design to a high-voltage process; directly transplant the existing low-voltage circuit design to a high-voltage CMOS process such as 0.18μm 5V / 18V. The technical problem is:

[0013] (a) Long design cycle and low efficiency: The device models, parasitic parameters, speed and matching characteristics of high voltage process are completely different from those of low voltage process. The original design cannot be directly reused. Circuit simulation, layout design and tape-out verification must be carried out again. The cycle is usually as long as 6-12 months.

[0014] (b) Performance degradation: High-voltage devices are usually inferior to low-voltage devices of the same size in terms of speed, transconductance and matching accuracy, which leads to a decrease in key performance indicators such as bandwidth, accuracy and noise of LDOs;

[0015] (c) High R&D costs: Not only do new tape-out costs need to be paid, but also a lot of manpower needs to be invested in redesign and testing, which is a huge waste for teams that already have mature low-voltage IP.

[0016] In summary, those skilled in the art urgently need a novel LDO circuit solution composed solely of low-voltage devices, namely a low-dropout voltage regulator circuit adapted to high-voltage power supplies based on low-voltage devices. This circuit should possess comprehensive overvoltage protection, secure control signal management, and reliable start-up and shutdown logic. Summary of the Invention

[0017] The core technical problem solved by this invention is: how to construct a low-dropout regulator (LDO) circuit that can directly withstand high voltage input and generate a stable low voltage output to drive other ordinary low voltage circuits, without using complex and expensive hybrid withstand voltage processes, without adding external power chips, and without redesigning high voltage processes, using only standard, mature, and low-cost common low voltage process devices.

[0018] The importance of this core issue being addressed by those skilled in the art lies in the following:

[0019] First, we need to break through the application boundaries of low-voltage technology. Currently, the most advanced digital, analog, and RF circuits are all based on deep submicron or nanometer-level low-voltage technology, which offers significant advantages in design efficiency and performance. If the high-voltage compatibility issue cannot be resolved, these designs will be limited to the low-voltage domain and cannot be directly applied to scenarios requiring higher power domains, such as automotive electronics, industrial control, and fast charging.

[0020] Secondly, it enables true design reuse and cost reduction. If, without altering the existing vast amount of low-voltage IP, a clever "adapter" circuit (i.e., the LDO of this application) can be used to directly operate in a high-voltage environment, it will greatly shorten the product development cycle and reduce tape-out and system costs. This is crucial for the consumer electronics and IoT markets that pursue rapid iteration and are cost-sensitive.

[0021] In order to solve the above-mentioned core technical problems, this invention designs a low-dropout voltage regulator circuit based on low-voltage devices adapted to high-voltage power supplies. Its purpose is to retain all the advantages of low-voltage technology (low cost, high density, high performance, and mature design) while giving it the ability to work in the high-voltage power supply domain, thereby breaking down the technical barriers between "low-voltage design" and "high-voltage application".

[0022] To achieve the above objectives, the specific technical solution of the present invention is a low-dropout voltage regulator circuit based on low-voltage devices adapted to high-voltage power supplies, comprising:

[0023] Reference voltage generation module, used to generate a stable reference voltage;

[0024] An overvoltage protection module has an input terminal for receiving a high voltage power supply voltage (VDDH). The overvoltage protection module includes at least one common gate transistor with a fixed gate bias for initially clamping the high voltage power supply voltage and outputting a first intermediate voltage. The gate of the common gate transistor is biased at a preset intermediate potential, so that the voltage borne by the common gate transistor and the low voltage devices in the subsequent circuit does not exceed its safe withstand voltage value.

[0025] The error amplification module has its first input terminal coupled to the reference voltage generation module to receive the reference voltage, and its second input terminal coupled to the output terminal (VOUT) of the low dropout voltage regulator circuit or the voltage divider feedback node, for amplifying the difference between the two and generating an error control signal.

[0026] The power regulating transistor has its control terminal coupled to the output terminal of the error amplification module, its input terminal coupled to the output terminal of the overvoltage protection module to receive the first intermediate voltage, and its output terminal serving as the output terminal VOUT (i.e., output terminal (VOUT)) of the low-dropout voltage regulator circuit, used to adjust the output current according to the error control signal to stabilize the output voltage.

[0027] The output capacitor is coupled between the output terminal (VOUT) and ground.

[0028] In at least one embodiment, it further includes:

[0029] A voltage divider clamping network, coupled between the output of the error amplification module and the control terminal of the power adjustment transistor, or coupled to an internal node of the error amplification module, is used to limit the voltage range of the error control signal or the drive signal generated therefrom to the safe gate voltage range of the target MOS transistor.

[0030] In at least one embodiment, a Power Down control module is further included, the Power Down control module comprising:

[0031] The first switching transistor is connected in series between the output terminal of the overvoltage protection module and the power supply terminal of the error amplification module;

[0032] The second switching transistor is connected in series between the ground terminal of the error amplifier module and the system ground;

[0033] In response to the Power Down enable signal, the first switch and the second switch are configured to be turned off simultaneously, so that the high voltage power supply voltage is divided by the first switch and the second switch, ensuring that the voltage each of them withstands is within its safe withstand voltage range.

[0034] It's important to note that the overvoltage protection module, the first switching transistor, and the second switching transistor primarily form the overvoltage protection circuit. This overvoltage protection circuit is a distributed network of fixed-bias common-gate transistors throughout the circuit, spanning almost the entire current path from the high-voltage power supply (VDDH) to GND. Topologically, it's not considered a standalone module. In terms of coupling, it's coupled within various modules such as the reference voltage generation circuit, the error amplifier circuit, and the low-voltage drive circuit. 。 .

[0035] In at least one embodiment, the Power Down control module further includes at least one gate-fixed biased common-gate transistor connected in series with the first switch and / or the second switch to provide further voltage division when the high-voltage power supply voltage exceeds a predetermined threshold, thereby extending the power supply voltage range that the circuit can withstand.

[0036] In at least one embodiment, a startup circuit is further included, the startup circuit comprising:

[0037] The pull-up path has one end coupled to the control terminal of the power regulator and the other end coupled to the input terminal of the power regulator or the high voltage power supply voltage.

[0038] The state detection and control logic has its input coupled to the output (VOUT) and its output coupled to the control terminal of the pull-up path;

[0039] Specifically, when the voltage at the output terminal (VOUT) is lower than the startup threshold, the state detection and control logic turns on the pull-up path, pulls up the control terminal of the power adjustment transistor, thereby increasing the voltage at the output terminal (VOUT); when the voltage at the output terminal (VOUT) reaches a predetermined value, the state detection and control logic turns off the pull-up path, disconnecting the startup circuit from the main circuit topology, thus preventing additional static power consumption.

[0040] In at least one embodiment, a low-power drive circuit is further included, which is connected in parallel or switchably with the error amplification module and the power adjustment transistor, for providing sustained power to the output terminal (VOUT) in light load or sleep mode, and its static power consumption is much lower than that of the error amplification module.

[0041] In at least one embodiment, a control method for a low-dropout voltage regulator circuit based on low-voltage devices adapted to a high-voltage power supply is shown. The method is applied to the circuit and includes the following steps:

[0042] A. The high voltage power supply voltage (VDDH) is received through the overvoltage protection module, and the high voltage power supply voltage is clamped to a first intermediate voltage using a common gate transistor with a fixed gate bias. The first intermediate voltage and the voltage of each node inside the circuit do not exceed the safe withstand voltage value of the low voltage device.

[0043] B. The error control signal is generated by comparing the reference voltage and the feedback signal characterizing the output voltage through the error amplification module.

[0044] C. The voltage range of the error control signal is limited to a safe range by the voltage divider clamping network, and the power regulation transistor is driven.

[0045] D. The power regulating transistor adjusts the current from the first intermediate voltage to the output terminal (VOUT) according to the limited error control signal to stabilize the output voltage.

[0046] In at least one embodiment, the step of performing a Power Down operation in response to a Power Down enable signal is further included:

[0047] At the same time, the first switch connected in series in the power supply path and the second switch connected in series in the ground path are turned off, so that the high voltage power supply voltage is shared by the first switch and the second switch.

[0048] In at least one embodiment, a startup operation step is also included:

[0049] Detect the voltage at the output terminal (VOUT);

[0050] When the voltage at the output terminal (VOUT) is lower than the start-up threshold, the pull-up path is turned on to pull up the control terminal of the power regulator transistor, thereby increasing the voltage at the output terminal (VOUT).

[0051] When the voltage at the output terminal (VOUT) reaches a predetermined value, the pull-up path is automatically turned off.

[0052] In at least one embodiment, a mode switching step is also included:

[0053] When the downstream load circuit is in normal operating mode, the error amplifier module and power regulator are used as the main regulation path.

[0054] When the downstream load circuit is in low-power sleep mode, the main regulation path is turned off, and the low-power drive circuit with lower static power consumption is enabled to maintain the voltage at the output terminal (VOUT).

[0055] In at least one embodiment, a computer-readable storage medium is shown storing a computer program thereon, which, when executed, enables the implementation of the steps of the method.

[0056] Compared with existing technologies (such as BCD process, off-chip buck converter, and high-voltage process transfer), the technical solution disclosed in this application has the following non-obvious technical features:

[0057] First, this application uses a common-gate transistor with a fixed gate bias as the core overvoltage protection device: Existing technologies typically use high-voltage resistant devices to withstand high voltage, or use simple protection methods such as diode clamping; it is difficult for those skilled in the art to conceive that by simply setting a fixed intermediate potential gate bias for a common common-gate transistor in a low-voltage process, the source and drain potentials can be automatically limited to a safe range when subjected to high voltage, while the transistor's own voltage does not exceed the limit; this is a revolutionary protection approach that utilizes the inherent characteristics of low-voltage devices to "attack the enemy's shield with the enemy's spear";

[0058] Second, this application adopts a voltage divider design in Power Down mode where the power supply and ground switches are turned off simultaneously. The conventional approach is to set only one switch in the power supply path or the ground path. It is difficult for those skilled in the art to conceive that, during turn-off, by turning off two switches (such as MP4 and MN6) connected in series between the power supply and ground simultaneously, the voltage divider effect is utilized so that each switch only bears a portion of the input voltage, thereby ensuring the safety of the low-voltage switch when turning off the high-voltage input. Furthermore, to extend the withstand voltage range, a common-gate transistor with a fixed gate bias is connected in series with the switch to further divide the voltage, which is even less obvious.

[0059] Third, this application integrates a pull-up startup circuit to prevent low-voltage degeneracy: LDOs may fall into a low-voltage non-ideal operating point (degeneracy) during startup; conventional LDO designs may rely on complex bandgap reference startup circuits; it is difficult for those skilled in the art to conceive of using a branch composed of a PMOS transistor (MP3) and an NMOS transistor (MN5) controlled by a pre-stage voltage divider and logic to actively pull up the gate of the regulating transistor when the output is low, and the branch automatically turns off after startup with no static power consumption; this "use-and-go" low-cost startup circuit design with zero additional power consumption is unique in high-voltage and low-voltage hybrid designs;

[0060] Fourth, this application adopts a resistor voltage divider clamping strategy for controlling the voltage range of the control signal: directly driving a MOS transistor operating in a high-voltage domain with a low-voltage logic signal would lead to gate overvoltage; it is difficult for those skilled in the art to imagine that instead of simply adding a level converter, a clever resistor voltage divider network is used to precisely clamp the control signal (such as the high potential of the inverter) within the safe withstand voltage range of the low-voltage device, while ensuring that the MOS transistor can be fully turned on or off, thus achieving the best balance between cost, power consumption and safety.

[0061] Compared with the prior art, the present invention has the following beneficial effects:

[0062] 1. This invention has ultimate safety and reliability: precise voltage clamping and current shunting are achieved through a common gate transistor with fixed gate bias, which completely eliminates the overvoltage stress on low-voltage devices, significantly reduces the risk of device breakdown, and improves the overall lifespan and robustness of the circuit.

[0063] 2. This invention features low power consumption and high performance: In Power Down mode, the power supply and ground switch are turned off simultaneously, resulting in extremely low leakage current; the startup circuit is automatically cut off after startup is complete, without consuming any static current; at the same time, during normal operation, due to the absence of high-voltage device performance defects, the LDO maintains the inherent high bandwidth and low noise characteristics of low-voltage technology.

[0064] 3. This invention boasts perfect design reusability and extremely low cost: This is the most outstanding benefit of this solution. It allows any existing, proven common low-voltage process circuit (such as low-voltage LDO, analog front-end, digital core, etc.) to operate under high-voltage power without any modification, simply by connecting it to the output terminal. This completely breaks through the application limitations of low-voltage processes, eliminating the need for expensive BCD processes, adding off-chip chips, and redesigning high voltage, thus minimizing material costs (BOM), tape-out costs, and R&D costs.

[0065] 4. This invention features a simple structure and easy integration: the entire circuit uses only standard low-voltage process devices, without involving any special high-voltage devices or complex isolation structures, has a small layout area, is fully compatible with standard low-voltage CMOS processes, is easy to integrate into a system-on-a-chip (SoC), and has extremely high mass production value.

[0066] 5. This invention features reliable startup and no degenerate state: The built-in pull-up startup circuit ensures that the LDO can quickly and reliably enter the expected stable working state when powered on, avoiding the fatal problem of subsequent circuits failing to start due to falling into a low-voltage degenerate state. Attached Figure Description

[0067] Figure 1 This is an overall structural block diagram of the circuit described in this invention;

[0068] Figure 2 This is the schematic diagram of the core circuit of the LDO described in this invention;

[0069] Figure 3 This is a schematic diagram of the power down and start up control circuit of the conventional drive circuit described in this invention;

[0070] Figure 4 This is a schematic diagram of the LDO low-power drive circuit described in this invention;

[0071] Figure 5 This is the flow chart of the method described in this invention. Detailed Implementation

[0072] The technical solutions of this application will now be described in detail with reference to the accompanying drawings. The described embodiments are merely some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0073] In this application, low-voltage process devices refer to semiconductor devices manufactured using standard, mature deep submicron or nanometer-level CMOS processes (e.g., processes with gate oxide breakdown voltages of 1.8V, 3.3V, or 5V), such as MOSFETs, resistors, and capacitors. Their main role in this application is as the basic building blocks of this circuit, offering advantages such as low cost, high speed, high integration, and mature models. The core objective of this invention is to use only such devices, avoiding the use of any high-voltage devices, thereby reducing costs and achieving design reuse.

[0074] In this application, a common-gate transistor with a fixed gate bias refers to a MOSFET connected in a common-gate configuration in a circuit (signal input from the source and output from the drain). Its gate is connected to a constant, preset intermediate potential, rather than following the signal change. Its main function in this application is as a "gate" for overvoltage protection. When the source or drain voltage fluctuates, the fixed gate bias causes the transistor to enter the saturation region or linear region, thereby clamping the source and drain voltages within a safe range, while ensuring that its own drain-source and gate-source / drain voltages do not exceed the limit. This is one of the core innovations of this invention and a key enabling technology that allows low-voltage devices to "withstand" high voltage.

[0075] In this application, resistive voltage divider refers to a circuit technique that uses two or more resistors connected in series to obtain a voltage value lower than the total voltage from the intermediate node. Its main function in this application is to generate the fixed gate bias voltage required for a common-gate transistor, and to accurately attenuate control signals in the high-voltage domain (such as the high potential of an inverter) to the safe gate voltage range of low-voltage devices. This is a low-cost, high-linearity method for voltage conversion and limiting without additional static power consumption, and is an important auxiliary means for realizing the design of all-low-voltage devices.

[0076] In this application, Power Down control refers to a control mechanism that puts the circuit into a low-power or completely off state. Its main function in this application is to achieve a unique "dual-ended shutdown" design (simultaneously shutting off the power supply and ground switches), ensuring that there is no single path that bears the full power supply voltage in the shutdown state, thereby protecting the low-voltage switching transistor. It effectively solves the core problem of damage to the low-voltage switching transistor due to excessive voltage when shutting off high voltage in traditional single-switch transistor shutdown methods.

[0077] In this application, the pull-up startup circuit refers to an auxiliary circuit that actively pulls the voltage of a critical node (such as the gate of a power transistor) to a high level at the moment of circuit startup. Its main function in this application is to force the output voltage of the LDO to rise rapidly from zero, preventing it from falling into some non-ideal low-voltage stable states (degenerate states) and ensuring successful startup. LDOs, especially multi-loop or complex biased LDOs, may have multiple stable operating points. This circuit solves the potentially fatal problem of "startup failure" at extremely low cost and does not increase power consumption after startup.

[0078] In this application, the low-power drive circuit refers to an auxiliary drive path in the LDO, connected in parallel with the main error amplifier, specifically designed for light-load or standby modes, and with extremely low quiescent current. Its main function in this application is to maintain the voltage on the output capacitor with a quiescent current in the microamplitude or even nanoamplitude range when the downstream load (such as an IoT sensor) enters sleep mode, thus preparing for a rapid response upon wake-up. This circuit meets the stringent requirements of battery-powered devices for extremely low power consumption while retaining the high performance of the main path under heavy loads.

[0079] refer to Figure 1 This paper illustrates a schematic block diagram of a low-dropout voltage regulator circuit based on low-voltage devices adapting to high-voltage power supplies, according to one or more embodiments of this application. The circuit is applied in scenarios requiring the conversion of high-voltage power supplies (e.g., 4.2V, 5.0V, 12V, or even higher) to safe and stable low-voltage power supplies (e.g., 3.3V, 1.8V) to directly power subsequent low-voltage process circuits that are not resistant to high voltage (e.g., digital cores, analog front-ends, etc. designed using low-voltage CMOS processes). The circuit mainly includes: a reference voltage generation module, an overvoltage protection module, an error amplification module, a power adjustment transistor, an output capacitor, and optional voltage divider clamping network, a power-down control module, a startup circuit, and a low-power drive circuit.

[0080] refer to Figure 1 and combined Figure 2 The schematic diagram of the LDO core circuit shown illustrates the specific configuration and connection relationship of each module, and the following embodiment is obtained:

[0081] In one or more embodiments, the input of the overvoltage protection module is used to receive a high-voltage power supply voltage VDDH (e.g., 4.2V from a lithium battery or 12V from an industrial bus). The module includes at least one common-gate transistor with a fixed-bias gate (e.g., Figure 2 (MP0, MP1, MN3, etc. in the text).

[0082] In one or more embodiments, the overvoltage protection module is provided with a bias generation branch, which is connected to a resistor divider network (e.g., Figure 2The series connection of R0 and R1 on the left generates a preset intermediate potential Vbias_cg. This intermediate potential is stably connected to the gate of each common-gate transistor. Figure 2 Taking MP0 as an example, its source is connected to VDDH, its gate is connected to Vbias_cg, and its drain outputs the first intermediate voltage Vmid. When VDDH rises or a transient overvoltage occurs, the source potential of MP0 rises. Since the gate is fixed, its source-gate voltage V_SG increases, forcing MP0 into the saturation region or linear region, thereby clamping the drain potential Vmid to a safe value (e.g., around Vbias_cg + |Vthp|), ensuring that the voltage of low-voltage devices in the subsequent circuit (including MP1, MP2, and the transistors inside the error amplifier module 130) does not exceed their process withstand voltage limit (e.g., the maximum drain-source / gate-source voltage corresponding to 1.8V or 3.3V devices).

[0083] In one or more embodiments, the first input terminal (e.g., the inverting input terminal) of the error amplification module is coupled to the reference voltage generation module to receive a stable reference voltage Vref (e.g., 1.2V); its second input terminal (non-inverting input terminal) is coupled to the output terminal VOUT of the low-dropout regulator circuit or the voltage divider feedback node (e.g., the output sampling voltage obtained through the resistor divider FB). The error amplification module is used to amplify the difference between Vref and the feedback voltage to generate an error control signal Vctrl.

[0084] In one or more embodiments, the error amplification module itself is also powered by Vmid, and all its internal components are low-voltage process devices.

[0085] In one or more embodiments, the control terminal (gate) of the power regulator is coupled to the output of the error amplifier module via node VG (and, if necessary, via voltage divider clamping network 160); its input terminal (source) is coupled to the output of the overvoltage protection module to receive the first intermediate voltage Vmid; and its output terminal (drain) serves as the output VOUT of the low-dropout regulator circuit. The power regulator adjusts its on-resistance according to Vctrl, thereby controlling the current flowing from Vmid to VOUT to stabilize the output voltage VOUT. Typically, a large-size NMOS transistor is used as the power regulator.

[0086] In one or more embodiments, the output capacitor is coupled between the output terminal VOUT and ground to smooth the output voltage and ensure loop stability.

[0087] In one or more embodiments, the voltage divider clamping network (see...) Figure 3The resistor network of MP2, MN0 and their input terminals is coupled between the output of the error amplifier module and the control terminal of the power adjustment transistor, and is also used to limit the internal logic control signals (such as the high potential of the inverter) within a safe range.

[0088] When further executed in one or more embodiments, Figure 3 The inverter composed of MP2 and MN0 does not have its power supply directly connected to Vmid. Instead, it uses common gate transistors such as MP0 and MP1 and resistors to divide the voltage, so that the high level of the inverter is clamped within the safe gate voltage value of low-voltage devices (e.g., 3.3V).

[0089] In one or more embodiments, the Power Down control module (see...) Figure 3 (MP4, MN6 and related control logic), including:

[0090] The first switching transistor MP4 is connected in series between the output terminal Vmid of the overvoltage protection module and the power supply terminal of the error amplifier module.

[0091] The second switch MN6 is connected in series between the ground terminal of the error amplifier module and the system ground.

[0092] In response to the Power Down enable signal PD (active high), the first switch MP4 and the second switch MN6 are configured to turn off simultaneously. At this time, if Vmid is high (e.g., close to VDDH), the drain-source voltages of MP4 and MN6 share Vmid, with each transistor only bearing about Vmid / 2, thus ensuring that both are within their safe withstand voltage range.

[0093] In one or more embodiments, the startup circuit (see...) Figure 3 The MP3 and MN5 branches include: a pull-up path (a series branch consisting of MP3 and MN5), where the source of MP3 is coupled to Vmid (or directly coupled to VDDH), the drain of MP3 is coupled to the control terminal VG of the power regulator, the source of MN5 is grounded, the drain of MN5 is connected to the drain of MP3, and the gate of MN5 is connected to the control signal; and state detection and control logic ( Figure 3(Implemented using a voltage divider and inverter network in the pre-amplifier stage). The input of this logic is coupled to the output VOUT (either via a voltage divider or direct connection), and the output is coupled to the gate of MP3 in the pull-up path. The power regulator in this circuit is an NMOS transistor, labeled MN_OUT. The functions of MP3 and MN5 are as follows: When VOUT is low, MN1 is on and MN4 is off, pulling the gate of MP3 low and pushing the gate of MN5 high. Thus, both MP3 and MN5 are on, pulling the gate of the regulator MN_OUT high, thereby pulling the output VOUT of the NMOS regulator high. After VOUT is high, MN1 is off and MN4 is on, keeping both MP3 and MN5 off and no longer affecting the state of the regulator. An additional function of MP3 is to turn off after VOUT is high, preventing MN5 from continuously conducting and affecting the state of the regulator when PDN is low.

[0094] In one or more embodiments, the low-power driving circuit (see Figure 4 The main regulation path (error amplifier module + power regulator) is connected in parallel with the error amplifier module and the power regulator (or can be switched via a switch). When under light load or when the downstream load circuit is in sleep mode, the main regulation path (error amplifier module + power regulator) is shut down by the Power Down control module, and the low-power drive circuit is enabled. This circuit also uses a common-gate transistor with a fixed gate bias for overvoltage protection, and its static power consumption is only about 1% of that of a conventional drive circuit (e.g., 100uA for a conventional circuit, 1uA for a low-power circuit), used to maintain VOUT and provide a small load current.

[0095] In one or more embodiments, the Power Down control module further includes at least one common-gate transistor with a fixed gate bias (e.g., Figure 3 (While not directly shown, it is mentioned in the description that it can be connected in series). Specifically, when the high-voltage supply voltage VDDH exceeds a predetermined threshold (e.g., greater than 10V, while the withstand voltage of a single low-voltage switch is 5V), a common-gate transistor with a fixed gate bias is connected in series between the drain and source of the first switch MP4, or a similar common-gate transistor is connected in series between the drain and source of the second switch MN6. These series-connected common-gate transistors further share the voltage in Power Down mode, ensuring that the voltage drop across each device does not exceed its safe withstand voltage. For example, if VDDH = 12V and the low-voltage switch has a withstand voltage of 5V, a four-stage voltage divider can be achieved by connecting two common-gate transistors and two switches in series, with each stage handling approximately 3V.

[0096] In one or more embodiments, the voltage divider clamping network can employ resistor dividers with different resistance ratios to accommodate different gate oxide withstand voltage levels. For example, for a 1.8V low-voltage device, the high potential of the inverter can be clamped below 1.8V; for a 3.3V device, it can be clamped below 3.3V.

[0097] In one or more embodiments, the voltage division value of the bias generation branch in the overvoltage protection module is determined as follows:

[0098] Assuming the high-voltage power supply VDDH = 5V, the maximum allowable gate-source voltage of the low-voltage device VGS_max = 1.8V, and the threshold voltage of the common-gate transistor |Vth| = 0.5V. To ensure the common-gate transistor is in the on-state during normal operation and that the source-drain voltage is safe, the gate bias Vbias_cg is set to VDDH - (VGS_max - margin), for example, Vbias_cg = 3.3V. Vbias_cg is generated from VDDH through the voltage divider formed by the series resistors R1 and R2: R2 / (R1+R2) * VDDH = Vbias_cg. Therefore, R1 / R2 = (VDDH - Vbias_cg) / Vbias_cg.

[0099] In one or more embodiments, the logic for generating the Power Down enable signal PD is as follows:

[0100] This signal is generated by an external digital control unit. When PD=1, a complementary signal PD_N is first generated through an inverter. The gate of MP4 is connected to PD_N (active low), and the gate of MN6 is connected to PD (active high). To ensure that both switches are turned off simultaneously, PD and PD_N must be strictly complementary to avoid brief intermediate states.

[0101] Specifically, a non-overlapping clock generation circuit (not shown) consisting of two inverters connected in series is used to drive MP4 and MN6 to ensure that the two transistors do not conduct simultaneously during switching, thus preventing large current from being drawn through.

[0102] In one or more embodiments, the state detection and control logic in the startup circuit is specifically implemented as follows (see...). Figure 3The circuit uses MP0, MP1, and resistors to form a voltage divider, generating a detection voltage Vdet from Vmid. This Vdet is connected to the input of an inverter (composed of MP2 and MN0). The output of this inverter, after further logic processing, controls the gate of MP3. When VOUT is 0, Vdet is a lower value (e.g., Vmid * (R voltage divider ratio)), and the inverter output is high. The power regulator in this circuit is an NMOS transistor. When VOUT is lower than the start-up threshold (when VOUT is lower than the threshold, the start-up circuit is in operation), the state detection and control logic activates the pull-up path, pulling the gate VG of the power regulator transistor high to near Vmid. This action turns on the NMOS power regulator transistor. Simultaneously, the low-power drive circuit (or another auxiliary charging branch) also contributes to the pull-up of the gate VG of the power regulator transistor, causing VOUT to rise. When VOUT reaches a predetermined value, the error amplifier module 130 operates normally and takes over control, and the start-up circuit is turned off.

[0103] In one or more embodiments, to ensure the synchronization of control signals in Power Down mode and prevent the other device from momentarily bearing the full voltage due to one of MP4 and MN6 turning off first, the Power Down control module employs synchronization logic. Specifically, the PD signal first generates PD_delayed through a delay unit (e.g., two inverters in series). Then, PD and PD_delayed are passed through NAND gates and OR gates respectively to generate non-overlapping PD_P and PD_N control signals. In this way, during the turn-off process, MP4 and MN6 are simultaneously driven to the turn-off state, ensuring the reliability of voltage sharing.

[0104] In addition, if the circuit operates in a multi-power-domain environment, a level converter is added to convert the control signal of the low-voltage domain (such as the PD from the 1.8V digital core) into a level that can drive the high-voltage side switching transistor. At the same time, the voltage of the converted signal is guaranteed not to exceed the gate withstand voltage of the switching transistor through resistor voltage division.

[0105] In one or more embodiments, in response to an abnormal condition in the circuit, such as a transient overvoltage of VDDH exceeding the maximum clamping capability of the overvoltage protection module (e.g., exceeding a predetermined threshold by 1.5 times), the common-gate transistor will enter a deep saturation region, and its drain-source voltage will rise sharply, potentially causing device breakdown. To avoid permanent damage, the circuit may also include a current-limiting resistor (not shown) connected in series at the VDDH input, or an external transient voltage suppressor (TVS). When overcurrent or overvoltage is detected, a global Power Down signal can be triggered, shutting down the entire LDO and sending a fault interrupt to the system controller.

[0106] This circuit achieves the core objective of directly withstanding high-voltage input and outputting a stable low voltage using only low-voltage process devices. Its beneficial effects are:

[0107] ① The common gate overvoltage protection design with fixed gate bias ensures that the voltage of all internal nodes is limited to the safe range of low-voltage devices, completely avoiding the risk of breakdown.

[0108] ②The Power Down dual-ended turn-off design enables the switching transistor to automatically divide the voltage when turned off, eliminating the need for high-voltage components;

[0109] ③ The startup circuit has zero quiescent current after startup and effectively prevents degeneracy.

[0110] ④ It can directly drive any existing low-voltage design, enabling design reuse and significantly reducing costs.

[0111] refer to Figure 5 This diagram illustrates a schematic flowchart of a low-dropout voltage regulator circuit control method based on a low-voltage device adapting to a high-voltage power supply, according to an embodiment of this application. This method is applied to the aforementioned circuit, and is particularly suitable for battery-powered IoT devices or industrial control modules where a stable power supply to a low-voltage core chip is required under high-voltage input.

[0112] In one or more embodiments, the method includes operating S510, whereby the overvoltage protection module of the circuit receives a high-voltage power supply voltage VDDH (e.g., 4.2V) and utilizes multiple gate-fixed biased common-gate transistors (e.g., Figure 2 The common-gate transistors MP0, MP1, MN3, etc., clamp VDDH and output a first intermediate voltage Vmid. Specifically, when VDDH rises, the source potential of MP0 increases, while the gate is fixed at a preset potential Vbias_cg, causing the source-gate voltage of MP0 to increase and limiting its drain voltage Vmid≈Vbias_cg+|Vthp|. This Vmid and the voltages of each node within the circuit do not exceed the safe withstand voltage of low-voltage devices (e.g., 3.3V).

[0113] In one or more embodiments, the method includes operation S520, in which the error amplification module compares a reference voltage Vref (e.g., 1.2V) with a feedback voltage Vfb obtained from the output VOUT through a voltage divider feedback network (e.g., voltage divider R1, R2), and generates an error control signal Vctrl. The voltage range of Vctrl is typically between ground and the power supply voltage (i.e., Vmid) of the error amplification module, but since Vmid may still be higher than the gate voltage limit of the low-voltage device, further processing is required.

[0114] In one or more embodiments, the method includes operation S530, in which a voltage divider clamping network limits the voltage range of an error control signal Vctrl (or a drive signal generated therefrom) within a safe gate voltage range for driving a target MOSFET (such as a power regulator). For example, by... Figure 3 The resistors at the front end of the inverter, which consists of MP2 and MN0, divide the voltage so that the high level of the inverter is only a portion of Vmid (e.g., 3 / 8 Vmid), thereby ensuring that the voltage applied to the gate of the power regulator does not exceed its gate oxide breakdown voltage.

[0115] In one or more embodiments, the method includes operation S540, in which the power regulation transistor adjusts the current from a first intermediate voltage Vmid to the output VOUT based on a limited drive signal (i.e., the voltage on VG). When VOUT is lower than a target value, the error amplification module lowers the VG level (for a PMOS regulation transistor), thereby increasing the on-current and boosting VOUT; conversely, it raises VG, reduces the current, and ultimately stabilizes VOUT. It should be noted that step S540 is also applicable to an NMOS regulation transistor.

[0116] In one or more embodiments, the method further includes performing a Power Down operation S550 in response to a Power Down enable signal (e.g., PD=1 from the system controller). Operation S550 specifically includes simultaneously turning off a first switch MP4 connected in series in the power path and a second switch MN6 connected in series in the ground path, so that the high-voltage power supply voltage Vmid is shared by the first and second switches. In this way, each switch only bears about half the voltage, ensuring it operates in a safe region. If Vmid is higher (e.g., 12V), the Power Down control module may further include series-connected common-gate transistors with fixed gate bias for further multi-stage voltage division.

[0117] In one or more embodiments, the method further includes a startup operation S560. For example... Figure 3 As shown, the operation includes: detecting the voltage at the output terminal VOUT; when VOUT is lower than the start-up threshold (e.g., 0.3V), the gate of the power regulation transistor (NMOS) is pulled high to near Vmid through the pull-up path (MP3 is turned on) by the state detection logic, so that the power regulation transistor (NMOS) is turned on; at the same time, the low-power drive circuit (or another pre-charge circuit) starts to charge the output capacitor, so that VOUT gradually increases; when VOUT reaches a predetermined value (e.g., 90% of the target voltage), the error amplification module can work normally and take over the control. At this time, the state detection logic automatically turns off MP3, the start-up circuit exits, and no longer consumes any static power.

[0118] In one or more embodiments, the method further includes a mode switching operation S570: when the downstream load circuit is in normal operating mode, the error amplification module and the power adjustment tube are enabled as the main regulation path; when the downstream load circuit is in low-power sleep mode, the main regulation path is turned off by the Power Down control module, and a low-power drive circuit with lower static power consumption is enabled to maintain the voltage of the output terminal VOUT (e.g., maintain 1.8V for use by the wake-up circuit).

[0119] In one or more embodiments, the resistor ratio of the voltage divider clamping network in step S530 is designed as follows: Assuming Vmid = 3.6V and the maximum allowable gate-source voltage VGS_max of the low-voltage PMOS transistor is 1.8V, the high level of the drive signal needs to be limited to Vmid + VGS_max. Note: The PMOS transistor only conducts when the gate is lower than the source. For a PMOS transistor with the source connected to Vmid, its gate voltage is allowed to be between Vmid - VGS_max and Vmid. Therefore, there is no need to limit the high level with a voltage divider; instead, it is necessary to limit the low level to not be lower than Vmid - VGS_max. For safety, the gate swing range is usually limited to between Vmid - 1.8V and Vmid. This can be achieved by connecting a source follower or level shifter circuit in series at the output of the error amplifier. For simplification, this application uses a resistor voltage divider to clamp the high level of the control signal at Vmid and the low level at Vmid - 1.8V. Step S530 is also applicable to NMOS regulating transistors.

[0120] In one or more embodiments, two diodes or Zener diodes may be connected in series between VG and ground, but here a resistor divider method is used: two resistors are connected in series between the error amplifier output and ground, the intermediate node is connected to the gate of the regulating transistor, and a gate-fixed biased NMOS common gate transistor is used to clamp the low potential.

[0121] It is important to note that in the S550 Power Down operation, to prevent instantaneous high-voltage surges caused by timing differences between MP4 and MN6 during the turn-off process, the controller employs a non-overlapping clock generation technique. Specifically, the system first reads a status register to confirm that there are no ongoing interrupts or critical transactions; then, it synchronizes the PD signal to the Vmid clock domain via a latch (using a level shifter); next, it generates two complementary control signals, PD_MP4 and PD_MN6, with dead times, to drive MP4 and MN6 respectively. In the actual circuit implementation, the dead time can be generated by an RC delay circuit, ensuring that the other switch only begins to operate after one switch is completely turned off. Although simultaneous turn-off in this circuit does not require a dead time, for robustness, a very short (e.g., 10ns) simultaneous turn-on inhibit region is still set.

[0122] In one or more embodiments, in response to VOUT failing to reach a predetermined value for an extended period (e.g., more than 1 ms) during startup operation S560, the internal counter of the startup circuit times out, triggering an error flag and forcibly pulling the LDO output and the power transistor gate to ground to prevent damage to subsequent circuitry. Simultaneously, this error status can be notified to the system controller via an interrupt pin, allowing the system controller to execute a reset or power-on procedure.

[0123] It should be noted that through the coordinated operation of steps S510 to S570, this control method enables LDOs composed of low-voltage process devices to safely and efficiently convert high-voltage input into stable low-voltage output, with extremely low leakage current and reliable startup in Power Down mode. More importantly, this method can be applied to the high-voltage power domain without modifying any existing common low-voltage designs, greatly expanding the application boundaries of low-voltage processes and reducing system costs.

[0124] In one or more embodiments, this application also provides a computer-readable storage medium having stored thereon computer program instructions (or instruction set). When the instructions are executed by one or more processors (e.g., a microcontroller, DSP, or CPU), the processors perform the aforementioned control method. This storage medium is particularly suitable for integration within a power management chip or for storage as firmware in IoT nodes or industrial controllers.

[0125] The computer-readable storage medium includes non-volatile memory (such as Flash, EEPROM) or volatile memory (such as SRAM). Instructions stored in the storage medium include:

[0126] Overvoltage protection configuration command: used to set the generation parameters of the common gate bias voltage (e.g., configure the voltage division ratio of the resistor voltage divider network) so that the overvoltage protection module 120 can adapt to different VDDH input ranges.

[0127] Error amplification control instructions: used to read the reference voltage and feedback voltage, and calculate the digital equivalent value of the error control signal Vctrl (if a digital LDO architecture is used); in analog LDOs, these instructions may only be used for calibration and adjustment.

[0128] Voltage divider clamping network configuration command: Used to adjust the tap position of the resistor voltage divider network to adapt to different target output voltages;

[0129] Power Down management command: In response to the sleep signal issued by the system, generate dual synchronous shutdown signals PD_MP4 and PD_MN6, and ensure that they meet the non-overlapping timing requirements;

[0130] Startup state machine instructions: Implement startup detection after power-on, pull-up path driving, and exit logic, including setting timer and comparator thresholds;

[0131] Mode switching instruction: Switches between normal operation mode and low power mode according to the load status (obtained by external interrupt or polling), and controls the enable of the main path and low power drive circuit.

[0132] In one or more embodiments, the storage medium further includes instructions for implementing an error handling process. Specifically, in response to reading an LDO output overvoltage or overcurrent flag, the instructions perform the following operations:

[0133] First, immediately set the Power Down control register to forcibly shut down the main circuit;

[0134] Secondly, record the system status (including VDDH, VOUT, temperature, etc.) at the time of the fault to the log storage area;

[0135] Finally, a non-maskable interrupt (NMI) is sent to the host via the system bus, awaiting a recovery command.

[0136] In one or more embodiments, the storage medium also stores a calibration parameter table. For example, due to process variations, the threshold voltage Vth of the common gate transistor may deviate. By executing the calibration program in the storage medium, the trimming bit of the resistor divider network can be automatically adjusted during the chip testing phase so that Vbias_cg falls precisely within the target value range.

[0137] In one or more embodiments, to ensure the atomicity of register configuration in low-power mode, the Power Down management instructions use a "read-modify-write" sequence when modifying the switching transistor control register, and acquire a mutex lock before the operation. Specifically, this includes: reading the current register value; performing a bitwise OR / AND operation between the bit to be modified and the mask; writing back the new value; and releasing the mutex lock. This avoids partial write errors caused by interrupts. Furthermore, write-protected bits are set for critical registers (such as the overvoltage protection threshold register), requiring a specific key to be written before modification, preventing hardware damage caused by software anomalies.

[0138] In one or more embodiments, in response to a timeout during the execution of the startup state machine or the detection of an output short circuit, the error handling instruction performs at least one of the following operations: terminates the current startup sequence, records an error log (stored in a non-volatile area), rolls back the system state to the default state before power-on reset, and outputs a low-level pulse through a dedicated pin to notify the external monitoring circuit.

[0139] It should be noted that the computer-readable storage medium provided in this application enables a general-purpose processor or microcontroller to fully control the aforementioned LDO circuit, achieving automated high-voltage input adaptation, low-voltage output stabilization, and ultra-low power management in sleep mode. This medium greatly simplifies system software design, allowing engineers to deploy low-voltage IP directly in high-voltage scenarios without needing to concern themselves with the underlying high-voltage protection details.

[0140] The specific embodiments described above further illustrate the implementation details of the circuit structure, control method, and storage medium of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0141] The above technical solutions only embody the preferred technical solutions of the present invention. Any modifications that may be made by those skilled in the art to certain parts thereof embody the principles of the present invention and fall within the protection scope of the present invention.

Claims

1. A low-dropout voltage regulator circuit based on low-voltage devices adapted to high-voltage power supplies, characterized in that, include: Reference voltage generation module, used to generate a stable reference voltage; An overvoltage protection module has an input terminal for receiving a high-voltage power supply voltage VDDH. The overvoltage protection module includes at least one common-gate transistor with a fixed gate bias for initially clamping the high-voltage power supply voltage and outputting a first intermediate voltage. The gate of the common-gate transistor is biased at a preset intermediate potential so that the voltage borne by the common-gate transistor and the low-voltage devices in the subsequent circuit does not exceed its safe withstand voltage value. The error amplification module has its first input terminal coupled to the reference voltage generation module to receive the reference voltage, and its second input terminal coupled to the output terminal VOUT of the low dropout voltage regulator circuit or the voltage divider feedback node, which is used to amplify the difference between the two and generate an error control signal. The power regulating transistor has its control terminal coupled to the output terminal of the error amplification module, its input terminal coupled to the output terminal of the overvoltage protection module to receive the first intermediate voltage, and its output terminal serving as the output terminal VOUT of the low-dropout voltage regulator circuit, used to adjust the output current according to the error control signal to stabilize the output voltage. The output capacitor is coupled between the output terminal VOUT of the low-dropout voltage regulator circuit and ground. Also includes: A voltage divider clamping network is coupled between the output terminal of the error amplification module and the control terminal of the power adjustment transistor, or coupled to an internal node of the error amplification module, for limiting the voltage range of the error control signal or the drive signal generated therefrom to the safe gate voltage range of the target MOS transistor. It also includes a Power Down control module, which comprises: The first switching transistor is connected in series between the output terminal of the overvoltage protection module and the power supply terminal of the error amplification module; The second switching transistor is connected in series between the ground terminal of the error amplifier module and the system ground; In response to the Power Down enable signal, the first switch and the second switch are configured to be turned off simultaneously, so that the high voltage power supply voltage is divided by the first switch and the second switch, ensuring that the voltage each of them withstands is within its safe withstand voltage range.

2. The circuit according to claim 1, characterized in that, The Power Down control module also includes at least one common-gate transistor with a fixed gate bias, which is connected in series with the first switch and / or the second switch to provide further voltage division when the high-voltage power supply voltage exceeds a predetermined threshold, thereby expanding the power supply voltage range that the circuit can withstand.

3. The circuit according to claim 1, characterized in that, It also includes a startup circuit, the startup circuit comprising: The pull-up path has one end coupled to the control terminal of the power regulator and the other end coupled to the input terminal of the power regulator or the high voltage power supply voltage. The state detection and control logic has its input terminal coupled to the output terminal VOUT of the low dropout voltage regulator circuit, and its output terminal coupled to the control terminal of the pull-up path. Specifically, when the voltage at the output terminal VOUT of the low-dropout voltage regulator circuit is lower than the startup threshold, the state detection and control logic turns on the pull-up path, pulls up the control terminal of the power adjustment transistor, thereby increasing the voltage at the output terminal VOUT of the low-dropout voltage regulator circuit; when the voltage at the output terminal VOUT reaches a predetermined value, the state detection and control logic turns off the pull-up path, disconnecting the startup circuit from the main circuit topology, thus preventing additional static power consumption.

4. The circuit according to claim 1, characterized in that, It also includes a low-power drive circuit, which is connected in parallel or switchably with the error amplification module and the power adjustment transistor to provide sustained power to the output terminal VOUT in light load or sleep mode, and its static power consumption is much lower than that of the error amplification module.

5. A control method for a low-dropout voltage regulator circuit based on low-voltage devices adapted to a high-voltage power supply, the method being applied to the circuit as described in any one of claims 1 to 4, characterized in that, Includes the following steps: A. The overvoltage protection module receives the high voltage VDDH and uses a common gate transistor with fixed gate bias to clamp the high voltage to a first intermediate voltage. The first intermediate voltage and the voltage of each node inside the circuit do not exceed the safe withstand voltage value of the low voltage device. B. The error control signal is generated by comparing the reference voltage and the feedback signal characterizing the output voltage through the error amplification module. C. The voltage range of the error control signal is limited to a safe range by the voltage divider clamping network, and the power regulation transistor is driven. D. The power regulating transistor adjusts the current from the first intermediate voltage to the output terminal VOUT of the low-dropout voltage regulator circuit according to the limited error control signal, so as to stabilize the output voltage.

6. The method according to claim 5, characterized in that, It also includes the steps of performing a Power Down operation in response to a Power Down enable signal: At the same time, the first switch connected in series in the power supply path and the second switch connected in series in the ground path are turned off, so that the high voltage power supply voltage is shared by the first switch and the second switch.

7. The method according to claim 5, characterized in that, It also includes mode switching steps: When the downstream load circuit is in normal operating mode, the error amplifier module and power regulator are used as the main regulation path. When the downstream load circuit is in low-power sleep mode, the main regulation path is turned off, and the low-power drive circuit with lower static power consumption is enabled to maintain the voltage at the output terminal VOUT of the low-dropout regulator circuit.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed, it can perform the steps of the method as described in any one of claims 5 to 7.

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