Semiconductor structure and method of manufacturing the same, electronic device

Abstract

The present disclosure provides a semiconductor structure, a manufacturing method thereof, and an electronic device. The manufacturing method of the semiconductor structure comprises: alternately performing a first step and a second step on a substrate to form a stack structure; wherein the first step comprises epitaxially growing a sacrificial layer on the substrate or a gate layer, and the second step comprises epitaxially growing the gate layer on the sacrificial layer; forming a channel hole through the stack structure; forming a gate isolation groove through the stack structure; removing the sacrificial layer based on the gate isolation groove, and forming an interlayer insulating layer in the space where the sacrificial layer is removed; after forming the interlayer insulating layer, laterally etching the plurality of gate layers from the channel hole to form a plurality of side cavities; and performing an oxidation treatment on the gate layer from the channel hole to form a barrier layer in the side cavity. The epitaxially grown gate layer and the sacrificial layer can improve the etching process of the channel hole to improve the channel hole morphology; and the barrier layer obtained by oxidizing the gate layer is conducive to reducing the leakage current of the storage unit.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and its manufacturing method, and an electronic device. Background Technology

[0002] In recent years, with the rapid development of artificial intelligence and big data, higher demands have been placed on the storage density and performance of memory. Traditional two-dimensional (2D) memory mainly improves storage density by reducing feature size. However, as process nodes approach physical limits, this approach faces numerous bottlenecks and continuously rising manufacturing costs. To overcome this predicament, three-dimensional (3D) memory has emerged. By vertically stacking memory cells, it significantly improves storage density and data transfer efficiency within a limited chip area, thus meeting the urgent needs for storage capacity and bandwidth in high-performance computing scenarios. 3D floating-gate NAND memory is an important type of 3D memory and has been widely used in consumer and enterprise storage fields. How to continuously improve storage density while balancing process feasibility and device performance remains one of the key technological challenges facing the industry. Summary of the Invention

[0003] This disclosure provides a semiconductor structure, a method for manufacturing the same, and an electronic device.

[0004] Some embodiments of this disclosure provide a method for manufacturing a semiconductor structure, the method comprising: A first step and a second step are performed alternately on a substrate to form a stacked structure; wherein the first step includes epitaxially growing a sacrificial layer on the substrate or on a gate layer, and the second step includes epitaxially growing a gate layer on the sacrificial layer; Forming channel holes through the stacked structure; A gate isolation trench is formed that extends through the stacked structure; The sacrificial layer is removed based on the gate isolation trench, and an interlayer insulating layer is formed in the space where the sacrificial layer is removed; After the interlayer insulating layer is formed, multiple gate layers are laterally etched from the channel via to form multiple side cavities; The gate layer is oxidized from within the channel hole to form a barrier layer within the side cavity.

[0005] Some embodiments of this disclosure provide a semiconductor structure, including: A stacked structure comprising an epitaxially grown gate layer and an interlayer insulating layer alternately stacked in a vertical direction; A channel structure extends through the stacked structure along the vertical direction; wherein the channel structure includes a barrier layer, the material of which includes an oxide obtained by oxidizing the gate layer; A gate isolation structure is located in and extends through the stacked structure.

[0006] This disclosure also provides an electronic device, including: Host; A memory system, coupled to the host, comprising: A memory controller and at least one memory coupled to the memory controller, the memory comprising a semiconductor structure as described in any of the preceding claims.

[0007] The semiconductor structure manufacturing method provided in this disclosure involves epitaxially growing a sacrificial layer and a gate layer in the first and second steps, respectively. This epitaxial growth provides a gate layer and a sacrificial layer with good vertical uniformity and few defects. Furthermore, the low interface defect rate between the gate layer and the sacrificial layer suppresses lateral etching of the channel hole sidewalls, resulting in better anisotropic etching characteristics. This improves the vertical morphology of the channel hole and controls the sidewall morphology, leading to smoother sidewalls and smaller taper in the channel hole. This alleviates the layer limit on the stacked structure and facilitates the development of three-dimensional NAND memories towards higher layer counts and higher densities. Moreover, the epitaxially grown gate layer has a single-crystal structure, and the barrier layer obtained by oxidizing the gate layer is uniform, dense, and has few defects. This improves the electrical characteristics of the memory cell including the gate layer and barrier layer, such as lower leakage current and higher breakdown field strength, thereby enhancing the reliability of the memory cell. Attached Figure Description

[0008] Figure 1 A schematic flowchart illustrating a method for manufacturing a semiconductor structure according to an embodiment of this disclosure; Figure 2 A schematic diagram of the stacking structure provided in the embodiments of this disclosure; Figure 3a A schematic diagram of the formation of a channel hole provided in an embodiment of this disclosure; Figure 3b This is a top view of the stacked structure after the formation of the channel holes provided in an embodiment of the present disclosure; Figure 4 This is a schematic diagram of a support structure formed within a channel hole, provided by an embodiment of this disclosure; Figure 5a This is a schematic diagram of the formation of a gate isolation trench provided in an embodiment of this disclosure; Figure 5b This is a top view of the stacked structure after forming the gate isolation trench provided in an embodiment of the present disclosure; Figure 6A schematic diagram of the removal of the sacrificial layer provided in an embodiment of this disclosure; Figure 7 This is a schematic diagram of the formation of an interlayer insulating layer provided in an embodiment of the present disclosure; Figure 8 A schematic diagram of the release channel hole provided in an embodiment of this disclosure; Figure 9 This is a schematic diagram of the formation of the side cavity and the barrier layer provided in an embodiment of the present disclosure; Figure 10 This is a schematic diagram of the formation of a first intermediate material layer provided in an embodiment of the present disclosure; Figure 11 A schematic diagram illustrating the formation of a temporary protective layer provided in an embodiment of this disclosure; Figure 12 A schematic diagram illustrating the formation of a first intermediate layer and the removal of a temporary protective layer provided in an embodiment of this disclosure; Figure 13 A schematic diagram of the formation of the second intermediate layer provided in an embodiment of this disclosure; Figure 14 This is a schematic diagram of the formation of a floating gate layer provided in an embodiment of the present disclosure; Figure 15 This is a schematic diagram of the formation of a tunneling layer provided in an embodiment of the present disclosure; Figure 16 A schematic diagram of removing the barrier layer and the second intermediate layer at the bottom of the channel hole, provided for an embodiment of this disclosure; Figure 17 This is a schematic diagram of the formation of a channel layer provided in an embodiment of the present disclosure; Figure 18 This is a schematic diagram of the formation of a filling layer provided in an embodiment of the present disclosure; Figure 19 This is a schematic diagram of the formation of a groove provided in an embodiment of the present disclosure; Figure 20 A schematic diagram of forming a contact plug provided in an embodiment of this disclosure; Figure 21 A schematic diagram of a semiconductor structure provided in an embodiment of this disclosure; Figure 22 for Figure 21 A magnified schematic diagram of a local B region of the provided semiconductor structure; Figure 23 A schematic diagram of a memory provided for an embodiment of this disclosure; Figure 24 A schematic diagram of a memory system provided in an embodiment of this disclosure. Detailed Implementation

[0009] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0010] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0011] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0012] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0013] Spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0014] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0015] To fully understand this disclosure, detailed steps and structures will be presented in the following description to illustrate the technical solutions of this disclosure. Preferred embodiments of this disclosure are described in detail below; however, other embodiments may also be implemented in addition to these detailed descriptions.

[0016] This disclosure can be applied to various three-dimensional (3D) non-volatile memory (NVM) devices, such as NAND flash memory, NOR flash memory, resistive random-access memory (RRAM), phase-change memory (PCM) such as phase-change random-access memory (PCRAM), spin-transfer torque (STT)-magnetoresistive random-access memory (MRAM), and others. It can also be applied to charge-trapping based memory devices and floating-gate based memory devices. Furthermore, it can be applied to various memory types, such as SLC (single-level cell) devices, MLC (multi-level cell) devices, TLC (three-level cell) devices, QLC (four-level cell) devices, or PLC (five-level cell) devices, as well as various types of devices and systems, such as secure digital cards (SD cards), embedded multimedia cards (eMMC), or solid-state drives (SSDs), embedded systems, and others.

[0017] For example, in the fabrication process of 3D NAND flash memory, the stacked structure typically employs alternating layers of silicon oxide and polysilicon (OPOP stack). Due to the non-homogeneity of silicon oxide and polysilicon, the channel vias in the stacked structure generally have a large taper, meaning the diameter of the channel via is large at the top and small at the bottom, forming an inverted cone shape that is wider at the top and narrower at the bottom. This large taper affects the consistency of memory cell performance in the vertical direction. One way to improve the taper is to reduce the number of layers in the stacked structure, but this precisely limits the development of 3D NAND flash memory towards higher layers and higher densities.

[0018] In view of this, embodiments of the present disclosure provide a method for manufacturing a semiconductor structure to increase the number of stacked layers in a three-dimensional NAND memory. Figure 1 A schematic flowchart of a method for manufacturing a semiconductor structure according to an embodiment of this disclosure is provided. See also: Figure 1 The method for manufacturing this semiconductor structure includes: S100: The first step and the second step are performed alternately on the substrate to form a stacked structure; wherein the first step includes epitaxially growing a sacrificial layer on the substrate or on the gate layer, and the second step includes epitaxially growing a gate layer on the sacrificial layer. S200: Forms a channel hole through the stacked structure; S300: Forms a gate isolation trench that penetrates the stacked structure; S400: The sacrificial layer is removed based on the gate isolation trench, and an interlayer insulating layer is formed in the space where the sacrificial layer is removed; S500: After forming the interlayer insulating layer, multiple gate layers are laterally etched from the channel via to form multiple side cavities; S600: The gate layer is oxidized from inside the channel hole to form a barrier layer in the side cavity.

[0019] The semiconductor structure manufacturing method provided in this disclosure involves epitaxially growing a sacrificial layer and a gate layer in the first and second steps, respectively. This epitaxial growth provides a gate layer and a sacrificial layer with good vertical uniformity and few defects. Furthermore, the low number of defects at the interface between the gate layer and the sacrificial layer suppresses lateral etching of the channel hole sidewalls, resulting in better anisotropy during etching. This helps reduce the vertical taper of the channel hole, and the controlled sidewall morphology facilitates obtaining channel holes with smoother sidewalls and smaller tapers. This alleviates the layer limit on the stacked structure and helps 3D NAND memories develop towards higher layer counts and higher densities. Moreover, the epitaxially grown gate layer has a single-crystal structure, and the barrier layer obtained by oxidizing the gate layer is uniform, dense, and has few defects. This improves the electrical characteristics of the memory cell including the gate layer and the barrier layer, such as lower leakage current and higher breakdown field strength, thereby improving the reliability of the memory cell.

[0020] Figures 2 to 20 This is a schematic diagram of a semiconductor structure during the manufacturing process provided by an embodiment of this disclosure. The following is in conjunction with... Figure 1 , Figures 2 to 20 The method for manufacturing a semiconductor structure provided in the embodiments of this disclosure is described in detail.

[0021] See Figure 2 Step S100 is performed to epitaxially grow a stacked structure of alternating gate layer 210 and sacrificial layer 220 on substrate 100.

[0022] For example, the substrate 100 may be composed of one or more of silicon (Si), germanium (Ge), silicon-germanium (SiGe), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable semiconductor material.

[0023] Epitaxial growth refers to the process of growing a single-crystal thin film on a single-crystal substrate with the same or similar crystal orientation as the substrate. A single-crystal gate layer 210 can be obtained through epitaxial growth. For example, the material of the gate layer 210 includes single-crystal silicon.

[0024] The sacrificial layer 220 can be used as a single-crystal substrate for the epitaxial growth of the gate layer 210. The sacrificial layer 220 can be selected from materials with the same lattice structure and a close lattice constant as the gate layer 210. For example, the material of the sacrificial layer 220 includes one of silicon germanium, silicon germanium tin, silicon germanium carbon, silicon germanium carbon tin, etc.

[0025] It should be noted that since germanium and tin have larger atomic radii than silicon, the lattice constant of germanium-silicon and germanium-silicon-tin layers increases with increasing germanium and tin content. Excessive germanium and tin content can lead to a severe mismatch in the lattice constants of the sacrificial layer 220 and the gate layer 210, introducing excessive dislocation defects. Therefore, it is necessary to control the germanium, tin, and carbon content in the sacrificial layer to match the lattice constants of the sacrificial layer 220 and the gate layer 210, thereby ensuring a high-quality gate layer 210.

[0026] In some embodiments, when the sacrificial layer 220 is made of silicon-germanium or silicon-germanium-tin, the silicon content is controlled between 75 mol% and 85 mol%. (The text abruptly ends here, so the translation stops as well.) For example, the germanium content is 15 mol% to 25 mol%, meaning the value of X ranges from 0.15 to 0.25, such as 0.15, 0.18, 0.20, 0.22, 0.25, etc. In one specific embodiment, the material of the sacrificial layer 220 is, for example, , , , and, Taking silicon, germanium, and tin as an example, the total content of germanium and tin is 15 mol% to 25 mol%.

[0027] When the silicon content is within the above range, on the one hand, the lattice constants of the sacrificial layer and the gate layer can be better matched to ensure that a single crystal gate layer is obtained; on the other hand, the chemical composition of the sacrificial layer and the gate layer is different to achieve a specific large etching selectivity, so that the sacrificial layer or the gate layer can be etched separately in subsequent steps.

[0028] For example, the epitaxial growth processes of the gate layer and the sacrificial layer include, but are not limited to, chemical vapor deposition (e.g., reduced pressure chemical vapor deposition (RPCVD)) and molecular beam epitaxy (MBE) processes.

[0029] Taking a gate layer 210 comprising monocrystalline silicon and a sacrificial layer 220 comprising silicon-germanium as an example, the process of forming a stacked structure is as follows: The substrate 100 is placed in the reaction chamber of an epitaxial device (e.g., an RPCVD device), and silicon source gas and germanium source gas are introduced into the substrate surface to grow a first sacrificial layer 220. Then, the introduction of germanium source gas is stopped, while silicon source gas is continued, to grow a first gate layer 210 on the surface of the first sacrificial layer 220. Next, germanium source gas is introduced again, while silicon source gas is continued, to grow a second sacrificial layer 220 on the surface of the first gate layer 210, and so on, thereby obtaining a stacked structure in which gate layer 210 and sacrificial layer 220 are alternately stacked. For example, the germanium source gas includes, but is not limited to, germane (…). Germanium tetrachloride ( ), etc., silicon source gases include but are not limited to silanes ( ), dichlorosilane, ethylsilane ( )wait.

[0030] For example, the total number of gate layer 210 and sacrificial layer 220 in the stacked structure is greater than 100. In a specific embodiment, the total number of layers in the stacked structure can exceed 200. In related technologies, when the stacked structure uses silicon oxide and polysilicon stacks, the number of stacked layers is usually less than 100 (e.g., 80 layers), and the taper of the channel via increases significantly when the number of layers exceeds 100. In this embodiment, however, the epitaxially grown gate layer and sacrificial layer allow the number of layers in the stacked structure to be increased to 200, breaking the stacking layer limit of three-dimensional NAND memory and facilitating the improvement of its storage density.

[0031] For example, the thickness of the gate layer 210 can be from 20 nm to 40 nm, such as 20 nm, 25 nm, 30 nm, 35 nm, or 40 nm. For example, the thickness of the sacrificial layer 220 can be from 20 nm to 40 nm, such as 20 nm, 25 nm, 30 nm, 35 nm, or 40 nm. For example, the thickness of the gate layer 210 is greater than the thickness of the sacrificial layer 220.

[0032] In some embodiments, the gate layer 210 is made of monocrystalline silicon and N-type doped atoms. N-type doped atoms include, but are not limited to, phosphorus (P), arsenic (As), etc. For example, the concentration of N-type doped atoms is high, typically heavily doped, to give the gate layer a low resistance.

[0033] For example, the epitaxial growth of the gate layer 210 on the sacrificial layer 220 in step S100 includes: simultaneously introducing silicon source gas and N-type dopant source gas into the sacrificial layer 220 to deposit doped single-crystal silicon, which is then used as the gate layer 210.

[0034] Phosphorus source gases include, but are not limited to, phosphine ( Arsenic source gases include, but are not limited to, arsine ( Taking phosphorus-doped single-crystal silicon as an example, in the second step, the germanium source gas is stopped, while the silicon source gas and phosphorus source gas are continuously introduced. At a higher temperature, the silicon and phosphorus source gases undergo a thermal decomposition reaction, directly depositing phosphorus-doped single-crystal silicon. In-situ doping technology can improve the uniformity and controllability of doping, enhance the consistency of the gate layer composition in the vertical direction, and thus improve the consistency of storage performance in the vertical direction.

[0035] Besides in-situ doping techniques, other methods can be used to dope single-crystal silicon. In some embodiments, the manufacturing method further includes doping the gate layer 210 with N-type dopant atoms based on the gate isolation trench.

[0036] Specifically, in step S100, single-crystal silicon is epitaxially grown. After the subsequent formation of the gate isolation trench 420 and / or channel via 410, N-type dopant atoms are doped into the single-crystal silicon through the gate isolation trench 420 and / or channel via 410 using a thermal diffusion method. There are various options for the doping timing; in one embodiment, it can be... Figure 6 After the step "Removing the sacrificial layer based on the gate isolation trench 420" shown, N-type dopant source gas is introduced between the gate isolation trench 420 and the adjacent gate layers 210 in the vertical Z direction to uniformly dope the multiple gate layers 210. Furthermore, since the N-type dopant source gas can dope the gate layers simultaneously in both the horizontal and vertical directions, the doping efficiency is relatively high.

[0037] In another embodiment, the gate layer can be doped after the barrier layer is formed. It is understood that the barrier layer is obtained by oxidizing the gate layer. Doping the gate layer after its formation reduces the number of dopant atoms within the barrier layer, improving its isolation and blocking properties, thereby reducing leakage current and increasing the breakdown field strength.

[0038] It should be noted that this disclosure allows the gate layer to be doped at any suitable time after the barrier layer is formed. For example, the gate isolation trench can be reopened for doping after the channel layer is formed, i.e. after the channel structure is fully formed.

[0039] See Figure 3a and Figure 3b , Figure 3a yes Figure 3b According to the cross-sectional diagram along AA′, step S200 is performed to form a channel hole through the stacked structure.

[0040] For example, a first protective dielectric layer 310 and a second protective dielectric layer 320 are sequentially formed on the uppermost gate layer 210 (or the uppermost sacrificial layer 220). A first mask layer and a first photoresist layer are sequentially formed on the second protective dielectric layer 320; exposure and development steps are performed to obtain a patterned first photoresist layer; the first mask layer is etched based on the patterned first photoresist layer to obtain a patterned first mask layer, and then the first photoresist layer is removed; the second protective dielectric layer 320, the first protective dielectric layer 310, the sacrificial layer 220, and the gate layer 210 are sequentially etched based on the patterned first mask layer, thereby forming a plurality of channel vias 410 in the stacked structure. For example, the channel vias 410 may penetrate the stacked structure in the vertical direction Z and extend into the substrate 100, or the channel vias 410 may penetrate each gate layer 210 in the stacked structure but not extend into the substrate 100. Then, the first mask layer is removed to expose the top surface of the second protective dielectric layer 320.

[0041] For example, the etching process for forming the channel via 410 includes dry etching. For example, when the material of the gate layer 210 includes monocrystalline silicon and the material of the sacrificial layer 220 includes silicon-germanium, the following can be used: , and A mixed gas is used to dry etch the stacked structure to obtain channel holes 410 with small taper and flat sidewalls. Since single-crystal silicon and silicon-germanium are both materials composed of elements of the IVA, they have similar chemical properties, and the epitaxially grown single-crystal silicon and silicon-germanium have the same crystal lattice structure. Therefore, dry etching exhibits significant anisotropy, which effectively improves the aspect ratio, taper, sidewall flatness, and uniformity of the channel holes.

[0042] For example, the first protective dielectric layer 310 is made of silicon oxide, and the second protective dielectric layer 320 is made of silicon nitride.

[0043] See Figure 3b Multiple channel holes 410 are arranged in an array along intersecting first horizontal directions (e.g., the X direction) and second horizontal directions (e.g., the Y direction). This disclosure does not impose excessive restrictions on the array configuration of the channel holes 410, such as... Figure 3b As shown, the plurality of channel holes 410 can be arranged in a rectangular array. In other embodiments, the plurality of channel holes 410 can be arranged in a hexagonal array.

[0044] See Figure 4 Before forming the gate isolation trench, a support structure 340 is formed within the channel via 410. For example, the support structure 340 includes a support body 341 and a stop layer 342 surrounding the support body 341. The material of the support body 341 is, for example, polysilicon, and the material of the stop layer 342 is, for example, silicon nitride.

[0045] For example, the fabrication process of the support structure 340 is as follows: a stop material is deposited within the channel hole 410, and a support body material is deposited on the surface of the stop material until the channel hole 410 is filled; a planarization process is performed, retaining only the stop material and the support body material within the channel hole 410, resulting in a stop layer 342 and a support body 341. For example, the planarization process includes, but is not limited to, chemical mechanical polishing (CMP).

[0046] See Figure 5a and Figure 5b , Figure 5a yes Figure 5b In the cross-sectional view along AA′, step S300 is performed to form a gate isolation trench 420 that penetrates the stacked structure. Multiple gate isolation trenches 420 are arranged along a first horizontal direction X, and each gate isolation trench 420 extends along a second horizontal direction Y. The multiple gate isolation trenches 420 divide the stacked structure into multiple sub-stacked structures arranged along the first horizontal direction X. Figure 5b A partial top view of one of the sub-stack structures is shown. Each sub-stack structure has several channel holes 410 formed within it, and the memory cells formed by the channel holes in each sub-stack structure constitute a memory block. A memory block can be the smallest unit of an erase operation.

[0047] For example, the formation process of the gate isolation trench 420 is as follows: a second mask layer and a second photoresist layer are sequentially formed on the second protective dielectric layer 320; exposure and development steps are performed to obtain a patterned second photoresist layer; the second mask layer is etched based on the patterned second photoresist layer to obtain a patterned second mask layer, and then the second photoresist layer is removed; based on the patterned second mask layer, the second protective dielectric layer 320, the first protective dielectric layer 310, the sacrificial layer 220, and the gate layer 210 are sequentially etched to form a plurality of gate isolation trenches 420 in the stacked structure, the gate isolation trenches 420 penetrating the stacked structure and extending into the substrate 100. Afterwards, the second mask layer is removed. For example, the etching process for forming the gate isolation trench 420 includes dry etching.

[0048] See Figure 6 In step S400, the sacrificial layer 220 is removed by an isotropic etching process through the gate isolation trench 420.

[0049] In some embodiments, the stacked structure includes a core region and a stepped region surrounding the core region. Multiple vias 410 are located in the core region, and multiple gate plugs for leading out each gate layer are located in the stepped region. In this embodiment, the sacrificial layer 220 in the core region is removed at least by the gate isolation trench 420. Isotropic etching processes include wet etching or chemical dry etching. Taking wet etching as an example, after the etching solution enters the gate isolation trench 420, it etches each sacrificial layer 220 laterally. After removing each sacrificial layer 220 in the core region, etching is stopped. Within the core region, the stop layer 342 of the support structure 340 in the vias 410 has a large etching selectivity ratio with the sacrificial layer 220, so the support structure 340 is essentially not etched. The support structure 340 can support the stacked structure in the core region, preventing the stacked structure from collapsing after the sacrificial layer 220 is removed.

[0050] See Figure 7 An interlayer insulating layer 230 is deposited in the space formed by the gate isolation trench 420 after the sacrificial layer 220 is removed, and a gate isolation structure 360 ​​is formed in the gate isolation trench 420.

[0051] For example, the fabrication process of the interlayer insulating layer 230 and the gate isolation structure 360 ​​is as follows: Interlayer insulating material is deposited through the gate isolation trench 420 into the space between adjacent gate layers 210 in the vertical Z direction until the space between adjacent gate layers 210 is filled. Simultaneously, interlayer insulating material is also deposited within the gate isolation trench 420 and on the top surface of the second protective dielectric layer 320. Next, the interlayer insulating material within the gate isolation trench 420 and on the top surface of the second protective dielectric layer 320 is etched away, leaving only the interlayer insulating material between adjacent gate layers 210 to form the interlayer insulating layer 230. Gate isolation material is deposited within the gate isolation trench 420 until the gate isolation trench 420 is filled. Simultaneously, the gate isolation material is also located on the top surface of the second protective dielectric layer 320. Next, a planarization process is performed to remove the gate isolation material on the top surface of the second protective dielectric layer 320, leaving only the gate isolation material within the gate isolation trench 420, thus obtaining the gate isolation structure 360.

[0052] At this point, the stacked structure includes gate layers 210 and interlayer insulating layers 230 alternately stacked along the vertical direction Z, with the interlayer insulating layer 230 used to isolate the gate layers 210. For example, the material of the interlayer insulating layer 230 includes, but is not limited to, silicon oxide, silicon oxynitride, silicon nitride, and low-k dielectrics. The material of the gate isolation structure 360 ​​includes, but is not limited to, silicon oxide, silicon oxynitride, silicon nitride, and low-k dielectrics. In this embodiment, the material of the interlayer insulating layer 230 and the material of the gate isolation structure 360 ​​are both silicon oxide.

[0053] In addition to being composed entirely of gate isolation material, the gate isolation structure 360 ​​may also include an insulating layer and a conductive layer (not shown in the figure) located within the insulating layer in some other embodiments. Exemplarily, an insulating layer is formed by depositing interlayer insulating material through a gate isolation trench 420 into the space between adjacent gate layers 210 in the vertical Z direction. The insulating layer is located on the surface of the gate isolation trench 420 and is electrically isolated from the gate layers in the stacked layers. Next, a conductive layer, such as polysilicon, is deposited on the insulating layer to form a conductive layer that penetrates the stacked layers and connects to the source layer described later, serving as a lead-out contact of the source layer.

[0054] See Figure 6 and Figure 8 After the interlayer insulation layer 230 is formed, the support structure 340 is removed to release the channel hole 410.

[0055] For example, the process of removing the support structure 340 is as follows: dry etching of the support body 341 to remove at least a portion of the support body 341; then, wet etching to remove the remaining support body 341 and stop layer 342, completely releasing the channel via 410. It should be noted that in this embodiment, since the second protective dielectric layer 320 and the stop layer 342 are made of the same material, the second protective dielectric layer 320 is etched and thinned, causing the top surface of the gate isolation structure 360 ​​to be higher than the top surface of the second protective dielectric layer 320.

[0056] Figures 9 to 17 The process of fabricating a channel structure within a channel aperture 410 is illustrated. The channel structure includes a channel layer and multiple storage structures, with the channel layer extending vertically through a stacked structure and each storage structure surrounding the channel layer. For example, the storage structure includes a tunneling layer, a floating gate layer, and a barrier layer stacked sequentially outward from the channel layer in a horizontal direction.

[0057] See Figure 9 In step S500, multiple gate layers 210 are laterally etched within the channel holes 410 to form multiple side cavities 440. The lateral etching process includes wet etching, etc. Taking wet etching as an example, the etching solution enters each channel hole 410 and uniformly etches the gate layers 210 along the horizontal direction, forming multiple annular side cavities 440 spaced Z-spaced vertically. The outer contour of the annular side cavities 440 is similar in shape to the outer contour of the channel holes 410. For example, in this embodiment, both the outer contours of the annular side cavities 440 and the channel holes 410 are circular. The annular side cavities 440 formed based on adjacent channel holes 410 are isolated from each other along the horizontal direction.

[0058] See also Figure 9In step 600, the gate layer 210 is oxidized in situ from within the channel via 410. The side surface of the gate layer 210 exposed within the side cavity 440 is oxidized to form an insulating oxide layer 510. The barrier layer 510 is located within the side cavity 440 and surrounds the outer contour of the side cavity 440, without completely filling the side cavity 440.

[0059] In-situ oxidation processes include, but are not limited to, in-situ steam generation (ISSG), rapid thermal oxidation, and PECVD (Plasma-Enhanced Chemical Vapor Deposition) in-situ oxidation. Taking the gate layer 210 as an example, where the material is single-crystal silicon and ISSG oxidation is employed, the semiconductor structure is placed into the reaction chamber, and hydrogen gas is introduced into the reaction chamber. ) and oxygen ( A mixed gas is heated to heat the semiconductor structure. The gate layer 210 is exposed near the side surface of the side cavity 440 and undergoes a catalytic reaction, generating water vapor and atomic oxygen in situ. The atomic oxygen reacts with the single crystal silicon to form high-quality silicon oxide. The thickness of the silicon oxide can be precisely controlled by adjusting the gas pressure or changing the H2 concentration.

[0060] The barrier layer 510 is used to prevent the charge stored in the floating gate layer from leaking to the gate layer, thereby ensuring long-term data retention. Vacancies and defects within the barrier layer can become conductive channels, generating leakage current. In this embodiment, because the silicon oxide generated by in-situ oxidation of single-crystal silicon has good uniformity, high density, and very few defects, there are very few conductive channels, resulting in extremely low leakage current. This is beneficial for improving data retention and effectively enhancing the intrinsic electrical characteristics of the three-dimensional floating gate NAND memory cell.

[0061] In addition, such as Figure 9 As shown, in the in-situ oxidation process, the portion of the substrate 100 exposed inside the channel hole 410 is oxidized to form an oxide layer.

[0062] In some embodiments, the manufacturing method further includes forming a first intermediate layer on the surface of the barrier layer and the surface of the interlayer insulating layer within the side cavity before forming the floating gate layer.

[0063] Figures 10 to 12 The process of forming the first intermediate layer is illustrated. See [link to documentation] for details. Figure 10A first intermediate material layer 521 is deposited on the sidewalls and bottom of the channel hole 410, the surface of each side cavity 440, and the top surface of the second protective dielectric layer 320. The first intermediate material layer 521 is in contact with the barrier layer 510 within the side cavity 440 and does not completely fill the side cavity 440. For example, the deposition process of the first intermediate material layer 521 includes, but is not limited to, various chemical vapor deposition (CVD) and atomic layer deposition (ALD) processes. In this embodiment, a first intermediate material layer 521 in thin film form is deposited using plasma-enhanced chemical vapor deposition (PECVD).

[0064] See Figure 11 A temporary protective layer 370 is deposited on the surface of the first intermediate material layer 521, filling the remaining space of the side cavity 440. For example, the fabrication process of the temporary protective layer 370 is as follows: a temporary protective material is deposited to fill the side cavity 440, at which point the temporary protective material is still located within the channel hole 410 and on the top surface of the second protective dielectric layer 320. Next, the temporary protective material on the sidewalls of the channel hole 410 and the second protective dielectric layer 320 is removed using dry etching. The temporary protective material within the side cavity 440 is retained to obtain the temporary protective layer 370, which is used to protect the first intermediate material layer 521 within the side cavity 440 in subsequent processes, preventing it from being etched. Furthermore, as... Figure 11 As shown, during dry etching, some temporary material at the bottom of the channel hole 410 is partially blocked by the interlayer insulating layer 230, resulting in some residue.

[0065] For example, the temporary protective layer 370 is made of a material that has a large etch selectivity ratio with the first intermediate material layer 521. In this embodiment, the material of the temporary protective layer 370 includes polysilicon.

[0066] See Figure 12 The first intermediate material layer on the sidewall of the channel hole 410 is removed, exposing the interlayer insulating layer 230. The first intermediate material layer within the side cavity 440 is retained, resulting in a first intermediate layer 520. For example, wet etching is used to etch the first intermediate material layer until the first intermediate material layer on the sidewall of the channel hole 410 is removed, at which point the etching is stopped. Furthermore, during the etching process, the first intermediate material layer located on the top surface of the second protective dielectric layer 320 and the gate isolation structure 360 ​​is removed, as is the first intermediate material layer at the bottom of the channel hole 410 that is not covered by the remaining temporary protective layer 370.

[0067] During the etching process, the first intermediate material layer in the side cavity 440 is covered by the temporary protective layer 370, so it is retained to form the first intermediate layer 520. The first intermediate layer 520 comprises a side wall, a first bottom wall and a second bottom wall, wherein the side wall is in contact with the barrier layer 510, the first bottom wall and the second bottom wall are located at two opposite ends of the side wall along the vertical direction Z, extend toward the center of the channel hole 410 along the horizontal direction, and the first bottom wall and the second bottom wall are respectively in contact with two interlayer dielectric layers 230 adjacent in the vertical direction. As Figure 12 shown, the longitudinal cross-section shape of the first intermediate layer 520 is two "匚"-shapes with opposite openings.

[0068] By way of example, the material of the first intermediate layer 520 comprises at least one of silicon nitride and silicon oxynitride.

[0069] After forming the first intermediate layer 520, the temporary protective layer 370 is removed. At the same time, the residual temporary protective layer 370 at the bottom of the channel hole 410 is removed. By way of example, the process for removing the temporary protective layer 370 comprises wet etching.

[0070] In some embodiments, the manufacturing method further comprises: before forming the floating gate layer, forming a second intermediate layer on the surface of the first intermediate layer in the side cavity and the surface of the interlayer dielectric layer in the channel hole, wherein the floating gate layer is in contact with the second intermediate layer.

[0071] Processes for forming the second intermediate layer include but are not limited to various chemical vapor deposition (CVD), atomic layer deposition (ALD), etc. In this embodiment, plasma enhanced chemical vapor deposition (PECVD) is used to deposit the second intermediate layer in the form of a thin film.

[0072] Referring to Figure 13 , the second intermediate layer 530 completely covers the first intermediate layer 520 in the side cavity 440 and does not fill the side cavity 440. In addition, the second intermediate layer 530 also covers the surface of the interlayer dielectric layer 230 on the side wall of the channel hole 410, the surfaces of the first intermediate layer 520 and the oxide layer at the bottom of the channel hole 410, and the top surface of the second protective dielectric layer 320. By way of example, the material of the second intermediate layer 530 comprises silicon oxide.

[0073] Referring to Figure 14 , a floating gate layer 540 is formed in the side cavity 440. By way of example, the manufacturing process of the floating gate layer 540 is as follows: a floating gate material layer is deposited on the surface of the second intermediate layer 530 until the remaining space of the side cavity 440 is filled, meanwhile, the floating gate material layer is also located on the side wall and bottom of the channel hole 410, and the top surface of the stacked structure; then, the floating gate material layer is wet etched until the floating gate material layer on the side wall of the channel hole 410 is removed.

[0074] It should be noted that, referring to Figure 13 and Figure 14When forming the floating gate material layer, the remaining space within the side cavity 440 is small and elongated. Therefore, only a thin floating gate material layer is needed to fill the remaining space of the side cavity 440. At this time, the thickness of the floating gate material layer on the sidewalls and bottom of the channel hole 410 is much smaller than the horizontal dimension of the floating gate material layer within the side cavity 440. Therefore, a shorter wet etching process can remove the floating gate material layer on the sidewalls and bottom of the channel hole 410, as well as the top surface of the stacked structure. The floating gate material layer within the side cavity 440 is retained, resulting in the floating gate layer 540.

[0075] For example, the floating gate layer 540 is made of polycrystalline silicon. In one specific embodiment, the floating gate layer 540 is made of doped polycrystalline silicon, with the dopant ions being N-type dopant ions, such as phosphorus (P) or arsenic (As). The floating gate layer 540 is used to trap and store electrons; it is in a floating state and stores logic data "0" or "1" by the number of electrons stored within it. In other embodiments, the floating gate layer 540 is made of silicon nitride or silicon oxynitride.

[0076] Next, a tunneling layer 550 is formed on the surface of the floating gate layer 540. In some embodiments, when the material of the floating gate layer 540 includes a polysilicon layer, forming the tunneling layer 550 on the surface of the floating gate layer 540 includes: oxidizing the floating gate layer to form the tunneling layer on the surface of the floating gate layer.

[0077] See Figure 15 An in-situ oxidation process is performed, oxidizing the surface of the floating gate layer 540 exposed within the channel aperture 410 to form a tunneling layer 550. The tunneling layer 550 is located on the surface of the floating gate layer 540 and a portion of the second intermediate layer 530 to completely isolate the floating gate layer 540 from the subsequently formed channel layer. For example, multiple tunneling layers 550 arranged in the vertical Z direction are spaced apart from each other.

[0078] It should be noted that, in other embodiments, the tunneling layer 550 can also be formed by deposition. For example, a thin film-shaped tunneling layer 550 is deposited on the surface of the floating gate layer 540, the sidewalls of the channel hole 410, and the bottom. The tunneling layer 550 extends in the vertical direction Z and contacts the plurality of floating gate layers 540.

[0079] In some embodiments, see Figure 16 The manufacturing method further includes etching at least a second intermediate layer 530 and a barrier layer 510 at the bottom of the channel hole 410 to expose the substrate 100.

[0080] When the source layer is located within the substrate 100, the channel layer needs to extend into the substrate 100 and contact the source layer. Therefore, the insulating material at the bottom of the channel via 410 is etched through before the channel layer is formed. In other embodiments, the substrate 100 is removed in a subsequent process, and the source layer is deposited where the substrate 100 is removed. In this embodiment, the insulating material at the bottom of the channel via 410 can be etched to expose the channel layer after the substrate 100 is removed, and it is not necessary to etch the insulating material at the bottom of the channel via 410 at this step (i.e., before the formation of the channel layer).

[0081] In this embodiment, dry etching is used to punch through the second intermediate layer 530 and the barrier layer 510 at the bottom of the via 410, forming a connection 450 that exposes the substrate 100. It should be understood that if the tunneling layer 550 is also located at the bottom of the via 410, then in this step, it is also necessary to punch through the tunneling layer 550.

[0082] Next, a channel layer 560 is formed inside the channel hole 410 to contact the tunnel layer 550, and a filling layer 380 is formed on the surface of the channel layer 560 to fill the remaining space of the channel hole 410. Figure 17 and Figure 18 The process of forming the channel layer 560 and the filler layer 380 is shown.

[0083] See Figure 17 A channel material layer is deposited on the sidewalls and bottom of the channel via 410 and on the top surface of the second protective dielectric layer 320. The channel material layer contacts each tunneling layer 550 arranged in the vertical Z direction and contacts the substrate 100 at the connection port 450. For example, the deposition process of the channel material layer includes, but is not limited to, various chemical vapor deposition (CVD), atomic layer deposition (ALD), etc. The material of the channel material layer includes, but is not limited to, polycrystalline silicon, doped polycrystalline silicon, etc.

[0084] See Figure 18 A filler material layer is formed on the surface of the channel material layer, filling the remaining space of the channel hole 410. Next, a flattening ring process is performed to remove the filler material layer and channel material layer outside the channel hole 410, making the top surface of the stacked structure flat. At this point, the channel material layer and filler material layer inside the channel hole 410 form the channel layer 560 and filler layer 380, respectively, with the channel layer 560 extending in the vertical direction Z.

[0085] Thus, a channel structure is formed. In this embodiment, the channel structure includes a channel layer 560 extending in the vertical direction Z, and a tunneling layer 550, a floating gate layer 540, a second intermediate layer 530, a first intermediate layer 520 and a barrier layer 510 stacked sequentially from the channel layer 560 in the horizontal direction outward. The barrier layer 510 is in contact with the gate layer 210.

[0086] In some embodiments, the manufacturing method further includes: etching the filler layer to form a groove that exposes a portion of the sidewall of the channel layer; and forming a contact plug within the groove.

[0087] See Figure 19 The fill layer 380 is etched to remove a portion of it, forming a recess 460. The bottom surface of the recess 460 is higher than the top surface of the uppermost gate layer 210. For example, as... Figure 19 As shown, the bottom surface of the groove 460 is higher than or flush with the bottom surface of the second protective medium layer 320. The groove 460 exposes part of the sidewall of the channel layer 560.

[0088] Furthermore, since the materials of the gate isolation structure 360, the second intermediate layer 530, and the fill layer 380 are the same, the gate isolation structure 360 ​​and the second intermediate layer 530 are also partially etched when the fill layer 380 is etched.

[0089] See Figure 20 Conductive material is deposited within the groove 460. Simultaneously, the conductive material is also located within the space formed after the gate isolation structure 360 ​​and the second intermediate layer 530 are etched, and also on the top surface of the second protective dielectric layer 320. Next, a planarization process is performed to remove the conductive material from the top surface of the second protective dielectric layer 320, obtaining a planar surface. At this point, the conductive material located within the groove 460 forms the contact plug 610.

[0090] It should be noted that the conductive material on top of the gate isolation structure 360 ​​can be removed in subsequent processes.

[0091] In some embodiments, the manufacturing method further includes forming a plurality of horizontally extending bit lines (not shown) on the stacked structure, the bit lines being connected to the contact plug 610.

[0092] The semiconductor device manufacturing method provided in this disclosure prepares a stacked structure composed of alternating layers of single-crystal silicon and silicon-germanium through epitaxial growth. Compared with related technologies that use silicon oxide and polycrystalline silicon stacks, firstly, by using a single-crystal silicon / silicon-germanium superlattice stack as a base, the difficulty of the dry etching process for the channel holes, which limits the number of stacked layers in three-dimensional NAND, is greatly reduced. This is beneficial for stacking higher layers in three-dimensional floating-gate NAND memory and increasing storage density. Furthermore, by replacing the gate layer material with single-crystal silicon and using a barrier layer derived from single-crystal silicon oxidation, the gate layer resistance and barrier layer leakage current can be effectively reduced, thereby effectively improving the intrinsic electrical characteristics of the three-dimensional floating-gate NAND memory cell.

[0093] This disclosure also provides a semiconductor structure, which is prepared using the semiconductor structure manufacturing method shown in any of the above embodiments.

[0094] Figure 21 This is a schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure. Figure 22 for Figure 21 A magnified schematic diagram of region B in the middle section. See also... Figure 21 and Figure 22 The semiconductor structure includes: The stacked structure includes a gate layer 210 and an interlayer insulating layer 230 that are alternately stacked along the vertical direction Z; The channel structure 500 includes a channel layer 560 and a plurality of memory structures. The channel layer 560 passes through the stacked structure in a vertical direction Z, and the plurality of memory structures are arranged in a vertical direction Z, with each memory structure surrounding the channel layer 560. The memory structure includes a barrier layer 510, and the material of the barrier layer 510 includes an oxide obtained by oxidizing the gate layer 210. The gate isolation structure 360 ​​is located in the stacked structure and runs through the stacked structure.

[0095] In the semiconductor structure disclosed herein, the barrier layer is made of an oxide obtained by oxidizing the gate layer. Compared to a deposited barrier layer, the barrier layer formed by in-situ oxidation has higher density, fewer defects, and better insulation performance. Furthermore, the interface between the gate layer and the barrier layer is steeper, with fewer defects and impurities, resulting in higher interface quality. All of these factors help prevent the charge stored in the floating gate layer from leaking to the gate layer, thereby reducing leakage current, improving data retention, and effectively enhancing the intrinsic electrical characteristics of the three-dimensional floating gate NAND memory cell.

[0096] In some embodiments, the gate layer 210 is made of monocrystalline silicon and N-type doped atoms, and the barrier layer 510 is made of silicon oxide. N-type doped atoms include, but are not limited to, phosphorus (P), arsenic (As), etc. For example, the concentration of N-type doped atoms is high, for example, greater than 1 × 10⁻⁶. 19 atoms / cm 3 This is called heavy doping, which can reduce the resistance of the gate layer.

[0097] In some embodiments, the storage structure further includes a tunneling layer 550 and a floating gate layer 540 stacked sequentially outward from the channel layer 560 in a horizontal direction, with the floating gate layer 540 located between the tunneling layer 550 and the barrier layer 510; wherein the barrier layer 510, the floating gate layer 540, and the tunneling layer 550 are located between adjacent interlayer insulating layers 230 in the vertical direction Z. The barrier layer 510, the floating gate layer 540, and the tunneling layer 550 are all disposed around the channel layer 560.

[0098] For example, the floating gate layer 540 is made of polysilicon. In one specific embodiment, the floating gate layer 540 is made of doped polysilicon, with the dopant ions being N-type dopant ions, such as phosphorus (P) or arsenic (As). The floating gate layer 540 is used to capture and store electrons; it is in a floating state and stores logic data "0" or "1" by the number of electrons stored within it.

[0099] When a high voltage is applied to the gate layer, the tunneling layer allows electrons from the channel layer to pass through and enter the floating gate layer; when a low voltage is applied to the gate layer, it prevents charge leakage from the floating gate layer. For example, the material of the tunneling layer includes an oxide obtained by oxidizing the floating gate layer. Alternatively, the material of the tunneling layer may include deposited silicon oxide, silicon oxynitride, etc. In this embodiment, the tunneling layer obtained by oxidizing the floating gate layer has high density and good interface quality, which can reduce the leakage current of the floating gate layer and improve data retention time. Furthermore, the thickness of the tunneling layer prepared by the thermal oxidation process is well controllable, resulting in high vertical consistency of the memory cells.

[0100] In some embodiments, the channel structure further includes a first intermediate layer 520 and a second intermediate layer 530 sequentially disposed along the direction from the barrier layer 510 toward the floating gate layer 540. The first intermediate layer 520 includes a sidewall 524, a first bottom wall 522 and a second bottom wall 523. The sidewall 524 contacts the barrier layer 510. The first bottom wall 522 and the second bottom wall 523 are located at opposite ends of the sidewall 524 in the vertical direction Z and extend horizontally toward the channel layer 560. The first bottom wall 522 and the second bottom wall 523 respectively contact the adjacent interlayer insulating layer 230.

[0101] The second intermediate layer 530 is located on the inner surface of the first intermediate layer 520 and extends vertically Z-direction between the channel layer 560 and the interlayer insulation layer 230. The second intermediate layer 530 extends vertically overall, partially between the channel layer 560 and the interlayer insulation layer 230, and partially extends into the first intermediate layer, located between the first intermediate layer and the floating gate layer 540. The floating gate layer 540 is located within the first intermediate layer 520 and contacts the second intermediate layer 530. The tunneling layer 550 contacts the floating gate layer 540 and the second intermediate layer 530. The channel layer 560 contacts the tunneling layer 550 and the second intermediate layer 530.

[0102] For example, the material of the first intermediate layer 520 includes silicon nitride, and the material of the second intermediate layer 530 includes silicon oxide.

[0103] The first intermediate layer 520 and the second intermediate layer 530 increase the thickness of the dielectric material between the gate layer and the floating gate layer 540, further preventing charge leakage from the floating gate layer to the gate layer, thereby reducing leakage current. The first intermediate layer uses silicon nitride, which increases the dielectric constant of the dielectric material between the gate layer and the floating gate layer, and increases the coupling ratio of the gate layer to the floating gate layer, thus enabling programming at a lower operating voltage. The use of silicon nitride in the first intermediate layer effectively blocks the lateral diffusion of impurity atoms (such as phosphorus and arsenic doped in the gate layer), reduces impurities in the second intermediate layer, and reduces impurities at the interface between the second intermediate layer and the floating gate layer, which helps maintain a high barrier at the interface between the floating gate layer and the second intermediate layer, thereby reducing leakage current.

[0104] In some embodiments, the channel structure 500 further includes: a filling layer 380 and a contact plug 610, the filling layer 380 extending in the vertical direction Z; the contact plug 610 located on the filling layer 380; wherein the channel layer 560 surrounds the sidewalls of the filling layer 380 and the contact plug 610.

[0105] For example, the filler layer 380 may be made of silicon oxide, silicon nitride, silicon oxynitride, or a low-k dielectric material. The contact plug 610 may be made of metal, metal nitride, doped polysilicon, etc. Metals include, but are not limited to, copper, nickel, cobalt, tungsten, gold, silver, aluminum, etc. Metal nitrides include, but are not limited to, titanium nitride, cobalt nitride, tungsten nitride, etc.

[0106] For example, the bottom surface of the contact plug 610 is higher than the top surface of the uppermost gate layer 210.

[0107] This disclosure also provides a memory including the semiconductor structure described in any of the above embodiments.

[0108] Figure 23 A schematic diagram of the memory provided in an embodiment of this disclosure is shown below. Figure 23 The memory 10 includes a first semiconductor structure 20 and a second semiconductor structure 30 stacked along the vertical direction Z. The first semiconductor structure 20 and the second semiconductor structure 30 are connected to each other through an electrical connection structure 40. The first semiconductor structure 20 is a semiconductor structure as described in any of the above embodiments or a semiconductor structure prepared by the manufacturing method shown in any of the above embodiments. The second semiconductor structure 30 includes peripheral circuits, which are coupled to the gate layer and the channel layer in the first semiconductor structure 20.

[0109] For example, the electrical connection structure 40 may be a bonding pad, or a solder pad and bump, etc.

[0110] This disclosure also provides a memory system. Figure 24 A schematic diagram of a memory system provided in an embodiment of this disclosure, such as... Figure 24As shown, the memory system 60 includes one or more memories 10 and a memory controller 50. The memory 10 can be any three-dimensional (3D) non-volatile memory (NVM) device disclosed in this disclosure, such as NAND flash memory. The memory 10 includes the aforementioned... Figures 1 to 23 The semiconductor structure described in any of the embodiments, the memory 10 is similar to the one described above. Figures 1 to 23 The described semiconductor structure can solve the same technical problem and achieve the same expected results. The memory 10 may include a plurality of conductive interconnects that pass through a cover layer and contact conductive pads in a conductive pad layer, and the memory controller 50 may be coupled to the memory 10 through at least one of the plurality of conductive interconnects. The memory controller 50 is coupled to the memory 10 and configured to control the memory 10 via word lines operating a plurality of channel structures.

[0111] This disclosure also provides an electronic device including a host and a memory system, the host being coupled to the memory system. Examples of the electronic device include a storage device, a smartphone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a power bank. The host may include a processor of the electronic device, such as a central processing unit (CPU), or may include a system-on-a-chip (SoC), such as an application processor (AP). The host is configured to send or receive data to or from the one or more memory systems 60.

[0112] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined to obtain new method embodiments without conflict. Similarly, the features disclosed in the several product embodiments provided in this disclosure can be arbitrarily combined to obtain new product embodiments without conflict.

[0113] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that, include: A first step and a second step are performed alternately on a substrate to form a stacked structure; wherein the first step includes epitaxially growing a sacrificial layer on the substrate or on a gate layer, and the second step includes epitaxially growing a gate layer on the sacrificial layer; Forming channel holes through the stacked structure; A gate isolation trench is formed that extends through the stacked structure; The sacrificial layer is removed based on the gate isolation trench, and an interlayer insulating layer is formed in the space where the sacrificial layer is removed; After the interlayer insulating layer is formed, multiple gate layers are laterally etched from the channel via to form multiple side cavities; The gate layer is oxidized from within the channel hole to form a barrier layer within the side cavity.

2. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, The material of the gate layer includes monocrystalline silicon; and / or, The material of the sacrificial layer includes one of silicon germanium or silicon germanium tin, wherein the silicon content is between 75 mol% and 85 mol%.

3. The method for manufacturing a semiconductor structure according to claim 1 or 2, characterized in that, The epitaxial growth of the gate layer on the sacrificial layer includes: A silicon source gas and an N-type dopant source gas are simultaneously introduced into the sacrificial layer to deposit doped single-crystal silicon, which serves as the gate layer.

4. The method for manufacturing a semiconductor structure according to claim 1 or 2, characterized in that, The manufacturing method further includes: Based on the gate isolation trench, N-type doping atoms are doped into the gate layer.

5. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, The manufacturing method further includes: Before forming the gate isolation trench, a support structure is formed in the channel hole; After the interlayer insulation layer is formed, the support structure is removed to release the channel aperture.

6. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, The manufacturing method further includes: A floating grid layer is formed within the side cavity; A tunneling layer is formed on the surface of the floating grid layer; A channel layer is formed within the channel hole, which contacts the tunneling layer.

7. The method for manufacturing a semiconductor structure according to claim 6, characterized in that, The manufacturing method further includes: Before the floating grid layer is formed, a first intermediate layer is formed on the surface of the barrier layer and the surface of the interlayer insulating layer within the side cavity; A second intermediate layer is formed on the surface of the first intermediate layer in the side cavity and on the surface of the interlayer insulating layer in the channel hole; wherein the floating gate layer is in contact with the second intermediate layer.

8. The method for manufacturing a semiconductor structure according to claim 6 or 7, characterized in that, The manufacturing method further includes: A filling layer is formed on the surface of the channel layer to fill the remaining space of the channel holes; The filler layer is etched to form a groove that exposes a portion of the sidewalls of the channel layer; A contact plug is formed within the groove.

9. A semiconductor structure, characterized in that, include: A stacked structure comprising interlayer insulating layers and epitaxially grown gate layers alternately stacked in a vertical direction; A channel structure extends through the stacked structure along the vertical direction; wherein the channel structure includes a barrier layer, the material of which includes an oxide obtained by oxidizing the gate layer; A gate isolation structure is located in and extends through the stacked structure.

10. The semiconductor structure according to claim 9, characterized in that, The gate layer is made of monocrystalline silicon and N-type doped atoms, and the barrier layer is made of silicon oxide.

11. The semiconductor structure according to claim 9, characterized in that, The channel structure includes a channel layer extending along the vertical direction and a plurality of storage structures arranged at intervals along the vertical direction, each of the storage structures surrounding the channel layer along the vertical direction, and each storage structure including: The barrier layer, and the tunneling layer and the floating grid layer are stacked sequentially from the channel layer outward in the horizontal direction, with the floating grid layer located between the tunneling layer and the barrier layer; The barrier layer, the floating grid layer, and the tunneling layer are located between adjacent interlayer insulation layers in the vertical direction.

12. The semiconductor structure according to claim 11, characterized in that, The channel structure further includes: a first intermediate layer and a second intermediate layer arranged sequentially along the direction from the barrier layer to the floating grid layer; The first intermediate layer includes a sidewall, a first bottom wall, and a second bottom wall. The sidewall is in contact with the barrier layer. The first bottom wall and the second bottom wall are located at opposite ends of the sidewall along the vertical direction and extend towards the channel layer along the horizontal direction. The first bottom wall and the second bottom wall are in contact with the interlayer insulation layer. The second intermediate layer is located on the inner surface of the first intermediate layer and extends along the vertical direction between the channel layer and the interlayer insulation layer; the floating gate layer is located within the first intermediate layer and is in contact with the second intermediate layer.

13. The semiconductor structure according to claim 11, characterized in that, The semiconductor structure also includes: A filling layer extending along the vertical direction; A contact plug is located on the filler layer; wherein the channel layer surrounds the filler layer and the sidewalls of the contact plug.

14. An electronic device, characterized in that, include: Host; A memory system, coupled to the host, comprising: A memory controller and at least one memory coupled to the memory controller, the memory comprising the semiconductor structure of any one of claims 9 to 13.

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