A method for manufacturing a semiconductor structure and a semiconductor device

Abstract

The application discloses a semiconductor structure preparation method and a semiconductor device. The semiconductor structure preparation method comprises the following steps: providing a semiconductor substrate; the semiconductor substrate has a plurality of discrete fin portions; forming a dummy gate across the fin portions on the semiconductor substrate; forming a dummy gate sidewall on the sidewall surface of the dummy gate; the dummy gate sidewall is a composite film layer; forming a first oxide layer outside the dummy gate; removing the target film layer close to the side of the dummy gate in the dummy gate and the dummy gate sidewall to form a gate trench; and filling a metal material in the gate trench to form a metal gate. The scheme provided by the application can completely remove the dummy gate while ensuring the gate trench sidewall morphology.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing, specifically to a method for preparing a semiconductor structure and a semiconductor device. Background Technology

[0002] In the semiconductor manufacturing field, FinFET structures have attracted widespread attention due to their excellent electrical performance. In the gate-last process of FinFET manufacturing, dry etching is typically used to remove polysilicon dummy gates to fill them with metal material and form a metal gate. However, as device sizes continue to shrink, dry etching struggles to completely remove the polysilicon dummy gates from narrow trenches, resulting in significant dummy gate residue. Furthermore, the sidewall morphology after etching is difficult to guarantee, making it highly susceptible to voids during subsequent metal filling. This can lead to electrical failures such as leakage current, reducing the device's electrical performance and reliability.

[0003] Therefore, how to completely remove the dummy gate while maintaining the morphology of the gate trench sidewall has become an urgent technical problem to be solved. Summary of the Invention

[0004] This application provides a method for fabricating a semiconductor structure, another method for fabricating a semiconductor structure, and a semiconductor device, which can thoroughly remove dummy gates while maintaining the sidewall morphology of the gate trench. The specific solutions are as follows: In a first aspect, embodiments of this application provide a method for fabricating a semiconductor structure, the method comprising: providing a semiconductor substrate; the semiconductor substrate having a plurality of discrete fins; forming a dummy gate across the fins on the semiconductor substrate; forming a dummy gate sidewall on the sidewall surface of the dummy gate; the dummy gate sidewall being a composite film layer; forming a first oxide layer on the outer side of the dummy gate; removing the dummy gate and a target film layer on the side of the dummy gate sidewall near the dummy gate to form a gate trench; and filling the gate trench with a metal material to form a metal gate.

[0005] Optionally, forming a dummy gate sidewall on the sidewall surface of the dummy gate includes: forming a first nitride layer sidewall on the sidewall surface of the dummy gate; forming an oxide layer sidewall on the sidewall surface of the first nitride layer sidewall; and forming a second nitride layer sidewall on the sidewall surface of the oxide layer sidewall; wherein the first nitride layer sidewall, the oxide layer sidewall, and the second nitride layer sidewall constitute the dummy gate sidewall.

[0006] Optionally, forming a first nitride layer sidewall on the sidewall surface of the dummy gate includes: forming a first nitride layer on the substrate surface and the dummy gate surface; removing the first nitride layer on the substrate surface and the top surface of the dummy gate to form a first nitride layer sidewall; The step of forming an oxide layer sidewall on the sidewall surface of the first nitride layer sidewall includes: forming an oxide layer on the substrate surface, the surface of the first nitride layer sidewall, and the surface of the dummy gate; and removing the oxide layer on the substrate surface, the top surface of the first nitride layer sidewall, and the top surface of the dummy gate to form an oxide layer sidewall. The step of forming a second nitride layer sidewall on the sidewall surface of the oxide layer sidewall includes: forming a second nitride layer on the substrate surface, the oxide layer sidewall surface, the first nitride layer sidewall surface, and the dummy gate surface; and removing the second nitride layer on the substrate surface, the top surface of the oxide layer sidewall, the top surface of the first nitride layer sidewall, and the top surface of the dummy gate to form a second nitride layer sidewall.

[0007] Optionally, the target film layer is the sidewall of the first nitrided layer.

[0008] Optionally, the dummy gate is made of polycrystalline silicon; the step of removing the dummy gate and the target film layer on the side of the dummy gate sidewall near the dummy gate to form a gate trench includes: removing the dummy gate by dry etching and removing the first nitride layer sidewall by wet etching to form a gate trench.

[0009] Optionally, filling the gate trench with metal material to form a metal gate includes: forming a high dielectric constant dielectric layer on the sidewall of the gate trench; and filling the gate trench with the high dielectric constant dielectric layer on the sidewall with metal material to form a metal gate.

[0010] Optionally, forming a dummy gate across the fin on the semiconductor substrate includes: forming a second oxide layer on the surface of the semiconductor substrate and the surface of the fin; and forming a dummy gate across the fin on the second oxide layer.

[0011] Optionally, forming the first oxide layer outside the dummy gate includes: forming an initial first oxide layer on the substrate surface such that the initial first oxide layer extends 300 nm to 500 nm beyond the top surface of the dummy gate; and removing the initial first oxide layer above the top surface of the dummy gate to expose the top surface of the dummy gate, thereby forming the first oxide layer outside the dummy gate.

[0012] Optionally, the removal of the dummy gate by dry etching includes: removing the dummy gate by dry etching with a target gas; the ratio of the etching rate of the target gas for polysilicon to the etching rate for the nitride layer is greater than or equal to a first preset ratio; the removal of the first nitride layer sidewall by wet etching includes: removing the first nitride layer sidewall by wet etching with a target solution; the ratio of the etching rate of the target solution for the nitride layer to the etching rate for the oxide layer is greater than or equal to a second preset ratio.

[0013] Secondly, embodiments of this application provide another method for fabricating a semiconductor structure, the method comprising: providing a semiconductor substrate; forming a first conductive structure on the semiconductor substrate; forming a sidewall on the sidewall surface of the first conductive structure; the sidewall being a composite film layer; forming a sixth oxide layer on the outside of the first conductive structure; removing the first conductive structure and the target film layer on the sidewall closest to the first conductive structure to form a trench; and filling the trench with a conductive material to form a second conductive structure.

[0014] Thirdly, embodiments of this application provide a semiconductor device prepared by the method described in the first or second aspect of this application.

[0015] Compared with the prior art, this application has the following advantages: The semiconductor structure fabrication method provided in the first embodiment of this application includes the following steps: providing a semiconductor substrate; the semiconductor substrate having a plurality of discrete fins; forming a dummy gate across the fins on the semiconductor substrate; forming a dummy gate sidewall on the sidewall surface of the dummy gate; the dummy gate sidewall being a composite film layer; forming a first oxide layer on the outer side of the dummy gate; removing the dummy gate and a target film layer in the dummy gate sidewall near the dummy gate to form a gate trench; filling the gate trench with a metal material to form a metal gate. It can be seen that, because a composite film layer is formed on the sidewall surface of the dummy gate as a dummy gate sidewall, after removing the dummy gate, removing the target film layer in the dummy gate sidewall near the dummy gate can remove any remaining dummy gate residue that was not completely removed during the dummy gate removal process, resulting in a more thorough removal of the dummy gate. Furthermore, when removing the target film layer, the film layer adjacent to the target film layer in the dummy gate sidewall can be used as a stop layer, ensuring the sidewall morphology of the gate trench. Therefore, the semiconductor structure fabrication method provided in the first embodiment of this application can thoroughly remove dummy gates while maintaining the sidewall morphology of the gate trench. This makes it less likely for voids to form when filling the gate trench with metal material, thus ensuring a good contact interface between the metal gate and the source / drain electrodes, reducing contact resistance, and resulting in a device with better electrical signal characteristics, while reducing parasitic capacitance and contact resistance. Attached Figure Description

[0016] Figure 1 This is a flowchart of the method for preparing the semiconductor structure provided in the first embodiment of this application.

[0017] Figure 2 This is a schematic diagram of a semiconductor substrate having multiple discrete fins in the semiconductor structure fabrication method provided in the first embodiment of this application.

[0018] Figure 3 This is a schematic diagram of the formation of the second oxide layer in the semiconductor structure fabrication method provided in the first embodiment of this application.

[0019] Figure 4 This is a schematic diagram of the formation of polycrystalline silicon on the surface of the second oxide layer in the method for preparing the semiconductor structure provided in the first embodiment of this application.

[0020] Figure 5 This is a schematic diagram of the formation of a dummy gate in the semiconductor structure fabrication method provided in the first embodiment of this application.

[0021] Figure 6 A schematic diagram of the first nitride layer in the semiconductor structure fabrication method provided in the first embodiment of this application.

[0022] Figure 7 This is a schematic diagram of the formation of the first nitride layer sidewall in the semiconductor structure fabrication method provided in the first embodiment of this application.

[0023] Figure 8 This is a schematic diagram of the formation of an oxide layer in the semiconductor structure fabrication method provided in the first embodiment of this application.

[0024] Figure 9 This is a schematic diagram of the formation of oxide layer sidewalls in the semiconductor structure fabrication method provided in the first embodiment of this application.

[0025] Figure 10 This is a schematic diagram of the second nitride layer in the semiconductor structure fabrication method provided in the first embodiment of this application.

[0026] Figure 11 This is a schematic diagram of the formation of the second nitride layer sidewall in the semiconductor structure fabrication method provided in the first embodiment of this application.

[0027] Figure 12 This is a schematic diagram of the formation of the initial first oxide layer in the semiconductor structure fabrication method provided in the first embodiment of this application.

[0028] Figure 13 This is a schematic diagram of the formation of the first oxide layer in the semiconductor structure fabrication method provided in the first embodiment of this application.

[0029] Figure 14This is a schematic diagram of removing the dummy gate in the semiconductor structure fabrication method provided in the first embodiment of this application.

[0030] Figure 15 This is a schematic diagram of removing the target film layer in the semiconductor structure fabrication method provided in the first embodiment of this application.

[0031] Figure 16 This is a schematic diagram of forming a high dielectric constant dielectric layer on the sidewall of the gate trench in the semiconductor structure fabrication method provided in the first embodiment of this application.

[0032] Figure 17 This is a schematic diagram of filling the sidewall of the gate trench with metal material in the semiconductor structure fabrication method provided in the first embodiment of this application.

[0033] Figure 18 This is a flowchart of the method for preparing the semiconductor structure provided in the second embodiment of this application. Detailed Implementation

[0034] Many specific details are set forth in the following description to provide a full understanding of this application. However, this application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of this application; therefore, this application is not limited to the specific embodiments disclosed below.

[0035] It should be noted that the terms "first," "second," "third," etc., in the claims, specification, and drawings of this application are used to distinguish similar objects and are not used to describe a specific order or sequence. Such data are interchangeable where appropriate so that the embodiments of this application described herein can be implemented in a sequence other than that shown or described herein. Furthermore, the terms "comprising," "having," and their variations are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to these processes, methods, products, or apparatuses.

[0036] It should be understood that in the embodiments of this application, "at least one" means one or more, and "more than one" means two or more. "And / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. The character " / " generally indicates that the related objects before and after it are in an "or" relationship. "Contains A, B and / or C" means containing any one, two, or three of A, B, and C.

[0037] It should be understood that in the embodiments of this application, "B corresponding to A", "B corresponding to A", "A corresponds to B" or "B corresponds to A" means that B is associated with A, and B can be determined based on A. Determining B based on A does not mean that B is determined solely based on A; B can also be determined based on A and / or other information.

[0038] Based on the reasons mentioned in the background art, the first embodiment of this application provides a method for fabricating a semiconductor structure that can thoroughly remove dummy gates while ensuring the morphology of the gate trench sidewalls.

[0039] The technical solution of this application will be described in detail below through specific embodiments. It should be noted that the following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.

[0040] The following, combined with Figures 1-18 The method for preparing the semiconductor structure provided in the first embodiment of this application is introduced.

[0041] like Figure 1 As shown, the semiconductor structure fabrication method provided in the first embodiment of this application includes the following steps S101 to S106.

[0042] Step S101: Provide a semiconductor substrate; the semiconductor substrate has a plurality of discrete fins.

[0043] In semiconductor manufacturing processes, a semiconductor substrate refers to the basic material used to fabricate semiconductor structures. Semiconductor substrates can include, but are not limited to, pure single-crystal silicon (Si), gallium arsenide (GaAs), gallium nitride (GaN), and silicon carbide (SiC). The material of the semiconductor substrate can be selected according to actual needs during the fabrication process. The substrate can be a P-type substrate, which refers to a semiconductor wafer material formed by doping single-crystal silicon with acceptor impurities (such as boron, gallium, etc.). Its majority carriers are holes, thus enabling the material to exhibit P-type conductivity (hole concentration > electron concentration). As the physical support and electrical foundation of the entire chip, the P-type substrate not only determines the doping polarity of subsequent epitaxial layers and well regions but also directly affects the isolation characteristics and breakdown voltage performance of the device.

[0044] The semiconductor substrate may have multiple discrete fins, which are raised structures on a FinFET (Fin Field-Effect Transistor), i.e., thin strips protruding from the surface of the semiconductor substrate. In a FinFET, the fins are surrounded by a metal gate from the top and two sides. Compared to the single-sided control of a planar transistor, FinFETs can enhance the gate's electrostatic control over the channel, thereby effectively suppressing short-channel effects, reducing leakage current, and enabling devices to achieve high performance and low power consumption in smaller sizes.

[0045] The following combination Figure 2 The formation process of the fin is described below. First, the fin region to be formed can be defined on the surface of the semiconductor substrate 101 by photolithography. Then, an etching process is performed to form grooves on the surface of the semiconductor substrate 101 in areas other than the fin region, thus obtaining the fin 103. After that, an isolation layer 102 is formed on the surface of the semiconductor substrate. The material of the isolation layer 102 can be silicon oxide (SiO2).

[0046] Step S102: Form a dummy gate across the fin on the semiconductor substrate.

[0047] The dummy gate refers to a vacant structure used to define the gate location and protect the channel region. The dummy gate can be made of polycrystalline silicon, amorphous silicon, silicon oxide, amorphous carbon, etc. For ease of explanation, the following embodiments of this application will use polycrystalline silicon as an example. The dummy gate spans the fin and predefines the position and morphology of the subsequent metal gate. In subsequent source / drain doping, ion implantation, high-temperature annealing, and other processes, the dummy gate acts as a physical barrier to protect the underlying fin channel from damage and maintain the structural integrity and electrical properties of the channel region. After the high-temperature process is completed, the dummy gate is removed, leaving a gate trench spanning the fin. This gate trench is used to fill the metal gate, thereby realizing the fabrication of the metal gate.

[0048] In one specific implementation, it can be done as follows: Figure 2 A dummy gate is formed directly across the fin on the semiconductor substrate shown.

[0049] In another specific implementation, a second oxide layer can be first formed on the surface of the semiconductor substrate and the surface of the fin; a dummy gate spanning the fin can then be formed on the second oxide layer. The following is combined with... Figure 3 , Figure 4 as well as Figure 5 The process steps for forming a dummy gate spanning the fin on the second oxide layer are described below: like Figure 3 As shown, for Figure 2The semiconductor substrate shown can have a second oxide layer 104 formed on the surface of the semiconductor substrate 101, the surface of the isolation layer 102, and the surface of the fin 103 using techniques such as chemical vapor deposition (CVD) or atomic layer deposition (ALD); subsequently, as... Figure 4 As shown, polysilicon 105 can be formed on the second oxide layer 104. Specifically, polysilicon 105 can be formed on the second oxide layer 104 using processes such as chemical vapor deposition or furnace tube deposition. Then, fin regions can be defined on the surface of the polysilicon 105 using photolithography, and an etching process can be performed to remove the polysilicon from the regions of the polysilicon 105 other than the fin regions. Figure 5 As shown, a dummy gate 106 will be formed across the fin in the second oxide layer.

[0050] In this embodiment of the application, by pre-forming a second oxide layer on the semiconductor substrate, stress damage caused by other processes on the semiconductor substrate and the fin can be reduced, effectively protecting the semiconductor substrate and the fin.

[0051] Step S103: Form a dummy gate sidewall on the sidewall surface of the dummy gate. The dummy gate sidewall is a composite film layer.

[0052] In an optional embodiment, the dummy gate sidewall can be a nitride-oxide-nitride structure. In this embodiment, the nitride layer can be silicon nitride, and the oxide layer can be silicon oxide. In this embodiment, step S103 can be implemented by the following steps: forming a first nitride sidewall on the sidewall surface of the dummy gate; forming an oxide sidewall on the sidewall surface of the first nitride sidewall; forming a second nitride sidewall on the sidewall surface of the oxide sidewall; wherein the first nitride sidewall, the oxide sidewall, and the second nitride sidewall constitute the dummy gate sidewall.

[0053] The following combination Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 and Figure 11 The process steps for forming a nitride-oxide-nitride layer on the dummy gate sidewall are described below: First, it can be done through Figure 6 and Figure 7 The first nitrided layer sidewalls are formed. For example... Figure 6The diagram shown is a schematic of the first nitride layer in the semiconductor structure fabrication method provided in this application embodiment. The first nitride layer 107 can be formed on the surface of the semiconductor substrate (specifically, the surface of the second oxide layer 104) and the surface of the dummy gate 106 using techniques such as atomic layer deposition (ALD) or chemical vapor deposition (CVD). Then, as... Figure 7 The diagram shown is a schematic diagram of the formation of the first nitride layer sidewall in the semiconductor structure fabrication method provided in this application embodiment. After the first nitride layer 107 is formed, the first nitride layer on the surface of the semiconductor substrate (specifically the surface of the second oxide layer 104) and the top surface of the dummy gate 106 can be removed by dry etching to form the first nitride layer sidewall 108.

[0054] After that, it can be done through Figure 8 and Figure 9 An oxide layer sidewall is formed. For example... Figure 8 The diagram shown is a schematic of the formation of an oxide layer in the semiconductor structure fabrication method provided in this application embodiment. After forming the first nitride layer sidewall 108, an oxide layer 109 can be formed on the surface of the semiconductor substrate (specifically, the surface of the second oxide layer 104), the surface of the first nitride layer sidewall 108, and the surface of the dummy gate 106 using techniques such as atomic layer deposition (ALD) or chemical vapor deposition (CVD). Then, as... Figure 9 The diagram shown is a schematic diagram of forming oxide layer sidewalls in the semiconductor structure fabrication method provided in this application embodiment. After forming oxide layer 109, the oxide layers on the surface of the semiconductor substrate (specifically, the surface of the second oxide layer 104), the top surface of the first nitride layer sidewall 108, and the top surface of the dummy gate 106 can be removed by dry etching to form oxide layer sidewall 110.

[0055] Finally, it can be done through Figure 10 and Figure 11 The first nitrided layer sidewalls are formed. For example... Figure 10 The diagram shown is a schematic of the second nitride layer in the semiconductor structure fabrication method provided in this application embodiment. The second nitride layer 111 can be formed on the surface of the semiconductor substrate (specifically, the surface of the second oxide layer 104), the surface of the first nitride layer sidewall 108, the surface of the oxide layer sidewall 110, and the surface of the dummy gate 106 using techniques such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). Then, as... Figure 11The diagram shown is a schematic diagram of the formation of the second nitride layer sidewall in the semiconductor structure fabrication method provided in this application embodiment. After the second nitride layer 111 is formed, the second nitride layer on the surface of the semiconductor substrate (specifically, the surface of the second oxide layer 104), the top surface of the oxide layer sidewall 110, the top surface of the first nitride layer sidewall 108, and the top surface of the dummy gate 106 can be removed by dry etching to form the second nitride layer sidewall 112.

[0056] Chemical vapor deposition (CVD) is a semiconductor manufacturing process that uses gaseous precursors to react chemically on a heated solid surface to generate a solid film, which is then deposited onto a substrate. Atomic layer deposition (ALD) is a special type of CVD technique that uses two or more precursor gases, alternately pulsed into a reaction chamber, to cause a self-limiting surface chemical reaction on a heated solid substrate, thereby growing a solid film atomically.

[0057] Through the above steps, pseudo-gate sidewalls, including a first nitride layer sidewall 108, an oxide layer sidewall 110, and a second nitride layer sidewall 112, can be formed on both sides of the pseudo-gate 106. Since the pseudo-gate sidewalls include oxide layer sidewalls 110, on the one hand, the adhesion and bonding force of the pseudo-gate sidewalls can be improved, making the structure more stable; on the other hand, when forming the oxide layer sidewall 110, a rounded corner can be formed at the top corner. Compared to a sharp corner, a rounded corner at the top corner of the oxide layer sidewall 110 results in a more uniform electric field distribution, which can avoid the accumulation of localized strong electric fields and improve the electrical reliability of the device.

[0058] In another optional embodiment, the dummy gate sidewall can also be a nitride-oxide structure. In this embodiment, step S103 can be achieved by the following steps: forming a third nitride sidewall on the sidewall surface of the dummy gate; forming a third oxide sidewall on the sidewall surface of the third nitride sidewall; wherein the third nitride sidewall and the third oxide sidewall constitute the dummy gate sidewall.

[0059] In another optional embodiment, the dummy gate sidewall can be an oxide-nitride-oxide structure. In this embodiment, step S103 can be implemented by the following steps: forming a fourth oxide sidewall on the sidewall surface of the dummy gate; forming a fourth nitride sidewall on the sidewall surface of the fourth oxide sidewall; forming a fifth oxide sidewall on the sidewall surface of the fourth nitride sidewall; wherein the fourth oxide sidewall, the fourth nitride sidewall, and the fifth oxide sidewall constitute the dummy gate sidewall.

[0060] In this embodiment, the formed dummy gate sidewall is a composite structure with better adhesion, thus improving the structural stability. Furthermore, in subsequent steps, when removing the dummy gate, the dummy gate can be removed more thoroughly by further removing the target film layer on the dummy gate sidewall near the dummy gate.

[0061] Step S104: A first oxide layer is formed on the outside of the dummy gate.

[0062] After the dummy gate sidewall is formed, a first oxide layer can be formed on the outside of the dummy gate. The first oxide layer can be substantially the same as the top surface of the dummy gate. The first oxide layer is the interlayer dielectric layer used for electrical isolation.

[0063] The following combination Figure 12 and Figure 13 The process steps for forming the first oxide layer on the outside of the dummy gate are described below: like Figure 12 The diagram shown is a schematic of the formation of an initial first oxide layer in the semiconductor structure fabrication method provided in this application embodiment. The initial first oxide layer 113 can be formed on the surface of a semiconductor substrate. Specifically, the initial first oxide layer 113 can be formed by chemical vapor deposition on the surface of the semiconductor substrate (specifically, the surface of the second oxide layer 104), the surface of the dummy gate sidewalls (including the first nitride sidewall 108, the oxide sidewall 110, and the second nitride sidewall 112), and the surface of the dummy gate 106, such that the initial first oxide layer 113 extends 300nm to 500nm beyond the top surface of the dummy gate 106.

[0064] like Figure 13 The diagram shown is a schematic of the formation of a first oxide layer in the semiconductor structure fabrication method provided in this application embodiment. After forming the initial first oxide layer 113, the initial first oxide layer 113 located above the top surface of the dummy gate can be removed to expose the top surface of the dummy gate. Specifically, the initial first oxide layer 113 located above the top surface of the dummy gate can be removed by any method such as mechanical polishing, dry etching, or wet etching, and the process can be stopped on the top surface of the dummy gate, thereby forming the first oxide layer 114 on the outside of the dummy gate.

[0065] Step S105: Remove the dummy gate and the target film layer on the side of the dummy gate sidewall near the dummy gate to form a gate trench.

[0066] This step is used to thoroughly remove the dummy gate used as a placeholder, thereby forming a well-shaped gate trench that spans the fin on the semiconductor substrate. In subsequent processes, a metal gate will be filled in, thus realizing the fabrication of the metal gate.

[0067] The target film is the film layer on the side of the dummy gate sidewall that is close to the dummy gate. When the dummy gate sidewall has different structures, the material of the target film may be different.

[0068] Specifically, the pseudo-gate sidewall has the aforementioned nitride-oxide-nitride structure (e.g., ...). Figure 13 In the case of the structure shown (first nitride layer sidewall 108, oxide layer sidewall 110, and second nitride layer sidewall 112), the target film layer is the first nitride layer sidewall 108. In the case where the dummy gate sidewall is a nitride layer-oxide layer structure (such as the structure composed of the third nitride layer sidewall and the third oxide layer sidewall described above), the target film layer is the third nitride layer sidewall. In the case where the dummy gate sidewall is an oxide layer-nitride layer-oxide layer structure (such as the structure composed of the fourth oxide layer sidewall, the fourth nitride layer sidewall, and the fifth oxide layer sidewall described above), the target film layer is the fourth oxide layer sidewall.

[0069] Furthermore, when the dummy gate is made of polycrystalline silicon and the target film is a nitride layer sidewall (such as a first nitride layer sidewall or a third nitride layer sidewall), for ease of explanation, the following description will take the target film as a first nitride layer sidewall as an example. The process of removing the dummy gate and the target film on the side of the dummy gate sidewall that is close to the dummy gate to form a gate trench may specifically include the following steps: removing the dummy gate by dry etching and removing the first nitride layer sidewall by wet etching to form a gate trench.

[0070] The following combination Figure 14 and Figure 15 The process steps for forming the gate trench in the embodiments of this application are described below: like Figure 14 The diagram illustrates the removal of a dummy gate in the semiconductor structure fabrication method provided in this application embodiment. The dummy gate 106 spanning the fin can be removed by dry etching. Specifically, a target gas dry etching method can be used to remove the dummy gate 106 spanning the fin. Under the same etching conditions, the ratio of the etching rate of the target gas on polysilicon to the etching rate on the nitride layer can be greater than or equal to a first preset ratio, where the first preset ratio is greater than 1. Thus, when the target gas dry etching method is used to remove the dummy gate 106 spanning the fin, the ratio of the etching rate of the dummy gate 106 to the etching rate of the first nitride layer sidewall 108 is greater than or equal to the first preset ratio.

[0071] For example, the target gas can be a high-selectivity etching process containing hydrogen bromide (HBr) and oxygen (O2). The etching selectivity ratio of the target gas for polysilicon and nitride layers can be between 30:1 and 40:1, for example, any one of 30:1, 31:1, 32:1, 33:1, 34:1, 35:1, 36:1, 37:1, 38:1, 39:1, 40:1, etc. That is, when using this target gas for dry etching to remove... Figure 13 When the dummy gate 106 is made of polysilicon, the ratio of the etching rate of the dummy gate 106 to the etching rate of the first nitride layer sidewall 108 is between 30:1 and 40:1.

[0072] In this embodiment, by employing a target gas with an etching rate greater than a first preset ratio for polysilicon to nitride layer to remove the dummy gate from the polysilicon material using dry etching, the first nitride layer sidewall can be etched relatively slowly while removing the dummy gate. This avoids excessive damage to the first nitride layer sidewall while removing the dummy gate, keeping the damage to the first nitride layer sidewall within an acceptable range (e.g., within 5nm).

[0073] After that, as Figure 15 The diagram shown illustrates the removal of the target film layer in the semiconductor structure fabrication method provided in this application embodiment. The film layer can be removed by wet etching. Figure 14 The first nitride layer sidewall 108 is shown, and the oxide layer sidewall 110 is used as a stop layer for wet etching to remove the first nitride layer sidewall 108, resulting in... Figure 15 The structure is shown. Specifically, the sidewall 108 spanning the first nitride layer can be removed using wet etching with a target solution. Under the same etching conditions, the ratio of the etching rate of the target solution for the nitride layer to the etching rate for the oxide layer can be greater than or equal to a second preset ratio, where the second preset ratio is greater than 1. Thus, when the sidewall 108 spanning the first nitride layer is removed using wet etching with the target solution, the ratio of the etching rate of the first nitride layer sidewall 108 to the etching rate of the oxide layer sidewall 110 is greater than or equal to the second preset ratio, and the ratio of the etching rate of the first nitride layer sidewall 108 to the etching rate of the second oxide layer 104 on the fin surface is greater than or equal to the second preset ratio.

[0074] In this embodiment, by using a target solution where the ratio of the etching rate for the nitride layer to the etching rate for the oxide layer is greater than or equal to a second preset ratio, wet etching is employed to remove the first nitride layer sidewalls. This allows for relatively slow etching of the oxide layer sidewalls on both sides and the second oxide layer on the fin surface while removing the first nitride layer sidewalls. This avoids excessive damage to the oxide layer sidewalls on both sides and the second oxide layer on the fin surface during the removal of the first nitride layer sidewalls, keeping the damage to these areas within an acceptable range. Consequently, the resulting gate trench has a better morphology, reducing the likelihood of voids during subsequent metal filling. This ensures a good contact interface between the metal gate and the source / drain electrodes, reducing contact resistance and resulting in a device with better electrical signal characteristics, while also reducing parasitic capacitance and contact resistance.

[0075] Optionally, under the same etching conditions, the ratio of the etching rate of the target solution for the nitride layer to the etching rate for the silicon material can be greater than or equal to a third preset ratio. The third preset ratio is greater than 1. In this way, when using the target solution for wet etching to remove the sidewall 108 across the first nitride layer, excessive damage to the underlying silicon substrate and fins can be avoided.

[0076] For example, the target solution can be an 85% H3PO4 (phosphoric acid) solution, and the temperature can be between 150°C and 180°C. The temperature of the target solution can be any one of 150°C, 160°C, 170°C, 180°C, etc. The etching selectivity ratio of the target solution for the nitride layer and the oxide layer is between 90:1 and 110:1, for example, any one of 90:1, 92:1, 94:1, 96:1, 98:1, 100:1, 102:1, 104:1, 106:1, 108:1, 110:1, etc. That is, when using this target solution for wet etching to remove... Figure 14 When etching the first nitride layer sidewall 108, the ratio of the etching rate of the first nitride layer sidewall 108 to the etching rate of the oxide layer sidewall 110 is between 90:1 and 110:1. The etching selectivity ratio of this target solution for the nitride layer and silicon material is between 900:1 and 1100:1, for example, it can be any one of 900:1, 920:1, 940:1, 960:1, 980:1, 1000:1, 1020:1, 1040:1, 1060:1, 1080:1, 1100:1, etc. That is to say, when using this target solution for wet etching to remove… Figure 14When etching the first nitride layer sidewall 108, if the etching affects the silicon substrate or fin, the ratio of the etching rate of the first nitride layer sidewall 108 to the etching rate of the silicon substrate or fin is between 900:1 and 1100:1.

[0077] In this embodiment of the application, the first preset ratio, the second preset ratio, and the third preset ratio can be specifically set based on actual needs, and this application does not impose any restrictions on them.

[0078] As can be seen, when the dummy gate sidewall includes a first nitride layer sidewall, an oxide layer sidewall, and a second nitride layer sidewall, the first nitride layer sidewall is adjacent to the dummy gate, and the oxide layer sidewall is adjacent to the first nitride layer sidewall. Dry etching can remove the dummy gate with minimal damage to the first nitride layer sidewall, while wet etching can remove the first nitride layer sidewall with minimal damage to the oxide layer sidewall and the second oxide layer on the fin surface. This not only ensures the morphology of the sidewalls and bottom of the gate trench but also removes any remaining dummy gate residue during the removal of the first nitride layer sidewall, resulting in more thorough dummy gate removal. Furthermore, the remaining second oxide layer sidewall and second nitride layer sidewall on the gate trench sidewall improve adhesion and enhance structural stability.

[0079] Similarly, when the dummy gate sidewall includes a third nitride layer sidewall and a third oxide layer sidewall, the third nitride layer sidewall is adjacent to the dummy gate, and the third oxide layer sidewall is adjacent to the third nitride layer sidewall. Dry etching can remove the dummy gate with minimal damage to the third nitride layer sidewall, while wet etching can remove the third nitride layer sidewall with minimal damage to the third oxide layer sidewall and the second oxide layer on the fin surface. This not only preserves the morphology of the sidewalls and bottom of the gate trench but also removes any remaining dummy gate residue that was not completely removed during the removal of the first nitride layer sidewall, resulting in a more thorough removal of the dummy gate.

[0080] Optionally, when the dummy gate sidewall includes a fourth oxide layer sidewall, a fourth nitride layer sidewall, and a fifth oxide layer sidewall, the fourth oxide layer sidewall is adjacent to the dummy gate, and the fourth nitride layer sidewall is adjacent to the fourth oxide layer sidewall. The dummy gate can be removed by dry etching (e.g., using a combination of CH3F (fluoromethane) and He (helium) gas) with minimal damage to the fourth oxide layer sidewall and the second oxide layer at the bottom of the dummy gate. The fourth oxide layer sidewall can be removed by wet etching (e.g., using diluted hydrofluoric acid (DHF) or buffered oxide etchant (BOE, a mixture of HF and ammonium fluoride)) with minimal damage to the fourth nitride layer sidewall, thereby forming a gate trench.

[0081] Therefore, when the dummy gate sidewall is a composite film layer, removing the target film layer on the sidewall closest to the dummy gate after removing the dummy gate allows for the removal of any remaining dummy gate residue, resulting in a more thorough removal of the dummy gate. Furthermore, when removing the target film layer, the film layer adjacent to it in the dummy gate sidewall can be used as a stop layer, ensuring the sidewall morphology of the gate trench. This reduces the likelihood of voids when filling the gate trench with metal material, ensuring a good contact interface between the metal gate and the source / drain electrodes, reducing contact resistance, and resulting in a device with better electrical signal characteristics while lowering parasitic capacitance and contact resistance.

[0082] Step S106: Fill the gate trench with metal material to form a metal gate.

[0083] This step is used to form a metal gate. The metal material can be, for example, tungsten (W), cobalt (Co), etc.

[0084] In one specific example, the gate trench formed in step S105 can be directly filled with metal material to form a metal gate.

[0085] In another specific example, a high-k dielectric layer can be formed on the sidewall of the gate trench (i.e., the surface of the film layer adjacent to the target film layer in the pseudo-gate sidewall); a metal material is filled in the gate trench on which the high-k dielectric layer is formed to form a metal gate.

[0086] like Figure 16The diagram shown is a schematic diagram of forming a high dielectric constant dielectric layer on the sidewall of the gate trench in the semiconductor structure fabrication method provided in this application embodiment. A high dielectric constant dielectric layer 115 can be deposited on the surface of the oxide sidewall 110. The high dielectric constant dielectric layer 115 can be any one of the following materials: hafnium oxide (HfO2), zirconium oxide (ZrO2), lanthanum oxide (La2O3), yttrium oxide (Y2O3), and aluminum oxide (Al2O3).

[0087] like Figure 17 The diagram shown is a schematic diagram of filling the sidewall of the gate trench with metal material in the semiconductor structure fabrication method provided in this application embodiment. After forming a high dielectric constant dielectric layer 115 on the sidewall of the gate trench, metal material 116 (such as tungsten) can be filled in the gate trench where the high dielectric constant dielectric layer 115 is formed to form a metal gate.

[0088] In this embodiment, before filling the gate trench with metal material, a high-dielectric-constant dielectric layer is pre-formed on the sidewall of the gate trench. The high-dielectric-constant dielectric layer is separated from the adjacent dummy gate sidewall (e.g., Figure 17 The oxide layer sidewall 110 shown has better adhesion, which improves the stability of the structure.

[0089] The method for fabricating a semiconductor structure provided in this application includes the following steps: providing a semiconductor substrate; the semiconductor substrate having a plurality of discrete fins; forming a dummy gate across the fins on the semiconductor substrate; forming a dummy gate sidewall on the sidewall surface of the dummy gate; the dummy gate sidewall being a composite film layer; forming a first oxide layer on the outer side of the dummy gate; removing the dummy gate and a target film layer in the dummy gate sidewall near the dummy gate to form a gate trench; filling the gate trench with a metal material to form a metal gate. It can be seen that, because a composite film layer is formed on the sidewall surface of the dummy gate as a dummy gate sidewall, after removing the dummy gate, removing the target film layer in the dummy gate sidewall near the dummy gate can remove any remaining dummy gate residue that was not completely removed during the dummy gate removal process, resulting in a more thorough removal of the dummy gate. Furthermore, when removing the target film layer, the film layer adjacent to the target film layer in the dummy gate sidewall can be used as a stop layer, ensuring the sidewall morphology of the gate trench. Therefore, the semiconductor structure fabrication method provided in the first embodiment of this application can thoroughly remove dummy gates while maintaining the sidewall morphology of the gate trench. This makes it less likely for voids to form when filling the gate trench with metal material, thus ensuring a good contact interface between the metal gate and the source / drain electrodes, reducing contact resistance, and resulting in a device with better electrical signal characteristics, while reducing parasitic capacitance and contact resistance.

[0090] In a specific example, the semiconductor structure fabrication method provided in the first embodiment of this application can be applied to the fabrication of fin field-effect transistors. By forming a dummy gate sidewall with a composite film layer on the sidewall surface of the dummy gate used as a placeholder, after removing the dummy gate, the target film layer on the dummy gate sidewall closest to the dummy gate is removed, and the film layer adjacent to the target film layer in the dummy gate sidewall serves as a stop layer. This ensures both thorough removal of the dummy gate and the preservation of the sidewall morphology of the formed gate trench. Furthermore, the outer side of the metal gate formed after filling the gate trench with metal material is also attached with other film layers from the dummy gate sidewall besides the target film layer, improving adhesion and making the overall structure more stable. In addition, during source / drain ion implantation, the dummy gate sidewall acts as a barrier layer, preventing source / drain impurities from laterally diffusing into the fin channel in the gate trench, thereby preventing impurities from being incorporated into the fin channel and effectively suppressing the short-channel effect of the fin field-effect transistor.

[0091] The above is a detailed description of the method for preparing the semiconductor structure provided in the first embodiment of this application.

[0092] like Figure 18 The diagram shown is a flowchart of another method for fabricating a semiconductor structure according to the second embodiment of this application, including the following steps S201 to S206: Step S201: Provide a semiconductor substrate.

[0093] The semiconductor substrate refers to the basic material used to fabricate semiconductor structures. Unlike the first embodiment of this application, the semiconductor substrate provided in the second embodiment does not have multiple discrete fins formed on it.

[0094] Step S202: Form a first conductive structure on the semiconductor substrate.

[0095] Specifically, an initial first conductive structure can be obtained by depositing a conductive material on the surface of the semiconductor substrate (the surface of the semiconductor substrate may also have an oxide layer formed in advance). The conductive material may be, for example, polycrystalline silicon, metal, or other materials. Then, the region of the first conductive structure to be formed is defined on the initial first conductive structure by photolithography, and the conductive material in the initial first conductive structure other than the region of the first conductive structure to be formed is removed by etching, thereby forming the first conductive structure.

[0096] Step S203: A sidewall is formed on the sidewall surface of the first conductive structure; the sidewall is a composite film layer.

[0097] The sidewall formed here is similar to the pseudo-gate sidewall formed in the first embodiment of this application. It can be a nitride-oxide-nitride (NON) structure, an oxide-nitride-oxide structure, a nitride-oxide (NO) structure, or an oxide-nitride-oxide (ONO) structure. For a detailed description of the specific implementation of this step, please refer to the relevant description of the pseudo-gate sidewall in the first embodiment of this application; it will not be repeated here.

[0098] Step S204: A sixth oxide layer is formed on the outside of the first conductive structure.

[0099] The sixth oxide layer formed on the outside of the first conductive structure in this step is an interlayer dielectric layer. For details, please refer to the relevant description of the first oxide layer in the first embodiment of this application, which will not be repeated here.

[0100] Step S205: Remove the first conductive structure and the target film layer on the sidewall closest to the first conductive structure to form a trench.

[0101] This step is used to thoroughly remove the first conductive structure, thereby forming a trench with a good morphology on the semiconductor substrate. The specific implementation of this step can be found in the description of step S105 in the first embodiment of this application, and will not be repeated here.

[0102] In this embodiment, when the sidewall is a composite film layer, after removing the first conductive structure, removing the target film layer on the side of the dummy gate sidewall closest to the first conductive structure allows for the removal of any residual first conductive structure that was not completely removed during the initial removal, resulting in a more thorough removal of the first conductive structure. Furthermore, when removing the target film layer, the film layer adjacent to the target film layer in the sidewall can be used as a stop layer, ensuring the correct sidewall morphology of the formed trench. This reduces the likelihood of voids being generated when filling the trench with conductive material.

[0103] Step S206: Fill the trench with conductive material to form a second conductive structure.

[0104] The conductive material corresponding to the second conductive structure may be different from the conductive material corresponding to the first conductive structure. For example, the first conductive structure is polycrystalline silicon, and the second conductive structure is tungsten.

[0105] In this embodiment, the second conductive structure can be formed by directly filling the trench with conductive material, or a high dielectric constant layer can be formed first on the sidewall surface of the trench, and then conductive material can be filled in it to form the second conductive structure. The specific implementation of this step can be found in the description of step S106 in the first embodiment of this application, and will not be repeated here.

[0106] The second embodiment of this application provides another method for fabricating a semiconductor structure, comprising: providing a semiconductor substrate; forming a first conductive structure on the semiconductor substrate; forming a sidewall on the sidewall surface of the first conductive structure; the sidewall being a composite film layer; forming a sixth oxide layer on the outside of the first conductive structure; removing the first conductive structure and a target film layer in the sidewall near the first conductive structure to form a trench; and filling the trench with a conductive material to form a second conductive structure. It can be seen that, since a sidewall of a composite film layer is formed on the sidewall surface of the first conductive structure, removing the target film layer in the sidewall near the first conductive structure after removing the first conductive structure can remove any remaining first conductive structure material that was not completely removed during the removal of the first conductive structure, resulting in a more thorough removal of the first conductive structure. Furthermore, when removing the target film layer, the film layer adjacent to the target film layer in the sidewall can be used as a stop layer, ensuring the sidewall morphology of the formed trench. Therefore, the second embodiment of this application provides another method for fabricating a semiconductor structure that can thoroughly remove the first conductive structure while ensuring the trench sidewall morphology. In this way, voids are less likely to occur when filling the trench with conductive material to form a second conductive structure.

[0107] The second embodiment of this application provides another method for preparing a semiconductor structure that can be applied to the manufacture of fin field-effect transistors. This application does not specifically limit the application scenario.

[0108] The third embodiment of this application provides a semiconductor device, which can be prepared by the semiconductor structure preparation method provided in the first embodiment of this application or the semiconductor structure preparation method provided in the second embodiment of this application. For details, please refer to the detailed description of the semiconductor structure preparation method provided in the first embodiment of this application or the semiconductor structure preparation method provided in the second embodiment of this application, which will not be repeated here.

[0109] Although this application discloses preferred embodiments as described above, it is not intended to limit this application. Any person skilled in the art can make possible changes and modifications without departing from the spirit and scope of this application. Therefore, the scope of protection of this application should be determined by the scope defined in the claims of this application.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, The method includes: A semiconductor substrate is provided; the semiconductor substrate has a plurality of discrete fins; A dummy gate is formed across the fin on the semiconductor substrate; the dummy gate is made of polycrystalline silicon. A pseudo-gate sidewall is formed on the sidewall surface of the pseudo-gate; the pseudo-gate sidewall is a composite film layer; the pseudo-gate sidewall includes a first nitride layer sidewall on the sidewall surface of the pseudo-gate, an oxide layer sidewall on the sidewall surface of the first nitride layer sidewall, and a second nitride layer sidewall on the sidewall surface of the oxide layer sidewall. A first oxide layer is formed on the outside of the dummy gate; Removing the dummy gate and the target film layer near the dummy gate sidewall to form a gate trench includes: removing the dummy gate using a target gas dry etching process, and removing the first nitride layer sidewall using a target solution wet etching process; the ratio of the etching rate of the target gas on polysilicon to the etching rate on the nitride layer is greater than or equal to a first preset ratio; the ratio of the etching rate of the target solution on the nitride layer to the etching rate on the oxide layer is greater than or equal to a second preset ratio. Metal material is filled into the gate trench to form a metal gate.

2. The method according to claim 1, characterized in that, The process of forming a dummy gate sidewall on the sidewall surface of the dummy gate includes: A first nitride layer sidewall is formed on the sidewall surface of the dummy gate; An oxide layer sidewall is formed on the sidewall surface of the first nitrided layer sidewall; A second nitride layer sidewall is formed on the sidewall surface of the oxide layer sidewall; wherein the first nitride layer sidewall, the oxide layer sidewall, and the second nitride layer sidewall constitute the pseudo gate sidewall.

3. The method according to claim 2, characterized in that, The formation of a first nitride layer sidewall on the sidewall surface of the dummy gate includes: A first nitride layer is formed on the substrate surface and the dummy gate surface; Remove the first nitride layer from the substrate surface and the top surface of the dummy gate to form a first nitride layer sidewall; The process of forming an oxide layer sidewall on the sidewall surface of the first nitrided layer sidewall includes: An oxide layer is formed on the substrate surface, the sidewall surface of the first nitride layer, and the dummy gate surface; Remove the oxide layer from the substrate surface, the top surface of the first nitride layer sidewall, and the top surface of the dummy gate to form an oxide layer sidewall; The formation of a second nitrided layer sidewall on the sidewall surface of the oxide layer sidewall includes: A second nitride layer is formed on the substrate surface, the oxide layer sidewall surface, the first nitride layer sidewall surface, and the dummy gate surface; The second nitride layer is formed by removing the second nitride layer from the substrate surface, the top surface of the oxide layer sidewall, the top surface of the first nitride layer sidewall, and the top surface of the dummy gate.

4. The method according to claim 2, characterized in that, The target film is the sidewall of the first nitrided layer.

5. The method according to claim 2, characterized in that, The dummy gate is made of polycrystalline silicon; the process of removing the dummy gate and the target film layer on the sidewall of the dummy gate near the dummy gate to form a gate trench includes: The dummy gate is removed by dry etching, and the first nitride layer sidewall is removed by wet etching to form a gate trench.

6. The method according to claim 1, characterized in that, The step of filling the gate trench with metal material to form a metal gate includes: A high dielectric constant dielectric layer is formed on the sidewall of the gate trench; A metal gate is formed by filling the gate trench, in which a high dielectric constant dielectric layer is formed on the sidewall, with a metal material.

7. The method according to claim 1, characterized in that, The formation of a dummy gate across the fin on the semiconductor substrate includes: A second oxide layer is formed on the surface of the semiconductor substrate and the surface of the fin; A pseudo-gate is formed across the fin on the second oxide layer.

8. A method for fabricating a semiconductor structure, characterized in that, The method includes: Provide semiconductor substrates; A first conductive structure is formed on the semiconductor substrate; the first conductive structure is made of polycrystalline silicon. A sidewall is formed on the sidewall surface of the first conductive structure; the sidewall is a composite film layer; the sidewall includes a first nitrided layer sidewall, an oxide layer sidewall on the sidewall surface of the first nitrided layer sidewall, and a second nitrided layer sidewall on the sidewall surface of the oxide layer sidewall. A sixth oxide layer is formed on the outside of the first conductive structure; Removing the first conductive structure and the target film layer on the sidewall closest to the first conductive structure to form a trench includes: removing the first conductive structure using a target gas dry etching process, and removing the first nitride layer sidewall using a target solution wet etching process; the ratio of the etching rate of the target gas for polysilicon to the etching rate for the nitride layer is greater than or equal to a first preset ratio; the ratio of the etching rate of the target solution for the nitride layer to the etching rate for the oxide layer is greater than or equal to a second preset ratio. The trench is filled with conductive material to form a second conductive structure.

9. A semiconductor device, characterized in that, It is prepared by the method described in any one of claims 1 to 8.

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