A cadmium telluride absorption layer of a specific pattern structure and a solar cell manufacturing method

Abstract

The application discloses a cadmium telluride absorption layer with a specific pattern structure and a solar cell preparation method. The method uses a laser and a specific shape of a photo mask to prepare a conductive template array with a specific pattern structure on the surface of cadmium telluride. The specific pattern structure includes the following features: a sidewall angle > 80 degrees, a complete etching area of a hole bottom accounts for 24-85% of the total area, and a micrometer-level regular conductive template array forms a directional carrier transport channel. The conductive template array with the specific pattern structure is directly prepared on the surface of cadmium telluride, the balance between passivation and conductivity is optimized, the process flow is simplified, and the device efficiency is improved.

Description

Technical Field

[0001] This invention belongs to the field of solar cell technology, specifically relating to a cadmium telluride absorber layer with a specific pattern structure and a method for preparing solar cells. Background Technology

[0002] In the fabrication of CdTe thin-film solar cells, the cadmium chloride thermal treatment process has been proven to be a key step in improving the efficiency of cadmium telluride cells. Commonly used wet processes employ a cadmium chloride solution, which is applied to the cadmium telluride surface via spraying, roller coating, or immersion, followed by annealing at 300-550°C in an atmospheric or protective atmosphere. However, after the cadmium chloride thermal treatment, an oxide layer (such as TeO2 or CdO) inevitably forms on the surface of cadmium telluride. This oxide layer significantly increases interfacial resistance and hinders carrier transport. How to remove the oxide layer while maintaining the integrity and doping effect of the cadmium telluride film has become a pressing technical challenge.

[0003] The most common technique for removing oxide layers in existing technologies is chemical etching, especially acid etching. This method mainly uses strong acid solutions such as nitric acid and hydrochloric acid to etch the oxide layer for rapid removal. However, this technique suffers from the difficulty in precisely controlling the acid concentration, which may increase the surface roughness of cadmium telluride, thereby reducing the continuous coverage of the back contact layer and leading to enhanced back surface composite. Researchers have further proposed a method for physical etching of cadmium telluride surfaces. Typically, this process utilizes vacuum equipment to physically bombard the cadmium telluride film surface with plasma to remove the oxide layer. In recent years, with the advancement of laser processing technology, it has gradually become a key technology replacing traditional chemical etching and physical etching.

[0004] Patent CN 114695082 A discloses a method for treating the oxide layer formed after the conductive layer is exposed. This patent uses a hydrogen fluoride solution to clean and remove the oxide layer, and it is applied to the fabrication process of metal-insulator-metal integrated capacitors. Hydrogen fluoride is highly corrosive, penetrating, and extremely toxic, and its danger far exceeds that of ordinary acids, making it unfavorable for industrial production in terms of safety, process reliability, and environmental friendliness. Patent CN 119698136 A discloses a surface treatment technology applied to cadmium telluride absorber layers. This technology removes the oxide layer on the surface of cadmium telluride through laser etching, thereby forming a pyramid-shaped light-trapping structure. This method effectively enhances light reflection, thereby enhancing light absorption performance, and promotes the formation of excellent ohmic contact between the absorber layer and the back contact layer, thus reducing series resistance and increasing short-circuit current.

[0005] With the continuous development of laser technology, its application in thin film surface processing is expanding. Compared to chemical etching, laser etching technology has significantly improved etching precision and resolution, effectively avoiding the drilling problems that occur during chemical etching, and significantly reducing the risk of thin film surface damage. Patent CN 119698136 A discloses a surface treatment technology for cadmium telluride absorption layers. This technology uses laser etching to construct a pyramid-shaped light-trapping structure on the cadmium telluride surface. Although the traditional tetrahedral pyramid structure can improve light absorption efficiency, the number of reflections is limited to 1-2 times, resulting in high reflectivity. This structure significantly increases the surface area of ​​cadmium telluride (approximately 3-5 times), leading to an exponential increase in surface defect density, which in turn increases the carrier recombination rate. Furthermore, the sloping sidewalls of the tetrahedral pyramid make the carrier path more circuitous, increasing the recombination probability, which severely limits the improvement of device performance.

[0006] Currently, cadmium telluride surface oxide layer treatment technology faces several challenges, including the contradiction between oxide layer removal efficiency and quality, the imbalance between passivation effect and conductivity, and the complexity and high cost of the process. Laser processing technology offers new possibilities for solving these problems. Its high precision, high efficiency, and non-contact processing characteristics make it an important means to improve surface oxide layer treatment. Summary of the Invention

[0007] This invention provides a cadmium telluride absorber layer with a specific pattern structure and a method for fabricating solar cells. By using a combination of laser and photomask technology, a conductive template array with a specific pattern structure is directly fabricated on the surface of cadmium telluride, which optimizes the balance between passivation and conductivity, simplifies the process, and improves device efficiency.

[0008] To achieve the above objectives, in a first aspect, the present invention provides a cadmium telluride absorption layer with a specific pattern structure. By using a laser and a photomask in combination, a conductive template array with a specific pattern structure is prepared on the surface of cadmium telluride. The specific pattern structure includes the following features: sidewall angle > 80 degrees, the completely etched area at the bottom of the holes accounts for 24-85% of the total area, and the micron-sized regular conductive template array forms a directional carrier transport channel.

[0009] Preferably, the light-transmitting holes of the photomask are one of square, circular, hexagonal, triangular, rhomboid, or mixed shapes, and the mixed shapes include any two of square, circular, hexagonal, triangular, and rhomboid shapes; And / or, the photomask is composed of a substrate layer and a light-shielding film layer, wherein the substrate layer material of the photomask is selected from at least one of synthetic quartz glass, low-expansion borosilicate glass and soda glass; the light-shielding film layer of the photomask is a double-layer composite, wherein the upper material is chromium, oxygen, nitrogen and carbon with a thickness of 3~10nm; and the lower material is pure chromium with a thickness of 20~50nm. Alternatively, the light-transmitting holes of the photomask are square with a side length of 1~20μm, forming an array with a gap size of 1~20μm; the distance between the photomask and the cadmium telluride layer is 10~50 μm; Alternatively, the average surface roughness of the cadmium telluride absorbing layer is 6-26 nm, and the weighted average reflectivity is 7-15%; the EQE in the long-wavelength region is 70-86%.

[0010] Secondly, the present invention provides a surface treatment process for the aforementioned cadmium telluride absorber layer, comprising the following steps: (1) Clean the cadmium telluride layer after cadmium chloride annealing to remove the residual cadmium chloride on the surface and dry it with compressed gas; (2) The dried cadmium telluride layer is covered using a photomask. (3) After the cadmium telluride layer is covered, the oxide layer is selectively etched using a high-energy laser beam to form a conductive template array with a specific pattern structure.

[0011] Preferably, the photomask consists of a substrate layer and a light-shielding film layer. The substrate layer material of the photomask is selected from at least one of synthetic quartz glass, low-expansion borosilicate glass, and soda glass. The light-shielding film layer of the photomask is a double-layer composite material. The upper layer material is chromium-oxygen-nitrogen-carbon, which contains chromium (Cr), oxygen (O), nitrogen (N), and carbon (C) elements. Its composition, by mass percentage (wt%), meets the following range: chromium (Cr): 40%-70%, oxygen (O): 10%-40%, nitrogen (N): 5%-30%, carbon (C): 1%-15%, and the sum of the contents of each group is 100%, with a thickness of 3-10 nm. The lower layer material is pure chromium with a thickness of 20-50 nm.

[0012] Preferably, the light-transmitting holes of the photomask are a square array with a side length of 1~20 μm and a gap size of 1~20 μm; the distance between the photomask and the cadmium telluride layer is 10~50 μm.

[0013] Preferably, the wavelength of the high-energy laser beam is 300~700 nm, the high-energy laser beam is a pulsed laser, the pulse width of the pulsed laser is 7 ns~1 μs, the frequency of the pulsed laser is 20~150 KHz, and the scanning speed of the pulsed laser is 1000-5000 mm / s.

[0014] Thirdly, the present invention provides a method for preparing a cadmium telluride thin-film solar cell, the cadmium telluride thin-film solar cell comprising a glass substrate, a transparent conductive layer, a window layer, a back contact layer, a metal electrode layer, and a cadmium telluride absorber layer with a specific pattern structure, comprising the following steps: S1. Deposit a transparent conductive layer on a glass substrate; S2. Deposit a window layer on the transparent conductive layer; S3. Deposit a cadmium telluride absorption layer on the window layer; S4. Deposit cadmium chloride on the surface of cadmium telluride; S5. Annealing treatment is performed on cadmium telluride with cadmium chloride coating on the surface. S6. After annealing cadmium chloride, perform the surface treatment process described above to obtain a patterned cadmium telluride absorber layer. S7. On the patterned cadmium telluride absorber layer surface, a back contact layer and a metal electrode layer are deposited sequentially. S8. After deposition, metallization annealing is performed to obtain cadmium telluride thin-film solar cells.

[0015] Preferably, in step S1, the glass substrate is selected from soda-lime glass; And / or, in step S2, the transparent conductive layer deposition method is chemical vapor deposition or sputtering. And / or, the material of the transparent conductive layer is selected from at least one of fluorine-doped tin oxide, tin-doped indium oxide, and aluminum-doped zinc oxide; And / or, the deposition method of the window layer is selected from at least one of magnetron sputtering, thermal evaporation, near-space sublimation and gas phase transport; And / or, the material of the window layer is selected from at least one of cadmium sulfide, cadmium selenide, zinc oxide, magnesium-doped zinc oxide, indium oxide, gallium oxide, and indium gallium oxide; And / or, the thickness of the window layer is 10~300 nm.

[0016] Preferably, in step S3, the deposition method of the absorption layer is one of vacuum thermal evaporation, near-space sublimation, or gas phase transport. During the deposition of the absorption layer, the source temperature is 600~1200℃ and the substrate temperature is 400~600℃. The "source temperature" is an indirect but core control parameter in the thermal evaporation deposition process. It specifically refers to the equilibrium temperature reached by the evaporation source (the crucible / boat containing cadmium telluride powder or particles) when heated. In actual operation, this temperature is usually measured and controlled by a thermocouple placed close to the evaporation source container.

[0017] The absorber layer is made of cadmium telluride and has a thickness of 2-5 μm.

[0018] Preferably, in step S4, the deposition method of cadmium chloride is one of thermal evaporation, spraying, roller coating, or immersion. In step S5, the annealing temperature of the cadmium chloride is 300~550℃, and the annealing time is 10~50min.

[0019] Preferably, in step S7, the deposition method of the back contact layer and the metal electrode layer is selected from thermal evaporation or magnetron sputtering; The material of the back contact layer is selected from at least one of zinc telluride, copper-doped zinc telluride, or group V element-doped zinc telluride. The thickness of the back contact layer is 10~100nm; The material of the metal electrode layer is selected from at least one of molybdenum, aluminum, chromium, silver, copper or nickel; In step S8, the temperature of the metallization annealing treatment is 100~300℃, and the annealing time is 10~40min.

[0020] The beneficial effects of this invention are as follows: 1. This invention utilizes a combination of laser and photomask technology to directly fabricate a conductive template array with a specific pattern structure on the surface of cadmium telluride, aiming to achieve the following objectives: (1) By removing the oxide layer and constructing conductive channels in one step, the surface damage and environmental pollution caused by chemical corrosion can be effectively avoided.

[0021] (2) Construct a regular array to precisely control the carrier transport path and form directional carrier channels on the surface of the passivation layer to reduce the recombination probability.

[0022] (3) The conductive template array with a specific pattern structure can precisely control the light, and the vertical sidewall structure realizes multiple reflection paths, thereby reducing the surface reflectivity and increasing the effective optical path.

[0023] (4) By optimizing the geometric configuration of the regular array and controlling the passivation-conductivity region, the carrier transport path and surface recombination rate are adjusted to achieve a balance between passivation and conductivity, thereby improving the open-circuit voltage and fill factor of the battery.

[0024] 2. The cadmium telluride thin-film solar cells prepared by this invention improve photovoltaic performance. Compared with traditional acid washing, physical etching, and laser processes, it significantly reduces back surface damage and the concentration of defects on the back surface. The optimized conductive template array increases the device fill factor by ≥5% and the open-circuit voltage by 50 mV. Furthermore, the process flow is optimized by using a dry one-step method to remove the oxide layer and form patterns, replacing the traditional acid washing process and reducing waste liquid discharge by 90%. Attached Figure Description

[0025] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 This is a schematic diagram of the cadmium telluride absorber layer structure provided in an embodiment of the present invention; Figure 2 A process flow diagram of a cadmium telluride thin-film solar cell provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of the CdTe thin film provided in Embodiment 1 of the present invention. It features a 10×10μm light-shielding template unit array and a light-shielding area size of 1μm×1μm×25; the duty cycle is 25%. Figure 4 This is a schematic diagram of the CdTe thin film provided in Embodiment 2 of the present invention. The light-shielding template unit array has a 10×10μm structure, and the size of the light-shielding area is 2μm×2μm×9; the duty cycle is 36%. Figure 5 This is a schematic diagram of the CdTe thin film provided in Embodiment 3 of the present invention. The light-shielding template unit array has a 10×10μm structure, and the size of the light-shielding area is 3μm×3μm×4+3μm×1μm×4; the duty cycle is 48%. Figure 6 This is a schematic diagram of the CdTe thin film provided in Embodiment 4 of the present invention. The light-shielding template unit array has a 10×10μm structure, and the size of the light-shielding area is 4μm×4μm×4; the duty cycle is 64%. Explanation of reference numerals in the attached figures: 1. Substrate layer; 101. Glass substrate; 102. Transparent conductive layer; 103. Window layer; 104. Absorption layer; 105. Oxide layer; 106. Back contact layer; 107. Metal electrode layer; 2. Light-shielding film layer; 201. Light-shielding hole; 202. Light-shielding area; S41. Water washing; S43. Laser etching; S5. Back contact layer preparation; S6. Metal electrode preparation. Detailed Implementation

[0027] In this invention, unless otherwise stated, directional terms such as "up," "down," "left," and "right" are generally understood in conjunction with the accompanying drawings and the directions shown in actual applications.

[0028] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0029] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "over," and "on top" of the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0030] The endpoints and any values ​​of the ranges disclosed herein are not limited to the precise ranges or values, and should be understood to include values ​​close to these ranges or values. For numerical ranges, the endpoint values ​​of the various ranges, the endpoint values ​​of the various ranges and individual point values, and individual point values ​​can be combined with each other to obtain one or more new numerical ranges, which should be considered as specifically disclosed herein. The terms "optional" and "discretionary" mean that they may or may not be included (or may or may not be present).

[0031] The applicant of this invention has discovered that the existing cadmium telluride surface oxide layer treatment technology faces several problems, including the contradiction between oxide layer removal efficiency and quality, the imbalance between passivation effect and conductivity, and the problems of process complexity and high cost.

[0032] The contradiction between removal efficiency and surface quality specifically manifests as follows: While strong etchants like concentrated HNO3 and Br2 / methanol can quickly remove the oxide layer, they easily cause surface roughness, Cd / Te composition imbalance, and the introduction of lattice defects or micropores. Current treatment methods employ milder approaches, such as using dilute KI / I2 or low-concentration acids, which, while protecting the surface, are incompletely effective at removing thicker or denser oxide layers. Another imbalance exists between passivation effect and conductivity. Specifically, to reduce the surface density of states (Dit) and further suppress carrier recombination, wide-bandgap insulating / semiconductor layers such as Al2O3, MgF2, and CdS are introduced, or chemical passivation such as chalcogenide treatment is performed. However, this increases the interfacial barrier, hindering carrier transport and reducing conductivity. To achieve low contact resistance and efficient carrier extraction, ohmic contacts such as Cu / Au doping or graphite back electrodes are formed, further preserving the highly doped surface. However, this easily introduces deep-level defects, exacerbating surface recombination and weakening the passivation effect.

[0033] To address the aforementioned problems, this invention provides a cadmium telluride (CdT) absorber layer with a specific pattern structure. Utilizing a technique combining laser and a photomask of a specific shape, a conductive template array with a specific pattern structure is fabricated on the CdT surface. This specific pattern structure includes the following characteristics: sidewall angle > 80 degrees; a fully etched area occupying 24-85% of the total area, which can be any one or both of the following values: 24%, 30%, 35%, 40%, 45%, 50%, 55%, 60%, 65%, 70%, 75%, 80%, and 85%; and a micron-sized, regularly spaced conductive template array forming directional carrier transport channels. The average surface roughness of the CdT absorber layer is 6-26 nm, the weighted average reflectivity is 7-15%, and the EQE in the long-wavelength region is 70-86%.

[0034] The specific pattern structure in this invention has the following characteristics: (1) The sidewall design is steep, with a sidewall angle greater than 80 degrees (while the sidewall angle of plasma treatment is generally less than 80 degrees). By reducing the ineffective surface area, the increase in specific surface area is controlled within the range of 1.8 to 2.2 times. The hole structure reduces surface reflectivity and increases effective optical path through multiple reflections and absorption of light. (2) The proportion of the completely etched area at the bottom of the hole to the total area (duty cycle) is 24-85%. The complete etching at the bottom of the hole (conductive contact) and the oxide layer (passivation) retained between the holes work together to achieve precise partitioning of the passivation area and the conductive area. Through the synergistic optimization of the two, the precise layout of the micron-level island structure and the hole structure is achieved, thereby significantly enhancing the balance between the passivation effect and the conductivity. (3) The regular and orderly design enables the micron-level regular conductive template array to form a directional carrier transport channel, reducing the probability of carrier transport detours, effectively reducing the lateral diffusion distance of carriers, reducing carrier recombination loss, and improving the open circuit voltage and photoelectric conversion efficiency of cadmium telluride solar cells.

[0035] This invention also provides a method for preparing a cadmium telluride absorber layer, comprising the following steps: (1) Clean the cadmium telluride layer after cadmium chloride annealing with a cleaning solution to remove the residual cadmium chloride on the surface of cadmium telluride; (2) The cleaned cadmium telluride layer is thoroughly dried using dry compressed gas; (3) The dried cadmium telluride layer is covered using a photomask with a specific pattern; (4) After the cadmium telluride layer is covered, the oxide layer is selectively etched using a high-energy beam to form a conductive template array with different patterns.

[0036] In this embodiment, a high-energy laser beam is used to selectively etch the oxide layer. High-energy laser beams can achieve micron- or even sub-micron-level processing precision. Furthermore, it allows for precise control of the etching area, removing only the oxide layer at the target location without damaging the underlying CdTe functional layer. Laser etching is a non-contact process, avoiding particle contamination, scratches, or stress defects that may be introduced by traditional mechanical or chemical methods. This stress-free processing method is particularly important for the brittle thin-film material cadmium telluride. By adjusting the laser wavelength, energy density, and pulse width, the difference in optical absorption or thermal response between the oxide layer and CdTe can be utilized to achieve selective removal of the oxide layer. Surface oxide layers typically have high resistance or insulating properties, hindering carrier transport. Selective removal of the oxide layer exposes a clean CdTe surface, which is beneficial for subsequent metal electrode deposition or heterojunction formation, reducing contact resistance and improving device efficiency. Laser processing can also slightly melt or reconstruct the CdTe surface while removing the oxide layer, contributing to the formation of a denser, low-defect interface. Combined with subsequent passivation processes, device performance can be further improved.

[0037] In one embodiment of the present invention, the cleaning liquid in step (1) includes ultrapure water with a resistivity >18 MΩ·cm. After cadmium chloride annealing, unreacted CdCl2 and oxides such as TeO2 often remain on the CdTe surface. Ultrapure water has extremely low ion content, which can effectively dissolve and wash away these soluble salts and ionic impurities, avoiding their formation of complex centers or interface defects in subsequent processes. Ultrapure water with a resistivity >18 MΩ·cm contains almost no ionic or organic pollutants, minimizing secondary pollution. Ultrapure water has a near-neutral pH and contains no strong acid / alkali components, so it will not corrode or over-oxidize the CdTe surface. In contrast, water containing Cl... - SO4² - Cleaning solutions containing organic solvents may induce surface Te precipitation or Cd dissolution, disrupting lattice integrity. A clean surface after cleaning facilitates uniform deposition of the back electrode, achieving good ohmic contact and further improving device repeatability and yield. Residual impurities can lead to uneven contact resistance, localized short circuits, or increased leakage current.

[0038] In one embodiment of the present invention, the drying gas in step (2) is selected from clean, dry compressed air or dry nitrogen. Although ultrapure water is clean, if it evaporates naturally, trace impurities (such as dissolved CO2 forming carbonic acid or dust settling in the air) may still leave water stains or particles on the CdTe surface. Dry gas can quickly blow away the liquid film, achieving residue-free drying and keeping the surface clean. CdTe is prone to slow oxidation in humid environments, generating insulating byproducts such as TeO2 or Cd(OH)2, which affect subsequent electrode contact. Nitrogen is an inert gas that can further isolate oxygen and water vapor, providing a protective atmosphere while drying and inhibiting surface oxidation. Dry compressed air, if subjected to strict degreasing, dehydration, and filtration treatment, can also effectively reduce the risk of oxidation, but it is not as ideal as nitrogen.

[0039] In one embodiment of the present invention, the photomask in step (3) has a size of 10 mm × 10 mm, a thickness of 6.35 ± 0.1 mm, and a side length tolerance of ± 0.05 mm. The photomask defines the desired pattern, and the high-energy beam only acts on the unmasked area. This enables the achievement of micron-level or even submicron-level pattern resolution, meeting the requirements of high-density integration, monolithic interconnection, or local doping. CdTe surfaces often naturally form insulating oxides (such as TeO2, CdO), which hinder carrier transport. The high-energy beam has tunable parameters (wavelength, energy density, pulse width), allowing it to preferentially interact with the oxide layer while causing minimal damage to the underlying CdTe layer. The mask-protected area remains completely unaffected, ensuring the stability of the surface state in the non-etched area.

[0040] In one embodiment of the present invention, the photomask in step (3) consists of a substrate layer and a light-shielding film layer. The substrate material of the photomask is selected from at least one of synthetic quartz glass, low-expansion borosilicate glass, and soda ash glass. The selection of the substrate material is crucial to the accuracy, thermal stability, light transmittance, and service life of the mask. Synthetic quartz glass has an extremely low coefficient of thermal expansion (~0.55 × 10⁻⁶). -6 (℃), exhibiting excellent dimensional stability at high temperatures and high transmittance, making it suitable for precise laser etching; it possesses high purity, is bubble-free, and free of impurity metal ions, avoiding contamination; it also boasts a high laser damage threshold, making it suitable for repeated irradiation by high-energy beams. Low-expansion borosilicate glass has a low coefficient of thermal expansion, superior to ordinary glass, moderate cost, good mechanical strength, and a certain transmittance in the visible to near-ultraviolet range. Soda ash glass offers the advantages of lowest cost, ease of processing, and good visible light transmittance.

[0041] In one embodiment of the present invention, the light-shielding film layer of the photomask in step (3) is a double-layer composite material. The upper layer material is chromium-oxygen-nitrogen-carbon, which contains chromium (Cr), oxygen (O), nitrogen (N) and carbon (C) elements. Its composition, in terms of mass percentage (wt%), meets the following range: chromium (Cr): 40%-70%, oxygen (O): 10%-40%, nitrogen (N): 5%-30%, carbon (C): 1%-15%, and the sum of the contents of each group is 100%. The thickness is 3~10nm, which can be one or any two of the ranges of 3nm, 4nm, 5nm, 6nm, 7nm, 8nm, 9nm, 10nm; the lower layer material is pure chromium, with a thickness of 20~50nm, which can be one or any two of the ranges of 20nm, 25nm, 30nm, 35nm, 40nm, 45nm, 50nm. The dual-layer structure enables high-precision patterning through selective wet or dry etching. The CrONC layer can be rapidly removed with a specific etchant, while the Cr layer remains, or anisotropic pattern transfer can be further achieved using plasma etching. If mask defects occur, the CrONC surface layer is easily repaired using focused ion beams or lasers. The CrONC layer is a tunable anti-reflective coating; by controlling the O / N / C content, its refractive index and extinction coefficient can be precisely adjusted to achieve minimum reflectivity at specific laser wavelengths. This reduces multiple reflections and scattering of light on the mask surface, avoiding "halo effects" or interference from adjacent patterns, and further improves edge sharpness and resolution during etching. The lower pure Cr layer provides high optical density, ensuring complete light shielding and preventing light leakage that could lead to accidental etching of non-target areas. Under high-energy pulsed laser irradiation, the single-layer Cr film is prone to melting, peeling, or oxidation due to heat accumulation. The CrONC surface layer possesses a higher melting point, hardness, and chemical inertness, enabling the formation of a ceramic-like structure through nitrogen / carbon doping, which further enhances the thermal stability of the photomask. The presence of oxygen passivates the surface, inhibiting further oxidation and effectively dispersing laser energy, thus reducing thermal stress concentration. The pure Cr underlayer provides excellent adhesion and thermal conductivity, rapidly transferring heat to the substrate.

[0042] In one embodiment of the present invention, in step (3), the light-transmitting area of ​​the photomask is a square array with a side length of 1~20 μm, which can be one or any two of the following values: 1μm, 2μm, 3μm, 4μm, 5μm, 6μm, 7μm, 8μm, 9μm, 10μm, 11μm, 12μm, 13μm, 14μm, 15μm, 16μm, 17μm, 18μm, 19μm, 20μm; the gap size is 1~20 μm. μm can be any one or both of the following values: 1μm, 2μm, 3μm, 4μm, 5μm, 6μm, 7μm, 8μm, 9μm, 10μm, 11μm, 12μm, 13μm, 14μm, 15μm, 16μm, 17μm, 18μm, 19μm, and 20μm; further enabling high-density local processing. The square transparent array allows high-energy beams to selectively act on the CdTe surface oxide layer only in a predetermined micro-region. The high array density is suitable for realizing surfaces with high-efficiency, high-fill-factor microstructures. Carrier collection and current paths have been further optimized. In CdTe solar cells, the square lattice ohmic contact can shorten the lateral diffusion distance of minority carriers, reduce bulk recombination losses, and improve the short-circuit current (J). sc The microarray contacts achieve a better balance between electrical performance and optical loss compared to traditional continuous strip electrodes. The periodic microstructures can excite diffraction, scattering, or surface plasmon resonance effects, extending the optical path and enhancing the capture of near-bandgap photons by the CdTe absorption layer; this is particularly beneficial for utilizing weak absorption bands. The square discretized microarray structure allows the material to expand and contract freely at the gaps, further reducing overall stress accumulation and improving device reliability. The square design makes it easier to align crystal orientations or subsequent electrode grids than a circular design, improving consistency during manufacturing. The distance between the photomask and the cadmium telluride layer is 10~50 μm, which can be one or any two of the following values: 10μm, 12μm, 14μm, 16μm, 18μm, 20μm, 22μm, 24μm, 26μm, 28μm, 30μm, 32μm, 34μm, 36μm, 38μm, 40μm, 42μm, 44μm, 46μm, 48μm, and 50μm. Maintaining a large distance between the photomask and the CdTe layer can avoid direct contact between the photomask and the CdTe film, prevent particles and debris on the photomask surface from scratching the CdTe surface, prevent the photomask material from falling off due to friction and contaminating the entire device, and prevent the flexible or brittle CdTe layer from developing microcracks or peeling off due to pressure. When a high-energy beam acts on CdTe, it will generate local high temperature. If the photomask is close to the cadmium telluride layer, it may absorb scattered / reflected energy and heat up, causing thermal deformation of the substrate and thermal stress cracking or oxidation of the photomask. A larger spacing can provide thermal isolation space to ensure the stability of the mask size and the accuracy of the pattern.

[0043] In one embodiment of the present invention, the wavelength of the laser in step (4) is 300~700 nm, which can be a single wavelength or any combination of both. Different wavelengths correspond to different light-matter interaction mechanisms, thus giving the technology unique advantages in terms of material selectivity, processing precision, and process compatibility. By precisely selecting the wavelength, the photon energy can be made slightly higher than the oxide bond energy but lower than or close to the CdTe bulk damage threshold, achieving preferential photolysis of the oxide layer without significantly damaging the CdTe lattice. The pulse width of the pulsed laser is 7 ns~1 μs, which can be one or any combination of 7 ns, 107 ns, 207 ns, 307 ns, 407 ns, 507 ns, 607 ns, 707 ns, 807 ns, 907 ns, and 1 μs. Within this range, the microsecond-level pulse width can provide a suitable thermal interaction time, further promoting surface atomic rearrangement and repairing minor defects. While removing oxides, local recrystallization is induced, improving surface grain integrity and reducing dangling bonds. This allows for further regulation of the formation of slightly Te- or Cd-enriched surfaces, which is beneficial for subsequent back contact formation (such as p). + (Layer construction). The frequency of the pulsed laser is 20~150 kHz, which can be one or any combination of 20 kHz, 30 kHz, 40 kHz, 50 kHz, 60 kHz, 70 kHz, 80 kHz, 90 kHz, 100 kHz, 110 kHz, 120 kHz, 130 kHz, 140 kHz, and 150 kHz. Within this range, continuous, large-area, and uniform processing is achieved. The single-pulse coverage area is small, but the high overlap rate ensures processing consistency. The scanning speed of the pulsed laser is 1000-5000 mm / s, which can be any value within the range of 1000 mm / s, 1500 mm / s, 2000 mm / s, 2500 mm / s, 3000 mm / s, 3500 mm / s, 4000 mm / s, 4500 mm / s, and 5000 mm / s. Laser treatment can remove the insulating oxide layer that hinders the contact between the metal and CdTe, reducing the contact barrier. At the same time, it increases the effective contact area through surface microstructure, further reducing the series resistance. The pulsed laser releases energy in a short-duration, high-power form, which can create an instantaneous high energy density on the material surface, enabling the removal of only the oxide layer while preserving the complete CdTe crystal structure. It can also self-limit etching to avoid over-etching; through the control of the above-mentioned high-energy laser beam parameters, it is conducive to cooperating with photomasks of specific shapes, to forming specific pattern structures with sidewall angles > 88 degrees, and to reasonably control the proportion of the completely etched area at the bottom of the hole to the total area, so as to achieve precise and stable control of the surface patterning treatment of the cadmium telluride absorption layer.

[0044] This invention also provides a method for fabricating a cadmium telluride thin-film solar cell, comprising a glass substrate, a transparent conductive layer, a window layer, an absorber layer, a back contact layer, and a metal electrode layer, including the following steps: S1. A transparent conductive oxide thin film is deposited on a glass substrate to form a transparent conductive layer; In one embodiment of the present invention, a highly conductive and low-resistance layer of 600-800 nm thickness is formed on glass by magnetron sputtering deposition or chemical vapor deposition (CVD).

[0045] S2. Deposit a window layer on the transparent conductive layer; In one embodiment of the present invention, n-type CdS is deposited by chemical bath deposition (CBD) or magnetron sputtering deposition (PVD) to form a pn junction with CdTe. To reduce light absorption loss, ultrathin CdS or wider bandgap materials such as CdSe, ZnO, and MgZnO can be used to improve blue light transmittance.

[0046] S3. Deposit a cadmium telluride absorption layer on the window layer; In one embodiment of the present invention, the window layer is typically made of a wide-bandgap n-type semiconductor such as CdS or Mg. x Zn 1-x O, In2S3, etc., form a pn junction with p-type CdTe. Proper band alignment facilitates the injection of photogenerated electrons from CdTe into the window layer, blocks the back diffusion of holes, reduces interface recombination, and further increases the built-in potential, thereby improving the open-circuit voltage.

[0047] S4. Deposit cadmium chloride on the surface of cadmium telluride; S5. Annealing treatment is performed on cadmium telluride with cadmium chloride coating on the surface. In one embodiment of the present invention, annealing the CdTe covered with CdCl2 can promote the recrystallization and growth of CdTe grains, reduce grain boundary density, and reduce carrier scattering and recombination at grain boundaries.

[0048] S6. Perform the above surface treatment process on the cadmium telluride coating after cadmium chloride annealing. In one embodiment of the present invention, efficient light trapping is achieved on a high-quality bulk phase by constructing a specific pattern structure, which maximizes light management benefits without sacrificing electrical performance. Specific pattern structures, such as sidewall angles >88 degrees, extend the effective optical path through mechanisms such as multiple reflections, light trapping effects, and slow light effects, significantly improving long-wavelength absorption. This further shortens the lateral transport distance of charge carriers and suppresses recombination. The specific pattern can serve as a template for back-contact engineering, facilitating the deposition of high-work-function metals or p-type materials. + The doped layer further increases the back contact area, reduces the contact resistance, and enables selective carrier extraction.

[0049] S7. A back contact layer and a metal electrode layer are sequentially deposited on the patterned cadmium telluride surface. In one embodiment of the present invention, the patterned structure facilitates the formation of surface micro / nano structures, interface bandgap modulation, and selective carrier extraction. The patterned surface significantly increases the interface area between CdTe and the back contact layer. This provides more carrier tunneling or thermal emission channels, disperses current density, reduces local Joule heating, effectively lowers specific contact resistance, and improves the fill factor.

[0050] S8. After deposition, metallization annealing is performed to obtain cadmium telluride thin-film solar cells.

[0051] In one embodiment of the present invention, annealing can promote atomic interdiffusion and interfacial reaction between the metal / back contact layer and p-type CdTe, thereby reducing the Schottky barrier height. If the back contact layer contains doped elements, annealing can enable the metal elements to effectively enter the CdTe lattice, forming heavily doped p-type CdTe. + Layer, establish p + The -p homojunction enhances the built-in electric field, enabling selective hole extraction, blocking electron reverse injection, suppressing back-interface recombination, and increasing the open-circuit voltage. Annealing promotes grain growth, stress release, and pore closure in the metal layer, further improving the adhesion and density of the metal electrodes.

[0052] Optionally, in one embodiment, in step S1, the glass substrate is selected from soda-lime glass. Choosing soda-lime glass as the substrate material, rather than quartz, borosilicate glass, or flexible polymers, significantly reduces manufacturing costs.

[0053] Optionally, in one embodiment, in step S2, the above-mentioned transparent conductive layer deposition method is chemical vapor deposition or sputtering deposition.

[0054] Optionally, in one embodiment, in step S2, the deposition method of the window layer is selected from at least one of magnetron sputtering, thermal evaporation, near-space sublimation, and gas phase transport. Magnetron sputtering is the most balanced and promising option, especially suitable for cadmium-free, oxide-based window layers, which aligns with the trend of green manufacturing. Thermal evaporation performs excellently in high-efficiency laboratory batteries and is suitable for precise control. The material of the window layer is selected from at least one of cadmium sulfide, cadmium selenide, zinc oxide, magnesium-doped zinc oxide, indium oxide, gallium oxide, and indium gallium oxide. Compared to oxides, sulfides have a lower band gap and extremely high light transmittance in the infrared / near-infrared band. The thickness of the window layer is 10~300 nm, which can be one or any two of 10 nm, 50 nm, 100 nm, 150 nm, 200 nm, 250 nm, and 300 nm, significantly improving the utilization rate of short-wavelength photons and increasing J scIt reduced parasitic absorption and series resistance, thus improving FF; it suppressed interfacial recombination, thereby increasing V. oc It reduces material costs and process complexity; and improves overall efficiency by achieving better bandgap matching through bandgap control.

[0055] Optionally, in one embodiment, in step S3, the deposition method of the absorption layer is one of vacuum thermal evaporation, near-space sublimation, or gas-phase transport. The source temperature during deposition is 600~1200℃, which can be any value within the range of 600℃, 700℃, 800℃, 900℃, 1000℃, 1100℃, and 1200℃. A high source temperature provides sufficient CdTe vapor pressure, increasing the deposition rate and facilitating the formation of a dense and uniform thin film. The substrate temperature is 400~600℃, which can be any value within the range of 400℃, 450℃, 500℃, 550℃, and 600℃. A higher substrate temperature promotes grain growth, forming large through-grain growth, significantly reducing grain boundary recombination, and improving carrier lifetime.

[0056] Optionally, in one embodiment, in step S4, the method for depositing cadmium chloride is one of thermal evaporation, spraying, roller coating, or immersion. Thermal evaporation offers high purity and controllability, can be performed in a high vacuum environment, has few impurities, and allows for precise film thickness control. It also exhibits good uniformity, suitable for large-area uniform film formation. Furthermore, it has the characteristic of no solvent residue, belonging to a dry process, avoiding the organic residue or hydrolysis problems that may arise from solution methods. It has good compatibility with subsequent annealing and can be directly used in the CdCl2 activation annealing step. Spray deposition equipment is low-cost, requires no high vacuum system, and is simple to operate. It is suitable for large-area and continuous production. It has a high material utilization rate; compared to evaporation, the CdCl2 solution can be partially recovered. The process is flexible, allowing for film thickness control by adjusting the solution concentration and spray parameters. Roller coating enables high-throughput continuous processing, has good film thickness consistency, and allows for precise control of coating thickness through roller gaps or coating heads. It results in less material waste during use, with higher solution utilization compared to spraying. It has good environmental friendliness, with a closed-loop liquid supply system reducing volatilization and pollution. The immersion method is extremely simple, requiring only the sample to be immersed in a CdCl2 solution and then dried. Equipment investment is minimal, requiring only a container and heating device. It offers excellent coverage, providing good wetting and coating capabilities for complex morphologies or rough surfaces.

[0057] Optionally, in one embodiment, in step S5, the annealing temperature of the cadmium chloride is 300~550℃, which can be one or any two of 300℃, 350℃, 400℃, 450℃, 500℃, and 550℃. Within this temperature range, CdCl2 can significantly promote grain growth of the CdTe film, while passivating grain boundary (GB) defects, reducing grain boundary resistance, and decreasing the carrier recombination probability. CdCl2 annealing can effectively passivate intragranular defects (GI), reduce bulk defect density, increase photoluminescence intensity, and thus extend carrier lifetime. This is beneficial for increasing the open-circuit voltage (V) of the battery. oc The annealing time and fill factor (FF) are particularly important. The annealing time is 10 to 50 minutes, and can be any one or both of 10 minutes, 20 minutes, 30 minutes, 40 minutes, and 50 minutes.

[0058] Optionally, in one embodiment, in step S7, the deposition method of the back contact layer and the metal electrode layer is selected from thermal evaporation or magnetron sputtering. Thermal evaporation has low energy, causing almost no ion bombardment damage to the underlying sensitive semiconductor absorption layer, thus avoiding lattice destruction or interface defects. Performed under high vacuum, it results in less impurity contamination and is particularly suitable for metal electrodes requiring high purity. For samples with relatively flat surfaces, it can form continuous and dense metal films. Magnetron sputtering has excellent film adhesion and density; high-energy particle bombardment makes the film bond more firmly to the substrate, making it suitable for electrodes requiring long-term stability. It exhibits good large-area uniformity; industrial-grade sputtering equipment can achieve a thickness uniformity of ±3% over an area >1 m². The material of the back contact layer is selected from at least one of zinc telluride, copper-doped zinc telluride, or group V element-doped zinc telluride. Pure zinc telluride has good lattice matching, and ZnTe and CdTe have similar lattice constants, resulting in a low interface defect density. With its small valence band offset, ZnTe has a valence band apex slightly higher than CdTe, which facilitates hole transport from CdTe to the back electrode and reduces the hole barrier. It also features a wide bandgap, is transparent to visible light, does not absorb effective photons, and does not affect the device photocurrent. Copper-doped zinc telluride significantly enhances p-type conductivity, with Cu substituting for Zn to form acceptor levels, greatly increasing hole concentration. It also lowers the contact barrier, and its high work function matches the CdTe valence band, promoting hole extraction. Furthermore, it exhibits a self-doping diffusion effect, where trace amounts of Cu can diffuse into the CdTe absorption layer, passivating grain boundaries and increasing Vo. ocIt also exhibits good process compatibility, capable of deposition via thermal evaporation, sputtering, CBD, and other methods, facilitating integration. Group V element doping of zinc telluride (such as ZnTe:N, ZnTe:P, ZnTe:As) enables controllable p-type doping. Compared to Cu, Group V elements have lower diffusion coefficients and better thermal stability, improving long-term device reliability. It reduces metal contamination, avoids the use of transition metals like Cu, and lowers the risk of deep-level defects. Furthermore, it offers flexible bandgap engineering, allowing for fine-tuning of work function and carrier concentration with different dopants. The thickness of the back contact layer ranges from 10 to 100 nm, and can be any combination of 10 nm, 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, and 100 nm. Within this range, conductivity and transport efficiency achieve an optimal balance. This process can form a continuous, dense thin film that covers the micropores or rough areas on the CdTe surface, preventing direct contact between the metal electrode and CdTe that could lead to localized Schottky barriers or leakage. It also provides sufficient dopant acceptor concentration, establishing a high work function interface and promoting hole extraction from CdTe to the metal electrode. ZnTe itself is a wide-bandgap semiconductor; although it does not absorb visible light, excessive thickness can increase series resistance. Holes need to be transported to the metal electrode through this layer; excessive thickness increases the transport path, leading to carrier recombination within the layer. The metal electrode layer is made of at least one of molybdenum, aluminum, chromium, silver, copper, or nickel. ZnTe:Cu / Ni / Cu utilizes Ni to block Cu diffusion, balancing conductivity and stability. ZnTe:Cu / Mo simplifies the structure, while Mo provides mechanical support and a conductive pathway. In ZnTe:Cu / Cr / Ag, Ag provides high reflectivity and low resistance, while Cr enhances adhesion.

[0059] Optionally, in one embodiment, in step S8, the annealing temperature is 100~300℃, which can be a range of 100℃, 150℃, 200℃, 250℃, 300℃, or any two of these values, and the time is 10~40min, which can be a range of 10min, 20min, 30min, 40min, or any two of these values. Annealing promotes the diffusion of doped atoms into the CdTe absorber layer, forming a uniform p-type doped layer, which significantly reduces the potential barrier between the metal and semiconductor, decreases the back contact resistance, and increases the fill factor (FF) of the battery. Low-temperature short-time annealing can also limit the diffusion depth of the dopant near the back side, avoiding excessive penetration into the bulk layer and the generation of deep level traps, thereby further reducing dark current and series resistance.

[0060] The present invention will be described in detail below through embodiments.

[0061] Example 1 This embodiment provides a method for preparing a cadmium telluride thin-film battery. The cadmium telluride absorber layer described above has undergone back surface patterning treatment. The specific preparation process is as follows: Figure 1 As shown, the cadmium telluride thin-film battery includes a glass substrate 101, a transparent conductive layer 102, a window layer 103, an absorption layer 104, a back contact layer 106, and a metal electrode layer 107. The surface of the absorption layer 104 is covered with an oxide layer 105, which, after laser processing, forms a micron-scale conductive template array. In this embodiment, the glass substrate 101 is soda-lime glass; the transparent conductive layer 102 is made of fluorine-doped tin oxide (FTO); the window layer 103 is made of cadmium selenide (CdSe); the absorption layer 104 is made of cadmium telluride (CdTe); the back contact layer 106 is made of copper-doped zinc telluride (ZnTe:Cu); and the metal electrode layer 107 is made of molybdenum (Mo).

[0062] The method for preparing the cadmium telluride thin-film battery in this embodiment includes the following steps: S1. FTO is deposited on the surface of glass substrate 101 by chemical vapor deposition to obtain transparent conductive layer 102; S2. CdSe is deposited on the surface of the transparent conductive layer 102 by magnetron sputtering to obtain a window layer 103 with a thickness of 80 nm. S3. CdTe is deposited on the surface of window layer 103 using a near-space sublimation method. The source temperature is controlled at 600℃ and the substrate temperature at 550℃ during deposition, resulting in an absorption layer 104 with a thickness of 3 μm. After cadmium chloride spraying and high-temperature annealing, an oxide layer 105 is formed on the CdTe surface. The cadmium chloride annealing temperature is 390℃ and the time is 30 minutes. S4. A micron-scale conductive template array is constructed on the cadmium telluride surface using a surface patterning process that combines laser and photomask techniques. Specifically, this includes: S41. The annealed CdTe layer is repeatedly cleaned with ultrapure water and the sample surface is thoroughly dried with dry nitrogen gas. S42. Select a unit array structure as follows: Figure 3 The photomask shown covers the sample with a duty cycle of 25% (passivation area accounts for 75%). During this process, the distance between the photomask and the sample surface is maintained at 40 μm. S43. The oxide layer on the sample surface is etched using a laser to obtain a sample with a micron-sized regular conductive template array on the surface. The laser parameters are as follows: pulsed laser with a wavelength of 532 nm, a pulse width of 200 ns, a pulse frequency of 45 kHz, a scanning speed of 3000 mm / s, and a linear spot size. S5. ZnTe:Cu was deposited on the patterned cadmium telluride surface using magnetron sputtering to obtain a back contact layer 106 with a thickness of 30 nm. S6. Mo is deposited on the surface of the back contact layer 106 by magnetron sputtering to obtain a metal electrode layer 107 with a thickness of 130 nm.

[0063] S7. Anneal the battery cells at a temperature of 210°C for 20 minutes to obtain the cadmium telluride thin-film battery described above.

[0064] Example 2 This embodiment provides a method for preparing a cadmium telluride thin-film battery. The cadmium telluride absorber layer described above has undergone back surface patterning treatment. The specific preparation process is as follows: Figure 1 As shown, the cadmium telluride thin-film battery includes a glass substrate 101, a transparent conductive layer 102, a window layer 103, an absorption layer 104, a back contact layer 106, and a metal electrode layer 107. The surface of the absorption layer 104 is covered with an oxide layer 105, which, after laser processing, forms a micron-scale conductive template array. In this embodiment, the glass substrate 101 is soda-lime glass; the transparent conductive layer 102 is made of fluorine-doped tin oxide (FTO); the window layer 103 is made of cadmium selenide (CdSe); the absorption layer 104 is made of cadmium telluride (CdTe); the back contact layer 106 is made of copper-doped zinc telluride (ZnTe:Cu); and the metal electrode layer 107 is made of molybdenum (Mo).

[0065] The method for preparing the cadmium telluride thin-film battery in this embodiment includes the following steps: S1. FTO is deposited on the surface of glass substrate 101 by chemical vapor deposition to obtain transparent conductive layer 102; S2. CdSe is deposited on the surface of the transparent conductive layer 102 by magnetron sputtering to obtain a window layer 103 with a thickness of 80 nm. S3. CdTe is deposited on the surface of window layer 103 using a near-space sublimation method. The source temperature is controlled at 600℃ and the substrate temperature at 550℃ during deposition, resulting in an absorption layer 104 with a thickness of 3 μm. After cadmium chloride spraying and high-temperature annealing, an oxide layer 105 is formed on the CdTe surface. The cadmium chloride annealing temperature is 390℃ and the time is 30 minutes. S4. A micron-scale conductive template array is constructed on the cadmium telluride surface using a surface patterning process that combines laser and photomask techniques. Specifically, this includes: S41. The annealed CdTe layer is repeatedly cleaned with ultrapure water and the sample surface is thoroughly dried with dry nitrogen gas. S42. Select a unit array structure as follows: Figure 4The photomask shown covers the sample with a duty cycle of 36% (passivation area accounts for 64%). During this process, the distance between the photomask and the sample surface is maintained at 40 μm. S43. The oxide layer on the sample surface is etched using a laser to obtain a sample with a micron-sized regular conductive template array on the surface. The laser parameters are as follows: pulsed laser with a wavelength of 532 nm, a pulse width of 200 ns, a pulse frequency of 45 kHz, a scanning speed of 3000 mm / s, and a linear spot size. S5. ZnTe:Cu was deposited on the patterned cadmium telluride surface using magnetron sputtering to obtain a back contact layer 106 with a thickness of 30 nm. S6. Mo is deposited on the surface of the back contact layer 106 by magnetron sputtering to obtain a metal electrode layer 107 with a thickness of 130 nm.

[0066] S7. Anneal the battery cells at a temperature of 210°C for 20 minutes to obtain the cadmium telluride thin-film battery described above.

[0067] Example 3 This embodiment provides a method for preparing a cadmium telluride thin-film battery. The cadmium telluride absorber layer described above has undergone back surface patterning treatment. The specific preparation process is as follows: Figure 1 As shown, the cadmium telluride thin-film battery includes a glass substrate 101, a transparent conductive layer 102, a window layer 103, an absorption layer 104, a back contact layer 106, and a metal electrode layer 107. The surface of the absorption layer 104 is covered with an oxide layer 105, which, after laser processing, forms a micron-scale conductive template array. In this embodiment, the glass substrate 101 is soda-lime glass; the transparent conductive layer 102 is made of fluorine-doped tin oxide (FTO); the window layer 103 is made of cadmium selenide (CdSe); the absorption layer 104 is made of cadmium telluride (CdTe); the back contact layer 106 is made of copper-doped zinc telluride (ZnTe:Cu); and the metal electrode layer 107 is made of molybdenum (Mo).

[0068] The method for preparing the cadmium telluride thin-film battery in this embodiment includes the following steps: S1. FTO is deposited on the surface of glass substrate 101 by chemical vapor deposition to obtain transparent conductive layer 102; S2. CdSe is deposited on the surface of the transparent conductive layer 102 by magnetron sputtering to obtain a window layer 103 with a thickness of 80 nm. S3. CdTe is deposited on the surface of window layer 103 using a near-space sublimation method. The source temperature is controlled at 600℃ and the substrate temperature at 550℃ during deposition, resulting in an absorption layer 104 with a thickness of 3 μm. After cadmium chloride spraying and high-temperature annealing, an oxide layer 105 is formed on the CdTe surface. The cadmium chloride annealing temperature is 390℃ and the time is 30 minutes. S4. A micron-scale conductive template array is constructed on the cadmium telluride surface using a surface patterning process that combines laser and photomask techniques. Specifically, this includes: S41. The annealed CdTe layer is repeatedly cleaned with ultrapure water and the sample surface is thoroughly dried with dry nitrogen gas. S42. Select a unit array structure as follows: Figure 5 The photomask shown covers the sample with a duty cycle of 48% (passivation area accounts for 52%). During this process, the distance between the photomask and the sample surface is maintained at 40 μm. S43. The oxide layer on the sample surface is etched using a laser to obtain a sample with a micron-sized regular conductive template array on the surface. The laser parameters are as follows: pulsed laser with a wavelength of 532 nm, a pulse width of 200 ns, a pulse frequency of 45 kHz, a scanning speed of 3000 mm / s, and a linear spot size. S5. ZnTe:Cu was deposited on the patterned cadmium telluride surface using magnetron sputtering to obtain a back contact layer 106 with a thickness of 30 nm. S6. Mo is deposited on the surface of the back contact layer 106 by magnetron sputtering to obtain a metal electrode layer 107 with a thickness of 130 nm.

[0069] S7. Anneal the battery cells at a temperature of 210°C for 20 minutes to obtain the cadmium telluride thin-film battery described above.

[0070] Example 4 This embodiment provides a method for preparing a cadmium telluride thin-film battery. The cadmium telluride absorber layer described above has undergone back surface patterning treatment. The specific preparation process is as follows: Figure 1As shown, the cadmium telluride thin-film battery includes a glass substrate 101, a transparent conductive layer 102, a window layer 103, an absorption layer 104, a back contact layer 106, and a metal electrode layer 107. The surface of the absorption layer 104 is covered with an oxide layer 105, which, after laser processing, forms a micron-scale conductive template array. In this embodiment, the glass substrate 101 is soda-lime glass; the transparent conductive layer 102 is made of fluorine-doped tin oxide (FTO); the window layer 103 is made of cadmium selenide (CdSe); the absorption layer 104 is made of cadmium telluride (CdTe); the back contact layer 106 is made of copper-doped zinc telluride (ZnTe:Cu); and the metal electrode layer 107 is made of molybdenum (Mo).

[0071] The method for preparing the cadmium telluride thin-film battery in this embodiment includes the following steps: S1. FTO is deposited on the surface of glass substrate 101 by chemical vapor deposition to obtain transparent conductive layer 102; S2. CdSe is deposited on the surface of the transparent conductive layer 102 by magnetron sputtering to obtain a window layer 103 with a thickness of 80 nm. S3. CdTe is deposited on the surface of window layer 103 using a near-space sublimation method. The source temperature is controlled at 600℃ and the substrate temperature at 550℃ during deposition, resulting in an absorption layer 104 with a thickness of 3 μm. After cadmium chloride spraying and high-temperature annealing, an oxide layer 105 is formed on the CdTe surface. The cadmium chloride annealing temperature is 390℃ and the time is 30 minutes. S4. A micron-scale conductive template array is constructed on the cadmium telluride surface using a surface patterning process that combines laser and photomask techniques. Specifically, this includes: S41. The annealed CdTe layer is repeatedly cleaned with ultrapure water and the sample surface is thoroughly dried with dry nitrogen gas. S42. Select a unit array structure as follows: Figure 6 The photomask shown covers the sample with a duty cycle of 64% (passivation area accounts for 36%). During this process, the distance between the photomask and the sample surface is maintained at 40 μm. S43. The oxide layer on the sample surface is etched using a laser to obtain a sample with a regular micron-scale conductive template array on the surface. The laser parameters are as follows: pulsed laser with a wavelength of 532 nm, a pulse width of 200 ns, a pulse frequency of 45 kHz, a scanning speed of 3000 mm / s, and a linear spot size. S5. ZnTe:Cu was deposited on the patterned cadmium telluride surface using magnetron sputtering to obtain a back contact layer 106 with a thickness of 30 nm. S6. Mo is deposited on the surface of the back contact layer 106 by magnetron sputtering to obtain a metal electrode layer 107 with a thickness of 130 nm.

[0072] S7. Anneal the battery cells at a temperature of 210°C for 20 minutes to obtain the cadmium telluride thin-film battery described above.

[0073] Example 5 This embodiment provides a method for preparing a cadmium telluride thin-film battery. The cadmium telluride absorber layer described above has undergone back surface patterning treatment. The specific preparation process is as follows: Figure 1 As shown, the cadmium telluride thin-film battery includes a glass substrate 101, a transparent conductive layer 102, a window layer 103, an absorption layer 104, a back contact layer 106, and a metal electrode layer 107. The surface of the absorption layer 104 is covered with an oxide layer 105, which, after laser processing, forms a micron-scale conductive template array. In this embodiment, the glass substrate 101 is soda-lime glass; the transparent conductive layer 102 is made of fluorine-doped tin oxide (FTO); the window layer 103 is made of cadmium selenide (CdSe); the absorption layer 104 is made of cadmium telluride (CdTe); the back contact layer 106 is made of copper-doped zinc telluride (ZnTe:Cu); and the metal electrode layer 107 is made of molybdenum (Mo).

[0074] The method for preparing the cadmium telluride thin-film battery in this embodiment includes the following steps: S1. FTO is deposited on the surface of glass substrate 101 by chemical vapor deposition to obtain transparent conductive layer 102; S2. CdSe is deposited on the surface of the transparent conductive layer 102 by magnetron sputtering to obtain a window layer 103 with a thickness of 80 nm. S3. CdTe is deposited on the surface of window layer 103 using a near-space sublimation method. The source temperature is controlled at 600℃ and the substrate temperature at 550℃ during deposition, resulting in an absorption layer 104 with a thickness of 3 μm. After cadmium chloride spraying and high-temperature annealing, an oxide layer 105 is formed on the CdTe surface. The cadmium chloride annealing temperature is 390℃ and the time is 30 minutes. S4. A micron-scale conductive template array is constructed on the cadmium telluride surface using a surface patterning process that combines laser and photomask techniques. Specifically, this includes: S41. The annealed CdTe layer is repeatedly cleaned with ultrapure water and the sample surface is thoroughly dried with dry nitrogen gas. S42. Select a photomask with a unit array structure to cover the sample, with a duty cycle of 81% (passivation area ratio of 19%). During this process, the distance between the photomask and the sample surface is maintained at 40 μm; S43. The oxide layer on the sample surface is etched using a laser to obtain a sample with a micron-sized regular conductive template array on the surface. The laser parameters are as follows: pulsed laser with a wavelength of 532 nm, a pulse width of 200 ns, a pulse frequency of 45 kHz, a scanning speed of 3000 mm / s, and a linear spot size. S5. ZnTe:Cu was deposited on the patterned cadmium telluride surface using magnetron sputtering to obtain a back contact layer 106 with a thickness of 30 nm. S6. Mo is deposited on the surface of the back contact layer 106 by magnetron sputtering to obtain a metal electrode layer 107 with a thickness of 130 nm.

[0075] S7. Anneal the battery cells at a temperature of 210°C for 20 minutes to obtain the cadmium telluride thin-film battery described above.

[0076] Comparative Example 1 This comparative example provides a method for fabricating a cadmium telluride thin-film battery. The cadmium telluride thin-film battery includes a glass substrate 101, a transparent conductive layer 102, a window layer 103, an absorber layer 104, a back contact layer 106, and a metal electrode layer 107. In the comparative example, the glass substrate 101 is soda-lime glass; the transparent conductive layer 102 is made of fluorine-doped tin oxide (FTO); the window layer 103 is made of cadmium selenide (CdSe); the absorber layer 104 is made of cadmium telluride (CdTe); the back contact layer 106 is made of copper-doped zinc telluride (ZnTe:Cu); and the metal electrode layer 107 is made of molybdenum (Mo).

[0077] The method for preparing the cadmium telluride thin-film battery in this embodiment includes the following steps: S1. FTO is deposited on the surface of glass substrate 101 by chemical vapor deposition to obtain transparent conductive layer 102; S2. CdSe is deposited on the surface of the transparent conductive layer 102 by magnetron sputtering to obtain a window layer 103 with a thickness of 80 nm. S3. CdTe is deposited on the surface of window layer 103 using a near-space sublimation method. The source temperature is controlled at 600℃ and the substrate temperature at 550℃ during deposition, resulting in an absorption layer 104 with a thickness of 3 μm. After cadmium chloride spraying and high-temperature annealing, an oxide layer 105 is formed on the CdTe surface. The cadmium chloride annealing temperature is 390℃ and the time is 30 minutes. S4. The annealed CdTe layer was washed multiple times with ultrapure water, then immersed in dilute nitric acid solution for 5 seconds, and finally dried with dry nitrogen. S5. ZnTe:Cu was deposited on the back surface of cadmium telluride after acid washing by magnetron sputtering to obtain a back contact layer 106 with a thickness of 30 nm. S6. Mo is deposited on the surface of the back contact layer 106 by magnetron sputtering to obtain a metal electrode layer 107 with a thickness of 130 nm.

[0078] Comparative Example 2 This comparative example provides a method for fabricating a cadmium telluride thin-film battery. The cadmium telluride thin-film battery includes a glass substrate 101, a transparent conductive layer 102, a window layer 103, an absorber layer 104, a back contact layer 106, and a metal electrode layer 107. In the comparative example, the glass substrate 101 is soda-lime glass; the transparent conductive layer 102 is made of fluorine-doped tin oxide (FTO); the window layer 103 is made of cadmium sulfide (CdS); the absorber layer 104 is made of cadmium telluride (CdTe); the back contact layer 106 is made of copper-doped zinc telluride (ZnTe:Cu); and the metal electrode layer 107 is made of molybdenum (Mo).

[0079] The method for preparing the cadmium telluride thin-film battery in this embodiment includes the following steps: S1. FTO is deposited on the surface of glass substrate 101 by chemical vapor deposition to obtain transparent conductive layer 102; S2. CdSe is deposited on the surface of the transparent conductive layer 102 by magnetron sputtering to obtain a window layer 103 with a thickness of 80 nm. S3. CdTe is deposited on the surface of window layer 103 using a near-space sublimation method. The source temperature is controlled at 600℃ and the substrate temperature at 550℃ during deposition, resulting in an absorption layer 104 with a thickness of 3 μm. After cadmium chloride spraying and high-temperature annealing, an oxide layer 105 is formed on the CdTe surface. The cadmium chloride annealing temperature is 390℃ and the time is 30 minutes. S4. The annealed CdTe layer was repeatedly cleaned with ultrapure water, then the sample was thoroughly dried with dry nitrogen, and finally the sample was surface treated with plasma treatment.

[0080] S5. ZnTe:Cu was deposited on the back surface of cadmium telluride after plasma etching using magnetron sputtering to obtain a back contact layer 106 with a thickness of 30 nm. S6. Mo is deposited on the surface of the back contact layer 106 by magnetron sputtering to obtain a metal electrode layer 107 with a thickness of 130 nm.

[0081] Comparative Example 3 This embodiment provides a method for preparing a cadmium telluride thin-film battery. The cadmium telluride absorber layer described above has undergone back surface patterning treatment. The specific preparation process is as follows: Figure 1As shown, the cadmium telluride thin-film battery includes a glass substrate 101, a transparent conductive layer 102, a window layer 103, an absorption layer 104, a back contact layer 106, and a metal electrode layer 107. The surface of the absorption layer 104 is covered with an oxide layer 105, which, after laser processing, forms a micron-scale conductive template array. In this embodiment, the glass substrate 101 is soda-lime glass; the transparent conductive layer 102 is made of fluorine-doped tin oxide (FTO); the window layer 103 is made of cadmium selenide (CdSe); the absorption layer 104 is made of cadmium telluride (CdTe); the back contact layer 106 is made of copper-doped zinc telluride (ZnTe:Cu); and the metal electrode layer 107 is made of molybdenum (Mo).

[0082] The method for preparing the cadmium telluride thin-film battery in this embodiment includes the following steps: S1. FTO is deposited on the surface of glass substrate 101 by chemical vapor deposition to obtain transparent conductive layer 102; S2. CdSe is deposited on the surface of the transparent conductive layer 102 by magnetron sputtering to obtain a window layer 103 with a thickness of 80 nm. S3. CdTe is deposited on the surface of window layer 103 using a near-space sublimation method. The source temperature is controlled at 600℃ and the substrate temperature at 550℃ during deposition, resulting in an absorption layer 104 with a thickness of 3 μm. After cadmium chloride spraying and high-temperature annealing, an oxide layer 105 is formed on the CdTe surface. The cadmium chloride annealing temperature is 390℃ and the time is 30 minutes. S4. A micron-scale conductive template array is constructed on the cadmium telluride surface using a surface patterning process that combines laser and photomask techniques. Specifically, this includes: S41. The annealed CdTe layer is repeatedly cleaned with ultrapure water and the sample surface is thoroughly dried with dry nitrogen gas. S42. Select a pseudo-random photomask with completely random gap size, pattern type, and graphic size to cover the sample. During this process, the distance between the photomask and the sample surface is maintained at 40 μm; S43. Laser etching is used to etch the oxide layer on the sample surface to obtain a sample with a micron-sized irregular conductive template on the surface. The laser parameters are as follows: pulsed laser with a wavelength of 532 nm, a pulse width of 200 ns, a pulse frequency of 45 kHz, a scanning speed of 3000 mm / s, and a linear spot size. S5. ZnTe:Cu was deposited on the patterned cadmium telluride surface using magnetron sputtering to obtain a back contact layer 106 with a thickness of 30 nm. S6. Mo is deposited on the surface of the back contact layer 106 by magnetron sputtering to obtain a metal electrode layer 107 with a thickness of 130 nm.

[0083] S7. Anneal the battery cells at a temperature of 210°C for 20 minutes to obtain the cadmium telluride thin-film battery described above.

[0084] Comparative Example 4 This embodiment provides a method for preparing a cadmium telluride thin-film battery. The cadmium telluride absorber layer described above has undergone back surface patterning treatment. The specific preparation process is as follows: Figure 1 As shown, the cadmium telluride thin-film battery includes a glass substrate 101, a transparent conductive layer 102, a window layer 103, an absorption layer 104, a back contact layer 106, and a metal electrode layer 107. The surface of the absorption layer 104 is covered with an oxide layer 105, which, after laser processing, forms a micron-scale conductive template array. In this embodiment, the glass substrate 101 is soda-lime glass; the transparent conductive layer 102 is made of fluorine-doped tin oxide (FTO); the window layer 103 is made of cadmium selenide (CdSe); the absorption layer 104 is made of cadmium telluride (CdTe); the back contact layer 106 is made of copper-doped zinc telluride (ZnTe:Cu); and the metal electrode layer 107 is made of molybdenum (Mo).

[0085] The method for preparing the cadmium telluride thin-film battery in this embodiment includes the following steps: S1. FTO is deposited on the surface of glass substrate 101 by chemical vapor deposition to obtain transparent conductive layer 102; S2. CdSe is deposited on the surface of the transparent conductive layer 102 by magnetron sputtering to obtain a window layer 103 with a thickness of 80 nm. S3. CdTe is deposited on the surface of window layer 103 using a near-space sublimation method. The source temperature is controlled at 600℃ and the substrate temperature at 550℃ during deposition, resulting in an absorption layer 104 with a thickness of 3 μm. After cadmium chloride spraying and high-temperature annealing, an oxide layer 105 is formed on the CdTe surface. The cadmium chloride annealing temperature is 390℃ and the time is 30 minutes. S4. A pyramid-shaped light-trapping structure is constructed on the surface of cadmium telluride using laser processing technology, specifically including: S41. The annealed CdTe layer is repeatedly cleaned with ultrapure water and the sample surface is thoroughly dried with dry nitrogen gas. S42. The oxide layer on the sample surface is etched using a laser to obtain a sample with a pyramid-shaped light-trapping structure on the surface. The laser parameters are as follows: pulsed laser with a wavelength of 532 nm, a pulse width of 200 ns, a pulse frequency of 45 kHz, a scanning speed of 3000 mm / s, and a circular spot size. S5. ZnTe:Cu was deposited on the patterned cadmium telluride surface using magnetron sputtering to obtain a back contact layer 106 with a thickness of 30 nm. S6. Mo is deposited on the surface of the back contact layer 106 by magnetron sputtering to obtain a metal electrode layer 107 with a thickness of 130 nm.

[0086] S7. Anneal the battery cells at a temperature of 210°C for 20 minutes to obtain the cadmium telluride thin-film battery described above.

[0087] To objectively evaluate the performance, thin film properties, and morphology of the solar cells prepared in the embodiments of the present invention, they were characterized using standard testing methods recognized in the art: 1. Current-Voltage Characteristics (JV): Measured using an AAA-grade solar simulator and source meter under standard test conditions (AM 1.5G, 100 mW / cm², 25℃).

[0088] 2. External Quantum Efficiency (EQE): The EQE spectrum of the cell was measured according to the international standard IEC 60904-8. Specifically, a quantum efficiency testing system equipped with a monochromator, lock-in amplifier, and standard silicon / germanium detector was used, scanning in 5 nm steps within the wavelength range of 300 nm to 1000 nm. The system was calibrated using a standard silicon detector traceable to NIST prior to measurement.

[0089] 3. Sidewall tilt angle: The cross-section of the device was observed using a scanning electron microscope (SEM). The tilt angle was obtained by directly measuring the angle between the sidewall of the pattern and the substrate plane in the SEM image, or by precise calculation using the accompanying angle measurement software. At least five different locations were measured for each sample, and the results were averaged.

[0090] 4. Average Surface Roughness: Measured using an atomic force microscope (AFM) in tapping mode, according to international standard ISO 4287. The scanning area is typically 5 μm × 5 μm. The average surface roughness is the arithmetic mean deviation of the profile, directly provided by the instrument's accompanying software (NanoScope Analysis).

[0091] 5. Reflectivity: Measurements were performed according to international standard ISO 13696 (methods for testing the reflectivity of laser optical components) using a PerkinElmer Lambda 1050+ ultraviolet-visible-near-infrared spectrophotometer equipped with an integrating sphere. The measurement wavelength range covered 300-1000 nm, scanned in 5 nm steps. Baseline calibration was performed using a standard white plate with known reflectivity.

[0092] (a) Surface morphology and optical performance testing: The sidewall tilt angle, average surface roughness, reflectivity, and EQE of the surface-treated CdTe films in Examples 1-5 and Comparative Examples 1-4 were tested respectively. The test results are as follows. Table 1

[0093] To achieve the micron-scale regular conductive template array structure of the aforementioned pattern, the following process parameters were synergistically optimized.

[0094] Laser wavelength: Preferably, ultraviolet lasers in the range of 266 nm to 355 nm. Cadmium telluride has high absorption in this band, enabling cold processing, reducing the heat-affected zone, and facilitating the formation of steep sidewalls. Pulse width: 10 ps to 100 ns. Ultrashort pulses (picosecond level) can reduce heat diffusion and achieve more precise etching contours; nanosecond pulses, while ensuring processing efficiency, can also achieve highly vertical sidewalls through subsequent process adjustments.

[0095] Energy density (flux): 0.5 J / cm² to 3 J / cm². Too low an energy level will result in incomplete etching, while too high an energy level will easily cause material melting or rough sidewalls.

[0096] Scanning speed and repetition rate: Scanning speed from 100 mm / s to 1000 mm / s, repetition rate from 10 kHz to 200 kHz. The combination of high scanning speed and appropriate frequency can ensure processing efficiency while avoiding heat accumulation and maintaining steep sidewalls.

[0097] Photomask pattern shape and size: The photomask openings are designed as a regular square array, with light-transmitting holes ranging from 1 to 20 μm in size and gap dimensions ranging from 1 to 20 μm. This size range allows for the formation of effective micron-level directional carrier transport channels on the cadmium telluride surface, while ensuring a controllable percentage of the bottom fully etched area.

[0098] Mask contrast ratio: greater than 100:1. High-contrast masks ensure sharp laser energy distribution and reduce edge diffraction effects, which is key to achieving high sidewall angles.

[0099] According to the data in Table 1, when the duty cycle is no more than 36%, the accumulation of energy in the molten zone is limited due to the inhibitory effect of low porosity, the surface tension tends to be homogenized, and the sidewall tilt angle approaches 90°, thus maintaining a low surface roughness. Conversely, when the duty cycle reaches or exceeds 48%, the high porosity causes the laser energy to concentrate in local areas, forming more spherical molten protrusions, thereby gradually increasing the surface roughness. In the evaluation of optical performance, under the condition that the duty cycle is no more than 36%, the multiple reflection trap effect is enhanced, resulting in the lowest reflectivity; while when the duty cycle reaches or exceeds 48%, the number of photon escape channels increases, and the reflectivity increases accordingly. In particular, under the condition that the duty cycle is 36%, the sidewall tilt angle of the film surface reaches its maximum value, and both surface roughness and reflectivity are at their lowest levels. At this time, passivation and conductivity reach the best balance, the carrier collection efficiency is maximized, and the absorption capacity in the long-wavelength region is the strongest. In contrast, the irregular array of pores in Comparative Example 3 exhibits geometrically disordered pore distribution, resulting in higher surface roughness and reflectivity. Further comparison of the thin film surface reveals a pyramidal light-trapping structure with a fixed sidewall tilt angle of 54.7°, primarily resulting in single-reflection and thus higher reflectivity.

[0100] (II) Battery performance testing: The conversion efficiency, fill factor, short-circuit current and open-circuit voltage of the cadmium telluride thin-film batteries of Examples 1-5 and Comparative Examples 1-4 were tested respectively, and the test results are shown in Table 2 below.

[0101] Table 2

[0102] As shown in Table 2, the device performance of Embodiment 2 of the present invention is optimal, using a duty cycle of 36% ( Figure 4The mask template was processed under the laser parameters described above, resulting in a structure with a sidewall tilt angle of 88.2° and an average surface roughness of 8 nm. Calculations showed that the effective specific surface area of ​​this patterned absorption layer was 2.05 times that of the planar absorption layer. By reducing the ineffective surface area, the increase in specific surface area was precisely controlled within the range of 1.8 to 2.2 times. This moderate increase in specific surface area means that a large number of vertically oriented, highly efficient carrier transport channels are generated inside the device. The smooth, steep sidewalls ensure that carriers are rapidly extracted to the electrodes along the vertical direction, resulting in a very low probability of lateral recombination and maximizing carrier extraction efficiency. Traditional methods of significantly increasing surface area are often accompanied by severe surface recombination. This embodiment, by reducing the ineffective surface area (controlling roughness and sidewall tilt angle), ensures that almost all of the newly added surface area is "effective" and has good electrical contact, achieving an excellent balance between passivation and conductivity. According to the data provided in Table 2, compared with the device performance of the unpatterned cadmium telluride absorption layer, the embodiment of this invention demonstrates superiority in photoelectric conversion efficiency and various performance parameters. In particular, the performance of the embodiments of the present invention is significantly better than that of Comparative Examples 1 and 2 in terms of open-circuit voltage and short-circuit current. This indicates that almost all of the newly added surface area is converted into effective carrier collection channels without introducing serious recombination losses, ultimately improving the device efficiency to 20.3%. Compared to the embodiments, the device in Comparative Example 3 exhibits a lower open-circuit voltage and fill factor. Due to the disorder of its geometric structure, the irregular array is prone to causing detours in the carrier transport path, thereby increasing the probability of interface recombination. In addition, the irregular array is also prone to forming passivation dead zones, leading to the concentration of local defects. The pyramid light-trapping structure in Comparative Example 4 increases the carrier recombination rate, and the tilted sidewalls make the carrier path more detours, increasing the recombination probability. At the same time, the surface roughness is high, making it difficult to form a good ohmic contact with the back contact layer, thus making the device performance much lower than that of the embodiments with regular patterning. This proves that the regular patterning process of the present invention can significantly improve the performance of cadmium telluride solar cells, enabling them to achieve a higher level of photoelectric conversion efficiency.

[0103] The preferred embodiments of the present invention have been described in detail above; however, the present invention is not limited thereto. Within the scope of the inventive concept, various simple modifications can be made to the technical solutions of the present invention, including combinations of various technical features in any other suitable manner. These simple modifications and combinations should also be considered as the content disclosed in the present invention and are all within the protection scope of the present invention.

Claims

1. A surface treatment process for a cadmium telluride absorber layer, characterized in that, Includes the following steps: (1) Clean the cadmium telluride layer after cadmium chloride annealing to remove the residual cadmium chloride on the surface, dry it with compressed gas, and blow it dry thoroughly. After drying, an insulating oxide layer will naturally form on the surface. (2) Select a photomask with light-transmitting holes, use a high-energy laser beam to selectively etch the insulating oxide layer, pattern the insulating oxide layer, and deposit it to form a conductive layer; (3) The obtained conductive layer contacts the cadmium telluride absorption layer through the opening between the insulating oxide layers to form a conductive template array with a specific pattern structure; The conductive template array with the specific pattern structure has the following characteristics: the sidewall angle of the conductive template array is 80.9~88.5 degrees, the completely etched area at the bottom of the light-transmitting hole of the photomask accounts for 24-85% of the total area, and the micron-sized regular conductive template array forms a directional carrier transport channel.

2. The surface treatment process for the cadmium telluride absorber layer according to claim 1, characterized in that, The photomask consists of a substrate layer and a light-shielding film layer. The substrate layer material of the photomask is selected from at least one of synthetic quartz glass, low-expansion borosilicate glass, and soda glass. The light-shielding film layer of the photomask is a double-layer composite. The upper layer material is chromium-oxygen-nitrogen-carbon, which contains chromium, oxygen, nitrogen and carbon elements. Its composition, by mass percentage, meets the following range: chromium 40%-70%, oxygen 10%-40%, nitrogen 5%-30%, carbon 1%-15%, and the sum of the contents of each group is 100%, with a thickness of 3~10nm. The lower layer material is pure chromium with a thickness of 20~50nm.

3. The surface treatment process for the cadmium telluride absorber layer according to claim 1, characterized in that, The photomask has light-transmitting holes arranged in a square array with a side length of 1-20 μm and a gap size of 1-20 μm; the distance between the photomask and the cadmium telluride layer is 10-50 μm.

4. The surface treatment process for the cadmium telluride absorber layer according to claim 1, characterized in that, The wavelength of the high-energy laser beam is 300~700 nm, the high-energy laser beam is a pulsed laser, the pulse width of the pulsed laser is 7 ns~1 μs, the frequency of the pulsed laser is 20~150 KHz, and the scanning speed of the pulsed laser is 1000-5000 mm / s.

5. A cadmium telluride absorber layer with a specific pattern structure obtained by the surface treatment process of the cadmium telluride absorber layer as described in any one of claims 1 to 4, characterized in that, A conductive template array with a specific pattern structure was prepared on the surface of a cadmium telluride absorption layer by using a laser in conjunction with a photomask with a specific pattern. The conductive template array with the specific pattern structure has the following characteristics: the sidewall angle of the conductive template array is 80.9~88.5 degrees, the completely etched area at the bottom of the light-transmitting hole of the photomask accounts for 24-85% of the total area, and the micron-sized regular conductive template array forms a directional carrier transport channel. The cadmium telluride absorbing layer has an average surface roughness of 6-26 nm and a weighted average reflectance of 7-15%.

6. The cadmium telluride absorber layer according to claim 5, characterized in that, The light-transmitting holes of the photomask template are one of square, circular, hexagonal, triangular, rhomboid, or mixed shapes, and the mixed shapes include any two of square, circular, hexagonal, triangular, and rhomboid shapes; And / or, the photomask is composed of a substrate layer and a light-shielding film layer, wherein the substrate layer material of the photomask is selected from at least one of synthetic quartz glass, low-expansion borosilicate glass and soda glass; the light-shielding film layer of the photomask is a double-layer composite, wherein the upper material is chromium, oxygen, nitrogen and carbon with a thickness of 3~10nm; and the lower material is pure chromium with a thickness of 20~50nm. Alternatively, the light-transmitting holes of the photomask are square with a side length of 1~20 μm, forming an array with a gap size of 1~20 μm; the distance between the photomask and the cadmium telluride layer is 10~50 μm; Alternatively, the long-wavelength EQE of the cadmium telluride absorbing layer is 70-86%.

7. A method for preparing a cadmium telluride thin-film solar cell, characterized in that, A cadmium telluride thin-film solar cell comprises a glass substrate, a transparent conductive layer, a window layer, a back contact layer, a metal electrode layer, and a cadmium telluride absorber layer with a specific pattern structure as described in any one of claims 5-6, comprising the following steps: S1. Deposit a transparent conductive layer on a glass substrate; S2. Deposit a window layer on the transparent conductive layer; S3. Deposit a cadmium telluride absorption layer on the window layer; S4. Deposit cadmium chloride on the surface of cadmium telluride; S5. Annealing treatment is performed on cadmium telluride with cadmium chloride coating on the surface. S6. After annealing cadmium chloride, perform the surface treatment process as described in any one of claims 1 to 4 to obtain a patterned cadmium telluride absorber layer. S7. On the patterned cadmium telluride absorber layer surface, a back contact layer and a metal electrode layer are deposited sequentially. S8. After deposition, metallization annealing is performed to obtain cadmium telluride thin-film solar cells.

8. The method for preparing a cadmium telluride thin-film solar cell according to claim 7, characterized in that, In step S1, the glass substrate is selected from soda-lime glass; And / or, in step S2, the transparent conductive layer deposition method is chemical vapor deposition or sputtering. And / or, the material of the transparent conductive layer is selected from at least one of fluorine-doped tin oxide, tin-doped indium oxide, and aluminum-doped zinc oxide; And / or, the deposition method of the window layer is selected from at least one of magnetron sputtering, thermal evaporation, near-space sublimation and gas phase transport; And / or, the material of the window layer is selected from at least one of cadmium sulfide, cadmium selenide, zinc oxide, magnesium-doped zinc oxide, indium oxide, gallium oxide, and indium gallium oxide; And / or, the thickness of the window layer is 10~300 nm.

9. The method for preparing a cadmium telluride thin-film solar cell according to claim 7, characterized in that, In step S3, the deposition method of the absorption layer is one of vacuum thermal evaporation, near-space sublimation, or gas phase transport. During the deposition of the absorption layer, the source temperature is 600~1200℃ and the substrate temperature is 400~600℃; The absorber layer is made of cadmium telluride and has a thickness of 2-5 μm.

10. The method for preparing a cadmium telluride thin-film solar cell according to claim 7, characterized in that, In step S4, the deposition method of cadmium chloride is one of thermal evaporation, spraying, roller coating or immersion; In step S5, the annealing temperature of the cadmium chloride is 300~550℃, and the annealing time is 10~50min.

11. The method for preparing a cadmium telluride thin-film solar cell according to claim 7, characterized in that, In step S7, the deposition method of the back contact layer and the metal electrode layer is selected from one of thermal evaporation or magnetron sputtering; The material of the back contact layer is selected from at least one of zinc telluride, copper-doped zinc telluride, or group V element-doped zinc telluride. The thickness of the back contact layer is 10~100nm; The material of the metal electrode layer is selected from at least one of molybdenum, aluminum, chromium, silver, copper or nickel; In step S8, the temperature of the metallization annealing treatment is 100~300℃, and the annealing time is 10~40min.

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