A docking-coupled photodetector and its fabrication method

Abstract

This application relates to the field of photodetector technology and discloses a docking-coupled photodetector and its fabrication method. The photodetector includes a silicon substrate. A silicon oxide insulating layer and a germanium buffer layer of the same thickness are disposed adjacently on the silicon substrate. A silicon waveguide is disposed above the silicon oxide insulating layer. A P-type left contact layer, an N-type right contact layer, and an intrinsic absorption layer located between the P-type left contact layer and the N-type right contact layer are disposed above the germanium buffer layer. The doping types of the P-type left contact layer and the N-type right contact layer are opposite and interchangeable. The thicknesses of the P-type left contact layer, the N-type right contact layer, and the intrinsic absorption layer are all the same as the thickness of the silicon waveguide. The germanium buffer layer effectively reduces dark current caused by heteroepitaxial growth; the docking of the intrinsic absorption layer with the silicon waveguide improves light absorption efficiency and overcomes the problem of mutual constraint between device responsivity and bandwidth.

Description

Technical Field

[0001] This application relates to the field of photodetector technology, specifically to a docking-coupled photodetector and its fabrication method. Background Technology

[0002] With the rapid development of technologies such as cloud computing, the Internet of Things, and artificial intelligence, the transmission capacity of optical communication systems is facing increasing challenges. Silicon-based group IV materials (such as germanium and germanium-tin alloys) can effectively extend the photodetector band due to their high carrier mobility and tunable bandgap. Furthermore, their fabrication processes are compatible with CMOS technology, which helps reduce the cost of large-scale manufacturing. Waveguide-coupled photodetectors developed based on these materials can achieve efficient optical coupling and photoelectric conversion on silicon photonic chips, thus providing a feasible technical approach for building next-generation high-capacity, highly integrated, and low-cost optical communication systems, helping to overcome existing communication capacity bottlenecks.

[0003] In waveguide-coupled photodetectors, evanescent wave coupling and docking coupling are two main structural forms. Currently, the evanescent wave coupling structure, with its relatively simple fabrication and mature technology, is the mainstream choice for silicon-based group IV waveguide detectors. However, this structure has an inherent contradiction in performance between responsivity and bandwidth: an excessively short absorption layer reduces light absorption efficiency, while increasing its length leads to increased junction capacitance, thus limiting the response speed. Docking coupling structures have the advantage of high light absorption efficiency per unit length, but their fabrication complexity is higher, and existing silicon-based group IV docking-coupled detectors typically exhibit high heteromaterial mismatch dislocation densities in their intrinsic regions, resulting in a significant increase in device leakage current.

[0004] To address the aforementioned issues, it is necessary to optimize the existing waveguide coupling structure. By adjusting the position of the functional layer and reducing the defect density in the active region, the junction capacitance can be controlled while improving the optical absorption efficiency. This will synergistically optimize the leakage current, responsivity, and bandwidth of the device, further enhancing its practical performance in optical communication systems. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this application provides a docking-coupled photodetector and its fabrication method, which solves the problems of insufficient coupling efficiency and the mutual constraints between leakage current, responsivity and bandwidth in existing technologies.

[0006] To achieve the above objectives, this application provides the following technical solution: a docking-coupled photodetector includes a silicon substrate, on which a silicon oxide insulating layer and a germanium buffer layer of the same thickness are disposed adjacently. A silicon waveguide is disposed above the silicon oxide insulating layer. A P-type left contact layer, an N-type right contact layer, and an intrinsic absorption layer located between the P-type left contact layer and the N-type right contact layer are disposed above the germanium buffer layer. The doping types of the P-type left contact layer and the N-type right contact layer are opposite. The thicknesses of the P-type left contact layer, the N-type right contact layer, and the intrinsic absorption layer are all the same as the thickness of the silicon waveguide. The end face of the silicon waveguide is aligned with the end face of the intrinsic absorption layer in the horizontal direction.

[0007] Preferably, the P-type left contact layer, the intrinsic absorption layer, and the N-type right contact layer are arranged laterally in a direction perpendicular to the length of the silicon waveguide.

[0008] Preferably, the silicon substrate is a silicon material with a resistivity ≥10000Ω·cm;

[0009] The silicon oxide insulating layer is made of SiO2 or Si3N4 and has a thickness between 1 and 3 μm. The silicon waveguide is made of silicon material with a resistivity ≥10000Ω·cm.

[0010] Preferably, the germanium buffer layer is a germanium material with a resistivity ≥10Ω·cm; The materials of the P-type left contact layer (5) and the N-type right contact layer (6) are both Ge or Ge1-xSnx, where x is the molar composition of Sn element and 0≤x≤1, and the resistivity of the P-type left contact layer (5) and the N-type right contact layer (6) is ≤0.01Ω·cm. The intrinsic absorption layer (7) is made of Ge or Ge1-xSnx, where x is the molar composition of Sn and 0≤x≤1.

[0011] Preferably, it further includes electrode one and electrode two, wherein electrode one is fixed to the top surface of the P-type left contact layer and electrode two is fixed to the top surface of the N-type right contact layer.

[0012] Preferably, a method for fabricating a docking-coupled photodetector includes the following steps: A silicon-on-insulator (SiO2) is provided, comprising a handle layer, a box layer, and a top-Si layer; the handle layer serves as a silicon substrate, and the box layer serves as a silicon oxide insulating layer. The top-Si layer and the box layer in the specified area are patterned and etched using photolithography and etching processes to expose the handle layer; A germanium buffer layer is selectively epitaxially grown on the exposed handle layer surface, and the thickness of the germanium buffer layer is controlled to be the same as the thickness of the unetched box layer. A P-type left contact layer, an N-type right contact layer, and an intrinsic absorption layer are sequentially formed on the surface of the germanium buffer layer, and the thicknesses of the P-type left contact layer, the N-type right contact layer, and the intrinsic absorption layer are all controlled to be the same as the thickness of the unetched top-Si layer. The unetched top-Si layer is processed using photolithography and etching to form a silicon waveguide, and the end face of the silicon waveguide is aligned with the end face of the intrinsic absorption layer in the horizontal direction.

[0013] Preferably, the step of patterning and etching the top-Si layer and the box layer in the designated area using photolithography and etching processes specifically involves: A vertical downward etching process is used to remove material from the top-Si layer and the box layer in a specified area. The etching depth is equal to the sum of the thicknesses of the top-Si layer and the box layer.

[0014] Preferably, the step of sequentially forming a P-type left contact layer, an N-type right contact layer, and an intrinsic absorption layer on the surface of the germanium buffer layer specifically includes: A hard mask is deposited to cover the device area. The hard mask in the corresponding area of ​​the P-type left contact layer is removed by photolithography and etching. After the P-type left contact layer is formed in the exposed area by selective epitaxy or ion implantation, the remaining hard mask is removed by etching. A hard mask is deposited again, and the hard mask in the corresponding area of ​​the N-type right contact layer is removed by photolithography and etching. After the N-type right contact layer is formed in the exposed area by selective epitaxy or ion implantation, the remaining hard mask is removed by etching. A hard mask is deposited again, and the hard mask in the region corresponding to the intrinsic absorption layer is removed by photolithography and etching. After the intrinsic absorption layer is formed by selective epitaxy in the exposed area, the remaining hard mask is removed by etching.

[0015] Preferably, the material of the deposited hard mask is silicon oxide, and a buffered oxide etchant is used to etch away the remaining hard mask; In forming the P-type left contact layer, the N-type right contact layer, and the intrinsic absorption layer, chemical vapor deposition or molecular beam epitaxy is used for epitaxial growth.

[0016] Preferably, after forming the silicon waveguide, the method further includes: depositing electrode one on the surface of the P-type left contact layer and electrode two on the surface of the N-type right contact layer using electron beam evaporation or magnetron sputtering processes.

[0017] This application provides a docking-coupled photodetector and its fabrication method. It has the following advantages: 1. This application alleviates the lattice mismatch and thermal mismatch problems during heteroepitaxial growth by adding a germanium buffer layer between the silicon substrate and the active region above it, thereby improving the material quality of the active region and reducing the dark current of the device. Simultaneously, by utilizing selective epitaxy, the intrinsic absorption layer and the front-end silicon waveguide are precisely aligned horizontally to form a docking coupling structure, improving the light absorption efficiency per unit length. This eliminates the need to lengthen the device to ensure light absorption, effectively controlling the increase in parasitic capacitance and solving the problem of responsivity and bandwidth constraints in traditional devices.

[0018] 2. The intrinsic absorption region of this application is constructed using germanium or germanium-tin alloy materials. In practical applications, by appropriately increasing the tin content in the absorption layer, the carrier mobility and optical absorption coefficient of the material can be effectively improved. This not only accelerates the carrier transport rate within the detector and thus improves the response speed, but also further broadens the photoelectric response band of the device, thereby improving the overall signal-to-noise ratio and operating range of the detector.

[0019] 3. The photodetector of this application is designed based on all group IV materials (silicon, germanium, germanium-tin). The processing steps involved, such as photolithography, etching, and epitaxial growth, are highly compatible with existing standard CMOS integrated circuit manufacturing processes. It not only has high process stability and feasibility, making it easy to achieve low-cost, large-scale mass production, but also provides the basic conditions for high-density monolithic integration of optoelectronic devices and microelectronic chips in the future. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the structure of the docking coupled PIN photodetector according to an embodiment of this application; Figure 2 This is a schematic diagram of the structure of the silicon substrate exposed by etching the device region in the fabrication method of this application embodiment; Figure 3 This is a schematic diagram of the structure after epitaxial growth of a germanium buffer layer in the etched region in the preparation method of the embodiments of this application; Figure 4 This is a schematic diagram of the structure after epitaxial growth of the P-type left contact layer in the preparation method of the embodiments of this application; Figure 5 This is a schematic diagram of the structure after epitaxial growth of the N-type right contact layer in the preparation method of the embodiments of this application; Figure 6 This is a schematic diagram of the structure after epitaxial growth of the intrinsic absorption layer in the preparation method of the embodiments of this application; Figure 7 This is a schematic diagram of the structure after the silicon waveguide is etched and formed in the preparation method of the embodiments of this application.

[0021] Among them, 1. silicon substrate; 2. silicon oxide insulating layer; 3. germanium buffer layer; 4. silicon waveguide; 5. P-type left contact layer; 6. N-type right contact layer; 7. intrinsic absorption layer; 8. electrode one; 9. electrode two. Detailed Implementation

[0022] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0023] Reference Figure 1 A docking-coupled photodetector includes a silicon substrate 1. A silicon oxide insulating layer 2 and a germanium buffer layer 3 of the same thickness are disposed adjacently on the silicon substrate 1. A silicon waveguide 4 is disposed on the silicon oxide insulating layer 2. A P-type left contact layer 5, an N-type right contact layer 6, and an intrinsic absorption layer 7 located between the P-type left contact layer 5 and the N-type right contact layer 6 are disposed on the germanium buffer layer 3. The doping types of the P-type left contact layer 5 and the N-type right contact layer 6 are opposite. The thicknesses of the P-type left contact layer 5, the N-type right contact layer 6, and the intrinsic absorption layer 7 are all the same as the thickness of the silicon waveguide 4. The end face of the silicon waveguide 4 is aligned with the end face of the intrinsic absorption layer 7 in the horizontal direction.

[0024] Specifically, the photodetector structure in this embodiment can be fabricated based on a silicon-on-insulator (SOI) substrate. The handle layer of the SOI serves as the bottom silicon substrate 1, the box layer of the SOI serves as the silicon oxide insulating layer 2, and the top-Si layer of the SOI is used to form the silicon waveguide 4. In this embodiment, the thickness of the silicon oxide insulating layer 2 is preferably 2µm, and the corresponding thickness of the silicon waveguide 4 is preferably 220nm.

[0025] The P-type left contact layer 5, the intrinsic absorption layer 7, and the N-type right contact layer 6 are arranged horizontally in sequence along the length of the silicon waveguide 4.

[0026] Specifically, by using this lateral arrangement and selective epitaxy, the intrinsic absorption layer 7 of the detector and the front-end silicon waveguide 4 are precisely aligned in the horizontal direction, thereby forming a direct docking coupling of the incident light and improving the light absorption efficiency per unit length of the absorption region. At the same time, compared with the traditional evanescent wave coupling structure, it does not need to rely on increasing the length of the absorption region to improve light absorption, reducing the parasitic capacitance of the device and successfully overcoming the problem of mutual constraint between detector responsivity and bandwidth.

[0027] The silicon substrate 1 is a silicon material with a resistivity ≥10000Ω·cm; The silicon oxide insulating layer 2 is made of SiO2 or Si3N4 and has a thickness between 1 and 3 μm. Silicon waveguide 4 is made of silicon material with a resistivity ≥10000Ω·cm.

[0028] Specifically, the use of a high-resistivity silicon substrate 1 with a resistivity ≥10000Ω·cm and a high-resistivity silicon waveguide 4 can effectively reduce the parasitic capacitance of the material and reduce optical transmission loss; while the silicon oxide insulating layer 2 with a thickness between 1 and 3 μm (preferably 2 μm in this embodiment) provides excellent optical field confinement and electrical isolation effects, ensuring that the optical signal can be stably transmitted in the waveguide and absorption layer.

[0029] The germanium buffer layer 3 is a germanium material with a resistivity ≥10Ω·cm; The materials of the P-type left contact layer 5 and the N-type right contact layer 6 are both Ge or Ge1-xSnx, where x is the molar composition of Sn and 0≤x≤1, and the resistivity of the P-type left contact layer 5 and the N-type right contact layer 6 is both ≤0.01Ω·cm. The intrinsic absorber layer 7 is made of Ge or Ge1-xSnx, where x is the molar composition of Sn and 0 ≤ x ≤ 1.

[0030] Specifically, the added germanium buffer layer 3 effectively isolates the lattice and thermal mismatch between the upper active region and the bottom silicon substrate, improving the crystal quality of the active region and reducing the dark current noise of the detector. In this embodiment, the intrinsic absorption layer 7 is preferably a Ge1-xSnx layer, wherein the value of x is preferably in the range of 3% to 5%. By increasing the tin composition in the intrinsic absorption layer 7, not only is the carrier mobility effectively improved to accelerate the detector response speed, but the optical absorption coefficient is also increased and the optical response band is extended, thereby improving the overall signal-to-noise ratio and detection range of the detector.

[0031] The docking-coupled photodetector also includes electrode 8 and electrode 9. Electrode 8 is fixed to the top surface of the P-type left contact layer 5, and electrode 9 is fixed to the top surface of the N-type right contact layer 6.

[0032] In addition, the docking-coupled photodetector also includes an insulating protective layer that covers the entire surface of the photodetector to protect the device structure from oxidation and moisture. Holes are made in this insulating protective layer to expose electrode 8 and electrode 9, facilitating the connection of leads to external circuits.

[0033] Reference Figure 2 A method for fabricating a docking-coupled photodetector includes the following steps: Silicon-on-insulator is provided, comprising a handle layer, a box layer, and a top-Si layer; the handle layer serves as a silicon substrate 1, and the box layer serves as a silicon oxide insulating layer 2; The top-Si layer and box layer in a specified area are patterned and etched using photolithography and etching processes to expose the handle layer; A germanium buffer layer 3 is selectively epitaxially grown on the surface of the exposed handle layer, and the thickness of the germanium buffer layer 3 is controlled to be the same as the thickness of the unetched box layer. A P-type left contact layer 5, an N-type right contact layer 6, and an intrinsic absorption layer 7 are sequentially formed on the surface of the germanium buffer layer 3, and the thicknesses of the P-type left contact layer 5, the N-type right contact layer 6, and the intrinsic absorption layer 7 are all controlled to be the same as the thickness of the unetched top-Si layer. The unetched top-Si layer is processed using photolithography and etching to form a silicon waveguide 4, and the end face of the silicon waveguide 4 is aligned with the end face of the intrinsic absorption layer 7 in the horizontal direction.

[0034] Specifically, the preparation scheme based on all group IV materials (silicon, germanium, germanium-tin) is highly compatible with existing standard CMOS integrated circuit manufacturing processes. It not only has high process stability and feasibility, but also reduces the cost of large-scale manufacturing, making it very suitable for the mass production of next-generation high-capacity, highly integrated optical communication system chips.

[0035] The top-Si layer and box layer in a specified area are patterned and etched using photolithography and etching processes, specifically as follows: The etching process is used to etch vertically downwards, with the etching depth equal to the sum of the thicknesses of the top-Si layer and the box layer, removing the top-Si layer and box layer material in the specified area.

[0036] Specifically, in this step, photolithography and dry etching processes are used to etch the active area of ​​the device. In this stage, the thickness of the silicon oxide insulating layer 2 (box layer) is 2µm and the thickness of the waveguide layer (top-Si layer) is 220nm. Therefore, the total etching depth is precisely controlled to 2220nm until the bottom silicon substrate 1 is completely exposed.

[0037] Then refer to Figure 3 A germanium buffer layer 3 with a thickness of 2µm was epitaxially grown in situ in the etched area using chemical vapor deposition, so that its upper surface is flush with the upper surface of the unetched box layer.

[0038] Reference Figures 4 to 6 The steps of sequentially forming a P-type left contact layer 5, an N-type right contact layer 6, and an intrinsic absorption layer 7 on the surface of the germanium buffer layer 3 specifically include: A hard mask is deposited to cover the device area. The hard mask corresponding to the P-type left contact layer 5 is removed by photolithography and etching. After forming the P-type left contact layer 5 in the exposed area by selective chemical vapor deposition and in-situ doping, the remaining hard mask is removed by etching. The hard mask is deposited again, and the hard mask corresponding to the N-type right contact layer 6 is removed by photolithography and etching. After forming the N-type right contact layer 6 in the exposed area by selective chemical vapor deposition and in-situ doping, the remaining hard mask is removed by etching. A hard mask is deposited again, and the hard mask in the corresponding area of ​​the intrinsic absorption layer 7 is removed by photolithography and etching. After the intrinsic absorption layer 7 is formed in the exposed area by selective chemical vapor deposition, the remaining hard mask is removed by etching.

[0039] Specifically, in this step, each hard mask deposited is a 300nm thick silicon oxide layer. When epitaxially growing the left P-type contact layer 5, boron is used as the dopant atom to control the resistivity of the doped layer to 0.005Ω·cm; when epitaxially growing the right N-type contact layer 6, phosphorus is used as the dopant atom to control the resistivity of the doped layer to the same 0.005Ω·cm. This step-by-step masking and growth process ensures clear boundaries between regions and prevents cross-contamination.

[0040] The material of the deposited hard mask is silicon oxide, and a buffered oxide etchant is used to etch away the remaining hard mask. Specifically, a buffered oxide etchant (BOE) is used to etch and remove the remaining silicon oxide hard mask. The BOE solution has a high etch selectivity for silicon oxide, which can completely remove the hard mask without damaging the surface morphology of the underlying epitaxial germanium or germanium-tin alloy layer, thus ensuring the high quality of the interface between the subsequent doped layer and the electrode.

[0041] Reference Figure 7 After forming the silicon waveguide 4, the process also includes: depositing electrode 8 on the surface of the P-type left contact layer 5 and electrode 9 on the surface of the N-type right contact layer 6 using electron beam evaporation or magnetron sputtering processes.

[0042] Specifically, after completing the epitaxy of the PIN active structure, photolithography and etching processes are used to finely etch the reserved unetched top-Si region to fabricate a silicon waveguide 4 with a width and morphology that meet the requirements for optical transmission. Finally, metal electrodes are deposited to complete the device closed loop, which not only has low coupling loss and high detection efficiency, but also a high yield, making it valuable for industrial applications.

[0043] Working principle: When the optical signal is transmitted forward in the silicon waveguide 4, since the end face of the silicon waveguide 4 is precisely aligned with the end face of the intrinsic absorption layer 7 in the horizontal direction, the optical signal is directly injected into the interior of the intrinsic absorption layer 7 through docking coupling. The bottom silicon oxide insulating layer 2 plays a role in limiting the optical field and preventing the optical signal from leaking to the bottom silicon substrate 1. When the device is in operation, a reverse bias voltage is applied to electrode 8, which is fixed on the left P-type contact layer 5, and electrode 9, which is fixed on the right N-type contact layer 6, through an external circuit, thereby establishing a strong electric field in the lateral PIN structure formed by the left P-type contact layer 5, the intrinsic absorption layer 7, and the right N-type contact layer 6. Photons that enter the intrinsic absorption layer 7 are absorbed by germanium or germanium-tin material. The photon energy excites electrons in the valence band of the material to jump to the conduction band, thereby generating a large number of electron-hole pairs, i.e., photogenerated carriers, in the intrinsic absorption layer 7. Under the influence of the built-in electric field, these photogenerated carriers are rapidly separated and drift. Photogenerated holes drift towards the left P-type contact layer 5 and are eventually collected by electrode 8; photogenerated electrons drift towards the right N-type contact layer 6 and are eventually collected by electrode 9. The photogenerated carriers collected by electrodes 8 and 9 form a continuous photocurrent in the external circuit, thereby realizing the conversion of optical signals to electrical signals. In this process, the germanium buffer layer 3 effectively alleviates lattice mismatch and ensures the crystal quality of the upper absorption region, so that the device maintains a low dark current noise during operation.

Claims

1. A docking-coupled photodetector, characterized in that, The device includes a silicon substrate (1), on which a silicon oxide insulating layer (2) and a germanium buffer layer (3) of the same thickness are disposed adjacently in the horizontal direction. A silicon waveguide (4) is disposed above the silicon oxide insulating layer (2). A P-type left contact layer (5), an N-type right contact layer (6), and an intrinsic absorption layer (7) located between the P-type left contact layer (5) and the N-type right contact layer (6) are disposed above the germanium buffer layer (3). The doping types of the P-type left contact layer (5) and the N-type right contact layer (6) are opposite and interchangeable. The thicknesses of the P-type left contact layer (5), the N-type right contact layer (6), and the intrinsic absorption layer (7) are all the same as the thickness of the silicon waveguide (4). The end face of the silicon waveguide (4) is aligned with the end face of the intrinsic absorption layer (7) in the horizontal direction.

2. The docking-coupled photodetector according to claim 1, characterized in that, The P-type left contact layer (5), the intrinsic absorption layer (7), and the N-type right contact layer (6) are arranged laterally in a direction perpendicular to the length of the silicon waveguide (4).

3. The docking-coupled photodetector according to claim 1, characterized in that, The silicon substrate (1) is a silicon material with a resistivity ≥10000Ω·cm; The silicon oxide insulating layer (2) is made of SiO2 or Si3N4 and has a thickness between 1 and 3 μm. The silicon waveguide (4) is made of silicon material with a resistivity ≥10000Ω·cm.

4. A docking-coupled photodetector according to claim 1, characterized in that, The germanium buffer layer (3) is a germanium material with a resistivity ≥10Ω·cm; The materials of the P-type left contact layer (5) and the N-type right contact layer (6) are both Ge or Ge1-xSnx, where x is the molar composition of Sn element and 0≤x≤1, and the resistivity of the P-type left contact layer (5) and the N-type right contact layer (6) is ≤0.01Ω·cm. The intrinsic absorption layer (7) is made of Ge or Ge1-xSnx, where x is the molar composition of Sn and 0≤x≤1.

5. A docking-coupled photodetector according to claim 1, characterized in that, It also includes electrode one (8) and electrode two (9), wherein electrode one (8) is fixed to the top surface of the P-type left contact layer (5) and electrode two (9) is fixed to the top surface of the N-type right contact layer (6).

6. A method for fabricating a docking-coupled photodetector, characterized in that, The method for preparing a docking-coupled photodetector as described in any one of claims 1 to 5 includes the following steps: Silicon on insulator is provided, the silicon on insulator comprising a handle layer, a box layer and a top-Si layer; the handle layer is used as a silicon substrate (1), and the box layer is used as a silicon oxide insulating layer (2). The top-Si layer and the box layer in the specified area are patterned and etched using photolithography and etching processes to expose the handle layer; A germanium buffer layer (3) is selectively epitaxially grown on the exposed handle layer surface, and the thickness of the germanium buffer layer (3) is controlled to be the same as the thickness of the unetched box layer; When forming the germanium buffer layer (3), epitaxial growth is performed using chemical vapor deposition or molecular beam epitaxy. A P-type left contact layer (5), an N-type right contact layer (6), and an intrinsic absorption layer (7) are sequentially formed on the surface of the germanium buffer layer (3), and the thicknesses of the P-type left contact layer (5), the N-type right contact layer (6), and the intrinsic absorption layer (7) are controlled to be the same as the thickness of the unetched top-Si layer. The unetched top-Si layer is processed using photolithography and etching to form a silicon waveguide (4), and the end face of the silicon waveguide (4) is aligned with the end face of the intrinsic absorption layer (7) in the horizontal direction.

7. The preparation method according to claim 6, characterized in that, The process of patterning and etching the top-Si layer and the box layer in a designated area using photolithography and etching techniques is as follows: A vertical downward etching process is used to remove material from the top-Si layer and the box layer in a specified area. The etching depth is equal to the sum of the thicknesses of the top-Si layer and the box layer.

8. The preparation method according to claim 6, characterized in that, The steps of sequentially forming a P-type left contact layer (5), an N-type right contact layer (6), and an intrinsic absorption layer (7) on the surface of the germanium buffer layer (3) specifically include: A hard mask is deposited to cover the device area. The hard mask in the corresponding area of ​​the P-type left contact layer (5) is removed by photolithography and etching. After the P-type left contact layer (5) is formed in the exposed area by selective epitaxy combined with in-situ doping or ion implantation, the remaining hard mask is removed by etching. The hard mask is deposited again, and the hard mask in the corresponding area of ​​the N-type right contact layer (6) is removed by photolithography and etching. After the N-type right contact layer (6) is formed in the exposed area by selective epitaxy combined with in-situ doping or ion implantation, the remaining hard mask is removed by etching. The hard mask is deposited again, and the hard mask in the corresponding area of ​​the intrinsic absorption layer (7) is removed by photolithography and etching. After the intrinsic absorption layer (7) is formed by selective epitaxy in the exposed area, the remaining hard mask is removed by etching.

9. The preparation method according to claim 8, characterized in that, The material of the deposited hard mask is silicon oxide, and a buffered oxide etchant is used to etch away the remaining hard mask. When forming the P-type left contact layer (5), the N-type right contact layer (6), and the intrinsic absorption layer (7), chemical vapor deposition or molecular beam epitaxy is used for epitaxial growth.

10. The preparation method according to claim 6, characterized in that, After forming the silicon waveguide (4), the process further includes: depositing electrode one (8) on the surface of the P-type left contact layer (5) and electrode two (9) on the surface of the N-type right contact layer (6) using electron beam evaporation or magnetron sputtering processes.

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