A silicon substrate superconducting transmon qubit and a method of fabricating the same

Abstract

This application discloses a silicon substrate superconducting Transmon quantum bit and its fabrication method. The fabrication method includes: providing a silicon substrate; fabricating an annular groove pattern on a first surface of the silicon substrate; etching the groove pattern and etching the annular groove on the first surface of the silicon substrate; removing the oxide layer on the first surface of the silicon substrate by a first etching; continuing to grow an aluminum film on the first surface of the silicon substrate; etching to fabricate capacitor pads on the surface of the aluminum film; removing the oxide layer on the first surface of the silicon substrate by a second etching; fabricating a Josephson junction at the central support position between two capacitor pads on the silicon substrate, connecting the Josephson junction to the capacitor pads; removing the oxide layer on the first surface of the silicon substrate by a third etching; and obtaining a silicon substrate superconducting Transmon quantum bit; wherein the first etching, second etching, and third etching are all HF vapor phase etching.

Description

Technical Field

[0001] This application relates to the field of superconducting quantum chip micro / nano fabrication technology, specifically to a silicon substrate superconducting Transmon quantum bit and its fabrication method. Background Technology

[0002] The performance of superconducting qubits is primarily limited by the energy relaxation time (T1). Studies have shown that the native oxide layer (SiO2) and its two-level system (TLS) at the interface between the silicon substrate and the superconducting circuit are the main sources of energy dissipation. Research has also revealed that the loss weight at the metal-substrate (MS) interface (approximately 10⁻⁶) is a significant factor. -5 ) compared to the metal-air (MA) interface (approximately 10 -7 The loss is about two orders of magnitude higher, which is a key bottleneck limiting T1. Existing technologies attempt to reduce losses through wet etching or suspended structures, but structural damage or process residues still exist. Summary of the Invention

[0003] To address the aforementioned deficiencies in this field, this application aims to provide a silicon substrate superconducting Transmon quantum bit and its fabrication method.

[0004] According to one aspect of this application, a method for fabricating a silicon substrate superconducting Transmon quantum bit is provided, comprising: Define an annular groove pattern on the first surface of the silicon substrate; Etching groove patterns to fabricate annular groove structures on the first surface of a silicon substrate; The oxide layer on the first surface of the silicon substrate is removed by the first etching; An aluminum film is grown on the first surface of a silicon substrate having an annular groove structure; Capacitor pads are prepared by etching on the surface of an aluminum film; The oxide layer on the first surface of the silicon substrate is removed by a second etching process; A Josephson junction is fabricated at the center of an annular groove in a silicon substrate, and then connected to a capacitor pad. The oxide layer on the first surface of the silicon substrate is removed by a third etching process; a silicon substrate superconducting Transmon quantum bit is then obtained. The first, second, and third etching processes were all HF vapor phase etching.

[0005] According to some embodiments of this application, the etching depth of the groove pattern is 1-2 μm.

[0006] According to some embodiments of this application, the thickness of the silicon substrate is 500±10μm.

[0007] According to some embodiments of this application, the gas used for HF vapor phase etching is a mixture of N2, EtOH, and HF.

[0008] According to some embodiments of this application, the gas flow rates are: 1000-1500 sccm for N2, 200-350 sccm for EtOH, and 300-450 sccm for HF, and the sum of the total gas flow rates is ≤1950 sccm.

[0009] According to some embodiments of this application, the temperature of the gas used for HF vapor phase etching is 50~60℃, the etching time is ≤30min, and the gas pressure is 75±10Torr.

[0010] According to another aspect of this application, a silicon substrate superconducting Transmon quantum bit prepared by the above-described preparation method is also provided, comprising: A silicon substrate, the first surface of which has an annular groove structure; the annular groove structure includes a central support pillar and an annular groove region located around the central support pillar; Josephson knots grow above the central support post; The capacitor pads are grown in the annular groove region; the edges of the aluminum-based capacitor pads are suspended above the annular groove region and connected to the Josephson junction.

[0011] According to some embodiments of this application, the width of the central support column is 2-8 μm and the height is 1-2 μm.

[0012] According to some embodiments of this application, the width of the annular groove region is 1-3 μm and the depth is 1-2 μm.

[0013] According to some embodiments of this application, the capacitor pad is an aluminum-based capacitor pad. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of the fabrication process of silicon substrate superconducting Transmon qubits, which is an example embodiment of this application.

[0015] Figure 2 This is a schematic diagram of the packaging process for a silicon substrate superconducting Transmon quantum bit chip, which is an example embodiment of this application.

[0016] Figure 3 The locations and sample numbers of the silicon substrate superconducting Transmon qubits used for junction resistance testing are shown in the example embodiment of this application.

[0017] Figure 4 AFM morphology images of silicon substrate superconducting Transmon qubits before and after HF vapor phase etching, which are examples of embodiments of this application.

[0018] Figure 5 The image shows the SEM images of the same location in the EDS energy spectrum comparison analysis of the Transmon qubit without HF vapor phase etching, after HF vapor phase etching for 1 min, and after etching for 5 min. Detailed Implementation

[0019] The technical solution of this application will be clearly and completely described below with reference to the embodiments of this application. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0020] It should be particularly noted that similar substitutions and modifications made to this application are obvious to those skilled in the art, and they are all considered to be included in this application. Those skilled in the art can obviously make modifications or appropriate alterations and combinations to the methods and applications described herein without departing from the content, spirit, and scope of this application to implement and apply the technology of this application. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0021] Unless otherwise specified, this application is conducted under standard conditions or conditions recommended by the manufacturer. The raw materials or excipients used, as well as the reagents or instruments used, whose manufacturers are not specified, are all conventional products that can be obtained commercially.

[0022] The following is a detailed description of this application.

[0023] This application reveals that, in the prior art, superconducting qubits face an imbalance between performance improvement and process reliability and physical stability in the pursuit of low dielectric loss. The specific technical problems are as follows: Technical drawbacks of the fluorine-based wet process: Low manufacturing yield: The capillary forces generated during the drying stage of liquid phase etching can easily cause the adhesion and collapse of nanoscale microstructures (such as aluminum bridges or Josephson junctions), making it impossible to fabricate chips on a large scale.

[0024] Poor process reliability: The residue of HF solution in the micro-nano gaps is difficult to completely remove, which will introduce uncontrollable chemical impurities and lead to the degradation of superconducting film performance in the long term.

[0025] Technical drawbacks of the fully suspended Josephson knot scheme: Mechanical support failure: When the Josephson junction loses its physical support, the structure becomes fragile and unable to withstand the mechanical stress of flip-chip bonding, resulting in low packaging yield. Simultaneously, the bit frequency is highly sensitive to mechanical vibration, and coherence is severely affected by mechanical disturbances.

[0026] Electromagnetic environment degradation: The fully suspended structure causes the bits to deviate from the superconducting shielded ground plane, which significantly enhances the magnetic flux noise.

[0027] This application employs a unique "central solid support + peripheral annular groove" structure, which provides solid physical support for the fragile Josephson junction while moving the high electric field region at the edge of the aluminum-based capacitor pad to the air gap. This reduces the loss weight of the metal-substrate (MS) interface by about two orders of magnitude, achieving both low dielectric loss and high mechanical stability.

[0028] This application is the first to employ alcohol-catalyzed HF vapor-phase etching to replace the traditional wet process. It removes the natural oxide layer of silicon oxide non-destructively through vapor-phase reaction, solving the problems of structural adhesion and chemical residue caused by capillary forces in the liquid phase environment. Furthermore, the fabrication process of this application controls the time window from HF vapor-phase etching to sample encapsulation within 8 hours, strictly controlling the regeneration of the natural oxide layer. In short, this application systematically solves the contradiction between low dielectric loss and mechanical stability through a three-pronged innovation of "geometric design – vapor-phase cleaning – aging control".

[0029] In some examples, this application achieves the above-mentioned technical effects through the following technical solutions.

[0030] like Figure 1 As shown in the example embodiment of this application, a method for fabricating a silicon substrate superconducting Transmon quantum bit is provided, comprising: Step A: Provide a silicon substrate (a), spin-coat photoresist on the first surface of the silicon substrate (b), expose and develop to prepare an annular groove pattern; Step B: Etching the groove pattern to prepare an annular groove structure (Z) on the first surface of the silicon substrate (a); optionally, DRIE deep silicon etching to etch the annular groove to a depth of 1-2 μm.

[0031] Step C: Remove the photoresist (b) and remove the oxide layer (d) on the first surface of the silicon substrate (a) by the first etching. Step D: Continue growing an aluminum film (c) on the first surface of the silicon substrate having an annular groove structure (Z); optionally, the aluminum film thickness is 100 nm; Step E: Photolithography + etching + removal of residual photoresist, etching to prepare capacitor pads (Y) on the aluminum film surface; Step F: Remove the oxide layer (d) regenerated on the first surface of the silicon substrate by a second etching; Step G: Fabricate a Josephson junction (X) at the center of an annular groove in the silicon substrate, connecting the Josephson junction to the capacitor pad; optionally, fabricate the Josephson junction (X) on the upper surface of the silicon wafer using EBL and dual-angle evaporation processes. The growth location of the Josephson junction (X) must be accurately connected to the capacitor pad / interconnection line on the upper surface.

[0032] Step H: Remove the oxide layer (d) on the first surface of the silicon substrate by a third etching; and obtain the silicon substrate superconducting Transmon quantum bit.

[0033] In some example embodiments, this application uses, as Figure 2 The steps shown illustrate the packaging of the silicon substrate superconducting Transmon quantum bit chip of this application. Optionally, a flowchart of the process for treating the chip surface with hydrofluoric acid vapor phase etching before packaging is shown below. Figure 2 As shown, the total time for steps two through four should be controlled within 8 hours to prevent the natural oxide layer from reforming on the silicon substrate surface.

[0034] Optionally, after the upper and lower wafers of the silicon-based quantum chip are integrated using flip-chip bonding, the chip is placed in a hydrofluoric acid vapor phase etching machine. A suitable recipe and etching time are selected to treat the chip surface. After surface treatment, the chip is packaged in a sample box using wire bonding. The sample is then connected to the cooling system. After confirmation, the cooling system is cooled down.

[0035] Further optionally, the process parameters for the first, second, and third etching processes of this application are as follows: the temperature of the chamber and the process gas is between 50 and 60°C, and the process time does not exceed 30 minutes.

[0036] Optionally, the gas pressure for HF vapor phase etching is 75±10 Torr.

[0037] Optionally, the gas used for HF vapor phase etching is a mixture of N2, EtOH, and HF.

[0038] Optionally, the gas flow rates are: 1000-1500 sccm for N2, 200-350 sccm for EtOH, and 300-450 sccm for HF, and the sum of the total gas flow rates is ≤1950 sccm.

[0039] Test case The following experiments verify that the HF vapor phase etching method of this application can effectively remove the natural oxide layer on the surface of a superconducting quantum chip on an aluminum-based silicon substrate, without affecting the bit structure and junction resistance of the chip surface, i.e., without affecting the bit frequency: 1. Before chip processing, test the junction resistance of the bits, the AFM topography of specific regions, and the EDS energy spectrum of the scanning electron microscope.

[0040] The experimental results are shown below: The effect of hydrofluoric acid vapor phase treatment on aluminum-based Josephson junctions: Junction resistance test results show that HF ​​vapor phase treatment does not affect the junction resistance of the bit, and therefore does not affect the bit frequency. Figure 3,in, Figure 3 The test results for positions 1 and 2 are shown in Table 1.

[0041] Table 1

[0042] 2. Comparison of AFM morphology of the region before and after 1 min of HF vapor phase etching.

[0043] The effect of hydrofluoric acid vapor phase treatment on chip surface roughness: based on test results Figure 4 It can be seen that the surface roughness of the chip is improved to a certain extent after HF vapor phase treatment. Before HF treatment, the root mean square roughness is 2.6 nm; after HF treatment, the root mean square roughness is 2.1 nm.

[0044] 3. Data were collected from the same location on the quantum chip under the following conditions: no HF vapor phase etching, HF vapor phase etching for 1 min, and HF vapor phase etching for 5 min (locations are shown in the image). Figure 5 The SEM-EDS energy dispersive spectroscopy and elemental analysis results of the sample are shown in Table 2.

[0045] The effect of hydrofluoric acid vapor phase treatment on the Al / Si / O element ratio on the chip surface: As shown in Table 2, after hydrofluoric acid vapor phase treatment, the oxygen element ratio decreased from the initial 0.81% to 0.44%, proving that HF ​​vapor phase treatment can effectively remove the oxide layer on the chip surface.

[0046] Table 2

[0047] The silicon substrate superconducting Transmon quantum bit device fabricated using the method described in this application utilizes annular grooves to push the high-field region at the capacitor edge away from the silicon substrate, combined with vapor phase etching to non-destructively remove the natural oxide layer (SiO2), reducing the interface loss weight by approximately two orders of magnitude. The central support pillar provides robust physical support for the Josephson junction, effectively resisting mechanical vibration and reducing frequency drift, thus balancing mechanical stability and low noise performance. The HF vapor phase etching process eliminates microstructure adhesion and chemical residues caused by the HF liquid environment. This robust support structure ensures the chip can withstand the mechanical stresses of integration processes such as flip-chip bonding, significantly improving manufacturing yield and packaging compatibility, achieving a balance between high performance and reliability in large-scale production.

[0048] The above description of the embodiments is only for the purpose of helping to understand the method and core ideas of this application. It should be noted that, for those skilled in the art, several improvements and modifications can be made to this application without departing from the principles of this application, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A method of fabricating a superconducting Transmon qubit on a silicon substrate, the method comprising: include: A ring-shaped groove pattern is defined on the first surface of a silicon substrate using a photolithography process; The groove pattern is etched to form an annular groove structure on the first surface of the silicon substrate; The oxide layer on the first surface of the silicon substrate is removed by a first etching. An aluminum film is grown on the first surface of the silicon substrate having the annular groove structure; Capacitor pads are prepared by etching on the surface of the aluminum film; The oxide layer on the first surface of the silicon substrate is removed by a second etching. A Josephson junction is formed at the center of the annular groove on the silicon substrate, and the Josephson junction is connected to the capacitor pad. The silicon substrate superconducting Transmon quantum bit is obtained by removing the oxide layer on the first surface of the silicon substrate through a third etching. Wherein, the first etching, the second etching, and the third etching are all HF vapor phase etching; The gas used for the HF vapor phase etching is a mixture of N2, EtOH, and HF.

2. The method for fabricating silicon substrate superconducting Transmon qubits according to claim 1, characterized in that, The etching depth of the groove pattern is 1-2 μm.

3. The method for fabricating silicon substrate superconducting Transmon qubits according to claim 2, characterized in that, The thickness of the silicon substrate is 500±10μm.

4. The method for fabricating a silicon substrate superconducting Transmon quantum bit according to claim 1, characterized in that, The gas flow rates are: 1000-1500 sccm for N2, 200-350 sccm for EtOH, and 300-450 sccm for HF, and the sum of the total gas flow rates is ≤1950 sccm.

5. The method for fabricating a silicon substrate superconducting Transmon quantum bit according to claim 1, characterized in that, The temperature of the gas used for HF vapor phase etching is 50~60℃, the etching time is ≤30 min, and the gas pressure is 75±10 Torr.

6. A silicon substrate superconducting Transmon quantum bit prepared by the preparation method according to any one of claims 1-5, characterized in that, include: A silicon substrate, wherein a first surface of the silicon substrate has an annular groove structure, the annular groove structure including a central support pillar and an annular groove region located around the central support pillar; Josephson knots grow above the central support post; A capacitor pad is grown in the annular groove region, with the edge of the capacitor pad suspended above the annular groove region and connected to the Josephson junction.

7. The silicon substrate superconducting Transmon quantum bit according to claim 6, characterized in that, The width of the central support column is 2-8 μm and the height is 1-2 μm.

8. The silicon substrate superconducting Transmon quantum bit according to claim 7, characterized in that, The width of the annular groove region is 1-3 μm and the depth is 1-2 μm.

9. The silicon substrate superconducting Transmon quantum bit according to claim 6, characterized in that, The capacitor pads are aluminum-based capacitor pads.

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