A logic analyzer and method for real-time state analysis based on pipelines.

Abstract

This invention discloses a logic analyzer and method for real-time state analysis based on pipelines, belonging to the field of electronic digital data processing technology. It solves the problems of existing logic analyzers, such as inability to perform real-time online analysis, large data storage volume of invalid sampling points, high storage bandwidth consumption, and difficulty in dynamically compressing sampled data. It includes: a SerDes sampling module, which synchronously acquires a state clock signal and M digital channel signals; a serial-to-parallel conversion module, which converts serial sampled data into parallel sampled data; a two-stage pipeline processing module, where the first stage pipeline identifies valid edges of the parallel state clock sampled data, and the second stage pipeline extracts the states corresponding to valid edges from the parallel state sampled data, recording them as valid states; a shift register dynamic compression module, which synchronously writes valid states into the shift register; and a trigger judgment module, which generates state trigger signals in real time based on valid state trigger judgments. This invention can perform real-time state analysis and dynamically compress sampled data.

Description

Technical Field

[0001] This invention relates to the field of electronic digital data processing technology, and in particular to a logic analyzer and method based on pipelined real-time state analysis. Background Technology

[0002] Logic analyzers typically use the state clock signal provided by the system under test (SUT) as a reference clock signal. They acquire the logic levels of multiple digital channels provided by the SUT at the effective edges of the state clock signal, thereby obtaining the state sequence of the SUT at different times. This allows for further functions such as state triggering, protocol analysis, and fault location. Logic analyzers used in high-speed state triggering scenarios (such as high-speed embedded system testing) simultaneously acquire the state clock signal and multiple digital channel signals of the SUT to meet high-speed sampling requirements. The acquired serially sampled data is written into memory as a whole. After all data acquisition is complete, the back-end logic or software of the FPGA (Field-Programmable Gate Array) performs post-analysis based on the data in memory.

[0003] In the process of realizing this invention, the inventors discovered at least the following problems in the prior art: 1. The inability to perform real-time online analysis during data acquisition makes it difficult to support high-speed status triggering; 2. There are many invalid sampling points in the serial sampling data, which wastes a lot of storage resources, increases the data transfer bandwidth and subsequent analysis burden. In addition, the number and position of valid state data (the state corresponding to the valid edge of the state clock signal) in each working cycle of the FPGA in the logic analyzer are not fixed, making it difficult to effectively compress the sampling data using existing compression methods that use fixed position extraction or fixed ratio compression. Summary of the Invention

[0004] The purpose of this invention is to provide a logic analyzer and method based on pipelined real-time state analysis, to solve the technical problems of existing logic analyzers, such as the inability to perform real-time online analysis, large data storage of invalid sampling points, high storage bandwidth consumption, and difficulty in dynamically compressing sampled data. The various technical effects of the preferred solutions among the many technical solutions provided by this invention are detailed below.

[0005] To achieve the above objectives, the present invention provides the following technical solution: This invention provides a logic analyzer based on pipelined real-time state analysis, comprising: a SerDes sampling module, which synchronously acquires the state clock signal output by the system under test and Each digital channel signal is generated, and serial sampling data is produced. The integer is positive; the system under test is a high-speed embedded system; the serial-to-parallel conversion module is used to convert the serial sampling data into parallel sampling data, the parallel sampling data including parallel state clock sampling data aligned with sampling points and Parallel state sampling data from multiple digital channels; a two-stage pipelined processing module, within one FPGA work cycle: the first-stage pipeline identifies valid edges of the parallel state clock sampling data for the current FPGA work cycle; the second-stage pipeline, based on the valid edges identified by the first-stage pipeline in the previous FPGA work cycle, processes the data from the previous FPGA work cycle... Valid states are extracted from the parallel state sampling data of each digital channel. The valid edge is either a rising edge or a falling edge, and the valid state corresponds to the valid edge identified by the first-stage pipeline. The shift register dynamic compression module then extracts the valid states from the second-stage pipeline. The valid status of each digital channel is synchronously written to the shift register group; the trigger judgment module obtains the status in real time from the two-stage pipeline processing module and / or the shift register group. The effective status of each digital channel, based on real-time... The system determines the validity status of each digital channel and generates a status trigger signal.

[0006] Preferably, the number of sampling points of the parallel state clock sampling data and the parallel state sampling data are determined according to the ratio of the sampling rate of the SerDes sampling module to the internal operating frequency of the FPGA.

[0007] Preferably, the parallel state clock sampling data includes Clock sample value at each sampling point The value is a positive integer; in the two-stage pipeline processing module, the first stage pipeline performs effective edge identification on the parallel state clock sampling data, including: calculating the effective edge flag bit of each sampling point based on the clock sampling value of each sampling point and its previous sampling point, wherein the effective edge flag bit indicates whether there is a valid edge between each sampling point and its previous sampling point; The effective edge flag vector is composed of the effective edge flag bits of each sampling point.

[0008] Preferably, when the effective edge is a rising edge, the sampling point The valid edge flag is: ; When the effective edge is a falling edge, the sampling point The valid edge flag is: ; in, ; Indicates sampling point Previous sampling point The clock sample value; Indicates sampling point The result of inverting the clock sample value; Indicates sampling point Previous sampling point The result of inverting the clock sample value; Indicates sampling point The clock sample value.

[0009] Preferably, in the two-stage pipeline processing module, the second-stage pipeline starts from... The effective states are extracted in parallel from the parallel state sampling data of each digital channel, including: obtaining the effective edge flag vector obtained from the first-stage pipeline; and, based on the effective edge flag vector, extracting the effective states in parallel from... From the parallel state sampling data of the digital channels, extract the state corresponding to all sampling points whose effective edge flag bit is equal to the preset flag value.

[0010] Preferably, the logic analyzer further includes: a buffer module, which reads and stores valid states from the shift register when the number of valid states stored in the shift register reaches a preset storage quantity threshold; A storage module, connected to the buffer module, reads valid states from the buffer module and stores them.

[0011] Preferably, the shift register dynamic compression module synchronously writes the valid states of the M digital channels extracted by the second-stage pipeline into the shift register group, including: counting the number of valid edges identified by the first-stage pipeline based on the valid edge flag vector. ;like Then The corresponding effective edges The group's valid state is stored in the shift register group until the shift register group is full. After the shift register group is full, the data stored in the shift register group is... The group's valid state is stored in the buffer module, the shift register group is cleared, and the remaining... The group's valid state serves as the new starting data for the shift register group; if Then The corresponding effective edges The group's valid state is written to the shift register; where, This indicates the maximum number of valid state groups that the shift register can store; This indicates the number of valid state groups that the shift register has stored.

[0012] Preferably, the trigger determination module obtains the information in real time from the two-stage pipeline processing module and / or the shift register dynamic compression module. The valid status of each digital channel.

[0013] This invention provides a real-time status analysis method based on a pipeline, the method comprising: Synchronously acquire the status clock signal output by the system under test and Each digital channel signal is generated, and serial sampling data is produced. The integer is positive; the system under test is a high-speed embedded system; the serial sampling data is converted into parallel sampling data, which includes parallel state clock sampling data aligned with sampling points and... Parallel state sampling data from multiple digital channels; a two-stage pipeline is constructed within one FPGA work cycle: the first-stage pipeline identifies valid edges of the parallel state clock sampling data for the current FPGA work cycle; the second-stage pipeline, based on the valid edges identified by the first-stage pipeline in the previous FPGA work cycle, extracts data from the previous FPGA work cycle... Valid states are extracted from the parallel state sampling data of each digital channel. The valid edge is either a rising edge or a falling edge, and the valid state corresponds to the valid edge identified by the first-stage pipeline. The states extracted by the second-stage pipeline are then... The valid status of each digital channel is synchronously written to the shift register group; and the status is obtained in real time from the two-stage pipeline processing module and / or the shift register group. The effective status of each digital channel, based on real-time... The system determines the validity status of each digital channel and generates a status trigger signal.

[0014] Implementing one of the above-described technical solutions of the present invention has the following advantages or beneficial effects: The serial-to-parallel conversion module works synchronously with the SerDes sampling module. During the SerDes sampling process, it synchronously converts the serial sampling data into parallel sampling data that can be processed in parallel within each working cycle of the FPGA, reducing the pressure on the FPGA's internal logic frequency. To avoid the limitations of existing compression methods that rely on fixed-position decimation or fixed-ratio compression, this invention utilizes a two-stage pipeline processing module to extract data from the parallel sampling data. The valid states of each digital channel are analyzed using a two-stage pipeline with staggered processing. The state analysis process is divided into two FPGA work cycles. This pipeline splitting reduces the combinational logic complexity per work cycle, allows more time for edge extraction and data compression, increases the FPGA's maximum internal operating frequency, and enhances the reliability of high-speed state analysis. The first-stage pipeline identifies all valid edges bit-by-bit from the parallel state clock sampling data of the current FPGA work cycle. The second-stage pipeline synchronously retrieves data from the previous FPGA work cycle. Extracting the states corresponding to all valid edges from the parallel state sampling data of each digital channel, i.e., the valid states, ensures dynamic compression based on the actual position and number of valid states. After extracting the valid state data, the trigger judgment module can be started to perform trigger judgment without waiting for all data to be collected before trigger judgment, realizing real-time state analysis and high-speed triggering, supporting high-speed state triggering scenarios. At the same time, the shift register group only stores valid states, which can save more valid states and improve the state triggering depth and deep triggering real-time performance of the logic analyzer. The first pipeline identifies the valid bits bit by bit, and the valid state data extracted by the second pipeline is written into the shift register group. The valid state data is stored according to the alignment and order of the sampling points to avoid storing the states of invalid sampling points, thereby reducing the storage bandwidth. It can dynamically write the valid state data into the shift register group according to the actual number and position of the valid states, realizing variable-length valid dynamic data compression. When the state clock frequency of the system under test is low, the compression ratio can be increased; when the state clock frequency of the system under test is high, the compression ratio can be appropriately reduced, and the amount of data that needs to be processed and stored is greatly reduced. Attached Figure Description

[0015] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. In the drawings: Figure 1 This is an internal structure block diagram of the logic analyzer in Embodiment 1 of the present invention; Figure 2 This is another internal structure block diagram of the logic analyzer in Embodiment 1 of the present invention; Figure 3 This is a schematic diagram of the processing process of the two-stage pipeline processing module in Embodiment 1 of the present invention; Figure 4 This is a schematic diagram of a shift register in the shift register group being written to a valid state in Embodiment 1 of the present invention; Figure 5This is another internal structure block diagram of the logic analyzer in Embodiment 2 of the present invention; Figure 6 This is a flowchart of the real-time status analysis method of the logic analyzer in Embodiment 2 of the present invention; Figure 7 This is a flowchart illustrating the real-time status analysis method based on pipeline in Embodiment 3 of the present invention. Detailed Implementation

[0016] To make the objectives, technical solutions, and advantages of the present invention clearer, various exemplary embodiments described below will be referenced to the accompanying drawings, which form part of the exemplary embodiments, illustrating various exemplary embodiments that may be used to implement the present invention. Unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. It should be understood that they are merely examples of processes, methods, and apparatuses consistent with some aspects of the present invention disclosed as detailed in the appended claims, and other embodiments may be used, or structural and functional modifications may be made to the embodiments listed herein without departing from the scope and spirit of the present invention.

[0017] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," etc., indicate the orientation or positional relationship based on the accompanying drawings, and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the referred element must have a specific orientation, or be constructed and operated in a specific orientation. The terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. The term "multiple" means two or more. The terms "connected" and "linked" should be interpreted broadly, for example, they can be fixed connections, detachable connections, integral connections, mechanical connections, electrical connections, communication connections, direct connections, indirect connections through an intermediate medium, and can be the internal connection of two elements or the interaction relationship between two elements. The term "and / or" includes any and all combinations of one or more of the related listed items. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0018] To illustrate the technical solution described in this invention, specific embodiments are described below, showing only the parts related to the embodiments of this invention.

[0019] Example 1: This invention provides a logic analyzer based on pipelined real-time state analysis. In a preferred embodiment, such as... Figure 1 and Figure 2 As shown, the logic analyzer includes: The SerDes sampling module synchronously acquires the status clock signal and output of the system under test. Each digital channel signal is generated, and serial sampling data is produced. The integer is positive; the system under test is a high-speed embedded system. The serial-to-parallel conversion module is used to convert serial sampled data into parallel sampled data, which includes parallel state clock sampled data aligned with the sampling points and... Parallel state sampling data of several digital channels; The two-stage pipelined processing module: the first stage pipeline identifies valid edges of the parallel state clock sampling data, which are either rising or falling edges; the second stage pipeline then... The valid states are extracted in parallel from the parallel state sampling data of each digital channel. The valid states are the states corresponding to the valid edges identified by the first-stage pipeline. The shift register dynamic compression module extracts the data from the second-stage pipeline. The valid status of each digital channel is synchronously written to the shift register group; Trigger judgment module, real-time based The system determines the validity status of each digital channel and generates a status trigger signal.

[0020] Understandably, scenarios supporting high-speed state analysis typically utilize the parallel processing capabilities of FPGAs to improve the real-time performance and triggering speed of state analysis. To enhance state analysis speed and reduce the number of external components, the SerDes sampling module (Serializer / Deserializer), serial-to-parallel conversion module, two-stage pipeline processing module, shift register dynamic compression module, and triggering judgment module in this embodiment can all be implemented internally within the FPGA. Figure 1 As shown. Specifically, the SerDes sampling module and serial-to-parallel conversion module can be processed using the FPGA's embedded MGT (Multi-Gigabit Transceiver) and PCS (Physical Coding Sublayer) hard cores. The two-stage pipeline processing module, shift register dynamic compression module, and trigger judgment module can be directly described by hardware description languages ​​(such as Verilog, VHDL, etc.) and mapped onto the FPGA's programmable logic resources, directly implementing parallel valid edge recognition, valid state extraction, trigger judgment, and compression at the hardware layer. The SerDes sampling module has extremely high speed, enabling massive data throughput to effectively support high-speed state analysis scenarios.

[0021] Of course, some modules in this invention can also be implemented using independent chips to improve data throughput and reduce FPGA resource consumption. Please see [link to relevant documentation]. Figure 2 The SerDes sampling module uses an independent chip, such as the Texas Instruments TLK2711 high-speed serial transceiver chip, which can be connected to the FPGA's general-purpose I / O (input / output) pins via a parallel data bus.

[0022] It should be noted that the logic analyzer provided in this embodiment can be used as an instrument on the production test line of the system under test, or it can be used as a large module within the system under test. The system under test can be, for example, a high-speed embedded system. A high-speed embedded system refers to an embedded system with a working frequency typically above 100MHz, integrating high-speed serial / parallel interfaces, and running complex real-time tasks. Its internal logic state change rate is typically in the range of hundreds of Mbps to several Gbps. Examples include application processor systems based on ARM Cortex-A series processors, RISC-V (Fifth Generation Reduced Instruction Set Architecture) high-performance cores, FPGA-based high-speed data acquisition and processing systems, and DSP (Digital Signal Processor)-based digital signal processing systems.

[0023] The status clock signal output by the system under test is not limited to the synchronous clock signal when the processor accesses external memory or peripherals (output from the processor's external bus clock pin), the differential clock signal of the memory interface such as DDR (Double Data Rate SDRAM) (output from the memory interface clock pin), or a reference clock signal specially configured for testing purposes and obtained by multiplying or dividing the clock signal of the system under test. In each digital channel The values ​​are typically 1, 2, 4, 8, 16, 32, 64, etc., and are not limited to all or part of the signal lines in the processor address bus, processor data bus, processor control bus, or peripheral interface data bus of a high-speed embedded system.

[0024] In this embodiment, the serial sampling data generated by the SerDes sampling module can be represented as: ; in, This represents a sequence of clock sample values ​​obtained by continuously sampling the state clock signal. , , This indicates the signal of the first digital channel. , No. The state sample value sequence is obtained by continuously sampling the digital channel signal. "1" indicates that the state clock signal / digital channel signal is at a logic high level at the sampling point, and "0" indicates that the state clock signal / digital channel signal is at a logic low level at the sampling point. The states include logic high and logic low levels, corresponding to "1" and "0" respectively. The clock sample value sequence is used... Determine the valid state sampling time, i.e. the valid edge.

[0025] In this embodiment, as Figure 1 and Figure 2 As shown, the serial-to-parallel conversion module is connected to the SerDes sampling module and works synchronously to convert serial sampled data into parallel sampled data executed internally by the FPGA. Specifically, it converts the clock sample value sequence... Convert to include Parallel state clock sampling data from consecutive sampling points converts the state sample value sequence of each digital channel into a sequence including... Parallel state sampling data with consecutive sampling points, and parallel state clock sampling data and parallel state sampling data with aligned sampling points. The parallel sampling width should not exceed the maximum number of sampling points that the FPGA can process in each working cycle.

[0026] To improve the real-time performance of state analysis and fully utilize the parallel processing capabilities of the FPGA, preferably, the number of sampling points for parallel state clock sampling data and parallel state sampling data is [not specified]. (Parallel sampling width) is determined based on the ratio of the sampling rate of the SerDes sampling module to the internal operating frequency of the FPGA.

[0027] For example, ; in, This indicates the sampling frequency of the SerDes sampling module. The SerDes sampling module uses a sampling frequency... For state clock signal and Simultaneous sampling of signals from each digital channel; This indicates the internal processing clock frequency of the FPGA. It should be noted that when... When it is not an integer, for Round down to obtain the number of sampling points .

[0028] It is understandable that the parallel sampling data can be numbered according to the FPGA's duty cycle, with each FPGA duty cycle corresponding to a set of parallel sampling data. Greater than or equal to 0, the FPGA's first one work cycle Parallel state clock sampling data Represented as: ; like Figure 3 As shown, It can also be expressed as . They represent the first one work cycle Parallel state clock sampling data The 0th sampling point, the 1st sampling point, ..., the 2nd sampling point The clock sample value at each sampling point.

[0029] FPGA's first one work cycle The Parallel state sampling data of multiple digital channels It can be represented as: ; They represent The 0th sampling point, the 1st sampling point, ..., the 2nd sampling point The state corresponding to each sampling point. For example... Figure 3 As shown, It can also be expressed as . Indicates the index of the digital channel. .

[0030] In this embodiment, such as Figure 1 and Figure 2 As shown, the two-stage pipeline processing module is connected to the serial-to-parallel conversion module, and the two pipelines execute in parallel. Within one FPGA work cycle: the first-stage pipeline identifies valid edges of the parallel state clock sampling data for the current FPGA work cycle; the second-stage pipeline, based on the valid edges identified by the first-stage pipeline in the previous FPGA work cycle, processes the data from the previous FPGA work cycle... The valid state is extracted from the parallel state sampling data of each digital channel.

[0031] Specifically, in the FPGA's... one work cycle Inside, the two-stage pipeline processing module obtains the first... one work cycle Parallel state clock sampling data and Parallel state sampling data of digital channel signals ( ... ... The first-stage pipeline samples data from the parallel state clock. Perform effective edge recognition when At that time, the second-stage pipeline is based on the first-stage pipeline in the first stage. one work cycle from The identified valid edges are synchronously generated from... ... ... The text proposes the state corresponding to the valid edge, i.e., the valid state; when... At that time, the second-stage production line is not working. Indicates the first one work cycle Parallel state clock sampling data, ... ... Indicates the first one work cycle of Parallel state sampling data from multiple digital channels.

[0032] In one example, the parallel sampling width The FPGA operates at a clock speed of 200MHz and a sampling rate of 1.6Gbps. Plot the data flow in digital channel 1 of the two-stage pipeline, as follows: Figure 3 As shown. Among them, , , , , These represent the 0th working cycle of the FPGA. First working cycle 2 working cycles 3 working cycles 4 working cycles Within, parallel state sampling data of digital channel 1; similarly, , , , , These represent the parallel state clock sampling data during the 0th, 1st, 2nd, 3rd, and 4th working cycles of the FPGA, respectively. Figure 3 In the diagram, the second line represents the processing path of the first-level pipeline, and the third line represents the processing path of the second-level pipeline.

[0033] As you can see, Figure 3The two-stage pipeline employs a mis-step handling method, dividing the state analysis process into two FPGA work cycles. The first-stage pipeline identifies the valid edges of the state clock, and the second-stage pipeline extracts the state of the corresponding digital channel based on the identified valid edges. By splitting the pipeline, the combinational logic complexity per work cycle is reduced, the requirement for the FPGA's internal operating frequency is lowered, and the reliability of high-speed state analysis is enhanced.

[0034] In this preferred embodiment of Example 1, the parallel state clock sampling data includes The clock sampling value of each sampling point; in the two-stage pipeline processing module, the first stage pipeline performs effective edge identification on the parallel state clock sampling data, including: based on the clock sampling value of each sampling point and its previous sampling point, calculating the effective edge flag bit of each sampling point, the effective edge flag bit indicating whether there is a valid edge between each sampling point and its previous sampling point; The effective edge flag vector is composed of the effective edge flag bits of each sampling point. Indicates the sampling point index. .

[0035] When the effective edge is a rising edge, the sampling point The valid edge flag is: ; When the effective edge is a falling edge, the sampling point The valid edge flag is: ; Indicates sampling point Previous sampling point The clock sample value, Indicates sampling point The result of inverting the clock sample value Indicates sampling point Previous sampling point The result of inverting the clock sample value Indicates sampling point The clock sample value, The value can be 0 or 1. The value can be either 0 or 1. Thus, when the sampling point... Compared with the previous sampling point When there are valid edges, When sampling point Compared with the previous sampling point When there is no valid edge between them, .

[0036] It should be noted that when At that time, sampling points Previous sampling point This is the last sampling point in the parallel state clock sampling data of the FPGA's previous working cycle. It can be represented as , represents the clock sample value of the last sample point in the parallel state clock sampling data of the previous working cycle of the FPGA. ,or, This enables valid edge detection across work cycles, avoids missing valid edges, and improves the reliability of state analysis.

[0037] The effective edge flag vector is composed of the effective edge flag bits of each sampling point. The FPGA's... one work cycle The effective edge marker vector is represented as: ; in, , , They represent the first one work cycle In the parallel state clock sampling data, sampling point 0, sampling point 1, and sampling point The valid edge flag.

[0038] In the above preferred embodiment, the effective edge flag bit of each sampling point is obtained by performing logical operations on the clock sampling value of each sampling point and the previous sampling point. This facilitates the parallel implementation of effective edge detection of N sampling points at one time within the FPGA, resulting in an effective edge flag vector, which improves the processing speed. The introduction of effective edge detection across working cycles eliminates the detection blind zone at the boundary of the working cycle, improving the completeness and reliability of the state analysis. Furthermore, the effective edge flag vector is a sequence of 0 and 1, which facilitates the second-stage pipeline to quickly locate the effective edge position and extract the effective state, further improving the processing speed.

[0039] In this preferred embodiment of Example 1, in the two-stage pipeline processing module, the second-stage pipeline starts from... The valid states are extracted in parallel from the parallel state sampling data of each digital channel, including: obtaining the valid edge flag vector obtained from the first-stage pipeline; and, based on the valid edge flag vector, extracting the valid states in parallel from the data. From the parallel state sampling data of each digital channel, extract the states corresponding to all sampling points whose valid edge flag bit is equal to a preset flag value. The preset flag value is not limited to 1. The parallel state sampling data and the valid edge flag vector are aligned based on sampling points.

[0040] Specifically, the sampling points in the valid edge flag vector of the second-stage pipeline are determined. Valid edge flag Is it 1, when Then from Extract from parallel state sampling data of digital channels Each digital channel at the sampling point The state at the sampling point (which is the valid state at this time) is obtained to obtain the state of the system under test at the sampling point. place Bit states (logical states) form a set of valid states. : ; in, , , These represent the sampling points. A set of valid states The first digital channel, the second digital channel, and the third The status of each digital channel. The second-stage pipeline can synchronously obtain the valid status of all sampling points with valid edge flags set to 1 using the method described above.

[0041] The effective edge flag vector obtained in each FPGA working cycle The number of valid edges P identified from the parallel state clock sampling data in this working cycle is obtained by summing the valid edge flags. .

[0042] Correspondingly, obtain Group valid status: ; , , These represent the first valid edge, the second valid edge, and the third valid edge, respectively. The index of the sampling points at each valid edge. , , These represent the first valid edge, the second valid edge, and the third valid edge, respectively. A set of valid states at each valid edge.

[0043] In this embodiment, The valid states of a group are extracted in parallel according to the sampling point order, and the state data of sampling points that are not valid edges are discarded, reducing the storage data flow.

[0044] In this embodiment, as Figure 1 and Figure 2 As shown, the shift register dynamic compression module is connected to the two-stage pipeline processing module. The shift register group in the shift register dynamic compression module includes... One shift register, The valid states in each shift register are aligned according to the sampling point. Each shift register corresponds one-to-one with a digital channel and is used to store the valid state of the corresponding digital channel.

[0045] Figure 4 This demonstrates a storage example of the shift register corresponding to the first digital channel, where the valid edge is a rising edge, occurring in the 0th operating cycle of the FPGA. In the middle, starting from the 0th work cycle Parallel state clock sampling data Two rising edges are identified, and corresponding valid edge flag vectors are generated. (Not illustrated), based on the valid edge flag vector, two valid states (10) are extracted from the parallel state sampling data of the first digital channel, and 1 and 0 are written into the corresponding shift register. This is done in the first working cycle of the FPGA. Following the process described above, three valid state bits (1 1 0) are extracted from the parallel state sampling data of the first digital channel and written into the corresponding shift register. It can be seen that the shift register group only stores the state corresponding to the valid edges (valid states), discarding the states at invalid edges (invalid states), thus reducing data storage. Although the number of rising edges detected in each FPGA working cycle may differ, the shift register can dynamically shift and store data according to the actual number of valid states in each FPGA working cycle, achieving dynamic compression of variable-length state data and avoiding the loss of valid states or storage waste caused by a fixed compression ratio.

[0046] In this embodiment, as Figure 1 and Figure 2 As shown, the trigger judgment module is connected to both the two-stage pipeline processing module and the shift register dynamic compression module. Preferably, the trigger judgment module obtains data in real time from the two-stage pipeline processing module and / or the shift register group. The valid status of each digital channel.

[0047] Extracting valid states from the second-stage pipeline of a two-stage pipelined processing module for trigger judgment enables single-moment state trigger judgment. For example, in the scenario of analyzing the communication protocol between the processor and external memory in a high-speed embedded system, the state clock signal is the synchronous clock signal when the processor accesses the external memory (output from the processor's external bus clock pin), with four digital channels (…). () refers to all or part of the signal lines in the data bus between the processor and external memory. The trigger condition for detecting the packet header is that the valid states of the four digital channels are (0, 1, 0, 0), and if the second-stage pipeline obtains... In a group of valid states, if a group of valid states is detected as (0, 1, 0, 0), then it is considered that a communication protocol header has been detected, and the header generation is triggered. The generation state trigger signal is that a communication protocol header has been detected.

[0048] Based on the valid state sequence in the shift register group, deeper state sequence triggering can be achieved. In this case, the triggering condition is: when the valid state sequence of a digital channel in the shift register matches the preset trigger state sequence of that digital channel, the digital channel is considered successfully triggered, and a state trigger signal is generated. Of course, the triggering condition can also be set so that multiple digital channels need to satisfy a certain state sequence relationship; users can set this according to their actual needs, which will not be elaborated further here.

[0049] In this embodiment, the trigger judgment module can directly judge the current valid state data in real time, realizing high-speed state triggering without waiting for all data to be collected before performing post-analysis. Its output state trigger signal can be used to control subsequent acquisition depth, freeze the storage window, mark the trigger position, or notify the host computer to read data.

[0050] Example 2 This embodiment also provides a logic analyzer based on pipelined real-time state analysis. The difference from Embodiment 1 is that, please see... Figure 5 The logic analyzer also includes: The buffer module reads and stores the valid states from the shift register group when the number of valid states stored in the shift register group reaches a preset storage threshold. The storage module, connected to the buffer module, reads valid states from the buffer module and stores them to achieve deep state recording.

[0051] In this embodiment, as Figure 5 As shown, the buffer module is connected to the shift register. The preset storage capacity threshold is generally the maximum capacity of the shift registers in the shift register group. Since a set of valid states is stored in only one bit in a shift register, the preset storage capacity threshold can also be the maximum number of valid states that the shift register group can store. The buffer module is not limited to FIFO (First In First Out) modules or flexible buffers; it can be implemented inside the FPGA.

[0052] The buffer module is used to match the front-end valid state extraction rate with the back-end storage module's write rate. It buffers bursts of valid state data, ensuring that valid state data is temporarily stored in the buffer module and not lost when the back-end storage is busy writing, thus achieving a match between the state analysis rate and the back-end storage rate and improving the overall system stability. The storage module is not limited to DDR. The compressed state data in the buffer module is further written to the storage module for deep state recording and deep-triggered analysis.

[0053] Unlike existing technologies that store all serially sampled data, this invention only stores the valid state data corresponding to the valid edge of the state clock, thus achieving a greater state triggering depth with the same storage module capacity.

[0054] If the storage rate of serial sampled data is: Wherein, M+1 includes M digital channels and 1 state clock channel. The effective state data storage rate after compression in this invention is approximately: ,in, This is the actual effective edge frequency of the state clock. It can be seen that when... Significantly greater than In this way, the present invention can significantly reduce storage bandwidth requirements.

[0055] In a preferred embodiment of this example, the shift register dynamic compression module synchronously writes the valid states of the M digital channels extracted by the second-stage pipeline into the shift register group, including: The number of valid edges identified by the first-stage pipeline is counted based on the valid edge flag vector. ; like Then The corresponding effective edges The group's valid state is stored in the shift register group until the shift register group is full. After the shift register group is full, the data stored in the shift register group is... The group's valid state is stored in the buffer module, the shift register group is cleared, and the remaining... The group's valid state serves as the new starting data for the shift register group; like Then The corresponding effective edges The group's valid state is written to the shift register group; in, This indicates the maximum number of valid states that the shift register set can store; This indicates the number of valid state groups that have been stored in the shift register group.

[0056] In this embodiment, the buffer module can promptly read and store valid state data after the shift register is full, which can buffer sudden increases in valid states and improve overall stability. With the same memory capacity, more valid state points can be recorded due to the reduced amount of stored data, which can improve the state triggering depth of the logic analyzer. This allows the logic analyzer provided by the present invention to achieve deep, efficient, and real-time state analysis at a high state analysis clock rate.

[0057] Figure 6 A schematic diagram of the state analysis process of the logic analyzer provided by the present invention is shown in one example. Figure 6 In this context, "idle" represents the idle state. State transition condition: Start sampling; Sampling complete / abnormal; Enter serial-to-parallel conversion; Enter rising edge recognition; The clock channel detected a rising edge; The status data is valid; The cache has reached its threshold. The cache threshold has not been reached; FiFo module is full; Reach the set storage depth; The clock channel has no rising edge; The FiFo module is not full; Storage depth not reached; The state corresponding to the trigger condition has been detected.

[0058] Example 3: This embodiment discloses a real-time status analysis method based on a pipeline. Please see [link / reference]. Figure 7 The method includes: Step S1: Synchronously acquire the status clock signal output by the system under test and Each digital channel signal is generated, and serial sampling data is produced. The integer is positive; the system under test is a high-speed embedded system; Step S2, convert the serial sampling data into parallel sampling data, the parallel sampling data including parallel state clock sampling data aligned with sampling points and Parallel state sampling data of several digital channels; Step S3: Construct a two-stage pipeline. The first-stage pipeline is used to identify valid edges in the parallel state clock sampling data. The valid edge is either a rising edge or a falling edge. The second-stage pipeline is then used to... The valid states are extracted in parallel from the parallel state sampling data of each digital channel. The valid states are those corresponding to the valid edges identified by the first-stage pipeline. Specifically, within one FPGA work cycle: the first-stage pipeline identifies valid edges in the parallel state clock sampling data of the current FPGA work cycle; the second-stage pipeline, based on the valid edges identified by the first-stage pipeline in the previous FPGA work cycle, extracts valid states from the data of the previous FPGA work cycle. The effective state is extracted from the parallel state sampling data of each digital channel. The effective edge is either a rising edge or a falling edge. The effective state is the state corresponding to the effective edge identified by the first-stage pipeline. Step S4, extract the second-stage pipeline The valid status of each digital channel is synchronously written to the shift register group; Step S5: Obtain data in real time from the two-stage pipeline processing module and / or shift register group. The effective status of each digital channel, based on real-time... The system determines the validity status of each digital channel and generates a status trigger signal.

[0059] In this embodiment, steps S1, S2, S3, S4, and S5 correspond to the SerDes sampling module, serial-to-parallel conversion module, two-stage pipeline processing module, shift register dynamic compression module, and trigger judgment module in Embodiment 1, respectively. The specific implementation methods of each step will not be described in detail here.

[0060] In a preferred embodiment of this example, the method further includes: Step S6: When the number of valid states stored in the shift register group reaches a preset storage threshold, the valid states are read from the shift register group and stored using the buffer module.

[0061] Step S7: Use the storage module to read the valid status from the buffer module and store it.

[0062] In this embodiment, the specific structure and implementation of the buffer module and the storage module have been described in Embodiment 2, and will not be repeated here.

[0063] The above are merely preferred embodiments of the present invention. Those skilled in the art will understand that various changes or equivalent substitutions can be made to these features and embodiments without departing from the spirit and scope of the present invention. Furthermore, under the teachings of the present invention, these features and embodiments can be modified to adapt to specific situations and materials without departing from the spirit and scope of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application are within the protection scope of the present invention.

Claims

1. A logic analyzer based on pipelined real-time state analysis, characterized in that, include: The SerDes sampling module synchronously acquires the status clock signal and output of the system under test. Each digital channel signal is generated, and serial sampling data is produced. The integer is positive; the system under test is a high-speed embedded system; A serial-to-parallel conversion module is used to convert the serial sampled data into parallel sampled data, wherein the parallel sampled data includes parallel state clock sampled data aligned with sample points and Parallel state sampling data of one digital channel; the parallel state clock sampling data includes Clock sample value at each sampling point It is a positive integer; The two-stage pipelined processing module performs effective edge identification on the parallel state clock sampling data of the current FPGA working cycle within one FPGA working cycle. The second-stage pipeline is based on the valid edges identified by the first-stage pipeline in the previous FPGA cycle, starting from the previous FPGA cycle. The effective state is extracted from the parallel state sampling data of each digital channel. The effective edge is either a rising edge or a falling edge. The effective state is the state corresponding to the effective edge identified by the first-stage pipeline. In the two-stage pipeline processing module, the first-stage pipeline performs effective edge identification on the parallel state clock sampling data, including: calculating the effective edge flag bit of each sampling point based on the clock sampling value of each sampling point and its previous sampling point, wherein the effective edge flag bit indicates whether there is a valid edge between each sampling point and its previous sampling point; The effective edge flag vector is composed of the effective edge flag bits of each sampling point; The shift register dynamic compression module extracts the data from the second-stage pipeline. The valid status of each digital channel is synchronously written to the shift register group; The trigger judgment module obtains the data in real time from the two-stage pipeline processing module and / or the shift register group. The effective status of each digital channel, based on real-time... The valid status of each digital channel is used to trigger a judgment and generate a status trigger signal; The buffer module reads and stores the valid states from the shift register group when the number of valid states stored in the shift register group reaches a preset storage threshold. The shift register dynamic compression module extracts the data from the second-stage pipeline. The valid status of each digital channel is synchronously written to the shift register group, including: The number of valid edges identified by the first-stage pipeline is counted based on the valid edge flag vector. ; like Then The corresponding effective edges The group's valid state is stored in the shift register group until the shift register group is full. After the shift register group is full, the data stored in the shift register group is... The group's valid state is stored in the buffer module, the shift register group is cleared, and the remaining... The group's valid state serves as the new starting data for the shift register group; like Then The corresponding effective edges The group's valid state is written into the shift register group; in, This indicates the maximum number of valid state groups that the shift register group can store; This indicates the number of valid state groups that have been stored in the shift register group.

2. A logic analyzer based on pipelined real-time state analysis according to claim 1, characterized in that, The number of sampling points for the parallel state clock sampling data and the parallel state sampling data are determined based on the ratio of the sampling rate of the SerDes sampling module to the internal operating frequency of the FPGA.

3. A logic analyzer based on pipeline-based real-time state analysis according to claim 1, characterized in that, When the effective edge is a rising edge, the sampling point The valid edge flag is: ； When the effective edge is a falling edge, the sampling point The valid edge flag is: ； in, ; Indicates sampling point Previous sampling point The clock sample value; Indicates sampling point The result of inverting the clock sample value; Indicates sampling point Previous sampling point The result of inverting the clock sample value; Indicates sampling point The clock sample value.

4. A logic analyzer based on pipelined real-time state analysis according to claim 1, characterized in that, In the two-stage pipeline processing module, the second-stage pipeline starts from... The valid states are extracted in parallel from the parallel state sampling data of each digital channel, including: Obtain the effective edge flag vector obtained from the first-stage pipeline; Based on the effective edge flag vector, parallel from From the parallel state sampling data of each digital channel, extract the state corresponding to all sampling points whose effective edge flag bit is equal to the preset flag value.

5. A logic analyzer based on pipelined real-time state analysis according to any one of claims 1-4, characterized in that, The logic analyzer also includes: A storage module, connected to the buffer module, reads valid states from the buffer module and stores them.

6. A real-time state analysis method based on a pipeline, characterized in that, The method includes: Synchronously acquire the status clock signal output by the system under test and Each digital channel signal is generated, and serial sampling data is produced. The integer is positive; the system under test is a high-speed embedded system; The serial sampled data is converted into parallel sampled data, which includes parallel state clock sampled data aligned to the sample points and... Parallel state sampling data of one digital channel; the parallel state clock sampling data includes Clock sample value at each sampling point It is a positive integer; A two-stage pipeline is constructed within one FPGA work cycle: the first-stage pipeline identifies valid edges in the parallel state clock sampling data of the current FPGA work cycle; the second-stage pipeline, based on the valid edges identified by the first-stage pipeline in the previous FPGA work cycle, retrieves data from the previous FPGA work cycle... Valid states are extracted from the parallel state sampling data of each digital channel. The valid edge is either a rising edge or a falling edge. The valid state is the state corresponding to the valid edge identified by the first-stage pipeline. The first-stage pipeline performs valid edge identification on the parallel state clock sampling data, including: calculating a valid edge flag bit for each sampling point based on the clock sampling value of each sampling point and its previous sampling point. The valid edge flag bit indicates whether there is a valid edge between each sampling point and its previous sampling point. The effective edge flag vector is composed of the effective edge flag bits of each sampling point; Extract the second-stage pipeline The valid status of each digital channel is synchronously written to the shift register group; Real-time acquisition from the two-stage pipeline and / or the shift register group The effective status of each digital channel, based on real-time... The valid status of each digital channel is used to trigger a judgment and generate a status trigger signal; When the number of valid states stored in the shift register group reaches a preset storage threshold, the buffer module reads the valid states from the shift register group and stores them. The extraction of the second-stage pipeline The valid status of each digital channel is synchronously written to the shift register group, including: The number of valid edges identified by the first-stage pipeline is counted based on the valid edge flag vector. ; like Then The corresponding effective edges The group's valid state is stored in the shift register group until the shift register group is full. After the shift register group is full, the data stored in the shift register group is... The group's valid state is stored in the buffer module, the shift register group is cleared, and the remaining... The group's valid state serves as the new starting data for the shift register group; like Then The corresponding effective edges The group's valid state is written into the shift register group; in, This indicates the maximum number of valid state groups that the shift register group can store; This indicates the number of valid state groups that have been stored in the shift register group.

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