Write-after-read control apparatus based on sr-iov architecture
By introducing a write-after-read control device into the SR-IOV architecture and using PF and VF verification channels to manage read and write requests, the performance bottleneck of read and write access under the SR-IOV architecture is solved, parallel processing of read and write requests and data consistency are realized, and the overall performance and throughput of the chip are improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- 沐曦集成电路(南京)有限公司
- Filing Date
- 2026-06-03
- Publication Date
- 2026-07-31
AI Technical Summary
Under the SR-IOV architecture, traditional strong ordering and loose ordering mechanisms cannot fully utilize the parallel advantages of physical and virtual functions, resulting in read and write access performance bottlenecks. Furthermore, they cannot effectively distinguish and handle cross-virtual function read and write requests that do not require order preservation, leading to resource waste and overall low access efficiency.
Design a write-after-read control device, including a write request management module and a read request management module. Through the PF verification channel and N VF verification channels, it manages the read and write requests of physical functions and virtual functions respectively, performs write-after-read checks and blocking control, adapts to the multi-user characteristics of the SR-IOV architecture, and realizes fine-grained sequential control.
It improves the overall I/O throughput and performance of the chip in SR-IOV mode, breaks unnecessary sequential constraints, and enables read and write requests of multiple virtual functions to be processed in parallel, thereby improving data throughput and system performance.
Smart Images
Figure CN122346290B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of chip design technology, and in particular to a write-after-read control device based on the SR-IOV architecture. Background Technology
[0002] In chip design, when the Peripheral Component Interconnect Express (PCIe) bus issues read and write requests to functional modules, it can use either Strong Ordering (SO) or Relaxed Ordering (RO) to implement read and write access. If Strong Ordering is used, requests must be delivered to functional modules strictly according to the order of the read and write requests issued by the host, maintaining a strict read-after-write (RAW) ordering. If Relaxed Ordering (RO) is used, the bus or controller is allowed to process eligible transactions out of order. Specifically, write requests are allowed to precede other write requests, but read requests are not allowed to precede previous posted requests, unless the requester IDs are different; that is, read requests cannot precede previous write requests unless they originate from different requesters.
[0003] In a PCIe hardware virtualization extension architecture (Single Root I / O Virtualization, SR-IOV) scenario, the memory spaces accessed by different virtual functions (VFs) are isolated. There is no data dependency between read and write requests from different virtual functions that access different addresses. However, traditional strong ordering and loose ordering mechanisms cannot fully leverage the parallel advantages of multiple VFs under physical functions and virtual functions, resulting in unnecessary performance bottlenecks for read and write access in the SR-IOV scenario. This is reflected in at least the following points: (1) The SR-IOV architecture supports physical functions (PF) and virtual functions sharing hardware resources. The strong ordering mechanism does not distinguish between read and write requests of different VFs, causing requests of different functions to block each other and making fine-grained scheduling impossible; (2) For read and write requests across VFs or memory regions that do not require order preservation, the strong ordering mechanism still forces execution in the order of dispatch, resulting in wasted read and write channel resources and reduced overall access efficiency; (3) Loose ordering allows out-of-order execution and completion of transactions in different address spaces and different transaction types, but for transactions in the same address space and the same transaction type, strict order must still be guaranteed. Even with loose ordering, the PCIe side still maintains a relatively strict order preservation relationship between write and read, making it impossible to select read and write requests that truly require order preservation.
[0004] Therefore, how to intelligently manage the read and write order of various functions based on the SR-IOV architecture, select the read and write requests that truly need to be ordered, and improve chip performance while ensuring data correctness has become an urgent technical problem to be solved. Summary of the Invention
[0005] The purpose of this invention is to provide a write-after-read control device based on the SR-IOV architecture, which improves chip performance while ensuring data integrity.
[0006] According to a first aspect of the present invention, a write-after-read control device based on an SR-IOV architecture is provided. The device is disposed between an upstream interconnect bus and a downstream interconnect bus, and the device includes a write request management module and a read request management module. The write request management module is used to store all write requests received from the upstream bus but not completed. Each write request includes a unique identifier, a function identifier, and a write address. It is also used to delete the write request corresponding to the write response from the write request management module when a write response is received from the downstream interconnect bus. The function identifier is either a PF identifier or a VF identifier. The read request management module includes a PF verification channel and N VF verification channels {VF1, VF2, ..., VF...} n ,...,VF N}, VF n This is the verification channel corresponding to the nth virtual function in the SR-IOV architecture. The value of n ranges from 1 to N, where N is the total number of virtual functions in the SR-IOV architecture. Each verification channel is independent of the others. The PF verification channel is used to cache PF read requests. The PF read request includes a function identifier and a read address. When the PF verification channel is not empty, it is used to perform a write-after-read check on the first read request currently cached in the PF verification channel in each clock cycle based on all write requests stored in the write request management module. If a write-after-read is required, the first read request currently cached in the PF verification channel continues to block the PF verification channel. Otherwise, the first read request currently cached in the PF verification channel is output from the PF verification channel to the downstream bus. VF n The verification channel is used to cache VF. n Corresponding VF n Read request, VF n The read request includes a function identifier and a read address, and is used in VF n When the verification channel is not empty, in each clock cycle, based on all write request pairs stored in the write request management module, VF... n The first read request in the current cache of the verification channel undergoes a read-after-write check. If a read-after-write check is required, then VF... nThe first read request in the current cache in the verification channel continues to block VF. n Read and then write to verify the channel; otherwise, VF will be used. n The first read request in the current cache of the verification channel is from VF n The output from the verification channel is sent to the downstream bus.
[0007] Compared with existing technologies, this invention has significant advantages and beneficial effects. Through the above technical solution, the write-after-read control device based on the SR-IOV architecture provided by this invention achieves considerable technological advancement and practicality, and has broad industrial application value. It has at least the following beneficial effects: The device described in this invention uses a function-based sequential control for read-after-write operations, adapting to the multi-user characteristics of the SR-IOV architecture. It breaks unnecessary sequential constraints between different virtual functions, allowing read and write requests from multiple virtual functions to be processed in parallel, significantly improving the overall I / O throughput of the chip in SR-IOV mode. Individual physical functions also do not need to adhere to strict write-after-read order requirements, improving chip performance while ensuring data integrity. Attached Figure Description
[0008] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0009] Figure 1 This is a schematic diagram of a write-after-read control device based on the SR-IOV architecture provided in an embodiment of the present invention. Detailed Implementation
[0010] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0011] This invention provides a write-after-read control device based on the SR-IOV architecture, such as... Figure 1As shown, the device is positioned between the upstream interconnect bus and the downstream interconnect bus, and includes a write request management module and a read request management module. As an example, the upstream interconnect bus follows the PCIe protocol, and the downstream interconnect bus follows the AXI protocol. Read and write requests received by the upstream interconnect bus are converted to an AXI-compliant format before being sent to the device. Specifically, the downstream interconnect bus may be connected to a Distributed Network-on-Chip (DNOC).
[0012] The write request management module stores all incomplete write requests received from the upstream bus. Each write request includes a unique write request identifier, a function identifier, and a write address. It also deletes the write request corresponding to a write response from the write request management module when a write response is received from the downstream interconnect bus. The function identifier is either a PF identifier or a VF identifier. Taking a downstream interconnect bus conforming to the AXI protocol as an example, the unique write request identifier is AWID, which is the core transaction identifier for the write address channel in the AXI protocol. The write response carries a write response identifier (bid), which matches the AWID in the write request. The device fully complies with the AXI protocol (e.g., the awid / bid matching mechanism) and PCIe basic requirements, thus allowing seamless integration into existing chip design flows.
[0013] The read request management module includes a PF verification channel and N VF verification channels {VF1, VF2, ..., VF...} n ,...,VF N}, VF n This refers to the verification channel corresponding to the nth virtual function in the SR-IOV architecture, where n ranges from 1 to N, and N is the total number of virtual functions in the SR-IOV architecture. Each verification channel is independent of the others. It should be noted that the PF is responsible for the partitioning and allocation of the global resource pool. The VF can use the dedicated resources allocated by the PF while sharing the underlying hardware of the physical device, thereby maximizing resource utilization.
[0014] The PF check channel is used to cache PF read requests. Each PF read request includes a function identifier and a read address. When the PF check channel is not empty, it is used to perform a read-after-write check on the first read request currently cached in the PF check channel in each clock cycle based on all write requests stored in the write request management module. If a read-after-write check is required, the first read request currently cached in the PF check channel continues to block the PF check channel. Otherwise, the first read request currently cached in the PF check channel is output from the PF check channel to the downstream bus.
[0015] VF n The verification channel is used to cache VF.n Corresponding VF n Read request, VF n The read request includes a function identifier and a read address, and is used in VF n When the verification channel is not empty, in each clock cycle, based on all write request pairs stored in the write request management module, VF... n The first read request in the current cache of the verification channel undergoes a read-after-write check. If a read-after-write check is required, then VF... n The first read request in the current cache in the verification channel continues to block VF. n Read and then write to verify the channel; otherwise, VF will be used. n The first read request in the current cache of the verification channel is from VF n The output from the verification channel is sent to the downstream bus.
[0016] The device described in this embodiment of the invention employs fine-grained sequence control at the functional and memory address block level, precisely ensuring data consistency, supporting parallel access by multiple virtual functions, and ensuring that blocking a request for one virtual function does not affect other virtual functions, thus adapting to the multi-user characteristics of the SR-IOV architecture. Furthermore, it breaks unnecessary sequence constraints between different virtual functions, allowing read and write requests from multiple virtual functions to be processed in full parallel, significantly improving the overall I / O throughput of the chip in SR-IOV mode. In this device, individual physical functions do not need to adhere to strict write-after-read order requirements, improving the overall system performance.
[0017] It should be noted that in PF mode, only requests corresponding to PF exist, the PF verification channel is enabled, and the N VF verification channels are disabled. In VF mode, only requests corresponding to VF exist, the N VF verification channels are enabled, and the PF verification channel is disabled.
[0018] The device allocates an independent post-write read verification channel for each PF / VF based on the PF / VF attributes of the read request. When a read request for a certain function is blocked due to matching a write request, all subsequent read requests for that function are blocked on this channel until the previously blocked read request is sent downstream, at which point subsequent read requests can enter the post-write read check process in sequence. When a read request for a certain function is blocked, it does not affect the normal entry of read requests for other functions into their respective channels' post-write read check processes, thus achieving multi-functional cross-channel isolation.
[0019] As one embodiment, the write response includes a write response identifier. The write request management module, upon receiving a write response from the downstream interconnect bus, obtains the write response identifier corresponding to the write response and matches it with the unique write request identifier in the write request management module, then deletes the write request that matches the write response identifier. Taking the downstream interconnect bus following the AXI protocol as an example, the write response carries a write response identifier (bid), which matches the AWID in the write request.
[0020] As one embodiment, the PF verification channel is used to perform a post-write read check on the first read request currently cached in the PF verification channel in each clock cycle based on all write requests stored in the write request management module when the PF verification channel is not empty. Specifically, this includes: The PF verification channel is used to extract the PF identifier and read address of the first read request currently cached in the PF verification channel, and align the read address according to the preset address block size to obtain the corresponding address block identifier. It is also used to extract the function identifier and write address corresponding to each write request stored in the write request management module, and align the write address according to the preset address block size to obtain the corresponding address block identifier. If there is a write request with the function identifier being the PF identifier and the corresponding address block identifier being the same as the address block identifier corresponding to the first read request currently cached in the PF verification channel, it is determined that the first read request currently cached in the PF verification channel needs to continue writing and then reading. Otherwise, it is determined that the first read request currently cached in the PF verification channel does not need to continue writing and then reading. The preset address block size is the maximum length of a single access.
[0021] As one example, VF n The verification channel is used in VF n When the verification channel is not empty, in each clock cycle, based on all write request pairs stored in the write request management module, VF... n The first read request in the current cache of the verification channel undergoes a post-write read check, specifically including: The VF n The verification channel is used to extract VF. n Verify the VF of the first read request currently cached in the channel. n The function identifies and reads the address, aligns the read address according to a preset address block size, and obtains the corresponding address block identifier. It also extracts the function identifier and write address corresponding to each write request stored in the write request management module, aligns the write address according to a preset address block size, and obtains the corresponding address block identifier. If a function identifier of VF exists... n And the corresponding address block identifier is the same as VF n If the first read request in the current cache in the verification channel corresponds to a write request with the same address block identifier, then VF is determined. n The first read request in the current cache of the verification channel needs to continue with a write-then-read sequence; otherwise, check the VF.n The first read request in the current cache of the verification channel does not need to be followed by a write-to-read operation. The preset address block size is the maximum length of a single access.
[0022] It should be noted that the PF verification channel and VF n When performing post-write read checks, the verification channel employs a two-dimensional verification process. The first dimension is that the address of the write request, after being aligned to the same address block size, is identical to the address of the read request. The second dimension is that the PF / VF identifiers of the write request and the read request are identical. If a write request satisfies both conditions, it is determined that the current read request has a post-write read dependency, and the read request is blocked, preventing it from being immediately sent downstream. For blocked read requests, the above comparison operation is repeated every clock cycle until all conflicting write requests in the container have been completed and removed. Only then is the blocking lifted, and the read request can be sent downstream.
[0023] Preferably, the preset address block size is 256 bytes, which helps improve the overall system performance. The read address is aligned according to the preset address block size, and the corresponding address block identifier is obtained. Specifically, the read start address corresponding to the read request is obtained, and the read start address is divided by the preset address block size and rounded up to obtain the corresponding address block identifier.
[0024] In VF mode, N VF verification channels are enabled. At this time, multiple VFs may exist within the same period. n If the first read request in the current cache of the verification channel can be output to the downstream bus, one of them needs to be selected for output. As one embodiment, the read request management module also includes an arbitration unit, used in VF mode, to handle multiple read requests that need to be processed simultaneously within one clock cycle. n The first read request in the current cache of the verification channel is from VF n VF output to the downstream bus in the verification channel n When verifying a channel, select a VF according to the preset arbitration strategy. n The verification channel outputs the first read request of the current cache to the downstream bus. The preset arbitration strategy can be specifically set as a polling strategy or a priority strategy, etc.
[0025] The device described in this invention uses a function-based sequential control for read-after-write operations, adapting to the multi-user characteristics of the SR-IOV architecture. It breaks unnecessary sequential constraints between different virtual functions, allowing read and write requests from multiple virtual functions to be processed in parallel, significantly improving the overall I / O throughput of the chip in SR-IOV mode. Individual physical functions also do not need to adhere to strict write-after-read order requirements. While ensuring data integrity, it enhances the data throughput of the read / write control module and the entire chip, thereby improving chip performance.
[0026] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.
Claims
1. A write-after-read control device based on SR-IOV architecture, characterized in that, The device is located between the upstream interconnect bus and the downstream interconnect bus, and the device includes a write request management module and a read request management module. The write request management module is used to store all write requests received from the upstream interconnect bus but not completed. Each write request includes a unique identifier, a function identifier, and a write address. It is also used to delete the write request corresponding to the write response from the write request management module when a write response is received from the downstream interconnect bus. The function identifier is either a PF identifier or a VF identifier. The read request management module includes a PF verification channel and N VF verification channels {VF1, VF2, ..., VF...} n ,...,VF N }, VF n This is the verification channel corresponding to the nth virtual function in the SR-IOV architecture. The value of n ranges from 1 to N, where N is the total number of virtual functions in the SR-IOV architecture. Each verification channel is independent of the others. The PF verification channel is used to cache PF read requests. The PF read request includes a function identifier and a read address. When the PF verification channel is not empty, it is used to perform a write-after-read check on the first read request currently cached in the PF verification channel in each clock cycle based on all write requests stored in the write request management module. If a write-after-read is required, the first read request currently cached in the PF verification channel continues to block the PF verification channel. Otherwise, the first read request currently cached in the PF verification channel is output from the PF verification channel to the downstream interconnect bus. VF n The verification channel is used to cache VF. n Corresponding VF n Read request, VF n The read request includes a function identifier and a read address, and is used in VF n When the verification channel is not empty, in each clock cycle, based on all write request pairs stored in the write request management module, VF... n The first read request in the current cache of the verification channel undergoes a read-after-write check. If a read-after-write check is required, then VF... n The first read request in the current cache in the verification channel continues to block VF. n Read and then write to verify the channel; otherwise, VF will be used. n The first read request in the current cache of the verification channel is from VF n The verification channel outputs to the downstream interconnect bus.
2. The apparatus according to claim 1, characterized in that, The write response includes a write response identifier. The write request management module is used to obtain the write response identifier corresponding to the write response when it receives a write response from the downstream interconnect bus, and match it with the unique write request identifier in the write request management module, and delete the write request that matches the write response identifier.
3. The apparatus according to claim 1, characterized in that, In PF mode, the PF verification channel is enabled, and N VF verification channels are disabled. In VF mode, N VF verification channels are enabled, and the PF verification channel is disabled.
4. The apparatus according to claim 1, characterized in that, The PF verification channel is used to perform a post-write read check on the first read request currently cached in the PF verification channel in each clock cycle, based on all write requests stored in the write request management module. Specifically, this includes: The PF verification channel is used to extract the PF identifier and read address of the first read request currently cached in the PF verification channel, and align the read address according to the preset address block size to obtain the corresponding address block identifier. It is also used to extract the function identifier and write address corresponding to each write request stored in the write request management module, and align the write address according to the preset address block size to obtain the corresponding address block identifier. If there is a write request with the function identifier being the PF identifier and the corresponding address block identifier being the same as the address block identifier corresponding to the first read request currently cached in the PF verification channel, it is determined that the first read request currently cached in the PF verification channel needs to continue writing and then reading. Otherwise, it is determined that the first read request currently cached in the PF verification channel does not need to continue writing and then reading. The preset address block size is the maximum length of a single access.
5. The apparatus according to claim 1, characterized in that, VF n The verification channel is used in VF n When the verification channel is not empty, in each clock cycle, based on all write request pairs stored in the write request management module, VF... n The first read request in the current cache of the verification channel undergoes a post-write read check, specifically including: The VF n The verification channel is used to extract VF. n Verify the VF of the first read request currently cached in the channel. n The function identifies and reads the address, aligns the read address according to a preset address block size, and obtains the corresponding address block identifier. It also extracts the function identifier and write address corresponding to each write request stored in the write request management module, aligns the write address according to a preset address block size, and obtains the corresponding address block identifier. If a function identifier of VF exists... n And the corresponding address block identifier is the same as VF n If the first read request in the current cache in the verification channel corresponds to a write request with the same address block identifier, then VF is determined. n The first read request in the current cache of the verification channel needs to continue with a write-then-read sequence; otherwise, check the VF. n The first read request in the current cache of the verification channel does not need to be followed by a write-to-read operation. The preset address block size is the maximum length of a single access.
6. The apparatus according to claim 1, characterized in that, The read request management module also includes an arbitration unit, used in VF mode to handle multiple requests that need to be submitted simultaneously within one clock cycle. n The first read request in the current cache of the verification channel is from VF n VF output from the verification channel to the downstream interconnect bus n When verifying a channel, select a VF according to the preset arbitration strategy. n The verification channel outputs the first read request corresponding to the current cache to the downstream interconnect bus.
7. The apparatus according to claim 6, characterized in that, The preset arbitration strategy is either a polling strategy or a priority strategy.
8. The apparatus according to claim 1, characterized in that, The upstream interconnect bus follows the PCIe protocol, and the downstream interconnect bus follows the AXI protocol.
9. The apparatus according to claim 8, characterized in that, Read and write requests received by the upstream interconnect bus are converted into a format conforming to the AXI protocol before being sent to the device.
10. The apparatus according to claim 1, characterized in that, The default address block size is 256 bytes.