Methods for acquiring fluorescence intensity signals, fluorescence thermometers, and storage media.

Abstract

This disclosure provides a method for acquiring fluorescence intensity signals, a fluorescence thermometer, and a storage medium. The method uses the excitation signal transition to trigger ADC conversion and input capture with a unified time reference. Each time data is ready, the direct memory access controller automatically transfers the conversion result to memory. This not only ensures that the sampling window is strictly aligned with the fluorescence decay period, but also frees up the CPU. The sampling accuracy is no longer limited by the CPU's response delay, and silent acquisition of fluorescence intensity signals can be achieved without CPU intervention.

Description

Technical Field

[0001] This disclosure relates to the field of MCU technology, and in particular to a method for acquiring fluorescence intensity signals, a fluorescence thermometer, and a storage medium. Background Technology

[0002] Fluorescent fiber optic temperature measurement technology is a technology that uses the characteristic of fluorescence lifetime of fluorescent materials to change with temperature to achieve temperature sensing. Among them, the acquisition accuracy and sampling rate of fluorescence intensity signal directly affect the accuracy and real-time performance of temperature calculation.

[0003] In existing solutions, at a sampling rate of 50-100Ksps, the microcontroller unit (MCU) can only obtain 500-1000 sampling points during a fluorescence decay process of about 10ms. This is insufficient to meet the requirements of high-precision fluorescence lifetime calculation algorithms. Furthermore, each sampling requires the central processing unit (CPU) to drive the analog-to-digital converter (ADC) to manage the number of samples and extract the sampled data, which consumes a large amount of CPU resources. As the sampling rate increases, the time that the CPU can use for control and calculation tasks decreases. This is particularly unacceptable in embedded MCUs where resources are already limited. Summary of the Invention

[0004] In view of this, the purpose of this disclosure is to provide a method for acquiring fluorescence intensity signals, a fluorescence thermometer, and a storage medium to improve the overall performance of fluorescence fiber optic temperature measurement technology.

[0005] In a first aspect, embodiments of this disclosure provide a method for acquiring fluorescence intensity signals. The method includes: responding to an excitation signal generated by a preset timer changing from an effective excitation level to an ineffective excitation level, setting a start control signal of an analog-to-digital converter (ADC) to an effective state to enable the ADC to start converting the fluorescence intensity signal of the currently acquired fluorescent material, and enabling an input capture channel to listen to a data ready signal output by the ADC; wherein the effective excitation level is used to excite the fluorescent material to generate a fluorescence intensity signal; during the current excitation cycle, whenever an effective edge of the data ready signal is detected, a DMA request is triggered, and the conversion result of the ADC in the current excitation cycle is transmitted to a memory buffer via a communication bus; when the conversion result in the current excitation cycle reaches a preset data volume threshold, the start control signal is set to an ineffective state to instruct the ADC to stop conversion, disable the input capture channel, the DMA channel corresponding to the serial peripheral interface bus, and the DMA request source.

[0006] Secondly, this disclosure provides a fluorescence thermometer, including a processor and a memory. The memory stores machine-executable instructions that can be executed by the processor, and the processor executes the machine-executable instructions to implement the above-mentioned fluorescence intensity signal acquisition method.

[0007] Thirdly, embodiments of this disclosure provide a computer-readable storage medium storing computer-executable instructions. When the computer-executable instructions are called and executed by a processor, the computer-executable instructions cause the processor to implement the above-described method for acquiring fluorescence intensity signals.

[0008] The embodiments disclosed herein bring the following beneficial effects: The aforementioned fluorescence intensity signal acquisition method, fluorescence thermometer, and storage medium use the excitation signal transition to trigger ADC conversion and input capture with a unified time base. Each time data is ready, the Direct Memory Access (DMA) controller automatically transfers the conversion result to memory. This not only ensures that the sampling window is strictly aligned with the fluorescence decay period but also frees up the CPU. The sampling accuracy is no longer limited by the CPU's response delay. Silent acquisition of fluorescence intensity signals can be achieved without CPU involvement, and the accuracy can be configured as needed. This has a particularly significant effect on improving the performance of low- and mid-range devices.

[0009] Other features and advantages of this disclosure will be set forth in the following description and will be apparent in part from the description or may be learned by practicing the disclosure. The objects and other advantages of this disclosure are realized and obtained through the structures particularly pointed out in the description, claims and drawings.

[0010] To make the above-mentioned objects, features and advantages of this disclosure more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0011] To more clearly illustrate the technical solutions in the specific embodiments of this disclosure or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0012] Figure 1 This is a flowchart of one embodiment of the fluorescence intensity signal acquisition method in this disclosure; Figure 2 This is a graph showing the variation of various signals within one excitation cycle in a fluorescence intensity signal acquisition method provided in this embodiment of the present disclosure. Figure 3This is a schematic diagram of a fluorescence thermometer provided in an embodiment of this disclosure. Detailed Implementation

[0013] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0014] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in this disclosure, claims, and accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” or “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0015] It is understood that this disclosure can be used in fluorescent fiber optic temperature measurement systems. The principle of a fluorescent fiber optic temperature measurement system is to utilize the characteristic that the fluorescence lifetime of a fluorescent material changes with temperature to achieve temperature sensing. Specifically, the fluorescent fiber optic temperature measurement system sends a pulse excitation signal to a light-emitting device through a pulse excitation source, causing the light-emitting device to emit pulsed light. This pulsed light emission signal is transmitted to the fluorescent material inside the fiber optic probe. The fluorescent material is excited by the pulsed light emission signal and generates a corresponding fluorescence intensity signal. By utilizing the above characteristics to detect and fit the fluorescence intensity signal, temperature measurement is achieved.

[0016] For ease of understanding, the specific process of the embodiments of this disclosure is described below. Please refer to [link / reference]. Figure 1 One embodiment of the fluorescence intensity signal acquisition method in this disclosure includes: Step S10: In response to the excitation signal generated by the preset timer changing from an effective excitation level to an ineffective excitation level, the start control signal of the analog-to-digital converter is set to an effective state, so as to enable the analog-to-digital converter to start converting the fluorescence intensity signal of the currently acquired fluorescent material, and to enable the input capture channel to listen to the data ready signal output by the analog-to-digital converter; wherein, the effective excitation level is used to excite the fluorescent material to generate a fluorescence intensity signal; In this embodiment, a preset timer is used to generate periodic excitation signals. At the instant the excitation signal transitions from one level state to another, the analog-to-digital converter (ADC) is triggered to start operating, and the ADC's data ready (DRDY) signal is monitored. Based on the DRDY signal, the ADC reads and stores the data that has been converted and is ready. This process decouples the ADC's drive from the CPU, allowing the ADC's drive to no longer occupy CPU resources, thus freeing up CPU resources.

[0017] The preset timer can be integrated into the microcontroller (MCU). The initial count value, counting mode, and output waveform can be configured by software. The preset timer contains an automatic reload counter (such as 16-bit or 32-bit), which increments or decrements according to a preset clock frequency. When the count value is equal to the value of the comparison register, the output level flips, thereby forming a square wave signal with a specific period and duty cycle, which serves as the excitation signal in this embodiment.

[0018] In this embodiment, the excitation signal is used to drive the fluorescent excitation source (a light-emitting device, such as an LED or laser diode) to turn on and off. When the excitation signal is at an effective excitation level, the fluorescent excitation source is turned on and emits pulsed light, which is transmitted to the fluorescent material inside the fiber optic probe. When the excitation signal is at an ineffective excitation level, the fluorescent excitation source is turned off, the excitation source is extinguished, the fluorescent material stops being excited, and enters the spontaneous decay emission stage, generating a fluorescence intensity signal. This embodiment turns the excitation source off at the instant the excitation signal changes, and simultaneously begins to collect the fluorescence intensity signal of the fluorescent material, accurately synchronizing the start time of the fluorescence decay process, so that the accuracy of temperature measurement does not decrease due to performance improvement.

[0019] In one implementation, the effective excitation level can be higher than the invalid excitation level. That is, the effective excitation level is a relatively high level in the excitation signal, and the invalid excitation level is a relatively low level in the excitation signal. The transition from the effective excitation level to the invalid excitation level is a falling edge in the excitation signal, which can be completed within nanoseconds. It is an ideal time reference point and is bound to the sampling start action, which can eliminate the uncertainty caused by software looping and delay waiting.

[0020] An analog-to-digital converter (ADC) is an electronic device that converts continuously changing analog voltage signals into discrete digital quantities. In this embodiment, the ADC is used to convert the analog voltage of fluorescence intensity output by the photodetector into a digital value, where the fluorescence intensity signal is the analog voltage of fluorescence intensity output by the photodetector. After each analog-to-digital conversion, the ADC outputs a level change (e.g., a falling edge from high to low) through its dedicated pin to notify the external controller that new data is ready to be read.

[0021] During one excitation cycle of the excitation signal, the ADC can complete multiple analog-to-digital conversions, meaning the data ready signal can generate multiple valid edges. The frequency of the data ready signal is related to the ADC's output data rate (ODR). For example, when ODR = 400 ksps, the data ready signal generates a valid edge every 2.5 microseconds; however, the specific value is not limited here.

[0022] In this embodiment, the start and stop of the ADC conversion is controlled by the start control signal. The control logic of the start control signal may be different for different ADC models. In one embodiment, the effective state of the start control signal may be a relatively high level or a relatively low level, etc., which is not limited here.

[0023] In this embodiment of the disclosure, the ADC continuously outputs the conversion result during the active state of the start control signal. In one implementation, the start control signal may be a level signal output from a General Purpose Input Output (GPIO) pin, configured to be connected to a dedicated control pin of the ADC (e.g., a pin labeled START, CONVST, CS, or EN) for controlling the start and stop of the ADC conversion.

[0024] The input capture channel is used to detect edge events (such as rising, falling, or double edges) on the input pin and, upon the occurrence of such an event, jumps to execute the capture / compare interrupt service routine. In this embodiment, the input capture channel is configured to detect a valid edge event of the data ready signal. When the data ready signal is detected, a Direct Memory Access (DMA) request is triggered. The valid edge can be a falling edge of the data ready signal. The input capture channel can belong to the aforementioned preset timer or other timers; specific details are not limited here.

[0025] In one implementation, the DRDY pin of the ADC can be configured to be connected to the input capture channel. After each conversion, the DRDY pin generates a valid edge. When the input capture channel captures this valid edge, a DMA request can be triggered through the capture / compare interrupt service routine.

[0026] Enabling the start control signal of the analog-to-digital converter also enables / activates the DMA channel and DMA request source corresponding to the serial peripheral interface bus. It is understood that the DMA controller can include multiple independent channels / data streams, each configured to respond to requests from a specific peripheral, mapped to one or more request sources, and automatically transfer data between the peripheral and memory. Here, the DMA channel corresponding to the serial peripheral interface bus refers to the DMA channel configured to respond to SPI peripheral requests, and the DMA request source corresponding to the serial peripheral interface bus refers to the DMA request source configured to originate from an SPI peripheral.

[0027] Step S20: During the current excitation cycle, whenever a valid edge of the data ready signal is detected, a DMA request is triggered, and the conversion result of the analog-to-digital converter in the current excitation cycle is transferred to the memory buffer via the communication bus. An excitation cycle is the time period from the start of the effective excitation level of the excitation signal to the start of the next effective excitation level. Within an excitation cycle, the ADC's DRDY signal can generate multiple effective edges. Each time a valid edge is detected, a DMA request is triggered, and the conversion result of the ADC in the current excitation cycle is transferred to the memory buffer via the communication bus.

[0028] In this embodiment, the DMA request is a hardware-level trigger signal, triggered by an input capture event captured by the input capture channel, without CPU intervention. The DMA request can be sent to the DMA controller to notify the DMA controller to execute a preset data transfer procedure. In this embodiment, the preset data transfer procedure includes: transferring the conversion result of the analog-to-digital converter in the current excitation cycle to the memory buffer via the communication bus.

[0029] The communication bus is the physical channel for digital signal transmission between the MCU and the ADC. It can be a Serial Peripheral Interface (SPI) bus, an I2C (Inter-Integrated Circuit) bus, or a parallel bus, etc. In this embodiment, the communication bus is a Serial Peripheral Interface bus.

[0030] In this embodiment, the conversion result includes the binary digital value obtained by the ADC after performing analog-to-digital conversion on the analog voltage of fluorescence intensity. The conversion result of the current excitation cycle is transmitted to the memory buffer through the communication bus. The memory buffer can be managed using a preset caching strategy, which is not limited here.

[0031] Step S30: When the conversion result in the current excitation cycle reaches the preset data volume threshold, the start control signal is set to an invalid state to instruct the analog-to-digital converter to stop conversion, disable the input capture channel, the DMA channel corresponding to the serial peripheral interface bus, and the DMA request source.

[0032] Understandably, since the duration of an excitation cycle (e.g., 50 ms) is longer than the duration of the fluorescence decay process (e.g., 10 ms), it is only necessary to collect the fluorescence intensity signal during the decay period. Continuing to sample during the remaining time period of the excitation cycle after decay is complete would only introduce noise and waste resources. Based on this, this embodiment stops collecting the fluorescence intensity signal when the conversion result in the current excitation cycle reaches a preset data volume threshold, until the next excitation cycle arrives.

[0033] In one implementation, the preset data volume threshold can be the maximum number of conversion results that need to be collected within the current excitation cycle, and can be flexibly set according to factors such as the decay period of the fluorescent material, the required temperature measurement accuracy, and the capacity of the DMA buffer (i.e., the memory buffer mentioned above).

[0034] In this embodiment, by setting the start control signal to an invalid state, the ADC can be stopped from converting, the input acquisition channel can be stopped from listening to the data ready signal output by the analog-to-digital converter, and the DMA channel and DMA request source corresponding to the serial peripheral interface bus can be disabled, thereby cutting off the overall trigger link and stopping the acquisition process of the fluorescence intensity signal.

[0035] In one implementation, after step S30, the conversion result in the memory buffer can be transferred to a designated storage area via a direct memory access controller. It is understood that a DMA controller can efficiently move data between memory and peripherals or between memory modules without CPU intervention.

[0036] In this embodiment, the DMA controller is configured in memory-to-memory transfer mode. This mode uses the DMA hardware state machine to copy data blocks from the source address (memory buffer) to the target address (specified storage area). The conversion result can be used for temperature fitting calculations or machine learning training, etc., and is not specifically limited here. The specified storage area is a non-volatile storage area.

[0037] As an example, and not a limitation, Figure 2The diagram shown illustrates the variation of various signals in one excitation cycle according to an embodiment of this disclosure. Assuming the effective excitation level and the ineffective excitation level are relatively high and relatively low, respectively, the effective state of the start control signal is relatively high, and the effective edge of the data ready signal is a falling edge, then the variation diagram of various signals in this embodiment is as follows: Figure 2 As shown, Figure 2 This does not constitute a limitation on the duration of the signal or the ratio of the relationship.

[0038] The fluorescence intensity signal acquisition method provided by the above embodiments uses the excitation signal transition to trigger ADC conversion and input capture with a unified time base. Each time the data is ready, the Direct Memory Access (DMA) controller automatically transfers the conversion result to memory. This not only ensures that the sampling window is strictly aligned with the fluorescence decay period, but also frees up the CPU. The sampling accuracy is no longer limited by the CPU response delay. Silent acquisition of fluorescence intensity signals can be achieved without CPU participation. The accuracy can also be configured as needed, which has a particularly significant effect on improving the performance of low- and mid-range devices.

[0039] Next, the specific acquisition method of fluorescence intensity signal will be explained.

[0040] In one embodiment, the method further includes: modulating the excitation signal generated by a preset timer into a periodic pulse signal with a specified excitation period and an effective excitation level lasting for a specified duration in each period by pulse width modulation, wherein the effective excitation level is higher than the ineffective excitation level.

[0041] Pulse Width Modulation (PWM) is a technique that uses digital square wave signals to simulate analog signal levels. It controls average output power by changing the duty cycle (i.e., the ratio of high-level duration to the period) of a high-level signal (an effective excitation level) at a fixed frequency. In this embodiment, a preset timer is configured in PWM output mode to generate a periodic pulse signal with a specified excitation period and a high-level duration.

[0042] In this embodiment, by setting the Auto-Reload Register (ARR) to determine the counting period (i.e., the PWM period) and setting the Capture / Compare Register (CCR) to determine the comparison point (i.e., the duration of the high level), a precise periodic square wave can be obtained as the excitation signal.

[0043] In this embodiment, the square wave output by PWM is directly used to drive the fluorescent excitation light source (a light-emitting device, such as an LED or a laser diode). During the high level (an effective excitation level), the light source is lit and the fluorescent material is excited; during the low level (an ineffective excitation level), the light source is turned off and the fluorescent material begins to decay and emit light, generating a fluorescence intensity signal.

[0044] In this embodiment, PWM is used to drive the fluorescence excitation circuit, rather than the ADC itself. The PWM period controls the fluorescence excitation period, rather than the ADC sampling period. In this embodiment, the ADC start signal is controlled by a pin (such as the START pin) used to generate a start control signal. This pin is set to a high level when the PWM capture / compare interrupt is triggered and set to a low level when the DMA transfer is completed interrupt.

[0045] The timer operates in two modes: master mode and slave mode. Input capture can be used in both modes, regardless of the timer's operating mode. Input capture occurs when the capture / compare channel detects a valid edge of an external input and latches the count value (without altering the counter's operation). Reset mode is a type of slave mode. In this mode, the timer responds to trigger input signals generated by external devices or other peripherals, resetting the timer count value (forcibly clearing the counter) and generating a timer reset time. These two modes belong to different functional modules within the timer peripheral and generate different peripheral events.

[0046] Specifically, the specified excitation period can be configured to 50ms, and the duration of the effective excitation level per period can be configured to 8ms. This duration is sufficient for the fluorescent material to reach the saturated excitation state. The typical value is a few milliseconds to tens of milliseconds. Too long a duration will cause unnecessary power consumption or thermal effects. The specific duration can be freely configured according to the response speed of the fluorescent material and the power of the excitation light source.

[0047] In one embodiment, the method further includes: configuring a preset phase-locked loop clock source to a specified frequency, and outputting the clock source of the specified frequency to the analog-to-digital converter through the clock source output pin as the operating clock of the analog-to-digital converter.

[0048] In this embodiment, the ADC's operating clock is provided by a preset phase-locked loop (PLL) clock source. The operating clock directly determines the ADC's sampling rate and conversion accuracy. By configuring the clock source to a specified frequency within the frequency range allowed by the ADC, the ADC can determine the data refresh rate based on the clock source and the internally set oversampling ratio (OSR), and continuously output the conversion results at this rate.

[0049] To achieve more flexible fractional frequency multiplication capabilities, the preset phase-locked loop (PLL) clock source can reuse the dedicated clock source PLLI2S of the I2S peripheral. The PLL clock source includes a phase comparator, a voltage-controlled oscillator (VCO), and a frequency divider. By configuring the input division factor (M), multiplication factor (N), and output division factor (R), the preset PLL clock source can be configured to a specified frequency. In one embodiment, the specified frequency is 25.6MHz, but this is not a specific limitation.

[0050] It is understandable that the ADC's operating clock frequency (i.e., the specified frequency) is related to the ADC's data refresh rate and its internal oversampling rate. The relationship between these three factors is shown in the following formula:

[0051] Where ODR represents the data refresh rate and OSR represents the oversampling rate. This indicates the specified frequency.

[0052] In this embodiment, the clock source output pin (Microcontroller Clock Output, MCO) is a pin specifically used to output the internal clock signal to the outside. This pin can select the output clock source as the preset phase-locked loop clock source by configuring the multiplexing function, and the frequency division coefficient can be set, such as 1, 2, 3, 4, 5, etc., which are not limited here.

[0053] In one implementation, the configuration register of the analog-to-digital converter can be written via the communication bus to enable the converter to operate in a control mode driven by an external clock (a preset phase-locked loop clock source) and controlled by a start control signal to start and stop the conversion.

[0054] In one embodiment, the method further includes: calculating a target oversampling rate of the analog-to-digital converter based on a specified frequency and a target data refresh rate that the analog-to-digital converter needs to achieve; and configuring the oversampling rate of the built-in digital filter of the analog-to-digital converter as the target oversampling rate via a communication bus.

[0055] In this embodiment, the target ODR can be preset according to the dynamic characteristics of the fluorescence decay curve and the requirements of measurement accuracy, and is used to indicate the number of times the analog-to-digital converter outputs conversion results per second. For example, to achieve high time resolution fitting, ODR can be set to 400ksps (i.e., one sampling point every 2.5 microseconds), and the specific value is not limited here.

[0056] This embodiment is based on Given the desired ODR, the target oversampling rate of the analog-to-digital converter (ADC) is calculated using the formula described above. In one implementation, the target oversampling rate needs to belong to the set of selectable OSRs supported by the ADC, such as 32, 64, 128, 256, etc. If the calculated target oversampling rate is not an integer supported by the ADC, a similar OSR can be selected from the above set, and then the ADC can be adjusted according to the selected OSR. .

[0057] In one embodiment, the method further includes: configuring the operating mode of the analog-to-digital converter to a gated start-stop conversion mode; wherein the gated start-stop conversion mode is used to indicate that the start of the conversion of the analog-to-digital converter is controlled by the valid state of the start control signal and the stop of the conversion is controlled by the invalid state of the start control signal.

[0058] It is understandable that an ADC can be configured to multiple operating modes, such as single conversion mode (one conversion is initiated each time it is triggered), continuous conversion mode (free operation, continuous conversion), gated start-stop conversion mode, etc. Different operating modes determine how the ADC responds to external control signals and the start-stop logic of the conversion process. In this embodiment, the operating mode of the analog-to-digital converter is configured as gated start-stop conversion mode.

[0059] In the gated start-stop conversion mode, the ADC conversion start is controlled by the valid state of the start control signal, and the conversion stop is controlled by the invalid state of the start control signal. When the start control signal is in a valid state (e.g., high level), the ADC continuously performs conversions. When the start control signal becomes invalid (e.g., low level), the ADC immediately stops conversion after completing the currently ongoing conversion (if any) and waits for the next cycle.

[0060] This implementation allows the opening and closing of the sampling window to be determined entirely by the timing of the level change of the start control signal, which can be strictly synchronized with the start and end of the fluorescence decay cycle. Outside the window, the ADC is in an idle state, which can significantly reduce power consumption.

[0061] In one embodiment, the step of setting the start control signal of the analog-to-digital converter to an active state in response to the excitation signal generated by the preset timer changing from an active excitation level to an inactive excitation level includes: triggering a capture / compare interrupt service routine of the preset timer in response to the excitation signal generated by the preset timer changing from an active excitation level to an inactive excitation level, wherein the capture / compare interrupt service routine includes: setting the start control signal of the analog-to-digital converter to an active state, enabling the input capture channel for capturing the data ready signal, and the DMA channel and DMA request source corresponding to the input capture channel and the serial peripheral interface bus.

[0062] In this embodiment, the preset timer is configured in PWM output mode to generate the excitation signal. When a level transition occurs in the PWM output (from an active excitation level to an inactive excitation level), the preset timer can generate a "Capture / Compare Interrupt" through the capture / compare channel to trigger the capture / compare interrupt service routine. In this embodiment, the input capture channel, configured to enable the data ready signal, is configured to enable / enable the DMA channel and DMA request source corresponding to the input capture channel and the serial peripheral interface bus.

[0063] In the capture / compare interrupt service routine, the GPIO output level connected to the START pin of the analog-to-digital converter (used to generate the start control signal) can be set to an active state (e.g., high) using general-purpose input / output operations. General-purpose input / output operations are simple register write operations with extremely short execution times.

[0064] In one embodiment, the method further includes: configuring the input capture channel of a preset timer to capture the valid edge of a data ready signal; triggering a DMA request whenever a valid edge of the data ready signal is detected during the current excitation cycle, and transmitting the conversion result of the analog-to-digital converter in the current excitation cycle to a memory buffer via a communication bus, comprising: sending a DMA request to a direct memory access controller whenever the input capture channel of the preset timer captures the valid edge of the data ready signal during the current excitation cycle; controlling the receiving channel of the serial peripheral interface bus through the direct memory access controller, obtaining the conversion result from the analog-to-digital converter and storing it in the memory buffer when the serial peripheral interface bus generates a clock signal.

[0065] In this embodiment, the input pin of the input capture channel can be connected to the DRDY pin of the ADC to capture the valid edge of the data ready signal to detect the completion time of each conversion. The rising edge generated on the DRDY pin of the ADC after completing a conversion is the valid edge. When the input capture channel captures the valid edge of the data ready signal, it latches the current timer counter value into the capture register and simultaneously generates an interrupt or DMA request.

[0066] In this embodiment, the communication bus is an SPI bus. The SPI bus is a synchronous serial communication interface that includes at least four lines: SCK (clock), MOSI (master output, slave input), MISO (master input, slave output), and CS (chip select). The SPI peripheral generates a clock and simultaneously sends and receives data. The SPI receive channel refers to the hardware path that receives data from the MISO line and stores it in the data register.

[0067] In this implementation, writing any value to the data transmit register immediately initiates the generation of the SCK clock on the SPI bus. Data is shifted out (MOSI) and simultaneously shifted in (MISO) on each edge of the clock, and the received data is automatically stored in the receive register. DMA can be configured to automatically move the contents of the receive register to a memory buffer, thereby achieving automatic reception without CPU intervention.

[0068] In one embodiment, the preset data volume threshold is the amount of data obtained at the target data refresh rate of the analog-to-digital converter within the fluorescence decay time of the fluorescent material; after the steps of setting the start control signal to an invalid state to instruct the analog-to-digital converter to stop conversion, disable the input capture channel, the DMA channel corresponding to the serial peripheral interface bus, and the DMA request source when the conversion result in the current excitation cycle reaches the preset data volume threshold, the method further includes: transferring the conversion result in the memory buffer to a designated storage area through a direct memory access controller.

[0069] In this embodiment, the preset data volume threshold is the amount of data obtained at the target data refresh rate of the analog-to-digital converter within the fluorescence decay time of the fluorescent material. For example, assuming a sampling rate of 400 ksps and a fluorescence decay time (i.e., the decay period of the fluorescent material) of 10 ms, the preset data volume threshold can be 4000. By configuring the preset data volume, this embodiment can align the sampling window with the fluorescence decay period, ensuring complete data acquisition while reducing the acquisition of invalid noise and saving storage space.

[0070] In this embodiment, after acquiring quantitative data, the conversion results in the memory buffer are transferred to a designated storage area via the DMA controller. It is understood that the DMA controller can efficiently move data between memory and peripherals or between memory modules without CPU intervention.

[0071] In one implementation, the DMA controller can be configured in a memory-to-memory transfer mode. This mode uses the DMA hardware state machine to copy data blocks from the source address (memory buffer) to the target address (specified storage area). The conversion result can be used for temperature fitting calculations, machine learning training, etc., without specific limitations here. The specified storage area is a non-volatile storage area.

[0072] This embodiment also provides a fluorescence thermometer, including a processor and a memory. The memory stores machine-executable instructions that can be executed by the processor. The processor executes the machine-executable instructions to implement the aforementioned fluorescence intensity signal acquisition method. This fluorescence thermometer can be a server or a terminal device.

[0073] See Figure 3As shown, the fluorescence thermometer includes a processor 100 and a memory 101. The memory 101 stores machine-executable instructions that can be executed by the processor 100. The processor 100 executes the machine-executable instructions to implement the above-mentioned method for acquiring fluorescence intensity signals.

[0074] Furthermore, Figure 3 The fluorescent thermometer shown also includes a bus 102 and a communication interface 103. The processor 100, the communication interface 103 and the memory 101 are connected through the bus 102.

[0075] The memory 101 may include high-speed random access memory (RAM) and may also include non-volatile memory, such as at least one disk storage device. Communication between this system network element and at least one other network element is achieved through at least one communication interface 103 (which can be wired or wireless), such as the Internet, wide area network, local area network, metropolitan area network, etc. The bus 102 may be an ISA bus, PCI bus, or EISA bus, etc. The bus can be divided into address bus, data bus, control bus, etc. For ease of representation, Figure 3 The symbol is represented by a single double-headed arrow, but this does not mean that there is only one bus or one type of bus.

[0076] The processor 100 may be an integrated circuit chip with signal processing capabilities. In implementation, each step of the above method can be completed by the integrated logic circuitry in the hardware of the processor 100 or by instructions in software form. The processor 100 may be a general-purpose processor, including a Central Processing Unit (CPU), a Network Processor (NP), etc.; it may also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field-Programmable Gate Array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this disclosure. The general-purpose processor may be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this disclosure can be directly manifested as execution by a hardware decoding processor, or execution by a combination of hardware and software modules in the decoding processor. The software module can reside in a readily available storage medium in the art, such as random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, or registers. This storage medium is located in memory 101. The processor 100 reads information from memory 101 and, in conjunction with its hardware, completes the steps of the method described in the foregoing embodiments, for example: In response to the excitation signal generated by the preset timer changing from an active excitation level to an inactive excitation level, the start control signal of the analog-to-digital converter (ADC) is set to an active state. This enables the ADC to begin converting the fluorescence intensity signal of the currently acquired fluorescent material and enables the input capture channel to listen for the data ready signal output by the ADC. The active excitation level is used to excite the fluorescent material to generate a fluorescence intensity signal. During the current excitation cycle, whenever an active edge of the data ready signal is detected, a DMA request is triggered, and the conversion result of the ADC in the current excitation cycle is transferred to the memory buffer via the communication bus. When the conversion result in the current excitation cycle reaches a preset data volume threshold, the start control signal is set to an inactive state to instruct the ADC to stop conversion, disable the input capture channel, and disable the DMA channel and DMA request source corresponding to the serial peripheral interface bus.

[0077] In this method, the excitation signal transition is used to trigger ADC conversion and input acquisition with a unified time base. Each time the data is ready, the Direct Memory Access (DMA) controller automatically moves the conversion result to memory. This not only ensures that the sampling window is strictly aligned with the fluorescence decay period, but also frees up the CPU. The sampling accuracy is no longer limited by the CPU's response delay. Silent acquisition of fluorescence intensity signals can be achieved without CPU participation. The accuracy can also be configured as needed, which has a particularly significant effect on improving the performance of low- and mid-range devices.

[0078] Optionally, the method further includes: modulating the excitation signal generated by a preset timer into a periodic pulse signal with a specified excitation period and an effective excitation level lasting for a specified duration in each period by pulse width modulation, wherein the effective excitation level is higher than the ineffective excitation level.

[0079] Optionally, the method further includes: configuring a preset phase-locked loop clock source to a specified frequency, and outputting the clock source of the specified frequency to the analog-to-digital converter through the clock source output pin as the operating clock of the analog-to-digital converter.

[0080] Optionally, the method further includes: calculating the target oversampling rate of the analog-to-digital converter based on the specified frequency and the target data refresh rate required by the analog-to-digital converter; and configuring the oversampling rate of the built-in digital filter of the analog-to-digital converter as the target oversampling rate via a communication bus.

[0081] Optionally, the method further includes: configuring the operating mode of the analog-to-digital converter to a gated start-stop conversion mode; wherein the gated start-stop conversion mode is used to indicate that the start of the conversion of the analog-to-digital converter is controlled by the valid state of the start control signal and the stop of the conversion is controlled by the invalid state of the start control signal.

[0082] Optionally, the step of setting the start control signal of the analog-to-digital converter to an active state in response to the excitation signal generated by the preset timer changing from an active excitation level to an inactive excitation level includes: triggering the capture / compare interrupt service routine of the preset timer in response to the excitation signal generated by the preset timer changing from an active excitation level to an inactive excitation level, wherein the capture / compare interrupt service routine includes: setting the start control signal of the analog-to-digital converter to an active state, enabling the input capture channel for capturing the data ready signal, and the DMA channel and DMA request source corresponding to the input capture channel and the serial peripheral interface bus.

[0083] Optionally, the method further includes: configuring the input capture channel of the preset timer to capture the valid edge of the data ready signal; triggering a DMA request whenever a valid edge of the data ready signal is detected during the current excitation cycle, and transmitting the conversion result of the analog-to-digital converter in the current excitation cycle to the memory buffer via the communication bus, including: sending a DMA request to the direct memory access controller whenever the input capture channel of the preset timer captures the valid edge of the data ready signal during the current excitation cycle; controlling the receiving channel of the serial peripheral interface bus through the direct memory access controller, obtaining the conversion result from the analog-to-digital converter and storing it in the memory buffer when the serial peripheral interface bus generates a clock signal.

[0084] Optionally, the preset data volume threshold is the amount of data obtained at the target data refresh rate of the analog-to-digital converter within the fluorescence decay time of the fluorescent material; after the steps of setting the start control signal to an invalid state to instruct the analog-to-digital converter to stop conversion, disable the input capture channel, the DMA channel corresponding to the serial peripheral interface bus, and the DMA request source when the conversion result in the current excitation cycle reaches the preset data volume threshold, the method further includes: transferring the conversion result in the memory buffer to a specified storage area through a direct memory access controller.

[0085] This embodiment also provides a computer-readable storage medium storing computer-executable instructions. When these computer-executable instructions are called and executed by a processor, they cause the processor to implement the aforementioned method for acquiring fluorescence intensity signals, for example: In response to the excitation signal generated by the preset timer changing from an active excitation level to an inactive excitation level, the start control signal of the analog-to-digital converter (ADC) is set to an active state. This enables the ADC to begin converting the fluorescence intensity signal of the currently acquired fluorescent material and enables the input capture channel to listen for the data ready signal output by the ADC. The active excitation level is used to excite the fluorescent material to generate a fluorescence intensity signal. During the current excitation cycle, whenever an active edge of the data ready signal is detected, a DMA request is triggered, and the conversion result of the ADC in the current excitation cycle is transferred to the memory buffer via the communication bus. When the conversion result in the current excitation cycle reaches a preset data volume threshold, the start control signal is set to an inactive state to instruct the ADC to stop conversion, disable the input capture channel, and disable the DMA channel and DMA request source corresponding to the serial peripheral interface bus.

[0086] In this method, the excitation signal transition is used to trigger ADC conversion and input acquisition with a unified time base. Each time the data is ready, the Direct Memory Access (DMA) controller automatically moves the conversion result to memory. This not only ensures that the sampling window is strictly aligned with the fluorescence decay period, but also frees up the CPU. The sampling accuracy is no longer limited by the CPU's response delay. Silent acquisition of fluorescence intensity signals can be achieved without CPU participation. The accuracy can also be configured as needed, which has a particularly significant effect on improving the performance of low- and mid-range devices.

[0087] Optionally, the method further includes: modulating the excitation signal generated by a preset timer into a periodic pulse signal with a specified excitation period and an effective excitation level lasting for a specified duration in each period by pulse width modulation, wherein the effective excitation level is higher than the ineffective excitation level.

[0088] Optionally, the method further includes: configuring a preset phase-locked loop clock source to a specified frequency, and outputting the clock source of the specified frequency to the analog-to-digital converter through the clock source output pin as the operating clock of the analog-to-digital converter.

[0089] Optionally, the method further includes: calculating the target oversampling rate of the analog-to-digital converter based on the specified frequency and the target data refresh rate required by the analog-to-digital converter; and configuring the oversampling rate of the built-in digital filter of the analog-to-digital converter as the target oversampling rate via a communication bus.

[0090] Optionally, the method further includes: configuring the operating mode of the analog-to-digital converter to a gated start-stop conversion mode; wherein the gated start-stop conversion mode is used to indicate that the start of the conversion of the analog-to-digital converter is controlled by the valid state of the start control signal and the stop of the conversion is controlled by the invalid state of the start control signal.

[0091] Optionally, the step of setting the start control signal of the analog-to-digital converter to an active state in response to the excitation signal generated by the preset timer changing from an active excitation level to an inactive excitation level includes: triggering the capture / compare interrupt service routine of the preset timer in response to the excitation signal generated by the preset timer changing from an active excitation level to an inactive excitation level, wherein the capture / compare interrupt service routine includes: setting the start control signal of the analog-to-digital converter to an active state, enabling the input capture channel for capturing the data ready signal, and the DMA channel and DMA request source corresponding to the input capture channel and the serial peripheral interface bus.

[0092] Optionally, the method further includes: configuring the input capture channel of the preset timer to capture the valid edge of the data ready signal; triggering a DMA request whenever a valid edge of the data ready signal is detected during the current excitation cycle, and transmitting the conversion result of the analog-to-digital converter in the current excitation cycle to the memory buffer via the communication bus, including: sending a DMA request to the direct memory access controller whenever the input capture channel of the preset timer captures the valid edge of the data ready signal during the current excitation cycle; controlling the receiving channel of the serial peripheral interface bus through the direct memory access controller, obtaining the conversion result from the analog-to-digital converter and storing it in the memory buffer when the serial peripheral interface bus generates a clock signal.

[0093] Optionally, the preset data volume threshold is the amount of data obtained at the target data refresh rate of the analog-to-digital converter within the fluorescence decay time of the fluorescent material; after the steps of setting the start control signal to an invalid state to instruct the analog-to-digital converter to stop conversion, disable the input capture channel, the DMA channel corresponding to the serial peripheral interface bus, and the DMA request source when the conversion result in the current excitation cycle reaches the preset data volume threshold, the method further includes: transferring the conversion result in the memory buffer to a specified storage area through a direct memory access controller.

[0094] The computer program product for the fluorescence intensity signal acquisition method, fluorescence thermometer, and storage medium provided in this disclosure includes a computer-readable storage medium storing program code. The instructions included in the program code can be used to execute the methods described in the preceding method embodiments. For specific implementation details, please refer to the method embodiments, which will not be repeated here.

[0095] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working process of the system and apparatus described above can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0096] Furthermore, in the description of the embodiments of this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this disclosure based on the specific circumstances.

[0097] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this disclosure, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this disclosure. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0098] In the description of this disclosure, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0099] Finally, it should be noted that the above embodiments are merely specific implementations of this disclosure, used to illustrate the technical solutions of this disclosure, and not to limit it. The protection scope of this disclosure is not limited thereto. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features, within the scope of the technology disclosed in this disclosure. Such modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this disclosure, and should all be covered within the protection scope of this disclosure. Therefore, the protection scope of this disclosure should be determined by the protection scope of the claims.

Claims

1. A method for acquiring fluorescence intensity signals, characterized in that, The method includes: The preset phase-locked loop clock source is configured to a specified frequency, and the clock source of the specified frequency is output to the analog-to-digital converter through the clock source output pin as the working clock of the analog-to-digital converter; Calculate the target oversampling rate of the analog-to-digital converter based on the specified frequency and the target data refresh rate required by the analog-to-digital converter; The oversampling rate of the built-in digital filter of the analog-to-digital converter is configured to the target oversampling rate via the communication bus; The operating mode of the analog-to-digital converter is configured as a gated start-stop conversion mode; wherein, the gated start-stop conversion mode is used to indicate that the start of the conversion of the analog-to-digital converter is controlled by the valid state of the start control signal, and the stop of the conversion is controlled by the invalid state of the start control signal; In response to the excitation signal generated by the preset timer changing from an effective excitation level to an ineffective excitation level, the start control signal of the analog-to-digital converter is set to an effective state, so as to enable the analog-to-digital converter to start converting the fluorescence intensity signal of the currently acquired fluorescent material, and to enable the input capture channel to listen to the data ready signal output by the analog-to-digital converter; wherein, the effective excitation level is used to excite the fluorescent material to generate a fluorescence intensity signal; During the current excitation cycle, whenever a valid edge of the data ready signal is detected, a DMA request is triggered, and the conversion result of the analog-to-digital converter in the current excitation cycle is transferred to the memory buffer via the communication bus. When the conversion result within the current excitation cycle reaches a preset data volume threshold, the start control signal is set to an invalid state to instruct the analog-to-digital converter to stop conversion, disable the input capture channel, the DMA channel corresponding to the serial peripheral interface bus, and the DMA request source.

2. The method according to claim 1, characterized in that, The method further includes: The excitation signal generated by the preset timer is modulated into a periodic pulse signal with a specified excitation period and an effective excitation level lasting for a specified duration in each period by pulse width modulation, wherein the effective excitation level is higher than the ineffective excitation level.

3. The method according to claim 1, characterized in that, The step of setting the start control signal of the analog-to-digital converter to an active state in response to the excitation signal generated by the preset timer changing from an active excitation level to an inactive excitation level includes: In response to the excitation signal generated by the preset timer changing from an active excitation level to an inactive excitation level, the capture / compare interrupt service routine of the preset timer is triggered. The capture / compare interrupt service routine includes: setting the start control signal of the analog-to-digital converter to an active state, enabling the input capture channel for capturing the data ready signal, and the DMA channel and DMA request source corresponding to the input capture channel and the serial peripheral interface bus.

4. The method according to claim 1, characterized in that, The method further includes: Configure the input capture channel of the preset timer to capture the valid edge of the data ready signal; During the current excitation cycle, whenever a valid edge of the data ready signal is detected, a DMA request is triggered, and the conversion result of the analog-to-digital converter in the current excitation cycle is transferred to the memory buffer via the communication bus, including: During the current excitation cycle, whenever the input capture channel of the preset timer captures a valid edge of the data ready signal, a DMA request is sent to the direct memory access controller. The direct memory access controller controls the receiving channel of the serial peripheral interface bus. When the serial peripheral interface bus generates a clock signal, the conversion result is obtained from the analog-to-digital converter and stored in the memory buffer.

5. The method according to claim 1, characterized in that, The preset data volume threshold is the amount of data obtained at the target data refresh rate of the analog-to-digital converter within the fluorescence decay time of the fluorescent material. After the steps of setting the start control signal to an invalid state to instruct the analog-to-digital converter to stop conversion, disabling the input capture channel, the DMA channel corresponding to the serial peripheral interface bus, and the DMA request source when the conversion result in the current excitation cycle reaches a preset data volume threshold, the method further includes: The conversion results in the memory buffer are transferred to the designated storage area via the direct memory access controller.

6. A fluorescence thermometer, characterized in that, The method includes a processor and a memory, the memory storing machine-executable instructions that can be executed by the processor, the processor executing the machine-executable instructions to implement the fluorescence intensity signal acquisition method according to any one of claims 1-5.

7. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions, which, when invoked and executed by a processor, cause the processor to implement the fluorescence intensity signal acquisition method according to any one of claims 1-5.

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