A chip test vector priority dynamic allocation system

Abstract

This invention provides a dynamic priority allocation system for chip test vectors, comprising: a test vector attribute library for storing a set of static attribute tags and fault causality tags for each test vector; a real-time status awareness module for collecting and updating global status data of the chip in real time during test execution; a multi-dimensional collaborative priority engine connected to the test vector attribute library and the real-time status awareness module for performing comprehensive priority analysis on the test vectors to be executed based on the static attribute tags and the global status data; and a scheduling decision module connected to the multi-dimensional collaborative priority engine for generating a test vector scheduling scheme for controlling the execution of an automated test equipment (ATE) based on the results of the comprehensive priority analysis, thereby improving the accuracy of chip test vector scheduling.

Description

Technical Field

[0001] This invention relates to the field of chip testing technology, and more specifically, to a dynamic priority allocation system for chip testing vectors. Background Technology

[0002] Traditional chip testing methods employ a static priority scheduling strategy, which predetermines a fixed execution order based on the coverage contribution of test vectors or historical fault detection rates, and this order remains unchanged throughout the testing process. While this method can meet basic testing needs for small-scale chips, it has gradually revealed numerous insurmountable limitations when dealing with large-scale, complex chips.

[0003] On the one hand, traditional chip testing methods often cannot adapt to dynamic state changes during the testing process. During testing, chips will experience real-time changes in physical state such as heat distribution, electromagnetic interference, and power supply noise. Static scheduling strategies completely ignore these dynamic factors, which may lead to chip overheating and burnout, false kills caused by electromagnetic interference, or inaccurate test results due to power supply noise. On the other hand, traditional chip testing methods often suffer from serious timing race and decision deadlock problems. That is, when multiple scheduling submodules are computed in parallel, due to the huge differences in the response time of each submodule, decision timing misalignment often occurs. The system either ignores the alarms of high-latency submodules and forces execution, or it must roll back the completed decisions, causing a sharp drop in scheduling efficiency. Summary of the Invention

[0004] In view of the aforementioned problems, and in conjunction with the first aspect of the present invention, embodiments of the present invention provide a dynamic allocation system for chip test vector priorities, comprising:

[0005] A test vector attribute library is used to store the static attribute tag set and fault causal relationship tag for each test vector. The static attribute tag set includes at least logical resource requirement tag, defect association tag, thermal impact tag, and electromagnetic interference fingerprint tag.

[0006] The real-time status awareness module is used to collect and update the chip's global status data in real time during test execution. The global status data includes at least the result sequence of executed test vectors, the chip's real-time two-dimensional thermal distribution map, power supply transient signal characteristics, and the remaining test time budget.

[0007] A multi-dimensional collaborative priority engine, connected to the test vector attribute library and the real-time state awareness module, is used to perform comprehensive priority analysis on the test vectors to be executed based on the static attribute tags and the global state data.

[0008] The multi-dimensional collaborative priority engine includes at least a logical concurrency and resource arbitration submodule, a fault location gain evaluation submodule, a thermal safety constraint submodule, a fault causal chain triggering submodule, a portfolio time budgeting submodule, an electromagnetic compatibility avoidance submodule, and a scheduling mode controller.

[0009] The scheduling decision module, connected to the multi-dimensional collaborative priority engine, is used to generate a test vector scheduling scheme for controlling the execution of the automated test equipment (ATE) based on the results of the comprehensive priority analysis.

[0010] Compared with the prior art, the present invention has the following beneficial effects:

[0011] By adopting a gated multi-stage pipeline architecture, physical feasibility rejection is prioritized and performance ranking is postponed, thereby alleviating the timing race and decision deadlock problems in traditional parallel architectures.

[0012] By using a scheduling modal controller, the system's objectives were unified across different testing phases, thus avoiding the problem of insufficient scheduling efficiency caused by conflicts between objectives across dimensions.

[0013] Through collaborative analysis among the sub-modules within the multi-dimensional collaborative priority engine, the real-time changes in physical states of the chip during testing, such as heat distribution, electromagnetic interference, and power supply noise, are taken into account, thereby improving the rationality and scientific nature of chip test vector scheduling. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of a chip test vector priority dynamic allocation system according to the present invention;

[0015] Figure 2 This is a schematic diagram of a multi-dimensional collaborative priority engine in a dynamic allocation system for chip test vector priorities according to the present invention. Detailed Implementation

[0016] The present invention will now be described in detail with reference to the accompanying drawings, such as... Figure 1 and Figure 2 As shown below, a detailed introduction to this chip test vector priority dynamic allocation system will be provided.

[0017] A test vector attribute library is used to store the static attribute tag set and fault causal relationship tag for each test vector. The static attribute tag set includes at least logical resource requirement tag, defect association tag, thermal impact tag, and electromagnetic interference fingerprint tag.

[0018] Specifically, the test vector attribute library is built offline in the form of a graph structure and stores the static attribute label set and fault causal relationship label of each test vector.

[0019] The logical resource requirement label is represented by a bitmask, with each bit corresponding to a physical resource. The physical resources include hardware resources inside the chip that can be independently occupied, such as clock domain, power island, bus, I / O port, and scan chain.

[0020] For example, for a chip containing 4 clock domains, 8 power islands, and 16 scan chains, its logic resource requirement label can be designed as a 28-bit bitmask, where bits 0-3 correspond to the 4 clock domains, bits 4-11 correspond to the 8 power islands, and bits 12-27 correspond to the 16 scan chains.

[0021] By performing a bitwise AND operation, we can determine whether there is a resource conflict between two test vectors. Continuing from the previous example, assuming that the 0th to 3rd bits of the bitmasks corresponding to test vectors A and B are both 0b0001, then after performing the bitwise AND operation, we can obtain 0b0001, which indicates that both A and B need to occupy the first clock domain. Therefore, we can determine that there is a resource conflict between them.

[0022] The defect association labels store the causal relationship and detection probability between physical defects and observable circuit nodes in the form of a Bayesian network. The nodes of the Bayesian network include physical defect nodes and observable circuit nodes, and the edges are used to characterize the causal relationship between nodes and the corresponding conditional probability. The conditional probability can be obtained by analyzing historical operation logs.

[0023] Physical defect nodes correspond to common physical defects that may occur during chip manufacturing, such as short circuits in the gate oxide layer, open circuits in metal lines, and poor contact holes; observable circuit nodes correspond to logic nodes inside the chip that can be observed through scan chains or I / O ports; each test vector is associated with the physical defect and observable circuit node it activates.

[0024] For example, for a defect where the input of a NAND gate is open, the corresponding Bayesian network node includes the defect node, the output node of the NAND gate, and the edge connecting them. The conditional probability of the edge is 0.98, which means that when the defect exists, there is a 98% probability that it will cause the NAND gate output to be abnormal. Suppose that a certain test vector activates the output node of the NAND gate, then the detection probability of the vector for the defect is 0.98.

[0025] The thermal impact label includes at least a power time-varying waveform, hotspot coordinates, and a thermal time constant. The power time-varying waveform represents the transient current curve per clock cycle during the execution of the test vector, reflecting the power consumption change of the test vector at different times. The hotspot coordinates represent the multiple physical locations inside the chip that generate the most heat during the execution of the test vector, such as a hotspot located at the center of the chip (500μm, 500μm). The thermal time constant represents the time constant of the chip's thermal response, reflecting the rate of temperature change of the chip, such as 10ms.

[0026] The electromagnetic interference fingerprint tag includes at least a frequency band energy distribution and a noise margin. The frequency band energy distribution is represented by the frequency band energy distribution obtained by performing a fast Fourier transform on the power time-varying waveform of the test vector, which is used to reflect the intensity of electromagnetic interference generated by the test vector at different frequencies. The noise margin is represented by the maximum electromagnetic interference intensity that the test vector can withstand when it is the object of disturbance. When this intensity is exceeded, the test result will be incorrect.

[0027] The fault causal relationship label is represented as a directed acyclic graph with propagation confidence, used to mark all root cause failure modes. The nodes of the directed acyclic graph are functional module failure modes, and the edges have propagation confidence, which are used to represent the probability that the failure of the upstream module leads to the failure of the downstream module. This confidence can be obtained by analyzing historical data. The root cause failure mode is the failure mode caused by failure of other modules, that is, the starting point of fault tracing.

[0028] For example, suppose a chip containing a processor core, memory, and interface modules has a fault causality graph containing three nodes: "processor core instruction decoding error", "memory data read / write error", and "interface module data transmission error". The edge from "processor core instruction decoding error" to "memory data read / write error" has a propagation confidence of 0.7, which means that there is a 70% probability that a processor core instruction decoding error will lead to a memory data read / write error.

[0029] The real-time status awareness module is used to collect and update the chip's global status data in real time during test execution. The global status data includes at least the result sequence of executed test vectors, the chip's real-time two-dimensional thermal distribution map, power supply transient signal characteristics, and the remaining test time budget.

[0030] Specifically, the real-time state awareness module includes the following sub-modules:

[0031] The logic state monitoring submodule is used to record the complete result sequence of executed test vectors, specifically:

[0032] Receive test result data returned by the automated test equipment (ATE). The test result data includes at least the execution time, pass / fail status, scan cell address and error logic value for each test vector.

[0033] For example, when a test vector fails to execute, the logic state monitoring submodule automatically records the address and error value of all scan units that output errors. For instance, the expected value of scan unit address 0x0010 is 0, but the actual value is 1; the expected value of scan unit address 0x0020 is 1, but the actual value is 0.

[0034] The real-time heat map generation submodule uses the Kalman filter algorithm, combined with the thermal effect labels of the currently executing test vector, the chip's RC thermal network model, and sparse observations from the chip's internal thermal diode sensors, to output a real-time two-dimensional thermal distribution map of the chip. Specifically:

[0035] First, based on the power time-varying waveforms in the thermal effect labels of all currently executed test vectors, the real-time power consumption of each functional module is obtained. The actual power consumption value is then input into a pre-established chip RC thermal network model to generate the prior two-dimensional thermal distribution of the entire chip.

[0036] The chip RC thermal network model is represented by a chip heat conduction model established by the finite element analysis method. It is used to divide the chip into several grid units, each of which is represented by a thermal resistance and a thermal capacity. The corresponding temperature distribution is obtained by solving the heat conduction equation.

[0037] The chip RC thermal network model is trained based on chip process parameters, layout, package heat dissipation coefficient, and environmental thermal boundary conditions. It traverses the chip's power consumption range under all operating conditions through finite element simulation, collects true global temperature data under different module power consumption combinations and different ambient temperatures, and constructs a model training dataset. With minimizing the mean square error between the simulated true temperature and the model's calculated temperature as the training objective, the thermal resistance, thermal capacity parameters of each grid element and the thermal coupling coefficient between elements are iteratively corrected.

[0038] Next, the readings of the thermal diode sensors distributed inside the chip are read to obtain sparse temperature observations.

[0039] Then, the prior heat map corresponding to the prior two-dimensional heat distribution is used as the predicted value of the system state, the reading of the thermal diode sensor is used as the observed value, and the Kalman filter algorithm is used to correct the prior heat map to output the real-time two-dimensional heat distribution map.

[0040] The specific implementation of the Kalman filter is as follows:

[0041] The system state vector is defined as the real-time temperature values ​​corresponding to all grid cells, forming a one-dimensional state matrix. , The vector represents the total number of discrete grid cells across the entire chip, with each element corresponding to the real-time temperature value of each grid cell.

[0042] The state transition matrix is ​​defined as follows: Square Array The matrix dimension corresponds one-to-one with the total number of grid cells. All elements of the matrix are calibrated by solving the transient heat conduction iterative equation based on the chip RC thermal network model. The diagonal elements of the matrix represent the temperature retention coefficient of a single grid cell, which is used to reflect the inherent decay characteristics of the cell temperature within a single iteration step. The off-diagonal elements represent the thermal coupling conduction coefficient between different grid cells, which is used to quantify the heat transfer, diffusion and interaction effects between adjacent grids.

[0043] The observation matrix is ​​defined as a two-dimensional matrix. ,in This represents the total number of on-chip thermal diode sensors. The total number of chip grid cells is represented by this matrix, which is a sparse mapping matrix. The row dimension of the matrix corresponds to each thermal sensor, and the column dimension corresponds to each grid cell. If the physical placement position of a sensor corresponds to a certain grid cell, the corresponding matrix element is assigned a value of 1, and the elements of other irrelevant grid cell positions are uniformly assigned a value of 0. Based on this matrix, a linear mapping between the sparse observation values ​​of the sensor and the true values ​​of the global grid temperature is realized.

[0044] The process noise covariance matrix is ​​fixed and calibrated based on the simulation error statistics during the model pre-training stage, and characterizes the uncertainty of the temperature prediction value of each grid cell; the measurement noise covariance matrix is ​​fixed based on the sensor factory calibration parameters and actual sampling error data, and thus characterizes the measurement noise error level of each sensor's real-time reading.

[0045] At each time step, based on the optimal state estimate and state transition matrix of the previous time step, the state estimate and covariance matrix of the current time step are predicted; the predicted state estimate is corrected based on the actual observations, and the covariance matrix is ​​updated synchronously. Through the iterative prediction-update process, the optimal temperature estimate is obtained.

[0046] An electromagnetic environment spectrum mask register is used to extract electromagnetic interference fingerprint tags from the electromagnetic interference fingerprints of all currently executing test vectors, and to synthesize the electromagnetic environment spectrum mask for the current chip test based on the electromagnetic interference fingerprint tags. Specifically:

[0047] When the system decides to include a test vector in the current execution batch, it first extracts the frequency band energy distribution from the electromagnetic interference fingerprint tag corresponding to that vector from the test vector attribute library. and compare it with the current electromagnetic environment spectrum mask. (f) Perform superposition to obtain the updated spectrum mask. Furthermore, when a test vector is completed, the corresponding frequency band energy distribution... From the current electromagnetic environment spectrum mask Subtract from the middle, thereby updating the electromagnetic environment spectrum mask again. .

[0048] Among them, the electromagnetic environment spectrum mask The initial value is 0, which characterizes the test environment as having no vector superposition interference and retaining only the basis environment noise; and throughout the entire test process, It will accumulate the frequency band energy distribution of all currently concurrently executing test vectors in real time. The electromagnetic interference spectrum in the data is collected to summarize the electromagnetic interference spectrum of all interference sources in the current real test scenario, so as to characterize the electromagnetic noise environment in which the chip is currently located.

[0049] The time budget monitoring submodule is used to maintain the remaining test time budget, specifically:

[0050] The remaining test time budget is expressed as the time interval from the current moment to the test deadline;

[0051] The time budget monitoring submodule is also used to monitor the current fault coverage and generate coverage gain per unit time;

[0052] The fault coverage rate is expressed as the ratio of the number of fault points covered by the executed test vectors to the total number of fault points;

[0053] The unit time coverage gain is expressed as the average increase in fault coverage per unit time within the most recent time window.

[0054] A multi-dimensional collaborative priority engine, connected to the test vector attribute library and the real-time state awareness module, is used to perform comprehensive priority analysis on the test vectors to be executed based on the static attribute labels and the global state data.

[0055] Specifically, the multi-dimensional collaborative priority engine includes at least a logical concurrency and resource arbitration submodule, a fault location gain evaluation submodule, a thermal safety constraint submodule, a fault causal chain triggering submodule, a portfolio time budgeting submodule, an electromagnetic compatibility avoidance submodule, and a scheduling mode controller;

[0056] The multi-dimensional collaborative priority engine adopts a three-level serial gated pipeline architecture. In this architecture, the test vector to be executed passes through the three pipelines sequentially. Each pipeline filters or scores the test vector, and only vectors that pass the previous pipeline can enter the next pipeline. Specifically:

[0057] The first-level pipeline is a physical feasibility fast rejection gating layer, which is executed in parallel by a logical concurrency and resource arbitration submodule and a thermal safety constraint submodule, outputting a logically conflict-free and thermally safe first candidate vector queue. .

[0058] The logical concurrency and resource arbitration submodule is used to determine whether there is a logical resource conflict between the test vector to be executed and the test vector that has been executed, and to perform priority arbitration on the conflicting vectors to determine the candidate vector queue that can be executed concurrently.

[0059] Meanwhile, the logical concurrency and resource arbitration submodule maintains a global resource lock register. This register uses a bitmask mechanism, where each bit corresponds to a physical resource. 1 indicates that the resource is occupied, and 0 indicates that the resource is idle.

[0060] For each vector to be executed, perform a bitwise AND operation between the resource mask corresponding to each physical resource in the bitmask of its logical resource requirement label and the current state of the global resource lock register:

[0061] If the result of the operation is 0, it means that all the resources required by the vector are idle and there is no resource conflict, so it can pass through the current pipeline.

[0062] If the result of the operation is not 0, it means that there is a resource conflict between the vector and the already executed vector, and priority arbitration is required. At this time, the priority arbitration mechanism is activated.

[0063] The priority arbitration mechanism is used to resolve the priority inversion problem when resource conflicts occur. Specifically:

[0064] When high priority vector The required physical resources are allocated to low-priority vectors. When occupied, the system will obtain Execution progress;

[0065] like If the execution progress is below the preset threshold, it indicates that the low-priority vector is in the initial stage of execution. At this time, the cost of preempting it is small, and the overhead of context switching is low, so resource preemption is possible. Therefore, it can be preempted and suspended. and allocate the released physical resources to .

[0066] like If the execution progress is not lower than the preset threshold, then... The priority has been temporarily raised to the same level as A consistent level ensures that execution is completed quickly to release occupied physical resources and avoid resource deadlock.

[0067] For example, suppose a high-priority vector Resources R1 and R2 are required, with a resource mask of 0b0011. The current state of the global resource lock register is 0b0010, indicating that resource R2 has been occupied by a low-priority vector. Occupied, assuming current If the execution progress is 20%, which is below the preset preemption threshold of 30%, the system will be suspended. and release resource R2 to , It can be executed immediately; if The execution progress is 40%, which is higher than the preset preemption threshold of 30%. At this point, the system will... The priority has been temporarily raised to the same level as The same level makes Execution can continue until it finishes and releases resource R2, then execution can continue. .

[0068] The thermal safety constraint submodule, based on the real-time two-dimensional thermal distribution map of the chip output by the real-time state perception module, simultaneously combines the thermal impact tags corresponding to the candidate test vectors to be executed to predict the expected peak temperature of the chip after the candidate test vectors are executed, and makes a thermal hazard judgment based on the expected peak temperature. Specifically:

[0069] The thermal safety constraint submodule first determines the current chip's real-time two-dimensional thermal distribution map. Based on the power time-varying waveform, hotspot coordinates, and thermal time constant in the thermal effect label of the candidate vector, predict the expected peak temperature of the chip after executing the vector. Specifically:

[0070] First, extract the real-time two-dimensional thermal distribution map of the current chip. Obtain the current base temperature at the hotspot coordinates corresponding to the candidate test vector. The substrate temperature is represented as the actual substrate temperature of the chip before it executes a new test vector.

[0071] Next, by combining the thermal impact label of the candidate policy vector, the corresponding peak power consumption is obtained. Equivalent thermal resistance Thermal time constant Three types of fixed thermal parameters.

[0072] Subsequently, based on the actual execution time of the test vector The dynamic temperature rise generated after the vector is executed is quantized by combining the chip transient temperature rise formula. The formula for the transient temperature rise of the chip can be expressed as:

[0073] ;

[0074] The physical meaning of the chip transient temperature rise formula is that the temperature rise in the chip's hot spot area increases exponentially with execution time; the longer the execution time, the closer the temperature rise is to the steady-state maximum temperature rise. .

[0075] Finally, the current base temperature With the dynamic temperature rise By superimposing the results, the expected peak temperature after executing the test vector is obtained. .

[0076] like Below the preset thermal safety threshold If so, the vector passes through the current pipeline stage;

[0077] like Not less than If so, the vector is marked as a thermal hazard vector and requires further processing.

[0078] For thermal hazard vectors, the thermal safety constraint submodule employs a two-level processing mechanism:

[0079] The first level is cold replacement lookup, which prioritizes querying the pre-built hot replacement vector lookup table, and filters out replacement vectors that cover the same or similar fault points and whose thermal power consumption meets the preset low power consumption conditions. If there is a replacement vector that meets the above conditions, the original thermal hazard vector is replaced by the replacement vector, and the replacement vector passes through this level pipeline.

[0080] The preset low-power conditions include at least the following:

[0081] The peak power consumption of the alternative vector must be lower than a preset threshold, such as 60% of the peak power consumption of the original thermal hazard vector.

[0082] The maximum temperature rise of the hotspot generated after the alternative vector is executed must be lower than the chip's preset thermal safety temperature rise margin, such as 3°C.

[0083] The fault coverage of the alternative vector shall not be lower than a preset threshold, such as not lower than 90% of the original thermal hazard vector.

[0084] The second level is virtual heat dissipation vector generation. If no suitable alternative vector exists, a sequence of virtual heat dissipation vectors is dynamically generated. Specifically:

[0085] First, locate the coordinates of the chip hotspot region that triggers the thermal hazard, and retrieve the chip thermal time constant for that region. Safe temperature threshold Simultaneously read the real-time temperature of the current hotspot. ,Will As an excess temperature difference.

[0086] Next, the minimum heat dissipation time is obtained by using the minimum heat dissipation time quantization function, combined with the thermal time constant and the over-temperature difference. The minimum heat dissipation time quantization function can be expressed as:

[0087] ;

[0088] in, The target cooling temperature is set with a preset safety margin to ensure that the hot spot temperature remains stable below the safe temperature threshold after heat dissipation is complete. .

[0089] Next, for the chip hotspot coordinate area that triggers thermal hazards, basic instructions such as all-zero shift, all-one latch, and empty timing jump are used to generate a minimum logic flip instruction sequence. The minimum logic flip instruction sequence is encapsulated into a virtual heat dissipation vector sequence and synchronously marked and bound to the corresponding hotspot module and the original thermal hazard vector identifier.

[0090] After the virtual heat dissipation vector sequence has been fully executed, the temperature of the chip hotspot area drops back to the safe range. The system automatically clears the current thermal hazard marker and sends the original thermal hazard test vector back into the first-stage pipeline to complete a new round of thermal safety prediction and feasibility assessment.

[0091] For example, suppose the real-time two-dimensional thermal distribution map of the current chip shows that the temperature of the central area of ​​the chip is 85°C, and the preset thermal safety threshold is 90°C. The thermal impact label of a certain candidate vector shows that after its execution, the temperature of the central area of ​​the chip will rise by 6°C to 91°C, which exceeds the thermal safety threshold. Therefore, it is marked as a thermal hazard vector.

[0092] The thermal safety constraint submodule first queries the thermal substitution vector lookup table and finds a substitution vector that covers the same fault point. After execution, it will only raise the temperature of the chip's central area by 3°C, reaching 88°C, which is below the thermal safety threshold. Therefore, the system replaces the original thermal hazard vector with this substitution vector, and the substitution vector passes through this stage pipeline.

[0093] If no such alternative vector exists, the system will generate a virtual heat dissipation vector sequence, which will be shifted to zero by the module in the central area of ​​the chip. After the virtual heat dissipation vector is executed, the temperature in the central area of ​​the chip will drop to 82°C. The original thermal hazard vector will be sent back to the first-stage pipeline for evaluation. At this time, the expected peak temperature after executing the vector is 88°C, which is lower than the thermal safety threshold. Only then can the vector pass through the pipeline.

[0094] The second-level pipeline is the electromagnetic compatibility (EMC) prediction gating layer, which is executed independently by the EMC avoidance submodule. This layer is used to process the first candidate vector queue output from the first-level pipeline. Perform a fast electromagnetic compatibility check and output the second candidate vector queue for electromagnetic compatibility. Specifically:

[0095] First, extract the emission spectrum of the mid-frequency energy distribution of the electromagnetic interference fingerprint tag from the candidate vectors. Compare the transmitted spectrum with the electromagnetic environment spectrum mask in the current electromagnetic environment spectrum mask register. Perform frequency band energy overlap integral calculation to obtain the electromagnetic conflict coefficient between the two. .

[0096] electromagnetic conflict coefficient The calculation formula can be expressed as:

[0097] ;

[0098] The integral range of the above formula is the preset frequency range of interest, and the conflict coefficient is... The larger the value, the more severe the conflict between the candidate test vector and the current electromagnetic environment.

[0099] It should be noted that since electromagnetic interference propagates mainly through two methods, spatial coupling and power conduction, spatial coupling is likely to occur between physically adjacent modules, while power conduction interference is likely to occur between modules sharing the same power network. Therefore, electromagnetic conflict determination is necessary.

[0100] If the electromagnetic conflict coefficient If the preset electromagnetic compatibility threshold is exceeded, it is further determined whether the circuit module corresponding to the candidate vector and the circuit module of the currently executing vector have a physical adjacency relationship or share the same power network. If any of the above conditions are met, it is determined that there is an electromagnetic conflict.

[0101] If an electromagnetic conflict is confirmed, the candidate test vector is prohibited from being executed concurrently with the conflict source vector in the current test batch, and its execution is delayed to the next batch. Alternatively, the pre-built electromagnetic compatibility alternative vector library can be consulted to select an adaptation vector that does not meet the above electromagnetic conflict conditions for replacement.

[0102] If the conflict coefficient does not exceed the preset electromagnetic compatibility threshold, or if there is no electromagnetic conflict, then a second candidate vector queue is generated based on the candidate vectors in the first candidate vector queue where there is no electromagnetic conflict.

[0103] For example, suppose the electromagnetic conflict coefficient of a candidate test vector is... The conflict coefficient was 0.8, exceeding the preset threshold of 0.7. Further analysis revealed that the circuit module corresponding to this candidate test vector was physically adjacent to the circuit module corresponding to a currently executing test vector, indicating a possible spatial coupling. Therefore, the system prohibited the candidate test vector from execution in the current batch and postponed it to the next batch. When the candidate vector was executed in the next batch, the conflict coefficient was recalculated. The value is 0.3, which is below the preset threshold, so it can pass through this level of pipeline.

[0104] The third-level pipeline, executed in parallel by the fault location gain evaluation submodule, the fault causal chain triggering submodule, and the portfolio time budgeting submodule, serves as the second candidate vector queue for the output of the second-level pipeline. Each vector in the algorithm generates a corresponding performance increment value and diagnostic priority factor, specifically:

[0105] The fault location gain evaluation submodule is used to update the candidate fault set based on the newly returned test results, obtain the expected conditional information gain of each test vector to be executed on reducing the size of the candidate fault set, and use the expected conditional information gain as a diagnostic priority factor. The candidate fault set is represented as a probability vector to maintain the current probability of all known physical defects. The initial value is the prior yield distribution of each fault.

[0106] The specific working process of the fault location gain evaluation submodule consists of the following three steps:

[0107] The first step is to update the candidate fault set. Whenever a new test result is returned, the posterior probability of each fault in the candidate fault set is updated using Bayes' theorem based on the pass / fail status of the test vector. Specifically:

[0108] If the test vector execution fails, the fault posterior probability... The following proportional relationship is satisfied:

[0109] ;

[0110] in, For the current test vector For target fault The inherent detection probability is a static, inherent parameter that binds the test vector to the corresponding fault. It has no real-time dynamic fluctuations and its value is set by domain experts through simulation or analysis of historical data.

[0111] If the test vector execution passes, the fault posterior probability is... The following proportional relationship is satisfied:

[0112] .

[0113] After the update is completed, the probability of all faults is normalized, and faults with a probability lower than a preset threshold are removed from the candidate fault set.

[0114] The second step is to process each test vector to be executed. Obtain the corresponding fault location gain based on the location gain function. The positioning gain function can be expressed as:

[0115] ;

[0116] in Represented as the entropy of the current candidate fault set;

[0117] Represented as the test vector to be executed The expected conditional entropy.

[0118] The fault location gain This is used to characterize the degree to which the uncertainty of the candidate fault set is reduced after executing the test vector. The greater the gain, the greater the contribution of the vector to fault localization.

[0119] The third step is to normalize the fault location gain of all test vectors to be executed to [0,1] using maximum value normalization. This normalized value is the diagnostic priority factor. ;

[0120] Right now ;

[0121] in, The maximum fault location gain among all vectors to be executed.

[0122] The fault causal chain triggering submodule is used to automatically generate an indivisible set of atomic vectors containing fast verification vectors from all downstream modules when a new root cause fault is detected, and to handle the case of missing follow-up vectors. Specifically:

[0123] First, the fault causal chain triggering submodule starts with the newly detected root cause fault, performs a breadth-first search of the fault causal relationship graph corresponding to the fault causal relationship label, collects the fast verification vectors of all reachable downstream modules, packages them into an indivisible atomic vector group, and assigns a confidence label to each edge. The propagation confidence contained in the confidence label is a static parameter value pre-set by domain experts based on simulation or analysis of historical data.

[0124] The indivisible atomic vector group is defined as a group in which all vectors must be executed consecutively and cannot be interrupted by other vectors.

[0125] If a downstream module does not have a dedicated verification vector, a supplementary scheduling will be automatically triggered, and the module's general functional test vector set will be included as a candidate. The diagnostic report will then indicate that "the conclusions in this part are based on general vectors and have limited confidence."

[0126] Next, based on all the currently selected reachable downstream failed nodes, propagation edges, and corresponding propagation confidence scores, a local causal subgraph to be pursued is constructed, and the total number of remaining downstream nodes that have not been verified within the subgraph is counted. ;

[0127] Get the current test vector to be executed In the local causal subgraph, the number of unverified downstream fault nodes that can be independently verified and effectively investigated is... ;

[0128] Among them, unverified downstream fault nodes are downstream failure nodes whose status is questionable and have not yet been verified by the system through any test vector. Nodes that have been verified and whose failure possibility has been ruled out do not participate in the traversal matching.

[0129] The specific judgment rule is as follows: if the test vector If the activation logic, scanning observation points, and IO test ports can completely cover the circuit functional range corresponding to a certain downstream fault node, and the inherent detection probability of the vector corresponding to the fault node is not 0, then it proves that the vector can independently activate the fault, capture the fault abnormal output, and complete the effective fault investigation, thereby determining that the node is a valid hit node.

[0130] After traversing all unverified downstream nodes, the system summarizes the total number of nodes that meet the above criteria, thereby obtaining the number of unverified downstream faulty nodes that can be effectively investigated. .

[0131] Next, the propagation confidence of causal edges within the local causal subgraph is combined, and the causal gain is obtained based on the causal tracing gain function. The causal tracking gain function can be expressed as:

[0132] ;

[0133] in, This represents the total number of nodes to be investigated in the current local causal subgraph.

[0134] The portfolio time budget submodule is used to model the remaining test time budget as investment principal and the test vectors to be executed as investment targets with expected returns and risk attributes, thereby generating a dynamic investment efficiency score for each test vector to reflect its investment efficiency.

[0135] The portfolio time budgeting submodule defines the expected return for each vector. ,risk and cost In the chip testing scenario, the expected return corresponds to the historical fault detection rate of the test vector, the risk corresponds to the standard deviation of the test vector execution time, and the cost corresponds to the average execution time of the test vector.

[0136] The dynamic investment efficiency score corresponding to each test vector is obtained based on the investment efficiency quantification function. The investment efficiency quantification function can be expressed as:

[0137] ;

[0138] in, The risk-free reward is the reward for executing an empty vector that does not contain any test content; it is usually set to 0.

[0139] The risk preference coefficient is forcibly set by the scheduling mode controller.

[0140] Detect modality, The assigned value approaches 0, with a default value of 0.01. Under this mode, any risk value satisfies... This means encouraging the system to select high-risk, high-efficiency test vectors that offer short-term, high-return, and high-gain benefits, sacrificing some execution stability to maximize test throughput efficiency, thereby enabling rapid screening of faults.

[0141] Diagnostic modality, The assignment is set to neutral, with a default value of 0.5. In this mode, the amplification and suppression effects of risk are balanced. Risk parameters, expected return parameters, and cost parameters participate in the quantification of investment efficiency simultaneously. It neither blindly pursues high gains nor excessively avoids small fluctuations, and takes into account the failure detection reward and execution stability of the vector, thereby ensuring the accuracy and reliability of failure location.

[0142] Minimum guarantee mode, The assigned value is too high; the default value is 1.0. In this modality, the risk... The amplification penalty effect is the strongest, the denominator of high volatility and high risk vectors increases sharply, the dynamic investment efficiency score is greatly reduced, thus encouraging the system to prioritize conservative vectors with stable execution, steady coverage improvement and extremely low risk.

[0143] The higher the dynamic investment efficiency score, the higher the investment efficiency of the test vector, and the better it matches the testing requirements of the corresponding modality.

[0144] The scheduling mode controller is used to arbitrate multi-dimensional target conflicts based on the global state data. The control system is in only one dominant mode at any given time and outputs the corresponding mode weight vector. The dominant mode includes at least a detection mode, a diagnostic mode, and a backup mode. Specifically:

[0145] The detection mode is the system's default initial mode, which is activated when the real-time status perception module does not detect any chip faults. The goal of the detection mode is to detect as many faulty chips as possible in the shortest possible time.

[0146] In the detection mode, the system takes the portfolio time budget submodule as the lead, and its weight is set to the highest value. The weights of the fault location gain evaluation submodule and the fault causal chain triggering submodule in the multi-dimensional collaborative priority engine are downgraded, and the downgraded weights are all lower than the preset ratio of the portfolio time budget submodule weight.

[0147] For example, in the detection mode, the weight of the portfolio time budgeting submodule is set to 1.0, and the weights of the fault location gain assessment submodule and the fault causal chain triggering submodule are set to 0.2. In this case, the system's scheduling decision is primarily determined by the output of the portfolio time budgeting submodule, and based on the risk preference coefficient... Prioritize and execute high-risk test vectors that are short-term, high-return, and high-gain to quickly screen out faulty chips.

[0148] The diagnostic mode is activated when the real-time status perception module detects at least one chip fault and the remaining test time reported by the time budget monitoring submodule is higher than a preset sufficient threshold. The goal of the diagnostic mode is to accurately diagnose the root cause of the fault and the scope of its impact.

[0149] In diagnostic mode, the system is dominated by the fault location gain evaluation submodule and the fault causal chain triggering submodule, with their weights set to the highest and equal. The weight of the portfolio time budgeting submodule is downgraded. In this mode, the system prioritizes fault location gain. Optimal test vectors and causal gain The optimal set of atomic vectors.

[0150] For example, in the diagnostic mode, the weights of the fault location gain assessment submodule and the fault causal chain triggering submodule are set to 1.0, and the weight of the portfolio time budgeting submodule is set to 0.5.

[0151] The minimum guarantee mode is activated when the remaining test time reported by the time budget monitoring submodule is lower than a preset sufficient threshold. The goal of the minimum guarantee mode is to achieve the minimum deliverable coverage before the time limit, thus ensuring the validity of the test results.

[0152] In the guaranteed return mode, the system is dominated by the portfolio time budget submodule, whose weight is set to the maximum value and an extremely conservative strategy is enforced, i.e., the corresponding risk preference coefficient. The default values ​​are set, and the weights of the fault location gain evaluation submodule and the fault causal chain triggering submodule are reduced to the minimum, such as 0.01, which is equivalent to a suspended state.

[0153] For example, in the guaranteed return mode, the weight of the portfolio time budget submodule is set to 1.0, and the risk preference coefficient is... When the weight is forcibly set to 1.0, the system will prioritize test vectors with short execution time and high stability. The weights of the fault location gain evaluation submodule and the fault causal chain triggering submodule are set to 0.01, which has almost no impact on the scheduling decision. The test ends when the test coverage reaches the minimum deliverable coverage or the test time is exhausted.

[0154] The scheduling decision module, connected to the multi-dimensional collaborative priority engine, is used to generate a test vector scheduling scheme for controlling the execution of the automated test equipment (ATE) based on the results of the comprehensive priority analysis.

[0155] The scheduling decision module, based on a preset comprehensive priority function, synchronously combines the outputs of each sub-module within the multi-dimensional collaborative priority engine to generate a corresponding comprehensive priority for each candidate test vector to be executed. The preset comprehensive priority function can be expressed as:

[0156] ;

[0157] in, This is the overall priority value.

[0158] The base priority score is a preset value. The value of this parameter is preset based on the number and importance of the fault points covered by the test vector. The more fault points covered and the more important they are, the higher the base priority score will be. For example, the base priority score of a vector that covers critical path faults is higher than that of a vector that covers non-critical path faults.

[0159] The efficiency increment is the weighted sum of causal gain and dynamic investment efficiency.

[0160] Right now ;

[0161] in, and These are the preset weights for the corresponding items, and the preset weight values ​​are different for each main mode. Specifically:

[0162] In detecting modes, and The default values ​​are 0.2 and 1.0 respectively, thus ensuring that in this mode, the focus is on testing efficiency and fault detection speed;

[0163] In diagnostic modality, and The default values ​​are 1.0 and 0.5 respectively, thus ensuring that in this mode, the focus is on fault tracing and causal link completion, with a balance and bias towards diagnostic capabilities;

[0164] In the guaranteed mode and The default values ​​are 0.01 and 1.0 respectively, thus ensuring that in this modality, the focus is on coverage as a safety net for delivery;

[0165] It should be noted that, and The default values ​​can be set or adjusted by domain experts based on historical data. The above default values ​​are the values ​​under ideal conditions, and the specific values ​​need to be set according to actual conditions.

[0166] This is the modal weight, which is set to 0 in the detection mode and the safety mode, and to 1 in the diagnostic mode.

[0167] For test vectors Diagnostic priority factors.

[0168] and These are the thermal safety factor and the electromagnetic compatibility factor, respectively, whose values ​​are determined by the outputs of the first and second stage pipelines. Specifically:

[0169] For test vectors that pass the first stage pipeline The value is set to 1.0. Similarly, for test vectors that pass the second-stage pipeline, The value is set to 1.0;

[0170] For vectors that do not pass through, or It is set to 0, which makes the comprehensive priority of the test vector extremely low, so that it will not be selected into the execution batch.

[0171] Finally, all candidate test vectors to be executed are arranged in descending order according to the comprehensive priority, and a test vector scheduling scheme for controlling the execution of the automated test equipment (ATE) is selected and generated in sequence.

[0172] This invention also provides an electronic device, comprising:

[0173] At least one processor; and at least one memory communicatively connected to the processor; wherein the memory stores instructions executable by at least one processor, the instructions being executed by at least one processor to enable at least one processor to perform the method proposed in Embodiment 1 of the present invention.

[0174] The following is a detailed introduction to the various components of the electronic device:

[0175] In this context, the processor is the control center of the electronic device. It can be a single processor or a collective term for multiple processing elements. For example, a processor can be one or more central processing units (CPUs), an application-specific integrated circuit (ASIC), or one or more integrated circuits configured to implement Embodiment 1 of this invention, such as one or more digital signal processors (DSPs) or one or more field-programmable gate arrays (FPGAs).

[0176] The processor can perform various functions of an electronic device by running or executing software programs stored in memory and by calling data stored in memory.

[0177] The memory is used to store the software program that executes the solution of the present invention, and the execution is controlled by the processor. For specific implementation methods, please refer to the above method embodiments, which will not be repeated here.

[0178] The memory can be a real-only memory (ROM) or other type of static storage device capable of storing static information and instructions, a random access memory (RAM) or other type of dynamic storage device capable of storing information and instructions, or an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only (CD-ROM), or other optical disc storage, optical disc storage (including compressed optical discs, laser discs, optical discs, digital universal optical discs, Blu-ray discs, etc.), magnetic disk storage media, or other magnetic storage devices, or any other medium capable of carrying or storing desired program code in the form of instructions or data structures and accessible by a computer, but is not limited thereto. The memory can be integrated with the processor or exist independently and coupled to the processor through an interface circuit of an electronic device; this embodiment of the invention does not specifically limit this.

[0179] The above embodiments can be implemented, in whole or in part, by software, hardware (such as circuits), firmware, or any other combination thereof. When implemented using software, the above embodiments can be implemented, in whole or in part, as a computer program product. The computer program product includes one or more computer instructions or computer programs. When the computer instructions or computer programs are loaded or executed on a computer, all or part of the processes or functions described in the embodiments of the present invention are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via limited means (e.g., infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more sets of available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium. A semiconductor medium can be a solid-state drive.

[0180] It should be understood that the term "and / or" in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three cases: A alone, A and B simultaneously, and B alone. A and B can be singular or plural. Additionally, the character " / " in this article generally indicates an "or" relationship between the preceding and following related objects, but it can also represent an "and / or" relationship. Please refer to the context for a more accurate understanding.

[0181] It should be understood that, in the embodiments of the present invention, the order of the above-mentioned process numbers does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0182] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. A dynamic priority allocation system for chip test vectors, characterized in that, include: A test vector attribute library is used to store the static attribute tag set and fault causal relationship tag for each test vector. The static attribute tag set includes at least logical resource requirement tag, defect association tag, thermal impact tag, and electromagnetic interference fingerprint tag. The real-time status awareness module is used to collect and update the chip's global status data in real time during test execution. The global status data includes at least the result sequence of executed test vectors, the chip's real-time two-dimensional thermal distribution map, power supply transient signal characteristics, and the remaining test time budget. A multi-dimensional collaborative priority engine, connected to the test vector attribute library and the real-time state awareness module, is used to perform comprehensive priority analysis on the test vectors to be executed based on the static attribute tags and the global state data. The multi-dimensional collaborative priority engine includes at least a logical concurrency and resource arbitration submodule, a fault location gain evaluation submodule, a thermal safety constraint submodule, a fault causal chain triggering submodule, a portfolio time budgeting submodule, an electromagnetic compatibility avoidance submodule, and a scheduling mode controller. The scheduling decision module, connected to the multi-dimensional collaborative priority engine, is used to generate a test vector scheduling scheme for controlling the execution of the automated test equipment (ATE) based on the results of the comprehensive priority analysis.

2. The chip test vector priority dynamic allocation system according to claim 1, characterized in that, Test vector attribute library, including: The test vector attribute library is built offline in the form of a graph structure and stores the static attribute tag set and fault causal relationship tags for each test vector. The logical resource requirement label is represented by a bitmask, with each bit corresponding to a physical resource; The defect association tags store the causal relationship and detection probability between physical defects and observable circuit nodes in the form of a Bayesian network. The thermally affected label includes at least the power time-varying waveform, hotspot coordinates, and thermal time constant; The electromagnetic interference fingerprint tag includes at least frequency band energy distribution and noise tolerance; The fault causality labels are represented as a directed acyclic graph with propagation confidence, used to label all root cause failure modes.

3. The chip test vector priority dynamic allocation system according to claim 1, characterized in that, The real-time status awareness module includes: The logic state monitoring submodule is used to record the complete result sequence of executed test vectors; The real-time heat map generation submodule uses the Kalman filter algorithm to combine the thermal effect label of the currently executed test vector, the chip RC thermal network model, and the sparse observations of the chip's internal thermal diode sensor to output a real-time two-dimensional thermal distribution map of the chip. An electromagnetic environment spectrum mask register is used to extract electromagnetic interference fingerprint tags from the electromagnetic interference fingerprints of all currently executing test vectors, and synthesize the electromagnetic environment spectrum mask for the current chip test based on the electromagnetic interference fingerprint tags. The time budget monitoring submodule is used to maintain the remaining test time budget.

4. The chip test vector priority dynamic allocation system according to claim 1, characterized in that, The multi-dimensional collaborative priority engine adopts a three-level serial gated pipeline architecture, which includes: The first level is executed in parallel by the logical concurrency and resource arbitration submodule and the thermal safety constraint submodule, and outputs the first candidate vector queue. The second stage is executed separately by the electromagnetic compatibility avoidance submodule, which performs a fast electromagnetic compatibility check on the first candidate vector output from the first stage and outputs a queue of second candidate vectors. The third level, executed in parallel by the fault location gain evaluation submodule, the fault causal chain triggering submodule, and the portfolio time budgeting submodule, is used to generate performance increment values ​​and diagnostic priority factors for each second candidate vector output from the second level.

5. A chip test vector priority dynamic allocation system according to claim 4, characterized in that, Level 1 includes: The logical concurrency and resource arbitration submodule determines whether there is a physical resource conflict between the test vector to be executed and the already executed test vector by performing a bitwise AND operation between the logical resource requirement mask of the test vector to be executed and the current state of global resources. When the resources required by a high-priority test vector are occupied by a low-priority test vector, if the execution progress of the low-priority test vector is less than a preset threshold, the high-priority test vector will preempt and suspend the low-priority test vector; otherwise, the priority of the low-priority test vector will be temporarily raised to the level of the high-priority test vector. The thermal safety constraint submodule predicts the expected peak temperature of the chip after the candidate test vector is executed, based on the real-time two-dimensional thermal distribution map of the chip output by the real-time state perception module and combined with the thermal impact label of the candidate test vector to be executed. If the expected peak temperature exceeds the preset thermal safety threshold, the candidate test vector is marked as a thermal hazard vector. For thermal hazard vectors, a pre-built thermal alternative vector lookup table is queried first to filter out alternative vectors that cover the same or similar fault points and whose thermal power consumption meets the preset low power consumption conditions. If an alternative vector exists, the corresponding thermal hazard vector is directly replaced. If no suitable alternative vector is found, a virtual heat dissipation vector sequence is generated based on preset rules. The alternative vectors and the virtual heat dissipation vector sequence together constitute the first candidate vector queue.

6. The chip test vector priority dynamic allocation system according to claim 4, characterized in that, Level Two includes: The electromagnetic compatibility avoidance submodule extracts the emission spectrum of candidate vectors in the first candidate vector queue and, in combination with the current electromagnetic environment spectrum mask, obtains the electromagnetic conflict coefficient. If the conflict coefficient exceeds the preset electromagnetic compatibility threshold, it is further determined whether there is an electromagnetic conflict. The electromagnetic conflict is defined as the circuit module corresponding to the candidate vector being physically adjacent to or sharing the same power network with the circuit module currently executing the test vector. If an electromagnetic conflict exists, the candidate vector is prohibited from being executed concurrently with the test vector corresponding to the conflict source in the current test batch; If the conflict coefficient does not exceed the preset electromagnetic compatibility threshold, or if there is no electromagnetic conflict, then a second candidate vector queue is generated based on the candidate vectors in the first candidate vector queue where there is no electromagnetic conflict.

7. A chip test vector priority dynamic allocation system according to claim 4, characterized in that, Level 3 includes: The fault location gain evaluation submodule generates a corresponding diagnostic priority factor for each vector to be executed in the second candidate vector queue based on the posterior probability of each fault in the candidate fault set to be maintained. The fault causal chain triggering submodule detects whether a root cause fault has occurred in real time. When a root cause fault is detected, it takes the root cause fault as the starting point, uses breadth-first search to traverse the fault causal relationship labels, and generates an atomic vector group containing the fast verification vectors of all downstream modules. The atomic vector group is used to diagnose the root cause and scope of influence of the root cause fault. The portfolio time budgeting submodule generates a corresponding dynamic investment efficiency score for each vector to be executed based on the historical performance of each vector to be executed in the second candidate vector queue.

8. A chip test vector priority dynamic allocation system according to claim 1, characterized in that, Scheduling mode controller, including: The scheduling mode controller is used to arbitrate multi-dimensional target conflicts based on the global state data. The control system is in only one dominant mode at any given time and outputs the corresponding mode weight vector. The main mode includes at least a detection mode, a diagnostic mode, and a backup mode.

9. A chip test vector priority dynamic allocation system according to claim 1, characterized in that, The scheduling decision module includes: The scheduling decision module generates a corresponding comprehensive priority for each candidate test vector to be executed based on a preset comprehensive priority function and in conjunction with the outputs of each sub-module in the multi-dimensional collaborative priority engine. All candidate test vectors to be executed are arranged in descending order according to the comprehensive priority, and a test vector scheduling scheme for controlling the execution of the automated test equipment (ATE) is selected and generated in sequence.

10. A chip test vector priority dynamic allocation system according to claim 9, characterized in that, Synthetic priority functions include: ； in, This is the overall priority value; The preset base priority score; For increased efficiency; Modal weights; As a diagnostic priority factor; Thermal safety factor; This is the electromagnetic compatibility factor.

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