Method for verifying yield design intent file and storage medium

Abstract

The present application relates to the technical field of chip design, in particular to a verification method and storage medium based on yield design intent file, which obtains a key module list, a non-key module list, a high-level clamp mapping table and a low-level clamp mapping table with fixed format by analyzing the yield design intent file; queries the high and low level clamp mapping table of each non-key module based on each non-key module in the non-key module list; generates the instantiation instruction of the high-level isolation unit or the instantiation instruction of the low-level isolation unit of each signal in combination with the non-key module list and the key module list for each signal in the high and low level clamp mapping table, and obtains the updated chip design; and performs simulation verification on the updated chip design, which achieves the purpose of standardization of the yield design intent file generating fixed format list and can be parsed and integrated into the automatic design and verification process.

Description

Technical Field

[0001] This invention relates to the field of chip design technology, and in particular to a verification method and storage medium based on yield design intent files. Background Technology

[0002] As semiconductor process nodes continue to evolve towards 5nm and below, chip integration and performance have significantly improved, but manufacturing complexity and cost have also risen sharply. In advanced processes, process fluctuations, random defects, and physical effects have an increasingly significant impact on circuit functionality and reliability, making chip yield a key factor restricting mass production feasibility. Yield not only directly determines the number of chips available for sale but also profoundly affects the unit cost and market competitiveness of a product. Therefore, embedding yield-oriented design intent in the early stages of chip design has become an indispensable design strategy under advanced nodes. Currently, the industry generally relies on documents written in natural language, such as Word text, flowcharts, or diagrams, to guide yield design and verification. However, such documents, based on natural language descriptions, lack formal semantics and unified expression standards, making them difficult to parse and process by EDA tools and unable to be integrated into automated design and verification processes. More seriously, the inherent ambiguity and polysemy of natural language can easily lead to misunderstandings between design engineers and verification engineers regarding the same intent, thereby inducing systemic defects in the manufacturing stage and ultimately causing yield losses. Therefore, there is an urgent need for a verification method based on standardized yield design intent documents that can be parsed and processed by EDA tools. Summary of the Invention

[0003] To address the aforementioned technical problems, the present invention adopts the following technical solution: a verification method based on a yield design intent file, comprising: parsing the yield design intent file to obtain a critical module list, a non-critical module list, a high-level clamping mapping table, and a low-level clamping mapping table with fixed formats, wherein the critical modules are modules that must work, and the non-critical modules are modules that can fail; the high-level clamping mapping table includes a first enable signal for clamping a high level when isolating a non-critical module and a list of first signals to be clamped to a high level; the low-level clamping mapping table includes a second enable signal for clamping a low level when isolating a non-critical module and a list of second signals to be clamped to a low level. Based on each non-critical module in the non-critical module list, the high-level clamping mapping table and the low-level clamping mapping table for each non-critical module are queried. For each signal in the high-level clamping mapping table and the low-level clamping mapping table, an instantiation instruction for a high-level isolation unit or an instantiation instruction for a low-level isolation unit is generated for each signal in combination with the non-critical module list and the critical module list, respectively, to obtain an updated chip design; and the updated chip design is simulated and verified.

[0004] Furthermore, the present invention also provides a non-transitory computer-readable storage medium storing at least one instruction or at least one program segment, wherein the at least one instruction or the at least one program segment is loaded and executed by a processor to implement the above-described method.

[0005] The present invention has at least the following beneficial effects: This invention provides a verification method based on yield design intent documents. It generates different lists in a fixed format from the yield design intent document, achieving standardization and eliminating the need for inefficient, error-prone, and non-reusable natural language-based intent documents, thus improving the efficiency of yield design and verification. It only needs to ensure the correctness of the yield design intent document to avoid oversights caused by manually writing design and verification code. The yield design intent document can be parsed by EDA tools and integrated into automated design and verification processes. Furthermore, it can be reused multiple times in the R&D process by steps such as front-end design and front-end verification, exhibiting good reusability. Attached Figure Description

[0006] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0007] Figure 1 A flowchart of a verification method based on a yield design intent file provided in an embodiment of the present invention; Figure 2 A schematic diagram illustrating the relationship between non-critical modules and critical modules in the original design provided for embodiments of the present invention; Figure 3 In order to be in Figure 2 The circuit diagram after the insertion of the isolation unit. Detailed Implementation

[0008] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0009] Unless otherwise defined, all technical and scientific terms used in the embodiments of this invention have the same meaning as commonly understood by those skilled in the art.

[0010] Please see Figure 1 It demonstrates a verification method based on chip yield, including: S100, parse the yield design intent file to obtain a critical module list, a non-critical module list, a high-level clamping mapping table, and a low-level clamping mapping table with a fixed format. The critical modules are modules that must work, and the non-critical modules are modules that can fail. The high-level clamping mapping table includes a first enable signal for clamping high level when isolating non-critical modules and a list of first signals to be clamped to high level. The low-level clamping mapping table includes a second enable signal for clamping low level when isolating non-critical modules and a list of second signals to be clamped to low level.

[0011] Critical modules are those that must continue to function normally during system operation, even if other non-critical modules fail. Non-critical modules are those that are allowed to fail due to faults during system operation, provided that their failure does not affect the functionality of critical modules. To improve manufacturing yield, non-critical modules are allowed to pass testing even with the possibility of failure.

[0012] In this context, the isolation status indicates that the corresponding non-critical module has been isolated, or in other words, disabled, meaning that the original output of the non-critical module is no longer valid. To ensure the normal operation of the critical module connected to the output of the non-critical module, the signal input from the non-critical module to the critical module needs to be forcibly set to the correct value through the isolation unit.

[0013] Clamping means forcing a signal to a preset logic level, such as high or low, to ensure that non-critical modules can still ensure that the signals input to critical modules are the correct values ​​even in isolation.

[0014] The enable signal is used to control whether the signal is clamped. For example, when the enable signal is valid, the first signal is clamped to a high level; when the enable signal is invalid, the first signal is output normally.

[0015] The basis for clamping the signals of non-critical modules to high or low level is to ensure that it does not affect the normal operation of the critical modules connected to them.

[0016] It should be noted that not all signals in non-critical modules need to be clamped to high or low levels; only signals that affect critical modules need to be clamped to high or low levels. Therefore, the sum of the first and second signal lists for the same non-critical module is less than or equal to the sum of all signals in the non-critical module itself.

[0017] By standardizing the list classification of critical and non-critical modules through four fixed formats in the yield design intent document, and using two types of mapping tables for each non-critical module, the standard of expression is unified. At the same time, it can be parsed by EDA tools, eliminating the inefficient, error-prone and non-reusable intent documents described by natural language, eliminating the comprehension bias of natural language, and improving the efficiency of yield design and verification.

[0018] The process of obtaining the yield design intent file involves two main steps. The first step is to list two types of mapping tables: critical modules, non-critical modules, and each non-critical module. The second step is to obtain the yield design intent template file. Then, based on the information listed in the first step, the yield design intent template file is populated, thereby generating the yield design intent file.

[0019] In one implementation, the step of generating the parsing yield design intent file includes: S110, Obtain the design object input by the user. The design object includes the critical module identifier list, the non-critical module identifier list, the first signal to be clamped to a high level and the second signal to be clamped to a low level when each non-critical module fails, which is output to the critical module.

[0020] Here, the critical module identifier, non-critical module identifier, first signal, and second signal are all full path names. That is, each name includes its hierarchical structure in the chip design. Taking the name of the first signal as an example, the name of the first signal is Top_A.Module_A1.singnal_a1, where singnal_a1 is the independent name of the current signal, Module_A1 is the name of the module to which singnal_a1 belongs, and Top_A is the name of the top-level design to which Module_A1 belongs.

[0021] S120, for each non-critical module, obtain a first enable signal for clamping to a high level and a second enable signal for clamping to a low level, and bind the first enable signal to the first signal list of the current non-critical module as a high-level clamping mapping table, and bind the second enable signal to the second signal list of the current non-critical module as a low-level clamping mapping table. It should be noted that a high-level clamping map may include one or more first enable signals. Similarly, a low-level clamping map may include one or more second enable signals.

[0022] S130, Obtain the yield design intent template file and identify the instructions and placeholders in the yield design intent template file.

[0023] The yield design intent template file includes: first instruction, second instruction, third instruction, and fourth instruction.

[0024] Furthermore, the first instruction is configured to: define a list of key modules, the list of key modules being defined by key module placeholders; wherein, the key module placeholders are configured to receive at least one key module identifier.

[0025] Placeholders are predefined in the yield design intent template file and have specific positions to indicate which parameters the user needs to fill in, thus enabling template instantiation. Corresponding placeholders are used to receive user-inputted module or signal names. During design intent template parsing, these placeholders are replaced with the user-inputted module or signal names, generating executable code.

[0026] In one implementation, the format of the first instruction includes a command identifier for creating a domain, a module type identifier, a module definition keyword, and a module list placeholder. The command identifier for creating a domain in the EDA tool is "create_domain", which indicates the creation of a domain containing critical modules. The module type identifier indicates the critical modules that must function and can be represented by "must". The module definition keyword is "blocks", which specifies the list of critical modules included in the current domain. The module list placeholder is represented by angle brackets "<>" and is used to receive at least one critical module from user input. Therefore, the format of the first instruction can be represented as "create_domain -must -blocks<>".

[0027] Furthermore, the second instruction is configured to: define a list of non-critical modules, the list of non-critical modules being defined by non-critical module placeholders; wherein, the non-critical module placeholders are configured to receive at least one non-critical module identifier.

[0028] In one implementation, the format of the second instruction is similar to that of the first instruction, differing only in the module type identifier. The format of the second instruction includes a command identifier for creating the domain, a module type identifier, a module definition keyword, and a module list placeholder. The module type identifier is used to indicate non-critical modules that can be disabled and can be represented by "option". As an example, the format of the second instruction could be represented as "create_domain-option-blocks<>".

[0029] Furthermore, the third instruction is configured to: define a high-level clamping mapping table, wherein the high-level clamping mapping table is defined by a first enable placeholder and a first signal placeholder to be clamped to a high level; wherein the first enable placeholder is configured to receive at least one first isolation enable signal; and the first signal placeholder is configured to receive at least one first signal.

[0030] In one implementation, the format of the third instruction includes a create isolation command identifier, a clamp-high indicator, an isolation enable keyword, a first enable placeholder, a first signal keyword, and a first signal placeholder. The create isolation command identifier in the EDA tool is "create_iso", used to indicate the creation of an isolation cell. The clamp-high indicator, used to instruct the current isolation cell to clamp the first signal high, can be represented by "Hi". The isolation enable signal is "ISO", used to introduce a list of isolation enable signals. The first enable placeholder, also represented by angle brackets "<>", is used to receive at least one isolation enable signal input by the user. The first signal keyword, used to introduce a list of first signals to be clamped, can be represented by "signals". The first signal placeholder, also represented by angle brackets "<>", is used to receive at least one first signal input by the user. As an example, the format of the third instruction can be represented as "create_iso-Hi-ISO<>-signals<>".

[0031] Furthermore, the fourth instruction is configured to: define a low-level clamping map, the low-level clamping map being defined by a second enable placeholder and a second signal placeholder to be clamped to a low level; wherein, the second enable placeholder is configured to receive at least one first enable signal; and the second signal placeholder is configured to receive at least one second signal.

[0032] The fourth instruction is similar to the third instruction, differing only in the high and low voltage levels. The format of the fourth instruction includes a create isolation command identifier, a clamp-low indicator, an isolation enable keyword, a second enable placeholder, a second signal keyword, and a second signal placeholder. As an example, the format of the fourth instruction can be represented as "create_iso-Lo-ISOn<>-signals<>".

[0033] It should be noted that by defining a fixed-format yield design intent template file, user-provided lists are automatically populated into the template using placeholders, generating a standardized executable configuration file. This ensures that all list creation operations are forced to use the predefined fixed format without increasing the complexity of user operations, thus standardizing list creation and effectively preventing configuration inconsistencies caused by missing parameters or format errors. Simultaneously, it provides a structured and verifiable execution foundation for verification.

[0034] S140, replace the corresponding placeholders in the yield design intent template file with the key module identifier list, non-key module identifier list, first enable signal and its first signal list in each non-key module, and second enable signal and its second signal list in each non-key module input by the user, to obtain the yield design intent file.

[0035] During the parsing of the design intent template, the system replaces key module placeholders with the key module identifier list input by the user, replaces non-key module placeholders with the non-key module identifier list, replaces the first enable placeholder and its first signal placeholder with the first enable signal and its first signal list in each non-key module, and replaces the second enable placeholder and its second signal placeholder with the second enable signal and its second signal list in each non-key module. In other words, the third instruction instantiates multiple times based on the number of first signals. Similarly, the fourth instruction instantiates multiple times based on the number of second signals. After parsing, a complete yield design intent file is finally obtained.

[0036] S200, based on each non-critical module in the non-critical module list, query the high-level clamping mapping table and low-level clamping mapping table of each non-critical module.

[0037] It should be noted that isolation units need to be generated for each signal belonging to a non-critical module in the yield design intent file.

[0038] S300: For each signal in the high-level clamping mapping table and the low-level clamping mapping table, combine the non-critical module list and the critical module list to generate an instantiation instruction for the high-level isolation unit or the low-level isolation unit for each signal, respectively, to obtain the updated chip design; perform simulation verification on the updated chip design.

[0039] It should be noted that the instantiation instruction generation process is fully automated, eliminating the need for designers to manually write instantiation instructions for each isolation unit, significantly improving design efficiency and reliability. The generated instantiation instructions strictly adhere to the original design intent, generating high-level isolation units for each first signal in the high-level clamping map and low-level isolation units for each second signal in the low-level clamping map. This method offers excellent scalability, adapting to designs of varying scales. By adjusting the mapping table and module list, it supports a full range of isolation unit configuration requirements, from simple designs to complex on-chip systems. Furthermore, the enable logic selection strategy is configurable, accommodating different security architecture requirements.

[0040] In one implementation, the updated chip design refers to: during the register-transfer level design phase, the system inserts isolated cells into the source code of a hardware description language (such as Verilog) according to instantiation instructions. Alternatively, during the gate-level netlist phase after logic synthesis, the system inserts isolated cells into the netlist according to instantiation instructions.

[0041] In one implementation, in step S300, the step of generating the instantiation instruction for the high-level isolation unit includes: S310, extract each first signal and its associated first enable signal from the yield design intent file.

[0042] S311, Obtain the output terminal of the non-critical module and the input terminal of the critical module of the first signal access.

[0043] S312, disconnect the connection of the first signal.

[0044] S313, Obtain the isolation unit, which is used to: force the output to be clamped at a high level when the enable input signal is high level, otherwise the output follows the input.

[0045] S314, connect the input terminal of the isolation unit to the output terminal of the non-critical module, and connect the output terminal of the isolation unit to the input terminal of the critical module; connect the enable input signal of the isolation unit to the first enable signal to generate an instantiation instruction for a high-level isolation unit.

[0046] The method for forcing a high-level output is as follows: The input terminal and the enable input signal of the isolation unit are simultaneously connected to an OR gate circuit. When the enable input signal is high, regardless of the value of the input terminal of the isolation unit, the output terminal of the isolation unit will always be high, meaning the input terminal of the critical module will always be high, thus achieving the purpose of forcing a high-level output clamping.

[0047] In one implementation, in step S300, the step of generating the instantiation instruction for the low-level isolation unit includes: S320, extract each second signal and its associated second enable signal from the yield design intent file.

[0048] S321, Obtain the output terminal of the non-critical module and the input terminal of the critical module of the second signal access.

[0049] S322, disconnect the connection of the second signal.

[0050] S323, Obtain the isolation unit, which is used to: force the output to be low-level clamped when the enable input signal is low, otherwise the output follows the input.

[0051] S324, connect the input terminal of the isolation unit to the output terminal of the non-critical module, and connect the output terminal of the isolation unit to the input terminal of the critical module; connect the enable input signal of the isolation unit to the second enable signal to generate an instantiation instruction for a low-level isolation unit.

[0052] The method for forcing a low-level output is as follows: The input terminal and the enable input signal of the isolation unit are simultaneously connected to an AND gate circuit. When the enable input signal is low, regardless of the value of the input terminal of the isolation unit, the output terminal of the isolation unit will always be low, meaning the input terminal of the critical module will always be low, thus achieving the purpose of forcing a low-level output clamping.

[0053] As an example, please see Figure 2 and Figure 3 , Figure 2 This diagram illustrates the relationship between non-critical module B and critical module A in the original design. The module driving critical module A may also include other non-critical modules; this explanation focuses on non-critical module B. Furthermore, there may be numerous signal connections between non-critical module B and critical module A. Figure 2 In this code, only `sig_opt_i` represents a signal that needs to be clamped to a high level, and `sig_opt_k` represents a signal that needs to be clamped to a low level. The `sig_opt_i` signal is connected to the `B_i` port of the non-critical module and the `A_i` port of the critical module A, respectively, and the `sig_opt_k` signal is connected to the `B_k` port of the non-critical module and the `A_k` port of the critical module A, respectively. Taking the generation steps of the instantiation instruction for a high-level isolation unit as an example, when inserting a high-level isolation unit, i.e., an OR gate unit, first from... Figure 2 First, obtain the first signal sig_opt_i and its bound first enable signal ISO_B. Then, obtain the output terminal B_i of the non-critical module connected to sig_opt_i and the input terminal A_i of the critical module. Disconnect sig_opt_i. Then refer to [link to relevant documentation]. Figure 3 Connect the input terminal of the isolation unit to B_i and the output terminal of the isolation unit to A_i; connect the enable input signal of the isolation unit to the first enable signal ISO_B to generate an instantiation instruction for a high-level isolation unit, thus completing the insertion step of the isolation unit. Figure 3 The low-level isolation unit is also an AND gate unit. The input of the AND gate unit includes the second enable signal ISOn_B and the second signal sig_opt_k, and the output signal is sig_mst_k. The generation steps of the instantiation instruction of the low-level isolation unit are the same as above, and will not be repeated here.

[0054] In one embodiment, the method further includes: S330, Generate error annotation code based on the yield design intent file. The steps for generating the error annotation code include: S331, extract each non-critical module from the list of non-critical modules in the yield design intent file.

[0055] S332, for each of the non-critical modules, extract the first signal to be clamped to a high level from the high-level clamping mapping table of each of the non-critical modules in the yield design intent file, and the second signal to be clamped to a low level from the low-level clamping mapping table.

[0056] S333 generates an instruction for each of the first signals to force it to a low level.

[0057] S334 generates an instruction for each of the second signals to force it to a high level.

[0058] It's important to note that the purpose of the error injection code is to perform fault injection verification. Specifically, it targets the first signal of a non-critical module that is considered a potential failure in the yield design intent file, simulates the failure scenario of that non-critical module, and injects an erroneous value. By observing whether the chip, especially the critical functional modules, can still output the expected correct value under this erroneous condition, the fault tolerance or isolation mechanism of the chip design is verified: if the output is correct, it proves that the chip design can effectively constrain the failure impact of non-critical modules, and the verification passes; if the output is incorrect, it indicates that the failure impact has been improperly propagated, and the design has a defect.

[0059] In one embodiment, the method further includes: S340, Generate assertion code for the first signal based on the yield design intent file, wherein the step of generating the assertion code includes: S341, extract each non-critical module from the list of non-critical modules in the yield design intent file.

[0060] S342, for each of the non-critical modules, extract each first signal and its bound first enable signal corresponding to each of the non-critical modules in the high-level clamping rule in the yield design intent file.

[0061] S343 generates an instruction to determine whether the first enable signal is valid.

[0062] S344 generates an instruction to determine whether the first signal is correctly clamped to a high level when the first enable signal is valid.

[0063] S345, generate an error message when the first enable signal is invalid.

[0064] It is important to note that when a non-critical module signal is injected with an error, it is crucial to determine whether the output of the critical module still maintains its normal value. If all relevant assertions pass throughout the error injection period, the design demonstrates proper error isolation capability; if any assertions fail, it indicates that the error has been improperly propagated, and the design is flawed.

[0065] In one embodiment, S400, the method further includes: S430, Generate assertion code for the second signal based on the yield design intent file, wherein the step of generating the assertion code includes: S431, extract each non-critical module from the list of non-critical modules in the yield design intent file; S432, for each of the non-critical modules, extract each second signal and its bound first enable signal corresponding to each of the non-critical modules in the yield design intent file in the low-level clamping mapping table; S433, generate an instruction to determine whether the second enable signal is valid; S434 generates an instruction to determine whether the second signal is correctly clamped to a low level when the second enable signal is valid.

[0066] S435 generates an error message when the second enable signal is invalid.

[0067] It should be noted that in other embodiments, two assertion codes can be generated for each non-critical module. One assertion code is used to monitor all first signals of the current non-critical module, and the other assertion code is used to monitor all second signals of the current non-critical module. Alternatively, one assertion code can be generated for each enable signal. Other implementations of generating assertion codes also fall within the scope of this invention.

[0068] In one embodiment, S400, the method further includes: S440, inject error code into a designated non-critical module to disable the output signal of the non-critical module.

[0069] S450, activate the instantiation instruction of the isolation unit associated with the specified non-critical module, and clamp the output signal of the non-critical module to a preset safety value; the preset safety value is a high level or a low level.

[0070] S460, Detect the operating status of the key module.

[0071] S470, if the key module satisfies the conditions in the assertion code, then the chip design is confirmed to be correct.

[0072] In summary, this invention provides a chip yield-based verification method. Its custom-formatted yield design intent file eliminates the need for inefficient, error-prone, and non-reusable natural language-based intent documents, thus improving the efficiency of yield design and verification. By ensuring only the correctness of the yield design intent file, it avoids oversights caused by manually writing design and verification code. Furthermore, the yield design intent file can be reused multiple times in the R&D process by front-end design and front-end verification stages, exhibiting good reusability.

[0073] Embodiments of the present invention also provide a non-transitory computer-readable storage medium that can be disposed in an electronic device to store at least one instruction or at least one program related to implementing a method in the method embodiments, wherein the at least one instruction or the at least one program is loaded and executed by the processor to implement the method provided in the above embodiments.

[0074] Embodiments of the present invention also provide an electronic device, including a processor and the aforementioned non-transitory computer-readable storage medium.

[0075] Embodiments of the present invention also provide a computer program product including program code, which, when the program product is run on an electronic device, causes the electronic device to perform the steps of the methods described above in various exemplary embodiments of the present invention.

[0076] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is used as an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above.

[0077] While specific embodiments of the invention have been described in detail by way of example, those skilled in the art should understand that the examples are for illustrative purposes only and not intended to limit the scope of the invention. Those skilled in the art should also understand that various modifications can be made to the embodiments without departing from the scope and spirit of the invention. The scope of this invention is defined by the appended claims.

Claims

1. A verification method based on yield design intent documents, characterized in that, include: Parse the yield design intent file to obtain a critical module list, a non-critical module list, a high-level clamping mapping table, and a low-level clamping mapping table with a fixed format. The critical modules are modules that must work, and the non-critical modules are modules that can fail. The high-level clamping mapping table includes a first enable signal for clamping high level when isolating non-critical modules and a list of first signals to be clamped to high level. The low-level clamping mapping table includes a second enable signal for clamping low level when isolating non-critical modules and a list of second signals to be clamped to low level. Based on each non-critical module in the list of non-critical modules, query the high-level clamping mapping table and low-level clamping mapping table for each non-critical module; For each signal in the high-level clamping mapping table and the low-level clamping mapping table, the instantiation instructions for the high-level isolation unit or the low-level isolation unit of each signal are generated by combining the non-critical module list and the critical module list, respectively, to obtain the updated chip design; The updated chip design was simulated and verified. The steps for generating the yield design intent file include: The design object obtained from user input includes a list of key module identifiers, a list of non-key module identifiers, a list of first signals to be clamped to a high level and a list of second signals to be clamped to a low level when each non-key module fails and outputs them to the key module. For each non-critical module, obtain a first enable signal for clamping to a high level and a second enable signal for clamping to a low level, and bind the first enable signal to the first signal list of the current non-critical module as a high-level clamping mapping table, and bind the second enable signal to the second signal list of the current non-critical module as a low-level clamping mapping table. Obtain the yield design intent template file and identify the instructions and placeholders for generating each list in the yield design intent template file; The corresponding placeholders in the yield design intent template file are replaced by the key module identifier list, non-key module identifier list, first enable signal and its first signal list in each non-key module, and second enable signal and its second signal list in each non-key module, as input by the user, to obtain the yield design intent file.

2. The method according to claim 1, characterized in that, The yield design intent file is obtained based on the yield design intent template file, which includes: Parse the yield design intent template file and identify the instructions and placeholders in the yield design intent template file, including: The first instruction is configured to: define a list of key modules, wherein the list of key modules is defined by key module placeholders; wherein the key module placeholders are configured to receive at least one key module identifier; The second instruction is configured to: define a list of non-critical modules, wherein the list of non-critical modules is defined by non-critical module placeholders; wherein the non-critical module placeholders are configured to receive at least one non-critical module identifier; The third instruction is configured to: define a high-level clamping mapping table, wherein the high-level clamping mapping table is defined by a first enable placeholder and a first signal placeholder to be clamped to a high level; wherein the first enable placeholder is configured to receive at least one first isolation enable signal; and the first signal placeholder is configured to receive at least one first signal. The fourth instruction is configured to: define a low-level clamping map, wherein the low-level clamping map is defined by a second enable placeholder and a second signal placeholder to be clamped to a low level; wherein the second enable placeholder is configured to receive at least one first enable signal; and the second signal placeholder is configured to receive at least one second signal.

3. The method according to claim 1, characterized in that, The steps for generating the instantiation instruction of the high-level isolation unit include: Extract each first signal and its associated first enable signal from the yield design intent file; Obtain the output terminals of the non-critical modules and the input terminals of the critical modules of the first signal access; Disconnect the first signal; The isolation unit is used to: force a high-level output clamp when the isolation signal is high, otherwise the output follows the input; Connect the input terminal of the isolation unit to the output terminal of the non-critical module, and connect the output terminal of the isolation unit to the input terminal of the critical module; connect the enable input signal of the isolation unit to the first enable signal to generate an instantiation instruction for a high-level isolation unit.

4. The method according to claim 1, characterized in that, The steps for generating the instantiation instruction of the low-level isolation unit include: Extract each second signal and its associated second enable signal from the yield design intent file; Obtain the output terminals of the non-critical modules and the input terminals of the critical modules of the second signal access; Disconnect the second signal; An isolation unit is acquired, which is used to: force a low-level output clamp when the enable input signal is low, otherwise the output follows the input; Connect the input terminal of the isolation unit to the output terminal of the non-critical module, and connect the output terminal of the isolation unit to the input terminal of the critical module; connect the enable input signal of the isolation unit to the second enable signal to generate an instantiation instruction for a low-level isolation unit.

5. The method according to claim 1, characterized in that, The method further includes: Error annotation code is generated based on the yield design intent file. The steps for generating the error annotation code include: Extract each non-critical module from the list of non-critical modules in the yield design intent file; For each of the non-critical modules, extract the first signal to be clamped to a high level from the high-level clamping mapping table of each non-critical module in the yield design intent file, and the second signal to be clamped to a low level from the low-level clamping mapping table. Generate an instruction for each of the first signals to force it to a low level; Generate an instruction for each of the second signals to force it to go high.

6. The method according to claim 1, characterized in that, The method further includes: The assertion code for the first signal is generated based on the yield design intent file. The steps for generating the assertion code include: Extract each non-critical module from the list of non-critical modules in the yield design intent file; For each of the non-critical modules, extract each first signal and its bound first enable signal corresponding to each of the non-critical modules in the high-level clamping mapping table in the yield design intent file; Generate an instruction to determine whether the first enable signal is valid; When the first enable signal is valid, generate an instruction to determine whether the first signal is correctly clamped to a high level; An error message is generated when the first enable signal is invalid.

7. The method according to claim 1, characterized in that, The method further includes: The assertion code for the second signal is generated based on the yield design intent file. The steps for generating the assertion code include: Extract each non-critical module from the list of non-critical modules in the yield design intent file; For each of the non-critical modules, extract each second signal and its bound first enable signal corresponding to each of the non-critical modules in the yield design intent file in the low-level clamping mapping table; Generate an instruction to determine whether the second enable signal is valid; When the second enable signal is valid, generate an instruction to determine whether the second signal is correctly clamped to a low level; An error message is generated when the second enable signal is invalid.

8. The method according to claim 1, characterized in that, The method further includes: Inject error-injecting code into designated non-critical modules to disable the output signals of those modules; Activate the instantiation instruction of the isolation unit associated with the specified non-critical module, and clamp the output signal of the non-critical module to a preset safety value; the preset safety value is either high or low. Detect the operating status of the key modules; If the key module satisfies the conditions in the assertion code, then the chip design is confirmed to be correct.

9. A non-transitory computer-readable storage medium, wherein the storage medium stores at least one instruction or at least one program segment, characterized in that, The at least one instruction or the at least one program segment is loaded and executed by the processor to implement the method as described in any one of claims 1-8.

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