Multilayer electronic assembly and method of manufacturing the same
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SAMSUNG ELECTRO MECHANICS CO LTD
- Filing Date
- 2025-12-31
- Publication Date
- 2026-07-07
Smart Images
Figure CN122348136A_ABST
Abstract
Description
[0001] This application claims the benefit of priority to Korean Patent Application No. 10-2025-0001513, filed on January 6, 2025, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field
[0002] This disclosure relates to a multilayer electronic component and a method for manufacturing the multilayer electronic component. Background Technology
[0003] Multilayer ceramic capacitors (MLCCs) are surface-mount capacitors used in a wide range of electronic products, such as imaging devices including liquid crystal displays (LCDs) and plasma display panels (PDPs), as well as computers, smartphones, and mobile phones. MLCCs, mounted on printed circuit boards, function by storing and releasing electrical energy. Their compact size, high capacitance, and ease of installation make them indispensable components in modern electronic devices.
[0004] With the rapid development of the small-sized device industry, led by wearable and mobile devices, the demand for MLCCs that simultaneously offer miniaturization and high capacitance is increasing. Achieving these performance goals typically requires reducing the thickness of the dielectric layer and internal electrodes within the MLCC structure.
[0005] Conventionally, conductive paste containing nickel (Ni) particles has been used to fabricate the internal electrodes in MLCCs. To achieve thinner internal electrodes, the particle size of the Ni particles has been continuously reduced. However, smaller Ni particles tend to lower the sintering initiation temperature, which can lead to a mismatch in the sintering behavior between the internal electrode and the dielectric layer (typically composed of perovskite compounds). Such a mismatch can cause the electrode to break, increasing the risk of short circuits and lowering the breakdown voltage (BDV) of the MLCC.
[0006] To address these issues, there is a need for alternative conductive materials associated with the internal electrodes that can maintain compatibility with the dielectric layer during sintering while still supporting miniaturization and high capacitance. Summary of the Invention
[0007] This disclosure relates to an improved multilayer electronic component and a method for manufacturing the multilayer electronic component.
[0008] One aspect of this disclosure is to provide a multilayer electronic component with excellent internal electrode connectivity and dielectric properties.
[0009] However, the aspects of this disclosure are not limited to those set forth herein, and will be more readily understood in the process of describing specific exemplary embodiments of this disclosure.
[0010] According to one aspect of this disclosure, a multilayer electronic component is provided, comprising: a body including a dielectric layer and inner electrodes alternately disposed with respect to the dielectric layer; and an outer electrode disposed on the body. In an embodiment, the inner electrode may include a silicide. In an embodiment, the average oxygen content relative to the weight of all elements in the interface region of the inner electrode may be less than or equal to 0.75 wt%, the interface region extending 100 nm from the interface between the inner electrode and the dielectric layer toward the interior of the inner electrode.
[0011] According to another aspect of this disclosure, a method for manufacturing a multilayer electronic component is provided, the method comprising: heat-treating silicide particles in a reducing atmosphere; forming a conductive paste comprising the heat-treated silicide particles; printing the conductive paste onto a dielectric sheet; stacking a plurality of dielectric sheets on which the conductive paste is printed to form a laminate; sintering the laminate to form a body comprising a dielectric layer and an inner electrode; and forming an outer electrode on the body.
[0012] According to another aspect of this disclosure, a method for manufacturing a multilayer electronic component is provided, comprising: (a) preparing silicide particles; (b) heat-treating the silicide particles in a reducing atmosphere to remove an oxide film; (c) forming a conductive paste comprising the heat-treated silicide particles; (d) printing the conductive paste onto a dielectric sheet to form an inner electrode pattern; (e) stacking a plurality of dielectric sheets on which the conductive paste is printed to form a laminate; (f) sintering the laminate to form a body comprising a dielectric layer and an inner electrode; and (g) forming an outer electrode on the body.
[0013] According to exemplary embodiments of this disclosure, multilayer electronic components can have excellent internal electrode connectivity and dielectric properties. Attached Figure Description
[0014] The above and other aspects, features and advantages of this disclosure will become clearer from the following detailed embodiments, taken in conjunction with the accompanying drawings, in which: Figure 1 This is a schematic perspective view of a multilayer electronic assembly according to an exemplary embodiment of the present disclosure; Figure 2 It is along Figure 1 A schematic cross-sectional view of line I-I'; Figure 3 It is along Figure 1 A schematic cross-sectional view taken from line II-II'; Figure 4 yes Figure 2 A schematic enlarged view of region A; Figure 5A This is a schematic diagram of an internal electrode formed using silicide particles, based on a comparative example. Figure 5B This is a schematic diagram of an internal electrode formed using silicide particles according to an exemplary embodiment; Figure 6A The images were obtained by taking pictures of the dielectric layer and inner electrode of Comparative Example 1 using a scanning electron microscope (SEM); Figure 6B The images were obtained by using SEM to capture images of the dielectric layer and inner electrode of Comparative Example 2. Figure 6C The images were obtained by using SEM to photograph the dielectric layer and inner electrode of Example Example 1; and Figure 6D The images were obtained by using SEM to photograph the dielectric layer and inner electrode of Example Example 2. Detailed Implementation
[0015] In the following description, exemplary embodiments of the present disclosure are illustrated with reference to the accompanying drawings. However, the present disclosure may be exemplified in many different forms and should not be construed as being limited to the specific exemplary embodiments set forth herein. Additionally, exemplary embodiments of the present disclosure may be provided to describe the present disclosure more completely to those skilled in the art. Therefore, for clarity of description, the shape and size of the elements in the drawings may be exaggerated, and elements denoted by the same reference numerals in the drawings are the same elements.
[0016] To clearly illustrate this disclosure, parts irrelevant to the description have been omitted, and dimensions (such as thickness) have been enlarged in the drawings to clearly indicate layers and regions. Throughout the specification, similar parts having the same function within the same area are indicated by similar reference numerals. Throughout the specification, unless otherwise expressly stated, when an element is referred to as "comprising" or "including," it means that the element may also include other elements, rather than excluding other elements.
[0017] In the accompanying drawings, the first direction X can be defined as the thickness direction, the second direction Y can be defined as the length direction, and the third direction Z can be defined as the width direction.
[0018] Multilayer electronic components Figure 1 This is a schematic perspective view of a multilayer electronic component according to an exemplary embodiment of the present disclosure.
[0019] Figure 2 It is along Figure 1 A schematic cross-sectional view taken from line I-I'.
[0020] Figure 3 It is along Figure 1 A schematic cross-sectional view taken from line II-II'.
[0021] Figure 4 yes Figure 2 A schematic enlarged view of region A.
[0022] In the following text, reference will be made to Figure 1 , Figure 2 , Figure 3 and Figure 4 A multilayer electronic assembly 100 according to an exemplary embodiment of the present disclosure is described in detail. Furthermore, a multilayer ceramic capacitor (MLCC) is described as an example of a multilayer electronic assembly, but the present disclosure is not limited thereto, and is applicable to various other electronic products (such as inductors, piezoelectric elements, rheostats, thermistors, etc.) formed using ceramic materials.
[0023] A multilayer electronic component 100 according to an example embodiment of the present disclosure may include a body 110 and external electrodes 131 and 132.
[0024] The specific shape of the main body 110 is not limited. However, as Figure 1 As shown, the body 110 may have a hexahedral shape or a shape similar to a hexahedron. Due to the shrinkage of the ceramic powder used to form the body 110 during the sintering process or the polishing of the corners, the body 110 may not have a hexahedral shape with perfect straight lines, but may have a generally hexahedral shape.
[0025] In an embodiment, the body 110 may have: a first surface 1 and a second surface 2, which are opposite to each other in a first direction; a third surface 3 and a fourth surface 4, which are connected to the first surface 1 and the second surface 2, and are opposite to each other in a second direction; and a fifth surface 5 and a sixth surface 6, which are connected to the first surface 1, the second surface 2, the third surface 3 and the fourth surface 4, and are opposite to each other in a third direction.
[0026] In one embodiment, the body 110 may include a dielectric layer 111 and internal electrodes 121 and 122 alternately disposed with the dielectric layer 111 in a first direction. In another embodiment, the plurality of dielectric layers 111 included in the body 110 may be in a sintered state, and adjacent dielectric layers 111 may be integrated with each other, such that the boundaries between them are not easily distinguishable without the use of SEM.
[0027] In an embodiment, the dielectric layer 111 may, for example, include a perovskite-type compound represented by ABO3 as the main component. In an embodiment, the dielectric layer 111 may, for example, include a perovskite-type compound containing Ba and Ti as the main component. In an embodiment, the perovskite-type compound may, for example, include BaTiO3, (Ba... 1-x Ca x TiO3 (0) <x<1)、Ba(Ti 1-y Cay )O3 (0 < y < 1), (Ba 1- x Ca x )(Ti 1-y Zr y )O3 (0 < x < 1, 0 < y < 1) and Ba(Ti 1-y Zr y )O3 (0 < y < 1), or one or more of them.
[0028] In the present disclosure, the "main component" of the dielectric layer 111 may refer to a component that accounts for a relatively large proportion in terms of weight percentage or atomic percentage compared to other components in the dielectric layer 111, and may refer to a component with a weight exceeding 50 wt% relative to the total dielectric composition or the entire dielectric layer, an atomic number exceeding 50 at% relative to the total dielectric composition or the entire dielectric layer, or a mole number exceeding 50 mol% relative to the total dielectric composition or the entire dielectric layer.
[0029] In an embodiment, the inner electrodes 121 and 122 may include, for example, a first inner electrode 121 and a second inner electrode 122 alternately arranged in the first direction, and the dielectric layer 111 is interposed between the first inner electrode 121 and the second inner electrode 122. That is, the first inner electrode 121 and the second inner electrode 122 (a pair of electrodes with different polarities) may be arranged opposite to each other, and the dielectric layer 111 is interposed between the first inner electrode 121 and the second inner electrode 122.
[0030] In an embodiment, the first inner electrode 121 may be spaced apart from the fourth surface 4 and connected to the first outer electrode 131 on the third surface 3. The second inner electrode 122 may be spaced apart from the third surface 3 and connected to the second outer electrode 132 on the fourth surface 4.
[0031] In the related art, an inner electrode conductive paste including Ni particles has been used to form the inner electrode, and in order to reduce the thickness of the inner electrode, the size of the Ni particles has been reduced. However, due to the reduction in the size of the Ni particles, the sintering start temperature of the Ni particles may decrease, and sintering mismatch between the inner electrode and the dielectric layer may occur. Such a sintering mismatch may deteriorate the connectivity of the inner electrode, resulting in short circuits and a decrease in the breakdown voltage (BDV) in the multilayer electronic component. In the present disclosure, the term "connectivity of the inner electrode" may be defined as the ratio of the length of the actual electrode part to the total electrode length of the inner electrode (e.g., the length from one end to the other end of the inner electrode in the second direction), and may refer to the degree to which the inner electrode of a single layer is formed uniformly and without disconnection.
[0032] According to an exemplary embodiment of this disclosure, the internal electrodes 121 and 122 may comprise silicides. Silicides are compounds of silicon and metals, and due to metal-silicon bonding, silicides can be chemically stable and can have high electrical conductivity. Silicides may have a melting point higher than that of Ni, thereby suppressing sintering mismatch between the internal electrodes and the dielectric layer 111, which primarily comprises perovskite-type compounds. Therefore, the internal electrodes 121 and 122 may have improved connectivity, thereby preventing short circuits and BDV degradation in the multilayer electronic assembly 100.
[0033] In embodiments, the inner electrodes 121 and 122 may, for example, include silicides as the main component. In this disclosure, the term "main component" for the inner electrodes 121 and 122 may refer to a component that constitutes a relatively large proportion by weight percentage or atomic percentage compared to other components in the inner electrodes 121 and 122, and may refer to a component that exceeds 50 wt% of the total weight of the conductive paste or the entire inner electrode, exceeds 50 at% of the atomic number of the conductive paste or the entire inner electrode, or exceeds 50 mol% of the molar number of the conductive paste or the entire inner electrode.
[0034] However, when the dielectric layer and inner electrode are formed separately by simultaneously sintering ceramic particles and silicide particles with an oxide film formed on their surfaces, the oxygen concentration at the interface between the dielectric layer and the inner electrode may be too high. When the oxygen concentration at the interface between the dielectric layer and the inner electrode is too high, an interface layer may form at the interface, comprising silicides with a crystal structure different from that of the silicides in the inner electrode. Furthermore, a second phase may form in the dielectric layer due to the diffusion of silicon included in the inner electrode. The interface layer and the second phase are likely the main causes of conductivity degradation of the inner electrode and dielectric properties of the dielectric layer.
[0035] Conversely, according to an exemplary embodiment of this disclosure, the average oxygen content relative to the weight of all elements in the interface region R1 (the region extending 100 nm from the interface IF between the inner electrodes 121 and 122 and the dielectric layer 111 toward the interior of the inner electrodes 121 and 122) can be less than or equal to 0.75 wt%. Since the average oxygen content relative to the weight of all elements in the interface region R1 is less than or equal to 0.75 wt%, the oxygen concentration in the interface region R1 can be sufficiently reduced to prevent the formation of an interface layer and / or a second phase. Therefore, the multilayer electronic component 100 can have excellent dielectric properties.
[0036] The lower limit of the average oxygen content relative to the weight of all elements in the interface region R1 is not limited and can be, for example, 0 wt% or greater. However, due to the diffusion of oxygen in the dielectric layer 111, the average oxygen content relative to the weight of all elements in the interface region R1 can be, for example, greater than or equal to 0.03 wt%.
[0037] The inner electrodes 121 and 122 may include a central region R2 (the region other than the interface region R1). The average oxygen content (wt%) of the central region R2 may be lower than the average oxygen content (wt%) of the interface region R1. The oxygen in the inner electrodes 121 and 122 may originate from: the raw materials of the inner electrodes 121 and 122 (e.g., including an oxide film formed on the surface of silicide particles) and / or a perovskite-type compound represented by ABO3 in the dielectric layer 111. Therefore, the average oxygen content (wt%) of the central region R2 may be lower than the average oxygen content (wt%) of the interface region R1 adjacent to the dielectric layer 111.
[0038] In this disclosure, the average oxygen content relative to the weight of all elements in interface region R1 can be less than or equal to 0.75 wt%, thereby sufficiently reducing the oxygen concentration in interface region R1 to prevent changes in the crystal structure of the silicide included in interface region R1. That is, interface region R1 and central region R2 can include silicides having the same crystal structure. Therefore, when the atomic percentage (at%) of silicon in interface region R1 is represented by S1, and the atomic percentage (at%) of silicon in central region R2 is represented by S2, the ratio of S1 to S2 (S1 / S2) can be greater than or equal to 0.9 and less than or equal to 1.1. Maintaining the same crystal structure of the silicides included in interface region R1 and central region R2 allows the conductivity of internal electrodes 121 and 122 to be maintained, thereby more effectively improving the dielectric properties of the multilayer electronic component 100.
[0039] In images obtained by taking cross-sections of the subject 110 in the first and second directions using SEM or scanning transmission electron microscopy (STEM), the interface IF between the inner electrodes 121 and 122 and the dielectric layer 111 can be distinguished based on color and / or contrast differences between the dielectric layer 111 and the inner electrodes 121 and 122. Optionally, the interface IF between the inner electrodes 121 and 122 and the dielectric layer 111 can be defined as the location where the content of elements included in the dielectric layer 111 and the inner electrodes 121 and 122 changes abruptly. In an example embodiment, a region where the atomic percentage (at%) of Ba relative to the number of atoms of all elements is greater than or equal to 9 at% can be defined as the dielectric layer 111, and the location where the atomic percentage (at%) of Ba relative to the number of atoms of all elements begins to be less than 9 at% can be defined as the interface IF between the inner electrodes 121 and 122 and the dielectric layer 111.
[0040] The average oxygen content in interface region R1 can be measured using energy-dispersive X-ray spectroscopy (EDS) analysis of images obtained in the following manner: after exposing cross-sections of the multilayer electronic assembly 100 obtained by polishing to its central portion in the third direction in the first and second directions, the interface region R1 of the internal electrodes 121 and 122 disposed in the central portion of the capacitor forming section Ac as described below is imaged using a high-angle annular dark-field scanning transmission electron microscope (HAADF-STEM) or STEM. Specifically, in the image obtained by imagening interface region R1 using HAADF-STEM, the average oxygen content (wt%) in interface region R1 can be obtained by measuring the oxygen content at any five or more points in interface region R1 using EDS and averaging the measured values. Similarly, the average oxygen content in central region R2 can be obtained by measuring the oxygen content (wt%) at any five or more points in central region R2 using both HAADF-STEM and EDS and averaging the measured values.
[0041] S1 and S2 can be obtained by measuring the atomic percentage (at%) of silicon instead of the oxygen content (wt%) using HAADF-STEM and EDS.
[0042] The type of silicide is not limited. Silicides may include one or more of Mo, Co, Zr, Hf, Ta, Ti, Cr, and Ni. Silicides may have crystal structures such as tetragonal, cubic, orthorhombic, or hexagonal. Silicides may be produced from materials with a sintering temperature of 1050 °C or higher and / or 10 6 The silicide is selected from silicides with a conductivity of S / m or higher for simultaneous sintering with the ceramic particles used to form dielectric layer 111. The silicide may be a disilicide in which the atomic numbers of metal and silicon are combined in a 1:2 ratio. The conductivity and sintering temperature of the disilicide are higher than those of the monosilicide in which the atomic numbers of metal and silicon are combined in a 1:1 ratio, thus the disilicide is more suitable for simultaneous sintering with the ceramic particles used to form dielectric layer 111. The silicide may include one or more of MoSi2, CoSi2, ZrSi2, and HfSi2.
[0043] The main body 110 may include: a capacitor forming portion Ac, in which a first inner electrode 121 and a second inner electrode 122 are alternately disposed and a dielectric layer 111 is disposed between the first inner electrode 121 and the second inner electrode 122 to form a capacitor; covering portions 112 and 113, disposed on two surfaces of the capacitor forming portion Ac that are opposite to each other in a first direction; and edge portions 114 and 115, disposed on two surfaces of the capacitor forming portion Ac that are opposite to each other in a third direction. The covering portions 112 and 113 and the edge portions 114 and 115 do not include inner electrodes and may have a structure similar to that of the dielectric layer 111.
[0044] The external electrodes 131 and 132 may include: a first external electrode 131 disposed on the third surface 3, the first external electrode 131 extending to at least one of a portion of the first surface 1, a portion of the second surface 2, a portion of the fifth surface 5, and a portion of the sixth surface 6; and a second external electrode 132 disposed on the fourth surface 4, the second external electrode 132 extending to at least one of a portion of the first surface 1, a portion of the second surface 2, a portion of the fifth surface 5, and a portion of the sixth surface 6.
[0045] The type or form of the external electrodes 131 and 132 is not limited, and the external electrodes 131 and 132 may have a multilayer structure. For example, the external electrodes 131 and 132 may include a base electrode layer 131a and 132a in contact with the inner electrodes 121 and 122, and plating layers 131b and 132b disposed on the base electrode layer 131a and 132a.
[0046] The substrate electrode layers 131a and 132a may be sintered electrode layers comprising metal and glass. The metals included in the sintered electrode layers may include, for example, Cu, Ni, Pd, Pt, Au, Ag, Pb, and / or alloys comprising them. The glass included in the sintered electrode layers may include, for example, one or more of Ba oxide, Ca oxide, Zn oxide, Al oxide, B oxide, and Si oxide.
[0047] The substrate electrode layers 131a and 132a may consist only of sintered electrode layers comprising metal and glass, but this disclosure is not limited thereto. The substrate electrode layers 131a and 132a may include, for example, a sintered electrode layer and a resin electrode layer, wherein the sintered electrode layer comprises metal and glass, and the resin electrode layer is disposed on the sintered electrode layer, and the resin electrode layer comprises metal particles and resin.
[0048] The metal particles contained in the resin electrode layer can be spherical particles and / or plate-shaped particles. The metal particles contained in the resin electrode layer may include, for example, Cu, Ni, Pd, Pt, Au, Ag, Pb, Sn, and / or alloys containing them. The resin contained in the resin electrode layer may include, for example, one or more of epoxy resin, acrylic resin, and ethyl cellulose.
[0049] The plating layers 131b and 132b may comprise, for example, Ni, Sn, Pd, and / or alloys comprising them, and may be formed using multiple layers. The plating layers 131b and 132b may be, for example, Ni plating layers or Sn plating layers, or may be formed as a structure in which Ni plating layers and Sn plating layers are sequentially formed on the substrate electrode layers 131a and 132a. The plating layers 131b and 132b may comprise multiple Ni plating layers and / or multiple Sn plating layers.
[0050] The accompanying drawings depict a multilayer electronic assembly 100 having two external electrodes 131 and 132, but this disclosure is not limited thereto, and the number and / or shape of the external electrodes may be changed depending on the form of the internal electrodes and / or other purposes.
[0051] The size of the multilayer electronic component 100 is not limited. However, in order to achieve miniaturization and high capacitance of the multilayer electronic component 100, in the case of multilayer electronic components with a size of 1005 (length: about 1.0 mm, width: about 0.5 mm, thickness: about 0.5 mm) or smaller (where the number of stacked layers is increased by reducing the thickness of the dielectric layer and the inner electrode), the connectivity of the inner electrode is likely to deteriorate due to the sintering mismatch between the dielectric layer and the inner electrode. Therefore, when the multilayer electronic component 100 according to the exemplary embodiment of this disclosure is manufactured as an ultra-small multilayer electronic component with a size of 1005 (length: about 1.0 mm, width: about 0.5 mm, thickness: about 0.5 mm) or smaller, the effect of improving the connectivity and dielectric properties of the inner electrode can become more significant.
[0052] The average thickness td of dielectric layer 111 and the average thickness te of each of inner electrodes 121 and 122 are not limited. However, when the multilayer electronic component 100 according to an exemplary embodiment of the present disclosure is manufactured into an ultra-small multilayer electronic component in which the average thickness td of dielectric layer 111 is less than or equal to 400 nm and / or the average thickness te of each of inner electrodes 121 and 122 is less than or equal to 400 nm, the effect of improving the connectivity and dielectric properties of the inner electrodes can become more significant.
[0053] The average thickness td of dielectric layer 111 and the average thickness te of each of inner electrodes 121 and 122 can refer to the average dimension of dielectric layer 111 in the first direction and the average dimension of each of inner electrodes 121 and 122 in the first direction, respectively. The average thickness td of dielectric layer 111 and the average thickness te of each of inner electrodes 121 and 122 can be measured, for example, by scanning a cross-section of body 110 in the first and second directions using a SEM at a magnification of 10000. More specifically, the average thickness td of dielectric layer 111 can be obtained by measuring the thickness of a single dielectric layer 111 at multiple points (e.g., five points spaced equally apart in the second direction) and calculating the average of the measured thicknesses. Similarly, the average thickness te of each of inner electrodes 121 and 122 can be obtained by measuring the thickness of a single inner electrode at multiple points (e.g., five points spaced equally apart in the second direction) and calculating the average of the measured thicknesses. Five points spaced apart from each other at equal intervals can be specified in the capacitor forming section Ac. When such an average thickness measurement is performed on the ten dielectric layers 111 and the ten inner electrodes 121 and 122, the average thickness of the dielectric layer 111 and the average thickness of each of the inner electrodes 121 and 122 can be further generalized.
[0054] The average thickness tc of each of the covers 112 and 113 is not limited. The average thickness tc of each of the covers 112 and 113 may, for example, be greater than or equal to 5 μm and less than or equal to 100 μm. For example, when the multilayer electronic assembly 100 has a size of 1005 (length: about 1.0 mm, width: about 0.5 mm) or smaller, the average thickness tc of each of the covers 112 and 113 may be greater than or equal to 5 μm and less than or equal to 35 μm. Here, the average thickness tc of each of the covers 112 and 113 may refer to the average thickness of each of the first cover 112 and the second cover 113. The average thickness tc of each of the covers 112 and 113 may refer to the average dimension of each of the covers 112 and 113 in the first direction, and may be a value obtained by averaging the dimensions of each of the covers 112 and 113 in the first and second directions in a cross-section of the body 110 at five points spaced apart from each other at equal intervals in the first direction.
[0055] The average thickness of each of edge portions 114 and 115 may refer to the average dimension of each of edge portions 114 and 115 in a third direction. The average thickness of each of edge portions 114 and 115 is not limited. The average thickness of each of edge portions 114 and 115 may, for example, be greater than or equal to 3 μm and less than or equal to 100 μm. For example, when the multilayer electronic assembly 100 has dimensions of 1005 (length: approximately 1.0 mm, width: approximately 0.5 mm) or smaller, the average thickness of each of edge portions 114 and 115 may be greater than or equal to 3 μm and less than or equal to 25 μm. The average thickness of each of edge portions 114 and 115 may refer to the average thickness of each of the first edge portion 114 and the second edge portion 115. The average thickness of each of the edge portions 114 and 115 can be obtained by averaging the dimensions in the third direction of each of the edge portions 114 and 115 measured at five points spaced apart from each other at equal intervals in a cross section of the body 110 in the first and third directions.
[0056] Methods for manufacturing multilayer electronic components Figure 5A This is a schematic diagram of an internal electrode formed using silicide particles, based on a comparative example. Figure 5B This is a schematic diagram of an internal electrode formed using silicide particles according to an example embodiment.
[0057] In the following text, reference will be made to Figure 2 , Figure 5A and Figure 5B A method for manufacturing a multilayer electronic component 100 according to an example embodiment of the present disclosure is described.
[0058] Raw material preparation operation First, silicide particles 10 for forming internal electrodes 121 and 122 can be prepared. A method for manufacturing a multilayer electronic component 100 according to an exemplary embodiment of this disclosure may include heat-treating the silicide particles 10 in a reducing atmosphere. The heat treatment removes the oxide film 11 formed on the surface of each silicide particle 10.
[0059] The reducing atmosphere can be, for example, 0.1% H2 / 99.9% N2 to 3.0% H2 / 97.0% N2 (i.e., 0.1% to 3.0% H2 and the balance N2, where the percentages can refer to volume percentages). Additionally, the heat treatment operation can be carried out at a temperature of 600°C or higher and 800°C or lower for 1 hour or longer and 5 hours or shorter, i.e., 1 hour to 5 hours at 600°C to 800°C.
[0060] Subsequently, a conductive paste including the heat-treated silicide particles 10 can be formed. The conductive paste may include the heat-treated silicide particles 10, a binder, and an organic solvent. The binder and the organic solvent may be materials known in the art. For example, polyvinyl butyral can be used as the binder, and ethanol can be used as the organic solvent.
[0061] In addition, ceramic particles for forming the dielectric layer 111 can be prepared. The ceramic particles may include, for example, one or more of BaTiO3, (Ba 1- x Ca x )TiO3 (0 < x < 1), Ba(Ti 1-y Ca y )O3 (0 < y < 1), (Ba 1-x Ca x )(Ti 1-y Zr y )O3 (0 < x < 1, 0 < y < 1), and Ba(Ti 1- y Zr y )O3 (0 < y < 1). The BaTiO3 particles can be synthesized, for example, by reacting a titanium raw material (such as titanium dioxide) with a barium raw material (such as barium carbonate). The synthesis method of the ceramic particles may include, for example, a solid-state method, a sol-gel method, or a hydrothermal synthesis method, but the present disclosure is not limited thereto.
[0062] Subsequently, the prepared ceramic particles can be dried and pulverized, and then mixed with an organic solvent and a binder to prepare a ceramic slurry.
[0063] Printing operation The ceramic slurry can be coated on a carrier film and dried to prepare a dielectric sheet. The conductive paste can be printed on the dielectric sheet to form an inner electrode pattern. The printing can be performed, for example, using a screen printing method or a gravure printing method.
[0064] Thereafter, a plurality of dielectric sheets printed with the conductive paste can be laminated and pressed to form a laminate. A predetermined number of dielectric sheets not printed with the conductive paste can be laminated on the upper and lower portions of the laminate to form covering portions 112 and 113 after sintering.
[0065] Cutting and sintering operations Thereafter, the laminate can be sintered to form a main body 110 including the dielectric layer 111 and the inner electrodes 121 and 122. If necessary, the laminate can be cut into sheets having a predetermined size, and the cut sheets can be sintered. The sintering can be performed in a reducing atmosphere or an oxidizing atmosphere at a temperature of 1000 °C or higher and 1400 °C or lower.
[0066] Refer to Figure 5A and Figure 5BThe heat-treated silicide particles 10 may have a low oxide film coverage 11, while the untreated silicide particles 10' may have a high oxide film coverage 11. Therefore, when the heat-treated silicide particles 10 are used to form the inner electrodes 121 and 122, no interface layer and / or second phase is formed. Conversely, when the untreated silicide particles 10' are used to form the inner electrodes 121' and 122', an interface layer IL may be formed at the interface between the inner electrodes 121' and 122' and the dielectric layer 111', and a second phase SP may be formed in the dielectric layer 111'. The interface layer IL may be formed due to excessively high oxygen concentration at the interface between the dielectric layer 111' and the inner electrodes 121' and 122'.
[0067] The interface layer IL may include, for example, a silicide having a crystal structure different from that of the silicide included in the inner electrodes 121' and 122'. For example, the silicide included in the inner electrodes 121' and 122' may be a disilicide, and the silicide included in the interface layer IL may be a monosilicide. The interface layer IL may degrade the conductivity of the inner electrodes 121' and 122'.
[0068] The second phase SP can be formed by the diffusion of silicon enriched in the inner electrodes 121' and 122' toward the dielectric layer 111'. The second phase SP can degrade the dielectric properties of the dielectric layer 111'.
[0069] External electrode formation operation Subsequently, external electrodes 131 and 132 can be formed. For example, when the substrate electrode layers 131a and 132a include sintered electrode layers, the body 110 can be immersed in an external electrode conductive paste comprising metal particles, glass frit, binder and organic solvent, and then the external electrode conductive paste can be sintered at a temperature of 500°C to 900°C to form sintered electrode layers.
[0070] For example, when the substrate electrode layers 131a and 132a include a resin electrode layer, the substrate can be immersed in a conductive resin composition including metal particles, resin, adhesive and organic solvent, and the conductive resin composition can be cured by heat treatment at a temperature of 250°C to 550°C to form a resin electrode layer.
[0071] Alternatively, plating layers 131b and 132b can be formed on the substrate electrode layers 131a and 132a by additional electroplating and / or electroless plating.
[0072] (Experimental Example 1) BaTiO3 powder, four silicide powders (MoSi2, CoSi2, ZrSi2, and HfSi2), and Ni powder with a diameter of 1 μm or smaller were prepared and then formed into pellets using a press. Subsequently, the shrinkage initiation temperature, defined as the temperature at which the pellet length begins to shrink by 5% or more, was measured using a thermomechanical analyzer (TMA) in a reducing atmosphere (2.4% H2). Table 1 below shows the difference in shrinkage initiation temperature ΔT between Ni and the silicides relative to BaTiO3. That is, when the shrinkage initiation temperature of BaTiO3 is represented by T1 and the shrinkage initiation temperature of Ni and the silicides by T2, ΔT (%) is calculated as {100 × (T1 - T2) / T2}, and is shown in Table 1 below.
[0073] [Table 1]
[0074] Referring to Table 1, it can be confirmed that the shrinkage initiation temperature difference between Ni and BaTiO3 is 48%, while the shrinkage initiation temperature difference between silicide and BaTiO3 is within 15%. Therefore, it can be confirmed that when silicide is used instead of Ni to form the internal electrode, the sintering mismatch between the dielectric layer, including perovskite-type compounds, and the internal electrode can be suppressed.
[0075] (Experimental Example 2) After heat-treating the CoSi2 powder under the conditions shown in Table 2 below, sample sheets containing a dielectric layer and an internal electrode were prepared using the heat-treated CoSi2 powder and barium titanate-based powder. Specifically, no heat treatment was performed in Comparative Example 1, and in Comparative Example 2, heat treatment was performed at 650°C for approximately 1 hour (hr) in a 2.4% H2 atmosphere. In Example Example 1, heat treatment was performed at 650°C for approximately 2 hours in a 2.4% H2 atmosphere, and in Example Example 2, heat treatment was performed at 650°C for approximately 4 hours in a 2.4% H2 atmosphere.
[0076] [Table 2]
[0077] For each sample, HAADF-STEM and EDS analysis were used to analyze the interface region extending 100 nm from the interface between the inner electrode and the dielectric layer toward the interior of the inner electrode. Specifically, the oxygen content (wt%) was measured at five arbitrary points in the interface region. Subsequently, the dielectric properties of each sample were evaluated.
[0078] The dielectric properties were evaluated as follows: the capacitance of the sample sheet was measured using an LCR meter (an instrument for testing inductance, capacitance, and resistance) at 1 kHz and AC 0.5 V / μm, and the relative permittivity of the dielectric layer was measured based on the thickness of the dielectric layer, the area of the internal electrode, and the number of stacked layers. The dielectric properties of Comparative Example 1 and Comparative Example 2, as well as Example Example 1 and Example Example 2, were then evaluated as normal (△), good (○), or excellent (◎).
[0079] [Table 3]
[0080] Figure 6A The images were obtained by taking pictures of the dielectric layer and inner electrode of Comparative Example 1 using a scanning electron microscope (SEM). Figure 6B The images were obtained by using SEM to photograph the dielectric layer and inner electrode of Comparative Example 2. Figure 6C The images were obtained by using SEM to capture images of the dielectric layer and inner electrode of Example Example 1. Figure 6D The images were obtained by using SEM to photograph the dielectric layer and inner electrode of Example Example 2.
[0081] In Comparative Example 1, it is confirmed that an interface layer IL is formed at the interface between dielectric layer 111' and inner electrodes 121' and 122', and a second phase SP is formed in dielectric layer 111'. Therefore, it is confirmed that the sample sheet of Comparative Example 1 has slightly inferior dielectric properties.
[0082] In Comparative Example 2, it is confirmed that the interface region has a lower average oxygen content (wt%) compared to Comparative Example 1, and no interface layer is formed at the interface between dielectric layer 111' and inner electrodes 121' and 122'. However, in Comparative Example 2, a second phase SP is also formed in dielectric layer 111'. Therefore, it is confirmed that the dielectric properties of the sample sheets of Comparative Example 1 and Comparative Example 2 are slightly worse than the dielectric properties of the sample sheets of Example Example 1 and Example Example 2 described later.
[0083] In Example 1 and Example 2, it is confirmed that the interface IF between the inner electrodes 121 and 122 and the dielectric layer 111 is distinguishable, and no interface layer is formed between the inner electrodes 121 and 122 and the dielectric layer 111, nor is a second phase formed in the dielectric layer 111. The average oxygen content in Example 1 and Example 2 is less than or equal to 0.75 wt% relative to the weight of all elements in the interface region; therefore, it is confirmed that the sample sheets of Example 1 and Example 2 possess excellent dielectric properties.
[0084] While exemplary embodiments have been described and illustrated above, it will be readily understood by those skilled in the art that modifications and variations may be made without departing from the scope of this disclosure as defined by the appended claims.
[0085] Furthermore, the term "example embodiment" as used herein does not refer to the same example embodiment, but is provided to emphasize features that differ from another example embodiment. However, the example embodiments provided herein are thought to be implementable by combining them entirely or partially with each other. For example, unless a contrary or contradictory description is provided in another example embodiment, an element described in a particular example embodiment may be understood as a description relating to that other example embodiment, even if it is not described in another example embodiment.
[0086] As used herein, the term "connection" can refer not only to a "direct connection" but also to an "indirect connection" via an adhesive layer or the like. The term "electrical connection" can include both cases where elements are "physically connected" and cases where elements are "not physically connected." Furthermore, the terms "first," "second," etc., are used to distinguish one element from another without implying any particular order and / or importance, or any other relationship to the elements. In some instances, without departing from the scope of the exemplary embodiments, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.
Claims
1. A multilayer electronic component, comprising: The main body includes a dielectric layer and internal electrodes alternately disposed with the dielectric layer; as well as External electrodes are disposed on the main body. The internal electrode comprises silicide. In the interface region of the inner electrode, the average oxygen content relative to the weight of all elements is less than or equal to 0.75 wt%, and the interface region extends 100 nm from the interface between the inner electrode and the dielectric layer toward the interior of the inner electrode.
2. The multilayer electronic component according to claim 1, wherein, The silicide includes one or more of Mo, Co, Zr, Hf, Ta, Ti, Cr, and Ni.
3. The multilayer electronic component according to claim 1, wherein, The silicide includes one or more of MoSi2, CoSi2, ZrSi2 and HfSi2.
4. The multilayer electronic component according to claim 1, wherein, The area of the internal electrode other than the interface region is the central region, and The average oxygen weight percentage in the central region is lower than the average oxygen weight percentage in the interface region.
5. The multilayer electronic component according to claim 1, wherein, The region of the internal electrode other than the interface region is the central region, and when the atomic percentage of silicon in the interface region is represented by S1 and the atomic percentage of silicon in the central region is represented by S2, the ratio of S1 to S2 is greater than or equal to 0.9 and less than or equal to 1.
1.
6. The multilayer electronic assembly according to claim 1, wherein, The average oxygen content of the interface region relative to the weight of all elements is greater than or equal to 0.03 wt%.
7. The multilayer electronic assembly according to claim 1, wherein, The internal electrode comprises the silicide as its main component.
8. The multilayer electronic component according to claim 1, wherein, The dielectric layer comprises a perovskite-type compound containing Ba and Ti as the main component.
9. The multilayer electronic component according to claim 1, wherein, The average thickness of the internal electrode is less than or equal to 400 nm.
10. The multilayer electronic assembly according to claim 1, wherein, The average thickness of the dielectric layer is less than or equal to 400 nm.
11. The multilayer electronic assembly according to claim 1, wherein, The silicide is a disilicide with a metal-to-silicon atomic ratio of 1:
2.
12. The multilayer electronic assembly according to claim 1, wherein, The silicide has a sintering temperature of 1050°C or higher and / or 10 6 S / m or higher conductivity.
13. A method for manufacturing a multilayer electronic component, the method comprising: The silicide particles were heat-treated in a reducing atmosphere; Forming a conductive paste comprising heat-treated silicide particles; The conductive paste is printed onto the dielectric sheet; Multiple dielectric sheets printed with the conductive paste are stacked to form a laminate; Sintering the laminate to form a body including a dielectric layer and an internal electrode; and An external electrode is formed on the main body.
14. The method according to claim 13, wherein, The heat treatment step removes the oxide film formed on the surface of each of the silicide particles.
15. The method according to claim 13, wherein, The heat treatment step is carried out at a temperature of 600°C or higher and 800°C or lower for 1 hour or longer and 5 hours or shorter.
16. A method for manufacturing a multilayer electronic component, comprising: (a) Preparation of silicide particles; (b) The silicide particles are heat-treated in a reducing atmosphere to remove the oxide film; (c) Forming a conductive paste comprising heat-treated silicide particles; (d) Print the conductive paste onto the dielectric sheet to form an internal electrode pattern; (e) Stacking multiple dielectric sheets printed with the conductive paste thereon to form a laminate; (f) Sintering the laminate to form a body including a dielectric layer and an internal electrode; and (g) An external electrode is formed on the body.
17. The method according to claim 16, wherein, The reducing atmosphere comprises 0.1% to 3.0% H2 by volume and the balance N2.
18. The method according to claim 16, wherein, The heat treatment is carried out at 600°C to 800°C for 1 to 5 hours.
19. The method of claim 16, wherein, The silicide includes at least one of MoSi2, CoSi2, ZrSi2, and HfSi2.